i915_gem_object.h 14 KB

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  1. /*
  2. * Copyright © 2016 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. */
  24. #ifndef __I915_GEM_OBJECT_H__
  25. #define __I915_GEM_OBJECT_H__
  26. #include <linux/reservation.h>
  27. #include <drm/drm_vma_manager.h>
  28. #include <drm/drm_gem.h>
  29. #include <drm/drmP.h>
  30. #include <drm/i915_drm.h>
  31. #include "i915_request.h"
  32. #include "i915_selftest.h"
  33. struct drm_i915_gem_object;
  34. /*
  35. * struct i915_lut_handle tracks the fast lookups from handle to vma used
  36. * for execbuf. Although we use a radixtree for that mapping, in order to
  37. * remove them as the object or context is closed, we need a secondary list
  38. * and a translation entry (i915_lut_handle).
  39. */
  40. struct i915_lut_handle {
  41. struct list_head obj_link;
  42. struct list_head ctx_link;
  43. struct i915_gem_context *ctx;
  44. u32 handle;
  45. };
  46. struct drm_i915_gem_object_ops {
  47. unsigned int flags;
  48. #define I915_GEM_OBJECT_HAS_STRUCT_PAGE BIT(0)
  49. #define I915_GEM_OBJECT_IS_SHRINKABLE BIT(1)
  50. #define I915_GEM_OBJECT_IS_PROXY BIT(2)
  51. /* Interface between the GEM object and its backing storage.
  52. * get_pages() is called once prior to the use of the associated set
  53. * of pages before to binding them into the GTT, and put_pages() is
  54. * called after we no longer need them. As we expect there to be
  55. * associated cost with migrating pages between the backing storage
  56. * and making them available for the GPU (e.g. clflush), we may hold
  57. * onto the pages after they are no longer referenced by the GPU
  58. * in case they may be used again shortly (for example migrating the
  59. * pages to a different memory domain within the GTT). put_pages()
  60. * will therefore most likely be called when the object itself is
  61. * being released or under memory pressure (where we attempt to
  62. * reap pages for the shrinker).
  63. */
  64. int (*get_pages)(struct drm_i915_gem_object *);
  65. void (*put_pages)(struct drm_i915_gem_object *, struct sg_table *);
  66. int (*pwrite)(struct drm_i915_gem_object *,
  67. const struct drm_i915_gem_pwrite *);
  68. int (*dmabuf_export)(struct drm_i915_gem_object *);
  69. void (*release)(struct drm_i915_gem_object *);
  70. };
  71. struct drm_i915_gem_object {
  72. struct drm_gem_object base;
  73. const struct drm_i915_gem_object_ops *ops;
  74. /**
  75. * @vma_list: List of VMAs backed by this object
  76. *
  77. * The VMA on this list are ordered by type, all GGTT vma are placed
  78. * at the head and all ppGTT vma are placed at the tail. The different
  79. * types of GGTT vma are unordered between themselves, use the
  80. * @vma_tree (which has a defined order between all VMA) to find an
  81. * exact match.
  82. */
  83. struct list_head vma_list;
  84. /**
  85. * @vma_tree: Ordered tree of VMAs backed by this object
  86. *
  87. * All VMA created for this object are placed in the @vma_tree for
  88. * fast retrieval via a binary search in i915_vma_instance().
  89. * They are also added to @vma_list for easy iteration.
  90. */
  91. struct rb_root vma_tree;
  92. /**
  93. * @lut_list: List of vma lookup entries in use for this object.
  94. *
  95. * If this object is closed, we need to remove all of its VMA from
  96. * the fast lookup index in associated contexts; @lut_list provides
  97. * this translation from object to context->handles_vma.
  98. */
  99. struct list_head lut_list;
  100. /** Stolen memory for this object, instead of being backed by shmem. */
  101. struct drm_mm_node *stolen;
  102. union {
  103. struct rcu_head rcu;
  104. struct llist_node freed;
  105. };
  106. /**
  107. * Whether the object is currently in the GGTT mmap.
  108. */
  109. unsigned int userfault_count;
  110. struct list_head userfault_link;
  111. struct list_head batch_pool_link;
  112. I915_SELFTEST_DECLARE(struct list_head st_link);
  113. unsigned long flags;
  114. /**
  115. * Have we taken a reference for the object for incomplete GPU
  116. * activity?
  117. */
  118. #define I915_BO_ACTIVE_REF 0
  119. /*
  120. * Is the object to be mapped as read-only to the GPU
  121. * Only honoured if hardware has relevant pte bit
  122. */
  123. unsigned int cache_level:3;
  124. unsigned int cache_coherent:2;
  125. #define I915_BO_CACHE_COHERENT_FOR_READ BIT(0)
  126. #define I915_BO_CACHE_COHERENT_FOR_WRITE BIT(1)
  127. unsigned int cache_dirty:1;
  128. /**
  129. * @read_domains: Read memory domains.
  130. *
  131. * These monitor which caches contain read/write data related to the
  132. * object. When transitioning from one set of domains to another,
  133. * the driver is called to ensure that caches are suitably flushed and
  134. * invalidated.
  135. */
  136. u16 read_domains;
  137. /**
  138. * @write_domain: Corresponding unique write memory domain.
  139. */
  140. u16 write_domain;
  141. atomic_t frontbuffer_bits;
  142. unsigned int frontbuffer_ggtt_origin; /* write once */
  143. struct i915_gem_active frontbuffer_write;
  144. /** Current tiling stride for the object, if it's tiled. */
  145. unsigned int tiling_and_stride;
  146. #define FENCE_MINIMUM_STRIDE 128 /* See i915_tiling_ok() */
  147. #define TILING_MASK (FENCE_MINIMUM_STRIDE-1)
  148. #define STRIDE_MASK (~TILING_MASK)
  149. /** Count of VMA actually bound by this object */
  150. unsigned int bind_count;
  151. unsigned int active_count;
  152. /** Count of how many global VMA are currently pinned for use by HW */
  153. unsigned int pin_global;
  154. struct {
  155. struct mutex lock; /* protects the pages and their use */
  156. atomic_t pages_pin_count;
  157. struct sg_table *pages;
  158. void *mapping;
  159. /* TODO: whack some of this into the error state */
  160. struct i915_page_sizes {
  161. /**
  162. * The sg mask of the pages sg_table. i.e the mask of
  163. * of the lengths for each sg entry.
  164. */
  165. unsigned int phys;
  166. /**
  167. * The gtt page sizes we are allowed to use given the
  168. * sg mask and the supported page sizes. This will
  169. * express the smallest unit we can use for the whole
  170. * object, as well as the larger sizes we may be able
  171. * to use opportunistically.
  172. */
  173. unsigned int sg;
  174. /**
  175. * The actual gtt page size usage. Since we can have
  176. * multiple vma associated with this object we need to
  177. * prevent any trampling of state, hence a copy of this
  178. * struct also lives in each vma, therefore the gtt
  179. * value here should only be read/write through the vma.
  180. */
  181. unsigned int gtt;
  182. } page_sizes;
  183. I915_SELFTEST_DECLARE(unsigned int page_mask);
  184. struct i915_gem_object_page_iter {
  185. struct scatterlist *sg_pos;
  186. unsigned int sg_idx; /* in pages, but 32bit eek! */
  187. struct radix_tree_root radix;
  188. struct mutex lock; /* protects this cache */
  189. } get_page;
  190. /**
  191. * Element within i915->mm.unbound_list or i915->mm.bound_list,
  192. * locked by i915->mm.obj_lock.
  193. */
  194. struct list_head link;
  195. /**
  196. * Advice: are the backing pages purgeable?
  197. */
  198. unsigned int madv:2;
  199. /**
  200. * This is set if the object has been written to since the
  201. * pages were last acquired.
  202. */
  203. bool dirty:1;
  204. /**
  205. * This is set if the object has been pinned due to unknown
  206. * swizzling.
  207. */
  208. bool quirked:1;
  209. } mm;
  210. /** Breadcrumb of last rendering to the buffer.
  211. * There can only be one writer, but we allow for multiple readers.
  212. * If there is a writer that necessarily implies that all other
  213. * read requests are complete - but we may only be lazily clearing
  214. * the read requests. A read request is naturally the most recent
  215. * request on a ring, so we may have two different write and read
  216. * requests on one ring where the write request is older than the
  217. * read request. This allows for the CPU to read from an active
  218. * buffer by only waiting for the write to complete.
  219. */
  220. struct reservation_object *resv;
  221. /** References from framebuffers, locks out tiling changes. */
  222. unsigned int framebuffer_references;
  223. /** Record of address bit 17 of each page at last unbind. */
  224. unsigned long *bit_17;
  225. union {
  226. struct i915_gem_userptr {
  227. uintptr_t ptr;
  228. struct i915_mm_struct *mm;
  229. struct i915_mmu_object *mmu_object;
  230. struct work_struct *work;
  231. } userptr;
  232. unsigned long scratch;
  233. void *gvt_info;
  234. };
  235. /** for phys allocated objects */
  236. struct drm_dma_handle *phys_handle;
  237. struct reservation_object __builtin_resv;
  238. };
  239. static inline struct drm_i915_gem_object *
  240. to_intel_bo(struct drm_gem_object *gem)
  241. {
  242. /* Assert that to_intel_bo(NULL) == NULL */
  243. BUILD_BUG_ON(offsetof(struct drm_i915_gem_object, base));
  244. return container_of(gem, struct drm_i915_gem_object, base);
  245. }
  246. /**
  247. * i915_gem_object_lookup_rcu - look up a temporary GEM object from its handle
  248. * @filp: DRM file private date
  249. * @handle: userspace handle
  250. *
  251. * Returns:
  252. *
  253. * A pointer to the object named by the handle if such exists on @filp, NULL
  254. * otherwise. This object is only valid whilst under the RCU read lock, and
  255. * note carefully the object may be in the process of being destroyed.
  256. */
  257. static inline struct drm_i915_gem_object *
  258. i915_gem_object_lookup_rcu(struct drm_file *file, u32 handle)
  259. {
  260. #ifdef CONFIG_LOCKDEP
  261. WARN_ON(debug_locks && !lock_is_held(&rcu_lock_map));
  262. #endif
  263. return idr_find(&file->object_idr, handle);
  264. }
  265. static inline struct drm_i915_gem_object *
  266. i915_gem_object_lookup(struct drm_file *file, u32 handle)
  267. {
  268. struct drm_i915_gem_object *obj;
  269. rcu_read_lock();
  270. obj = i915_gem_object_lookup_rcu(file, handle);
  271. if (obj && !kref_get_unless_zero(&obj->base.refcount))
  272. obj = NULL;
  273. rcu_read_unlock();
  274. return obj;
  275. }
  276. __deprecated
  277. extern struct drm_gem_object *
  278. drm_gem_object_lookup(struct drm_file *file, u32 handle);
  279. __attribute__((nonnull))
  280. static inline struct drm_i915_gem_object *
  281. i915_gem_object_get(struct drm_i915_gem_object *obj)
  282. {
  283. drm_gem_object_get(&obj->base);
  284. return obj;
  285. }
  286. __attribute__((nonnull))
  287. static inline void
  288. i915_gem_object_put(struct drm_i915_gem_object *obj)
  289. {
  290. __drm_gem_object_put(&obj->base);
  291. }
  292. static inline void i915_gem_object_lock(struct drm_i915_gem_object *obj)
  293. {
  294. reservation_object_lock(obj->resv, NULL);
  295. }
  296. static inline void i915_gem_object_unlock(struct drm_i915_gem_object *obj)
  297. {
  298. reservation_object_unlock(obj->resv);
  299. }
  300. static inline void
  301. i915_gem_object_set_readonly(struct drm_i915_gem_object *obj)
  302. {
  303. obj->base.vma_node.readonly = true;
  304. }
  305. static inline bool
  306. i915_gem_object_is_readonly(const struct drm_i915_gem_object *obj)
  307. {
  308. return obj->base.vma_node.readonly;
  309. }
  310. static inline bool
  311. i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj)
  312. {
  313. return obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE;
  314. }
  315. static inline bool
  316. i915_gem_object_is_shrinkable(const struct drm_i915_gem_object *obj)
  317. {
  318. return obj->ops->flags & I915_GEM_OBJECT_IS_SHRINKABLE;
  319. }
  320. static inline bool
  321. i915_gem_object_is_proxy(const struct drm_i915_gem_object *obj)
  322. {
  323. return obj->ops->flags & I915_GEM_OBJECT_IS_PROXY;
  324. }
  325. static inline bool
  326. i915_gem_object_is_active(const struct drm_i915_gem_object *obj)
  327. {
  328. return obj->active_count;
  329. }
  330. static inline bool
  331. i915_gem_object_has_active_reference(const struct drm_i915_gem_object *obj)
  332. {
  333. return test_bit(I915_BO_ACTIVE_REF, &obj->flags);
  334. }
  335. static inline void
  336. i915_gem_object_set_active_reference(struct drm_i915_gem_object *obj)
  337. {
  338. lockdep_assert_held(&obj->base.dev->struct_mutex);
  339. __set_bit(I915_BO_ACTIVE_REF, &obj->flags);
  340. }
  341. static inline void
  342. i915_gem_object_clear_active_reference(struct drm_i915_gem_object *obj)
  343. {
  344. lockdep_assert_held(&obj->base.dev->struct_mutex);
  345. __clear_bit(I915_BO_ACTIVE_REF, &obj->flags);
  346. }
  347. void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj);
  348. static inline bool
  349. i915_gem_object_is_framebuffer(const struct drm_i915_gem_object *obj)
  350. {
  351. return READ_ONCE(obj->framebuffer_references);
  352. }
  353. static inline unsigned int
  354. i915_gem_object_get_tiling(const struct drm_i915_gem_object *obj)
  355. {
  356. return obj->tiling_and_stride & TILING_MASK;
  357. }
  358. static inline bool
  359. i915_gem_object_is_tiled(const struct drm_i915_gem_object *obj)
  360. {
  361. return i915_gem_object_get_tiling(obj) != I915_TILING_NONE;
  362. }
  363. static inline unsigned int
  364. i915_gem_object_get_stride(const struct drm_i915_gem_object *obj)
  365. {
  366. return obj->tiling_and_stride & STRIDE_MASK;
  367. }
  368. static inline unsigned int
  369. i915_gem_tile_height(unsigned int tiling)
  370. {
  371. GEM_BUG_ON(!tiling);
  372. return tiling == I915_TILING_Y ? 32 : 8;
  373. }
  374. static inline unsigned int
  375. i915_gem_object_get_tile_height(const struct drm_i915_gem_object *obj)
  376. {
  377. return i915_gem_tile_height(i915_gem_object_get_tiling(obj));
  378. }
  379. static inline unsigned int
  380. i915_gem_object_get_tile_row_size(const struct drm_i915_gem_object *obj)
  381. {
  382. return (i915_gem_object_get_stride(obj) *
  383. i915_gem_object_get_tile_height(obj));
  384. }
  385. int i915_gem_object_set_tiling(struct drm_i915_gem_object *obj,
  386. unsigned int tiling, unsigned int stride);
  387. static inline struct intel_engine_cs *
  388. i915_gem_object_last_write_engine(struct drm_i915_gem_object *obj)
  389. {
  390. struct intel_engine_cs *engine = NULL;
  391. struct dma_fence *fence;
  392. rcu_read_lock();
  393. fence = reservation_object_get_excl_rcu(obj->resv);
  394. rcu_read_unlock();
  395. if (fence && dma_fence_is_i915(fence) && !dma_fence_is_signaled(fence))
  396. engine = to_request(fence)->engine;
  397. dma_fence_put(fence);
  398. return engine;
  399. }
  400. void i915_gem_object_set_cache_coherency(struct drm_i915_gem_object *obj,
  401. unsigned int cache_level);
  402. void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj);
  403. #endif