kfd_device_queue_manager.c 47 KB

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  1. /*
  2. * Copyright 2014 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. */
  23. #include <linux/ratelimit.h>
  24. #include <linux/printk.h>
  25. #include <linux/slab.h>
  26. #include <linux/list.h>
  27. #include <linux/types.h>
  28. #include <linux/bitops.h>
  29. #include <linux/sched.h>
  30. #include "kfd_priv.h"
  31. #include "kfd_device_queue_manager.h"
  32. #include "kfd_mqd_manager.h"
  33. #include "cik_regs.h"
  34. #include "kfd_kernel_queue.h"
  35. /* Size of the per-pipe EOP queue */
  36. #define CIK_HPD_EOP_BYTES_LOG2 11
  37. #define CIK_HPD_EOP_BYTES (1U << CIK_HPD_EOP_BYTES_LOG2)
  38. static int set_pasid_vmid_mapping(struct device_queue_manager *dqm,
  39. unsigned int pasid, unsigned int vmid);
  40. static int create_compute_queue_nocpsch(struct device_queue_manager *dqm,
  41. struct queue *q,
  42. struct qcm_process_device *qpd);
  43. static int execute_queues_cpsch(struct device_queue_manager *dqm,
  44. enum kfd_unmap_queues_filter filter,
  45. uint32_t filter_param);
  46. static int unmap_queues_cpsch(struct device_queue_manager *dqm,
  47. enum kfd_unmap_queues_filter filter,
  48. uint32_t filter_param);
  49. static int map_queues_cpsch(struct device_queue_manager *dqm);
  50. static int create_sdma_queue_nocpsch(struct device_queue_manager *dqm,
  51. struct queue *q,
  52. struct qcm_process_device *qpd);
  53. static void deallocate_sdma_queue(struct device_queue_manager *dqm,
  54. unsigned int sdma_queue_id);
  55. static void kfd_process_hw_exception(struct work_struct *work);
  56. static inline
  57. enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type)
  58. {
  59. if (type == KFD_QUEUE_TYPE_SDMA)
  60. return KFD_MQD_TYPE_SDMA;
  61. return KFD_MQD_TYPE_CP;
  62. }
  63. static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe)
  64. {
  65. int i;
  66. int pipe_offset = mec * dqm->dev->shared_resources.num_pipe_per_mec
  67. + pipe * dqm->dev->shared_resources.num_queue_per_pipe;
  68. /* queue is available for KFD usage if bit is 1 */
  69. for (i = 0; i < dqm->dev->shared_resources.num_queue_per_pipe; ++i)
  70. if (test_bit(pipe_offset + i,
  71. dqm->dev->shared_resources.queue_bitmap))
  72. return true;
  73. return false;
  74. }
  75. unsigned int get_queues_num(struct device_queue_manager *dqm)
  76. {
  77. return bitmap_weight(dqm->dev->shared_resources.queue_bitmap,
  78. KGD_MAX_QUEUES);
  79. }
  80. unsigned int get_queues_per_pipe(struct device_queue_manager *dqm)
  81. {
  82. return dqm->dev->shared_resources.num_queue_per_pipe;
  83. }
  84. unsigned int get_pipes_per_mec(struct device_queue_manager *dqm)
  85. {
  86. return dqm->dev->shared_resources.num_pipe_per_mec;
  87. }
  88. static unsigned int get_num_sdma_engines(struct device_queue_manager *dqm)
  89. {
  90. return dqm->dev->device_info->num_sdma_engines;
  91. }
  92. unsigned int get_num_sdma_queues(struct device_queue_manager *dqm)
  93. {
  94. return dqm->dev->device_info->num_sdma_engines
  95. * dqm->dev->device_info->num_sdma_queues_per_engine;
  96. }
  97. void program_sh_mem_settings(struct device_queue_manager *dqm,
  98. struct qcm_process_device *qpd)
  99. {
  100. return dqm->dev->kfd2kgd->program_sh_mem_settings(
  101. dqm->dev->kgd, qpd->vmid,
  102. qpd->sh_mem_config,
  103. qpd->sh_mem_ape1_base,
  104. qpd->sh_mem_ape1_limit,
  105. qpd->sh_mem_bases);
  106. }
  107. static int allocate_doorbell(struct qcm_process_device *qpd, struct queue *q)
  108. {
  109. struct kfd_dev *dev = qpd->dqm->dev;
  110. if (!KFD_IS_SOC15(dev->device_info->asic_family)) {
  111. /* On pre-SOC15 chips we need to use the queue ID to
  112. * preserve the user mode ABI.
  113. */
  114. q->doorbell_id = q->properties.queue_id;
  115. } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
  116. /* For SDMA queues on SOC15, use static doorbell
  117. * assignments based on the engine and queue.
  118. */
  119. q->doorbell_id = dev->shared_resources.sdma_doorbell
  120. [q->properties.sdma_engine_id]
  121. [q->properties.sdma_queue_id];
  122. } else {
  123. /* For CP queues on SOC15 reserve a free doorbell ID */
  124. unsigned int found;
  125. found = find_first_zero_bit(qpd->doorbell_bitmap,
  126. KFD_MAX_NUM_OF_QUEUES_PER_PROCESS);
  127. if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) {
  128. pr_debug("No doorbells available");
  129. return -EBUSY;
  130. }
  131. set_bit(found, qpd->doorbell_bitmap);
  132. q->doorbell_id = found;
  133. }
  134. q->properties.doorbell_off =
  135. kfd_doorbell_id_to_offset(dev, q->process,
  136. q->doorbell_id);
  137. return 0;
  138. }
  139. static void deallocate_doorbell(struct qcm_process_device *qpd,
  140. struct queue *q)
  141. {
  142. unsigned int old;
  143. struct kfd_dev *dev = qpd->dqm->dev;
  144. if (!KFD_IS_SOC15(dev->device_info->asic_family) ||
  145. q->properties.type == KFD_QUEUE_TYPE_SDMA)
  146. return;
  147. old = test_and_clear_bit(q->doorbell_id, qpd->doorbell_bitmap);
  148. WARN_ON(!old);
  149. }
  150. static int allocate_vmid(struct device_queue_manager *dqm,
  151. struct qcm_process_device *qpd,
  152. struct queue *q)
  153. {
  154. int bit, allocated_vmid;
  155. if (dqm->vmid_bitmap == 0)
  156. return -ENOMEM;
  157. bit = ffs(dqm->vmid_bitmap) - 1;
  158. dqm->vmid_bitmap &= ~(1 << bit);
  159. allocated_vmid = bit + dqm->dev->vm_info.first_vmid_kfd;
  160. pr_debug("vmid allocation %d\n", allocated_vmid);
  161. qpd->vmid = allocated_vmid;
  162. q->properties.vmid = allocated_vmid;
  163. set_pasid_vmid_mapping(dqm, q->process->pasid, q->properties.vmid);
  164. program_sh_mem_settings(dqm, qpd);
  165. /* qpd->page_table_base is set earlier when register_process()
  166. * is called, i.e. when the first queue is created.
  167. */
  168. dqm->dev->kfd2kgd->set_vm_context_page_table_base(dqm->dev->kgd,
  169. qpd->vmid,
  170. qpd->page_table_base);
  171. /* invalidate the VM context after pasid and vmid mapping is set up */
  172. kfd_flush_tlb(qpd_to_pdd(qpd));
  173. return 0;
  174. }
  175. static int flush_texture_cache_nocpsch(struct kfd_dev *kdev,
  176. struct qcm_process_device *qpd)
  177. {
  178. const struct packet_manager_funcs *pmf = qpd->dqm->packets.pmf;
  179. int ret;
  180. if (!qpd->ib_kaddr)
  181. return -ENOMEM;
  182. ret = pmf->release_mem(qpd->ib_base, (uint32_t *)qpd->ib_kaddr);
  183. if (ret)
  184. return ret;
  185. return kdev->kfd2kgd->submit_ib(kdev->kgd, KGD_ENGINE_MEC1, qpd->vmid,
  186. qpd->ib_base, (uint32_t *)qpd->ib_kaddr,
  187. pmf->release_mem_size / sizeof(uint32_t));
  188. }
  189. static void deallocate_vmid(struct device_queue_manager *dqm,
  190. struct qcm_process_device *qpd,
  191. struct queue *q)
  192. {
  193. int bit = qpd->vmid - dqm->dev->vm_info.first_vmid_kfd;
  194. /* On GFX v7, CP doesn't flush TC at dequeue */
  195. if (q->device->device_info->asic_family == CHIP_HAWAII)
  196. if (flush_texture_cache_nocpsch(q->device, qpd))
  197. pr_err("Failed to flush TC\n");
  198. kfd_flush_tlb(qpd_to_pdd(qpd));
  199. /* Release the vmid mapping */
  200. set_pasid_vmid_mapping(dqm, 0, qpd->vmid);
  201. dqm->vmid_bitmap |= (1 << bit);
  202. qpd->vmid = 0;
  203. q->properties.vmid = 0;
  204. }
  205. static int create_queue_nocpsch(struct device_queue_manager *dqm,
  206. struct queue *q,
  207. struct qcm_process_device *qpd)
  208. {
  209. int retval;
  210. print_queue(q);
  211. dqm_lock(dqm);
  212. if (dqm->total_queue_count >= max_num_of_queues_per_device) {
  213. pr_warn("Can't create new usermode queue because %d queues were already created\n",
  214. dqm->total_queue_count);
  215. retval = -EPERM;
  216. goto out_unlock;
  217. }
  218. if (list_empty(&qpd->queues_list)) {
  219. retval = allocate_vmid(dqm, qpd, q);
  220. if (retval)
  221. goto out_unlock;
  222. }
  223. q->properties.vmid = qpd->vmid;
  224. /*
  225. * Eviction state logic: we only mark active queues as evicted
  226. * to avoid the overhead of restoring inactive queues later
  227. */
  228. if (qpd->evicted)
  229. q->properties.is_evicted = (q->properties.queue_size > 0 &&
  230. q->properties.queue_percent > 0 &&
  231. q->properties.queue_address != 0);
  232. q->properties.tba_addr = qpd->tba_addr;
  233. q->properties.tma_addr = qpd->tma_addr;
  234. if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE)
  235. retval = create_compute_queue_nocpsch(dqm, q, qpd);
  236. else if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
  237. retval = create_sdma_queue_nocpsch(dqm, q, qpd);
  238. else
  239. retval = -EINVAL;
  240. if (retval) {
  241. if (list_empty(&qpd->queues_list))
  242. deallocate_vmid(dqm, qpd, q);
  243. goto out_unlock;
  244. }
  245. list_add(&q->list, &qpd->queues_list);
  246. qpd->queue_count++;
  247. if (q->properties.is_active)
  248. dqm->queue_count++;
  249. if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
  250. dqm->sdma_queue_count++;
  251. /*
  252. * Unconditionally increment this counter, regardless of the queue's
  253. * type or whether the queue is active.
  254. */
  255. dqm->total_queue_count++;
  256. pr_debug("Total of %d queues are accountable so far\n",
  257. dqm->total_queue_count);
  258. out_unlock:
  259. dqm_unlock(dqm);
  260. return retval;
  261. }
  262. static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q)
  263. {
  264. bool set;
  265. int pipe, bit, i;
  266. set = false;
  267. for (pipe = dqm->next_pipe_to_allocate, i = 0;
  268. i < get_pipes_per_mec(dqm);
  269. pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) {
  270. if (!is_pipe_enabled(dqm, 0, pipe))
  271. continue;
  272. if (dqm->allocated_queues[pipe] != 0) {
  273. bit = ffs(dqm->allocated_queues[pipe]) - 1;
  274. dqm->allocated_queues[pipe] &= ~(1 << bit);
  275. q->pipe = pipe;
  276. q->queue = bit;
  277. set = true;
  278. break;
  279. }
  280. }
  281. if (!set)
  282. return -EBUSY;
  283. pr_debug("hqd slot - pipe %d, queue %d\n", q->pipe, q->queue);
  284. /* horizontal hqd allocation */
  285. dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm);
  286. return 0;
  287. }
  288. static inline void deallocate_hqd(struct device_queue_manager *dqm,
  289. struct queue *q)
  290. {
  291. dqm->allocated_queues[q->pipe] |= (1 << q->queue);
  292. }
  293. static int create_compute_queue_nocpsch(struct device_queue_manager *dqm,
  294. struct queue *q,
  295. struct qcm_process_device *qpd)
  296. {
  297. struct mqd_manager *mqd_mgr;
  298. int retval;
  299. mqd_mgr = dqm->ops.get_mqd_manager(dqm, KFD_MQD_TYPE_COMPUTE);
  300. if (!mqd_mgr)
  301. return -ENOMEM;
  302. retval = allocate_hqd(dqm, q);
  303. if (retval)
  304. return retval;
  305. retval = allocate_doorbell(qpd, q);
  306. if (retval)
  307. goto out_deallocate_hqd;
  308. retval = mqd_mgr->init_mqd(mqd_mgr, &q->mqd, &q->mqd_mem_obj,
  309. &q->gart_mqd_addr, &q->properties);
  310. if (retval)
  311. goto out_deallocate_doorbell;
  312. pr_debug("Loading mqd to hqd on pipe %d, queue %d\n",
  313. q->pipe, q->queue);
  314. dqm->dev->kfd2kgd->set_scratch_backing_va(
  315. dqm->dev->kgd, qpd->sh_hidden_private_base, qpd->vmid);
  316. if (!q->properties.is_active)
  317. return 0;
  318. if (WARN(q->process->mm != current->mm,
  319. "should only run in user thread"))
  320. retval = -EFAULT;
  321. else
  322. retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe, q->queue,
  323. &q->properties, current->mm);
  324. if (retval)
  325. goto out_uninit_mqd;
  326. return 0;
  327. out_uninit_mqd:
  328. mqd_mgr->uninit_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
  329. out_deallocate_doorbell:
  330. deallocate_doorbell(qpd, q);
  331. out_deallocate_hqd:
  332. deallocate_hqd(dqm, q);
  333. return retval;
  334. }
  335. /* Access to DQM has to be locked before calling destroy_queue_nocpsch_locked
  336. * to avoid asynchronized access
  337. */
  338. static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm,
  339. struct qcm_process_device *qpd,
  340. struct queue *q)
  341. {
  342. int retval;
  343. struct mqd_manager *mqd_mgr;
  344. mqd_mgr = dqm->ops.get_mqd_manager(dqm,
  345. get_mqd_type_from_queue_type(q->properties.type));
  346. if (!mqd_mgr)
  347. return -ENOMEM;
  348. if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) {
  349. deallocate_hqd(dqm, q);
  350. } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
  351. dqm->sdma_queue_count--;
  352. deallocate_sdma_queue(dqm, q->sdma_id);
  353. } else {
  354. pr_debug("q->properties.type %d is invalid\n",
  355. q->properties.type);
  356. return -EINVAL;
  357. }
  358. dqm->total_queue_count--;
  359. deallocate_doorbell(qpd, q);
  360. retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
  361. KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
  362. KFD_UNMAP_LATENCY_MS,
  363. q->pipe, q->queue);
  364. if (retval == -ETIME)
  365. qpd->reset_wavefronts = true;
  366. mqd_mgr->uninit_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
  367. list_del(&q->list);
  368. if (list_empty(&qpd->queues_list)) {
  369. if (qpd->reset_wavefronts) {
  370. pr_warn("Resetting wave fronts (nocpsch) on dev %p\n",
  371. dqm->dev);
  372. /* dbgdev_wave_reset_wavefronts has to be called before
  373. * deallocate_vmid(), i.e. when vmid is still in use.
  374. */
  375. dbgdev_wave_reset_wavefronts(dqm->dev,
  376. qpd->pqm->process);
  377. qpd->reset_wavefronts = false;
  378. }
  379. deallocate_vmid(dqm, qpd, q);
  380. }
  381. qpd->queue_count--;
  382. if (q->properties.is_active)
  383. dqm->queue_count--;
  384. return retval;
  385. }
  386. static int destroy_queue_nocpsch(struct device_queue_manager *dqm,
  387. struct qcm_process_device *qpd,
  388. struct queue *q)
  389. {
  390. int retval;
  391. dqm_lock(dqm);
  392. retval = destroy_queue_nocpsch_locked(dqm, qpd, q);
  393. dqm_unlock(dqm);
  394. return retval;
  395. }
  396. static int update_queue(struct device_queue_manager *dqm, struct queue *q)
  397. {
  398. int retval;
  399. struct mqd_manager *mqd_mgr;
  400. struct kfd_process_device *pdd;
  401. bool prev_active = false;
  402. dqm_lock(dqm);
  403. pdd = kfd_get_process_device_data(q->device, q->process);
  404. if (!pdd) {
  405. retval = -ENODEV;
  406. goto out_unlock;
  407. }
  408. mqd_mgr = dqm->ops.get_mqd_manager(dqm,
  409. get_mqd_type_from_queue_type(q->properties.type));
  410. if (!mqd_mgr) {
  411. retval = -ENOMEM;
  412. goto out_unlock;
  413. }
  414. /*
  415. * Eviction state logic: we only mark active queues as evicted
  416. * to avoid the overhead of restoring inactive queues later
  417. */
  418. if (pdd->qpd.evicted)
  419. q->properties.is_evicted = (q->properties.queue_size > 0 &&
  420. q->properties.queue_percent > 0 &&
  421. q->properties.queue_address != 0);
  422. /* Save previous activity state for counters */
  423. prev_active = q->properties.is_active;
  424. /* Make sure the queue is unmapped before updating the MQD */
  425. if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) {
  426. retval = unmap_queues_cpsch(dqm,
  427. KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
  428. if (retval) {
  429. pr_err("unmap queue failed\n");
  430. goto out_unlock;
  431. }
  432. } else if (prev_active &&
  433. (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
  434. q->properties.type == KFD_QUEUE_TYPE_SDMA)) {
  435. retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
  436. KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN,
  437. KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
  438. if (retval) {
  439. pr_err("destroy mqd failed\n");
  440. goto out_unlock;
  441. }
  442. }
  443. retval = mqd_mgr->update_mqd(mqd_mgr, q->mqd, &q->properties);
  444. /*
  445. * check active state vs. the previous state and modify
  446. * counter accordingly. map_queues_cpsch uses the
  447. * dqm->queue_count to determine whether a new runlist must be
  448. * uploaded.
  449. */
  450. if (q->properties.is_active && !prev_active)
  451. dqm->queue_count++;
  452. else if (!q->properties.is_active && prev_active)
  453. dqm->queue_count--;
  454. if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS)
  455. retval = map_queues_cpsch(dqm);
  456. else if (q->properties.is_active &&
  457. (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
  458. q->properties.type == KFD_QUEUE_TYPE_SDMA)) {
  459. if (WARN(q->process->mm != current->mm,
  460. "should only run in user thread"))
  461. retval = -EFAULT;
  462. else
  463. retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd,
  464. q->pipe, q->queue,
  465. &q->properties, current->mm);
  466. }
  467. out_unlock:
  468. dqm_unlock(dqm);
  469. return retval;
  470. }
  471. static struct mqd_manager *get_mqd_manager(
  472. struct device_queue_manager *dqm, enum KFD_MQD_TYPE type)
  473. {
  474. struct mqd_manager *mqd_mgr;
  475. if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
  476. return NULL;
  477. pr_debug("mqd type %d\n", type);
  478. mqd_mgr = dqm->mqd_mgrs[type];
  479. if (!mqd_mgr) {
  480. mqd_mgr = mqd_manager_init(type, dqm->dev);
  481. if (!mqd_mgr)
  482. pr_err("mqd manager is NULL");
  483. dqm->mqd_mgrs[type] = mqd_mgr;
  484. }
  485. return mqd_mgr;
  486. }
  487. static int evict_process_queues_nocpsch(struct device_queue_manager *dqm,
  488. struct qcm_process_device *qpd)
  489. {
  490. struct queue *q;
  491. struct mqd_manager *mqd_mgr;
  492. struct kfd_process_device *pdd;
  493. int retval = 0;
  494. dqm_lock(dqm);
  495. if (qpd->evicted++ > 0) /* already evicted, do nothing */
  496. goto out;
  497. pdd = qpd_to_pdd(qpd);
  498. pr_info_ratelimited("Evicting PASID %u queues\n",
  499. pdd->process->pasid);
  500. /* unactivate all active queues on the qpd */
  501. list_for_each_entry(q, &qpd->queues_list, list) {
  502. if (!q->properties.is_active)
  503. continue;
  504. mqd_mgr = dqm->ops.get_mqd_manager(dqm,
  505. get_mqd_type_from_queue_type(q->properties.type));
  506. if (!mqd_mgr) { /* should not be here */
  507. pr_err("Cannot evict queue, mqd mgr is NULL\n");
  508. retval = -ENOMEM;
  509. goto out;
  510. }
  511. q->properties.is_evicted = true;
  512. q->properties.is_active = false;
  513. retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
  514. KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN,
  515. KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
  516. if (retval)
  517. goto out;
  518. dqm->queue_count--;
  519. }
  520. out:
  521. dqm_unlock(dqm);
  522. return retval;
  523. }
  524. static int evict_process_queues_cpsch(struct device_queue_manager *dqm,
  525. struct qcm_process_device *qpd)
  526. {
  527. struct queue *q;
  528. struct kfd_process_device *pdd;
  529. int retval = 0;
  530. dqm_lock(dqm);
  531. if (qpd->evicted++ > 0) /* already evicted, do nothing */
  532. goto out;
  533. pdd = qpd_to_pdd(qpd);
  534. pr_info_ratelimited("Evicting PASID %u queues\n",
  535. pdd->process->pasid);
  536. /* unactivate all active queues on the qpd */
  537. list_for_each_entry(q, &qpd->queues_list, list) {
  538. if (!q->properties.is_active)
  539. continue;
  540. q->properties.is_evicted = true;
  541. q->properties.is_active = false;
  542. dqm->queue_count--;
  543. }
  544. retval = execute_queues_cpsch(dqm,
  545. qpd->is_debug ?
  546. KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES :
  547. KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
  548. out:
  549. dqm_unlock(dqm);
  550. return retval;
  551. }
  552. static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,
  553. struct qcm_process_device *qpd)
  554. {
  555. struct mm_struct *mm = NULL;
  556. struct queue *q;
  557. struct mqd_manager *mqd_mgr;
  558. struct kfd_process_device *pdd;
  559. uint64_t pd_base;
  560. int retval = 0;
  561. pdd = qpd_to_pdd(qpd);
  562. /* Retrieve PD base */
  563. pd_base = dqm->dev->kfd2kgd->get_process_page_dir(pdd->vm);
  564. dqm_lock(dqm);
  565. if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
  566. goto out;
  567. if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
  568. qpd->evicted--;
  569. goto out;
  570. }
  571. pr_info_ratelimited("Restoring PASID %u queues\n",
  572. pdd->process->pasid);
  573. /* Update PD Base in QPD */
  574. qpd->page_table_base = pd_base;
  575. pr_debug("Updated PD address to 0x%llx\n", pd_base);
  576. if (!list_empty(&qpd->queues_list)) {
  577. dqm->dev->kfd2kgd->set_vm_context_page_table_base(
  578. dqm->dev->kgd,
  579. qpd->vmid,
  580. qpd->page_table_base);
  581. kfd_flush_tlb(pdd);
  582. }
  583. /* Take a safe reference to the mm_struct, which may otherwise
  584. * disappear even while the kfd_process is still referenced.
  585. */
  586. mm = get_task_mm(pdd->process->lead_thread);
  587. if (!mm) {
  588. retval = -EFAULT;
  589. goto out;
  590. }
  591. /* activate all active queues on the qpd */
  592. list_for_each_entry(q, &qpd->queues_list, list) {
  593. if (!q->properties.is_evicted)
  594. continue;
  595. mqd_mgr = dqm->ops.get_mqd_manager(dqm,
  596. get_mqd_type_from_queue_type(q->properties.type));
  597. if (!mqd_mgr) { /* should not be here */
  598. pr_err("Cannot restore queue, mqd mgr is NULL\n");
  599. retval = -ENOMEM;
  600. goto out;
  601. }
  602. q->properties.is_evicted = false;
  603. q->properties.is_active = true;
  604. retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe,
  605. q->queue, &q->properties, mm);
  606. if (retval)
  607. goto out;
  608. dqm->queue_count++;
  609. }
  610. qpd->evicted = 0;
  611. out:
  612. if (mm)
  613. mmput(mm);
  614. dqm_unlock(dqm);
  615. return retval;
  616. }
  617. static int restore_process_queues_cpsch(struct device_queue_manager *dqm,
  618. struct qcm_process_device *qpd)
  619. {
  620. struct queue *q;
  621. struct kfd_process_device *pdd;
  622. uint64_t pd_base;
  623. int retval = 0;
  624. pdd = qpd_to_pdd(qpd);
  625. /* Retrieve PD base */
  626. pd_base = dqm->dev->kfd2kgd->get_process_page_dir(pdd->vm);
  627. dqm_lock(dqm);
  628. if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
  629. goto out;
  630. if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
  631. qpd->evicted--;
  632. goto out;
  633. }
  634. pr_info_ratelimited("Restoring PASID %u queues\n",
  635. pdd->process->pasid);
  636. /* Update PD Base in QPD */
  637. qpd->page_table_base = pd_base;
  638. pr_debug("Updated PD address to 0x%llx\n", pd_base);
  639. /* activate all active queues on the qpd */
  640. list_for_each_entry(q, &qpd->queues_list, list) {
  641. if (!q->properties.is_evicted)
  642. continue;
  643. q->properties.is_evicted = false;
  644. q->properties.is_active = true;
  645. dqm->queue_count++;
  646. }
  647. retval = execute_queues_cpsch(dqm,
  648. KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
  649. if (!retval)
  650. qpd->evicted = 0;
  651. out:
  652. dqm_unlock(dqm);
  653. return retval;
  654. }
  655. static int register_process(struct device_queue_manager *dqm,
  656. struct qcm_process_device *qpd)
  657. {
  658. struct device_process_node *n;
  659. struct kfd_process_device *pdd;
  660. uint64_t pd_base;
  661. int retval;
  662. n = kzalloc(sizeof(*n), GFP_KERNEL);
  663. if (!n)
  664. return -ENOMEM;
  665. n->qpd = qpd;
  666. pdd = qpd_to_pdd(qpd);
  667. /* Retrieve PD base */
  668. pd_base = dqm->dev->kfd2kgd->get_process_page_dir(pdd->vm);
  669. dqm_lock(dqm);
  670. list_add(&n->list, &dqm->queues);
  671. /* Update PD Base in QPD */
  672. qpd->page_table_base = pd_base;
  673. pr_debug("Updated PD address to 0x%llx\n", pd_base);
  674. retval = dqm->asic_ops.update_qpd(dqm, qpd);
  675. if (dqm->processes_count++ == 0)
  676. dqm->dev->kfd2kgd->set_compute_idle(dqm->dev->kgd, false);
  677. dqm_unlock(dqm);
  678. return retval;
  679. }
  680. static int unregister_process(struct device_queue_manager *dqm,
  681. struct qcm_process_device *qpd)
  682. {
  683. int retval;
  684. struct device_process_node *cur, *next;
  685. pr_debug("qpd->queues_list is %s\n",
  686. list_empty(&qpd->queues_list) ? "empty" : "not empty");
  687. retval = 0;
  688. dqm_lock(dqm);
  689. list_for_each_entry_safe(cur, next, &dqm->queues, list) {
  690. if (qpd == cur->qpd) {
  691. list_del(&cur->list);
  692. kfree(cur);
  693. if (--dqm->processes_count == 0)
  694. dqm->dev->kfd2kgd->set_compute_idle(
  695. dqm->dev->kgd, true);
  696. goto out;
  697. }
  698. }
  699. /* qpd not found in dqm list */
  700. retval = 1;
  701. out:
  702. dqm_unlock(dqm);
  703. return retval;
  704. }
  705. static int
  706. set_pasid_vmid_mapping(struct device_queue_manager *dqm, unsigned int pasid,
  707. unsigned int vmid)
  708. {
  709. uint32_t pasid_mapping;
  710. pasid_mapping = (pasid == 0) ? 0 :
  711. (uint32_t)pasid |
  712. ATC_VMID_PASID_MAPPING_VALID;
  713. return dqm->dev->kfd2kgd->set_pasid_vmid_mapping(
  714. dqm->dev->kgd, pasid_mapping,
  715. vmid);
  716. }
  717. static void init_interrupts(struct device_queue_manager *dqm)
  718. {
  719. unsigned int i;
  720. for (i = 0 ; i < get_pipes_per_mec(dqm) ; i++)
  721. if (is_pipe_enabled(dqm, 0, i))
  722. dqm->dev->kfd2kgd->init_interrupts(dqm->dev->kgd, i);
  723. }
  724. static int initialize_nocpsch(struct device_queue_manager *dqm)
  725. {
  726. int pipe, queue;
  727. pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
  728. dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm),
  729. sizeof(unsigned int), GFP_KERNEL);
  730. if (!dqm->allocated_queues)
  731. return -ENOMEM;
  732. mutex_init(&dqm->lock_hidden);
  733. INIT_LIST_HEAD(&dqm->queues);
  734. dqm->queue_count = dqm->next_pipe_to_allocate = 0;
  735. dqm->sdma_queue_count = 0;
  736. for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
  737. int pipe_offset = pipe * get_queues_per_pipe(dqm);
  738. for (queue = 0; queue < get_queues_per_pipe(dqm); queue++)
  739. if (test_bit(pipe_offset + queue,
  740. dqm->dev->shared_resources.queue_bitmap))
  741. dqm->allocated_queues[pipe] |= 1 << queue;
  742. }
  743. dqm->vmid_bitmap = (1 << dqm->dev->vm_info.vmid_num_kfd) - 1;
  744. dqm->sdma_bitmap = (1 << get_num_sdma_queues(dqm)) - 1;
  745. return 0;
  746. }
  747. static void uninitialize(struct device_queue_manager *dqm)
  748. {
  749. int i;
  750. WARN_ON(dqm->queue_count > 0 || dqm->processes_count > 0);
  751. kfree(dqm->allocated_queues);
  752. for (i = 0 ; i < KFD_MQD_TYPE_MAX ; i++)
  753. kfree(dqm->mqd_mgrs[i]);
  754. mutex_destroy(&dqm->lock_hidden);
  755. kfd_gtt_sa_free(dqm->dev, dqm->pipeline_mem);
  756. }
  757. static int start_nocpsch(struct device_queue_manager *dqm)
  758. {
  759. init_interrupts(dqm);
  760. return pm_init(&dqm->packets, dqm);
  761. }
  762. static int stop_nocpsch(struct device_queue_manager *dqm)
  763. {
  764. pm_uninit(&dqm->packets);
  765. return 0;
  766. }
  767. static int allocate_sdma_queue(struct device_queue_manager *dqm,
  768. unsigned int *sdma_queue_id)
  769. {
  770. int bit;
  771. if (dqm->sdma_bitmap == 0)
  772. return -ENOMEM;
  773. bit = ffs(dqm->sdma_bitmap) - 1;
  774. dqm->sdma_bitmap &= ~(1 << bit);
  775. *sdma_queue_id = bit;
  776. return 0;
  777. }
  778. static void deallocate_sdma_queue(struct device_queue_manager *dqm,
  779. unsigned int sdma_queue_id)
  780. {
  781. if (sdma_queue_id >= get_num_sdma_queues(dqm))
  782. return;
  783. dqm->sdma_bitmap |= (1 << sdma_queue_id);
  784. }
  785. static int create_sdma_queue_nocpsch(struct device_queue_manager *dqm,
  786. struct queue *q,
  787. struct qcm_process_device *qpd)
  788. {
  789. struct mqd_manager *mqd_mgr;
  790. int retval;
  791. mqd_mgr = dqm->ops.get_mqd_manager(dqm, KFD_MQD_TYPE_SDMA);
  792. if (!mqd_mgr)
  793. return -ENOMEM;
  794. retval = allocate_sdma_queue(dqm, &q->sdma_id);
  795. if (retval)
  796. return retval;
  797. q->properties.sdma_queue_id = q->sdma_id / get_num_sdma_engines(dqm);
  798. q->properties.sdma_engine_id = q->sdma_id % get_num_sdma_engines(dqm);
  799. retval = allocate_doorbell(qpd, q);
  800. if (retval)
  801. goto out_deallocate_sdma_queue;
  802. pr_debug("SDMA id is: %d\n", q->sdma_id);
  803. pr_debug("SDMA queue id: %d\n", q->properties.sdma_queue_id);
  804. pr_debug("SDMA engine id: %d\n", q->properties.sdma_engine_id);
  805. dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
  806. retval = mqd_mgr->init_mqd(mqd_mgr, &q->mqd, &q->mqd_mem_obj,
  807. &q->gart_mqd_addr, &q->properties);
  808. if (retval)
  809. goto out_deallocate_doorbell;
  810. retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, 0, 0, &q->properties,
  811. NULL);
  812. if (retval)
  813. goto out_uninit_mqd;
  814. return 0;
  815. out_uninit_mqd:
  816. mqd_mgr->uninit_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
  817. out_deallocate_doorbell:
  818. deallocate_doorbell(qpd, q);
  819. out_deallocate_sdma_queue:
  820. deallocate_sdma_queue(dqm, q->sdma_id);
  821. return retval;
  822. }
  823. /*
  824. * Device Queue Manager implementation for cp scheduler
  825. */
  826. static int set_sched_resources(struct device_queue_manager *dqm)
  827. {
  828. int i, mec;
  829. struct scheduling_resources res;
  830. res.vmid_mask = dqm->dev->shared_resources.compute_vmid_bitmap;
  831. res.queue_mask = 0;
  832. for (i = 0; i < KGD_MAX_QUEUES; ++i) {
  833. mec = (i / dqm->dev->shared_resources.num_queue_per_pipe)
  834. / dqm->dev->shared_resources.num_pipe_per_mec;
  835. if (!test_bit(i, dqm->dev->shared_resources.queue_bitmap))
  836. continue;
  837. /* only acquire queues from the first MEC */
  838. if (mec > 0)
  839. continue;
  840. /* This situation may be hit in the future if a new HW
  841. * generation exposes more than 64 queues. If so, the
  842. * definition of res.queue_mask needs updating
  843. */
  844. if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) {
  845. pr_err("Invalid queue enabled by amdgpu: %d\n", i);
  846. break;
  847. }
  848. res.queue_mask |= (1ull << i);
  849. }
  850. res.gws_mask = res.oac_mask = res.gds_heap_base =
  851. res.gds_heap_size = 0;
  852. pr_debug("Scheduling resources:\n"
  853. "vmid mask: 0x%8X\n"
  854. "queue mask: 0x%8llX\n",
  855. res.vmid_mask, res.queue_mask);
  856. return pm_send_set_resources(&dqm->packets, &res);
  857. }
  858. static int initialize_cpsch(struct device_queue_manager *dqm)
  859. {
  860. pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
  861. mutex_init(&dqm->lock_hidden);
  862. INIT_LIST_HEAD(&dqm->queues);
  863. dqm->queue_count = dqm->processes_count = 0;
  864. dqm->sdma_queue_count = 0;
  865. dqm->active_runlist = false;
  866. dqm->sdma_bitmap = (1 << get_num_sdma_queues(dqm)) - 1;
  867. INIT_WORK(&dqm->hw_exception_work, kfd_process_hw_exception);
  868. return 0;
  869. }
  870. static int start_cpsch(struct device_queue_manager *dqm)
  871. {
  872. int retval;
  873. retval = 0;
  874. retval = pm_init(&dqm->packets, dqm);
  875. if (retval)
  876. goto fail_packet_manager_init;
  877. retval = set_sched_resources(dqm);
  878. if (retval)
  879. goto fail_set_sched_resources;
  880. pr_debug("Allocating fence memory\n");
  881. /* allocate fence memory on the gart */
  882. retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr),
  883. &dqm->fence_mem);
  884. if (retval)
  885. goto fail_allocate_vidmem;
  886. dqm->fence_addr = dqm->fence_mem->cpu_ptr;
  887. dqm->fence_gpu_addr = dqm->fence_mem->gpu_addr;
  888. init_interrupts(dqm);
  889. dqm_lock(dqm);
  890. /* clear hang status when driver try to start the hw scheduler */
  891. dqm->is_hws_hang = false;
  892. execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
  893. dqm_unlock(dqm);
  894. return 0;
  895. fail_allocate_vidmem:
  896. fail_set_sched_resources:
  897. pm_uninit(&dqm->packets);
  898. fail_packet_manager_init:
  899. return retval;
  900. }
  901. static int stop_cpsch(struct device_queue_manager *dqm)
  902. {
  903. dqm_lock(dqm);
  904. unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
  905. dqm_unlock(dqm);
  906. kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
  907. pm_uninit(&dqm->packets);
  908. return 0;
  909. }
  910. static int create_kernel_queue_cpsch(struct device_queue_manager *dqm,
  911. struct kernel_queue *kq,
  912. struct qcm_process_device *qpd)
  913. {
  914. dqm_lock(dqm);
  915. if (dqm->total_queue_count >= max_num_of_queues_per_device) {
  916. pr_warn("Can't create new kernel queue because %d queues were already created\n",
  917. dqm->total_queue_count);
  918. dqm_unlock(dqm);
  919. return -EPERM;
  920. }
  921. /*
  922. * Unconditionally increment this counter, regardless of the queue's
  923. * type or whether the queue is active.
  924. */
  925. dqm->total_queue_count++;
  926. pr_debug("Total of %d queues are accountable so far\n",
  927. dqm->total_queue_count);
  928. list_add(&kq->list, &qpd->priv_queue_list);
  929. dqm->queue_count++;
  930. qpd->is_debug = true;
  931. execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
  932. dqm_unlock(dqm);
  933. return 0;
  934. }
  935. static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm,
  936. struct kernel_queue *kq,
  937. struct qcm_process_device *qpd)
  938. {
  939. dqm_lock(dqm);
  940. list_del(&kq->list);
  941. dqm->queue_count--;
  942. qpd->is_debug = false;
  943. execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
  944. /*
  945. * Unconditionally decrement this counter, regardless of the queue's
  946. * type.
  947. */
  948. dqm->total_queue_count--;
  949. pr_debug("Total of %d queues are accountable so far\n",
  950. dqm->total_queue_count);
  951. dqm_unlock(dqm);
  952. }
  953. static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q,
  954. struct qcm_process_device *qpd)
  955. {
  956. int retval;
  957. struct mqd_manager *mqd_mgr;
  958. retval = 0;
  959. dqm_lock(dqm);
  960. if (dqm->total_queue_count >= max_num_of_queues_per_device) {
  961. pr_warn("Can't create new usermode queue because %d queues were already created\n",
  962. dqm->total_queue_count);
  963. retval = -EPERM;
  964. goto out_unlock;
  965. }
  966. if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
  967. retval = allocate_sdma_queue(dqm, &q->sdma_id);
  968. if (retval)
  969. goto out_unlock;
  970. q->properties.sdma_queue_id =
  971. q->sdma_id / get_num_sdma_engines(dqm);
  972. q->properties.sdma_engine_id =
  973. q->sdma_id % get_num_sdma_engines(dqm);
  974. }
  975. retval = allocate_doorbell(qpd, q);
  976. if (retval)
  977. goto out_deallocate_sdma_queue;
  978. mqd_mgr = dqm->ops.get_mqd_manager(dqm,
  979. get_mqd_type_from_queue_type(q->properties.type));
  980. if (!mqd_mgr) {
  981. retval = -ENOMEM;
  982. goto out_deallocate_doorbell;
  983. }
  984. /*
  985. * Eviction state logic: we only mark active queues as evicted
  986. * to avoid the overhead of restoring inactive queues later
  987. */
  988. if (qpd->evicted)
  989. q->properties.is_evicted = (q->properties.queue_size > 0 &&
  990. q->properties.queue_percent > 0 &&
  991. q->properties.queue_address != 0);
  992. dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
  993. q->properties.tba_addr = qpd->tba_addr;
  994. q->properties.tma_addr = qpd->tma_addr;
  995. retval = mqd_mgr->init_mqd(mqd_mgr, &q->mqd, &q->mqd_mem_obj,
  996. &q->gart_mqd_addr, &q->properties);
  997. if (retval)
  998. goto out_deallocate_doorbell;
  999. list_add(&q->list, &qpd->queues_list);
  1000. qpd->queue_count++;
  1001. if (q->properties.is_active) {
  1002. dqm->queue_count++;
  1003. retval = execute_queues_cpsch(dqm,
  1004. KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
  1005. }
  1006. if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
  1007. dqm->sdma_queue_count++;
  1008. /*
  1009. * Unconditionally increment this counter, regardless of the queue's
  1010. * type or whether the queue is active.
  1011. */
  1012. dqm->total_queue_count++;
  1013. pr_debug("Total of %d queues are accountable so far\n",
  1014. dqm->total_queue_count);
  1015. dqm_unlock(dqm);
  1016. return retval;
  1017. out_deallocate_doorbell:
  1018. deallocate_doorbell(qpd, q);
  1019. out_deallocate_sdma_queue:
  1020. if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
  1021. deallocate_sdma_queue(dqm, q->sdma_id);
  1022. out_unlock:
  1023. dqm_unlock(dqm);
  1024. return retval;
  1025. }
  1026. int amdkfd_fence_wait_timeout(unsigned int *fence_addr,
  1027. unsigned int fence_value,
  1028. unsigned int timeout_ms)
  1029. {
  1030. unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies;
  1031. while (*fence_addr != fence_value) {
  1032. if (time_after(jiffies, end_jiffies)) {
  1033. pr_err("qcm fence wait loop timeout expired\n");
  1034. /* In HWS case, this is used to halt the driver thread
  1035. * in order not to mess up CP states before doing
  1036. * scandumps for FW debugging.
  1037. */
  1038. while (halt_if_hws_hang)
  1039. schedule();
  1040. return -ETIME;
  1041. }
  1042. schedule();
  1043. }
  1044. return 0;
  1045. }
  1046. static int unmap_sdma_queues(struct device_queue_manager *dqm,
  1047. unsigned int sdma_engine)
  1048. {
  1049. return pm_send_unmap_queue(&dqm->packets, KFD_QUEUE_TYPE_SDMA,
  1050. KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, false,
  1051. sdma_engine);
  1052. }
  1053. /* dqm->lock mutex has to be locked before calling this function */
  1054. static int map_queues_cpsch(struct device_queue_manager *dqm)
  1055. {
  1056. int retval;
  1057. if (dqm->queue_count <= 0 || dqm->processes_count <= 0)
  1058. return 0;
  1059. if (dqm->active_runlist)
  1060. return 0;
  1061. retval = pm_send_runlist(&dqm->packets, &dqm->queues);
  1062. if (retval) {
  1063. pr_err("failed to execute runlist\n");
  1064. return retval;
  1065. }
  1066. dqm->active_runlist = true;
  1067. return retval;
  1068. }
  1069. /* dqm->lock mutex has to be locked before calling this function */
  1070. static int unmap_queues_cpsch(struct device_queue_manager *dqm,
  1071. enum kfd_unmap_queues_filter filter,
  1072. uint32_t filter_param)
  1073. {
  1074. int retval = 0;
  1075. if (dqm->is_hws_hang)
  1076. return -EIO;
  1077. if (!dqm->active_runlist)
  1078. return retval;
  1079. pr_debug("Before destroying queues, sdma queue count is : %u\n",
  1080. dqm->sdma_queue_count);
  1081. if (dqm->sdma_queue_count > 0) {
  1082. unmap_sdma_queues(dqm, 0);
  1083. unmap_sdma_queues(dqm, 1);
  1084. }
  1085. retval = pm_send_unmap_queue(&dqm->packets, KFD_QUEUE_TYPE_COMPUTE,
  1086. filter, filter_param, false, 0);
  1087. if (retval)
  1088. return retval;
  1089. *dqm->fence_addr = KFD_FENCE_INIT;
  1090. pm_send_query_status(&dqm->packets, dqm->fence_gpu_addr,
  1091. KFD_FENCE_COMPLETED);
  1092. /* should be timed out */
  1093. retval = amdkfd_fence_wait_timeout(dqm->fence_addr, KFD_FENCE_COMPLETED,
  1094. QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS);
  1095. if (retval)
  1096. return retval;
  1097. pm_release_ib(&dqm->packets);
  1098. dqm->active_runlist = false;
  1099. return retval;
  1100. }
  1101. /* dqm->lock mutex has to be locked before calling this function */
  1102. static int execute_queues_cpsch(struct device_queue_manager *dqm,
  1103. enum kfd_unmap_queues_filter filter,
  1104. uint32_t filter_param)
  1105. {
  1106. int retval;
  1107. if (dqm->is_hws_hang)
  1108. return -EIO;
  1109. retval = unmap_queues_cpsch(dqm, filter, filter_param);
  1110. if (retval) {
  1111. pr_err("The cp might be in an unrecoverable state due to an unsuccessful queues preemption\n");
  1112. dqm->is_hws_hang = true;
  1113. schedule_work(&dqm->hw_exception_work);
  1114. return retval;
  1115. }
  1116. return map_queues_cpsch(dqm);
  1117. }
  1118. static int destroy_queue_cpsch(struct device_queue_manager *dqm,
  1119. struct qcm_process_device *qpd,
  1120. struct queue *q)
  1121. {
  1122. int retval;
  1123. struct mqd_manager *mqd_mgr;
  1124. retval = 0;
  1125. /* remove queue from list to prevent rescheduling after preemption */
  1126. dqm_lock(dqm);
  1127. if (qpd->is_debug) {
  1128. /*
  1129. * error, currently we do not allow to destroy a queue
  1130. * of a currently debugged process
  1131. */
  1132. retval = -EBUSY;
  1133. goto failed_try_destroy_debugged_queue;
  1134. }
  1135. mqd_mgr = dqm->ops.get_mqd_manager(dqm,
  1136. get_mqd_type_from_queue_type(q->properties.type));
  1137. if (!mqd_mgr) {
  1138. retval = -ENOMEM;
  1139. goto failed;
  1140. }
  1141. deallocate_doorbell(qpd, q);
  1142. if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
  1143. dqm->sdma_queue_count--;
  1144. deallocate_sdma_queue(dqm, q->sdma_id);
  1145. }
  1146. list_del(&q->list);
  1147. qpd->queue_count--;
  1148. if (q->properties.is_active) {
  1149. dqm->queue_count--;
  1150. retval = execute_queues_cpsch(dqm,
  1151. KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
  1152. if (retval == -ETIME)
  1153. qpd->reset_wavefronts = true;
  1154. }
  1155. mqd_mgr->uninit_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
  1156. /*
  1157. * Unconditionally decrement this counter, regardless of the queue's
  1158. * type
  1159. */
  1160. dqm->total_queue_count--;
  1161. pr_debug("Total of %d queues are accountable so far\n",
  1162. dqm->total_queue_count);
  1163. dqm_unlock(dqm);
  1164. return retval;
  1165. failed:
  1166. failed_try_destroy_debugged_queue:
  1167. dqm_unlock(dqm);
  1168. return retval;
  1169. }
  1170. /*
  1171. * Low bits must be 0000/FFFF as required by HW, high bits must be 0 to
  1172. * stay in user mode.
  1173. */
  1174. #define APE1_FIXED_BITS_MASK 0xFFFF80000000FFFFULL
  1175. /* APE1 limit is inclusive and 64K aligned. */
  1176. #define APE1_LIMIT_ALIGNMENT 0xFFFF
  1177. static bool set_cache_memory_policy(struct device_queue_manager *dqm,
  1178. struct qcm_process_device *qpd,
  1179. enum cache_policy default_policy,
  1180. enum cache_policy alternate_policy,
  1181. void __user *alternate_aperture_base,
  1182. uint64_t alternate_aperture_size)
  1183. {
  1184. bool retval = true;
  1185. if (!dqm->asic_ops.set_cache_memory_policy)
  1186. return retval;
  1187. dqm_lock(dqm);
  1188. if (alternate_aperture_size == 0) {
  1189. /* base > limit disables APE1 */
  1190. qpd->sh_mem_ape1_base = 1;
  1191. qpd->sh_mem_ape1_limit = 0;
  1192. } else {
  1193. /*
  1194. * In FSA64, APE1_Base[63:0] = { 16{SH_MEM_APE1_BASE[31]},
  1195. * SH_MEM_APE1_BASE[31:0], 0x0000 }
  1196. * APE1_Limit[63:0] = { 16{SH_MEM_APE1_LIMIT[31]},
  1197. * SH_MEM_APE1_LIMIT[31:0], 0xFFFF }
  1198. * Verify that the base and size parameters can be
  1199. * represented in this format and convert them.
  1200. * Additionally restrict APE1 to user-mode addresses.
  1201. */
  1202. uint64_t base = (uintptr_t)alternate_aperture_base;
  1203. uint64_t limit = base + alternate_aperture_size - 1;
  1204. if (limit <= base || (base & APE1_FIXED_BITS_MASK) != 0 ||
  1205. (limit & APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) {
  1206. retval = false;
  1207. goto out;
  1208. }
  1209. qpd->sh_mem_ape1_base = base >> 16;
  1210. qpd->sh_mem_ape1_limit = limit >> 16;
  1211. }
  1212. retval = dqm->asic_ops.set_cache_memory_policy(
  1213. dqm,
  1214. qpd,
  1215. default_policy,
  1216. alternate_policy,
  1217. alternate_aperture_base,
  1218. alternate_aperture_size);
  1219. if ((dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) && (qpd->vmid != 0))
  1220. program_sh_mem_settings(dqm, qpd);
  1221. pr_debug("sh_mem_config: 0x%x, ape1_base: 0x%x, ape1_limit: 0x%x\n",
  1222. qpd->sh_mem_config, qpd->sh_mem_ape1_base,
  1223. qpd->sh_mem_ape1_limit);
  1224. out:
  1225. dqm_unlock(dqm);
  1226. return retval;
  1227. }
  1228. static int set_trap_handler(struct device_queue_manager *dqm,
  1229. struct qcm_process_device *qpd,
  1230. uint64_t tba_addr,
  1231. uint64_t tma_addr)
  1232. {
  1233. uint64_t *tma;
  1234. if (dqm->dev->cwsr_enabled) {
  1235. /* Jump from CWSR trap handler to user trap */
  1236. tma = (uint64_t *)(qpd->cwsr_kaddr + KFD_CWSR_TMA_OFFSET);
  1237. tma[0] = tba_addr;
  1238. tma[1] = tma_addr;
  1239. } else {
  1240. qpd->tba_addr = tba_addr;
  1241. qpd->tma_addr = tma_addr;
  1242. }
  1243. return 0;
  1244. }
  1245. static int process_termination_nocpsch(struct device_queue_manager *dqm,
  1246. struct qcm_process_device *qpd)
  1247. {
  1248. struct queue *q, *next;
  1249. struct device_process_node *cur, *next_dpn;
  1250. int retval = 0;
  1251. dqm_lock(dqm);
  1252. /* Clear all user mode queues */
  1253. list_for_each_entry_safe(q, next, &qpd->queues_list, list) {
  1254. int ret;
  1255. ret = destroy_queue_nocpsch_locked(dqm, qpd, q);
  1256. if (ret)
  1257. retval = ret;
  1258. }
  1259. /* Unregister process */
  1260. list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
  1261. if (qpd == cur->qpd) {
  1262. list_del(&cur->list);
  1263. kfree(cur);
  1264. dqm->processes_count--;
  1265. break;
  1266. }
  1267. }
  1268. dqm_unlock(dqm);
  1269. return retval;
  1270. }
  1271. static int get_wave_state(struct device_queue_manager *dqm,
  1272. struct queue *q,
  1273. void __user *ctl_stack,
  1274. u32 *ctl_stack_used_size,
  1275. u32 *save_area_used_size)
  1276. {
  1277. struct mqd_manager *mqd;
  1278. int r;
  1279. dqm_lock(dqm);
  1280. if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE ||
  1281. q->properties.is_active || !q->device->cwsr_enabled) {
  1282. r = -EINVAL;
  1283. goto dqm_unlock;
  1284. }
  1285. mqd = dqm->ops.get_mqd_manager(dqm, KFD_MQD_TYPE_COMPUTE);
  1286. if (!mqd) {
  1287. r = -ENOMEM;
  1288. goto dqm_unlock;
  1289. }
  1290. if (!mqd->get_wave_state) {
  1291. r = -EINVAL;
  1292. goto dqm_unlock;
  1293. }
  1294. r = mqd->get_wave_state(mqd, q->mqd, ctl_stack, ctl_stack_used_size,
  1295. save_area_used_size);
  1296. dqm_unlock:
  1297. dqm_unlock(dqm);
  1298. return r;
  1299. }
  1300. static int process_termination_cpsch(struct device_queue_manager *dqm,
  1301. struct qcm_process_device *qpd)
  1302. {
  1303. int retval;
  1304. struct queue *q, *next;
  1305. struct kernel_queue *kq, *kq_next;
  1306. struct mqd_manager *mqd_mgr;
  1307. struct device_process_node *cur, *next_dpn;
  1308. enum kfd_unmap_queues_filter filter =
  1309. KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES;
  1310. retval = 0;
  1311. dqm_lock(dqm);
  1312. /* Clean all kernel queues */
  1313. list_for_each_entry_safe(kq, kq_next, &qpd->priv_queue_list, list) {
  1314. list_del(&kq->list);
  1315. dqm->queue_count--;
  1316. qpd->is_debug = false;
  1317. dqm->total_queue_count--;
  1318. filter = KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES;
  1319. }
  1320. /* Clear all user mode queues */
  1321. list_for_each_entry(q, &qpd->queues_list, list) {
  1322. if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
  1323. dqm->sdma_queue_count--;
  1324. deallocate_sdma_queue(dqm, q->sdma_id);
  1325. }
  1326. if (q->properties.is_active)
  1327. dqm->queue_count--;
  1328. dqm->total_queue_count--;
  1329. }
  1330. /* Unregister process */
  1331. list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
  1332. if (qpd == cur->qpd) {
  1333. list_del(&cur->list);
  1334. kfree(cur);
  1335. dqm->processes_count--;
  1336. break;
  1337. }
  1338. }
  1339. retval = execute_queues_cpsch(dqm, filter, 0);
  1340. if ((!dqm->is_hws_hang) && (retval || qpd->reset_wavefronts)) {
  1341. pr_warn("Resetting wave fronts (cpsch) on dev %p\n", dqm->dev);
  1342. dbgdev_wave_reset_wavefronts(dqm->dev, qpd->pqm->process);
  1343. qpd->reset_wavefronts = false;
  1344. }
  1345. /* lastly, free mqd resources */
  1346. list_for_each_entry_safe(q, next, &qpd->queues_list, list) {
  1347. mqd_mgr = dqm->ops.get_mqd_manager(dqm,
  1348. get_mqd_type_from_queue_type(q->properties.type));
  1349. if (!mqd_mgr) {
  1350. retval = -ENOMEM;
  1351. goto out;
  1352. }
  1353. list_del(&q->list);
  1354. qpd->queue_count--;
  1355. mqd_mgr->uninit_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
  1356. }
  1357. out:
  1358. dqm_unlock(dqm);
  1359. return retval;
  1360. }
  1361. struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
  1362. {
  1363. struct device_queue_manager *dqm;
  1364. pr_debug("Loading device queue manager\n");
  1365. dqm = kzalloc(sizeof(*dqm), GFP_KERNEL);
  1366. if (!dqm)
  1367. return NULL;
  1368. switch (dev->device_info->asic_family) {
  1369. /* HWS is not available on Hawaii. */
  1370. case CHIP_HAWAII:
  1371. /* HWS depends on CWSR for timely dequeue. CWSR is not
  1372. * available on Tonga.
  1373. *
  1374. * FIXME: This argument also applies to Kaveri.
  1375. */
  1376. case CHIP_TONGA:
  1377. dqm->sched_policy = KFD_SCHED_POLICY_NO_HWS;
  1378. break;
  1379. default:
  1380. dqm->sched_policy = sched_policy;
  1381. break;
  1382. }
  1383. dqm->dev = dev;
  1384. switch (dqm->sched_policy) {
  1385. case KFD_SCHED_POLICY_HWS:
  1386. case KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION:
  1387. /* initialize dqm for cp scheduling */
  1388. dqm->ops.create_queue = create_queue_cpsch;
  1389. dqm->ops.initialize = initialize_cpsch;
  1390. dqm->ops.start = start_cpsch;
  1391. dqm->ops.stop = stop_cpsch;
  1392. dqm->ops.destroy_queue = destroy_queue_cpsch;
  1393. dqm->ops.update_queue = update_queue;
  1394. dqm->ops.get_mqd_manager = get_mqd_manager;
  1395. dqm->ops.register_process = register_process;
  1396. dqm->ops.unregister_process = unregister_process;
  1397. dqm->ops.uninitialize = uninitialize;
  1398. dqm->ops.create_kernel_queue = create_kernel_queue_cpsch;
  1399. dqm->ops.destroy_kernel_queue = destroy_kernel_queue_cpsch;
  1400. dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
  1401. dqm->ops.set_trap_handler = set_trap_handler;
  1402. dqm->ops.process_termination = process_termination_cpsch;
  1403. dqm->ops.evict_process_queues = evict_process_queues_cpsch;
  1404. dqm->ops.restore_process_queues = restore_process_queues_cpsch;
  1405. dqm->ops.get_wave_state = get_wave_state;
  1406. break;
  1407. case KFD_SCHED_POLICY_NO_HWS:
  1408. /* initialize dqm for no cp scheduling */
  1409. dqm->ops.start = start_nocpsch;
  1410. dqm->ops.stop = stop_nocpsch;
  1411. dqm->ops.create_queue = create_queue_nocpsch;
  1412. dqm->ops.destroy_queue = destroy_queue_nocpsch;
  1413. dqm->ops.update_queue = update_queue;
  1414. dqm->ops.get_mqd_manager = get_mqd_manager;
  1415. dqm->ops.register_process = register_process;
  1416. dqm->ops.unregister_process = unregister_process;
  1417. dqm->ops.initialize = initialize_nocpsch;
  1418. dqm->ops.uninitialize = uninitialize;
  1419. dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
  1420. dqm->ops.set_trap_handler = set_trap_handler;
  1421. dqm->ops.process_termination = process_termination_nocpsch;
  1422. dqm->ops.evict_process_queues = evict_process_queues_nocpsch;
  1423. dqm->ops.restore_process_queues =
  1424. restore_process_queues_nocpsch;
  1425. dqm->ops.get_wave_state = get_wave_state;
  1426. break;
  1427. default:
  1428. pr_err("Invalid scheduling policy %d\n", dqm->sched_policy);
  1429. goto out_free;
  1430. }
  1431. switch (dev->device_info->asic_family) {
  1432. case CHIP_CARRIZO:
  1433. device_queue_manager_init_vi(&dqm->asic_ops);
  1434. break;
  1435. case CHIP_KAVERI:
  1436. device_queue_manager_init_cik(&dqm->asic_ops);
  1437. break;
  1438. case CHIP_HAWAII:
  1439. device_queue_manager_init_cik_hawaii(&dqm->asic_ops);
  1440. break;
  1441. case CHIP_TONGA:
  1442. case CHIP_FIJI:
  1443. case CHIP_POLARIS10:
  1444. case CHIP_POLARIS11:
  1445. device_queue_manager_init_vi_tonga(&dqm->asic_ops);
  1446. break;
  1447. case CHIP_VEGA10:
  1448. case CHIP_VEGA20:
  1449. case CHIP_RAVEN:
  1450. device_queue_manager_init_v9(&dqm->asic_ops);
  1451. break;
  1452. default:
  1453. WARN(1, "Unexpected ASIC family %u",
  1454. dev->device_info->asic_family);
  1455. goto out_free;
  1456. }
  1457. if (!dqm->ops.initialize(dqm))
  1458. return dqm;
  1459. out_free:
  1460. kfree(dqm);
  1461. return NULL;
  1462. }
  1463. void device_queue_manager_uninit(struct device_queue_manager *dqm)
  1464. {
  1465. dqm->ops.uninitialize(dqm);
  1466. kfree(dqm);
  1467. }
  1468. int kfd_process_vm_fault(struct device_queue_manager *dqm,
  1469. unsigned int pasid)
  1470. {
  1471. struct kfd_process_device *pdd;
  1472. struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);
  1473. int ret = 0;
  1474. if (!p)
  1475. return -EINVAL;
  1476. pdd = kfd_get_process_device_data(dqm->dev, p);
  1477. if (pdd)
  1478. ret = dqm->ops.evict_process_queues(dqm, &pdd->qpd);
  1479. kfd_unref_process(p);
  1480. return ret;
  1481. }
  1482. static void kfd_process_hw_exception(struct work_struct *work)
  1483. {
  1484. struct device_queue_manager *dqm = container_of(work,
  1485. struct device_queue_manager, hw_exception_work);
  1486. dqm->dev->kfd2kgd->gpu_recover(dqm->dev->kgd);
  1487. }
  1488. #if defined(CONFIG_DEBUG_FS)
  1489. static void seq_reg_dump(struct seq_file *m,
  1490. uint32_t (*dump)[2], uint32_t n_regs)
  1491. {
  1492. uint32_t i, count;
  1493. for (i = 0, count = 0; i < n_regs; i++) {
  1494. if (count == 0 ||
  1495. dump[i-1][0] + sizeof(uint32_t) != dump[i][0]) {
  1496. seq_printf(m, "%s %08x: %08x",
  1497. i ? "\n" : "",
  1498. dump[i][0], dump[i][1]);
  1499. count = 7;
  1500. } else {
  1501. seq_printf(m, " %08x", dump[i][1]);
  1502. count--;
  1503. }
  1504. }
  1505. seq_puts(m, "\n");
  1506. }
  1507. int dqm_debugfs_hqds(struct seq_file *m, void *data)
  1508. {
  1509. struct device_queue_manager *dqm = data;
  1510. uint32_t (*dump)[2], n_regs;
  1511. int pipe, queue;
  1512. int r = 0;
  1513. r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->kgd,
  1514. KFD_CIK_HIQ_PIPE, KFD_CIK_HIQ_QUEUE, &dump, &n_regs);
  1515. if (!r) {
  1516. seq_printf(m, " HIQ on MEC %d Pipe %d Queue %d\n",
  1517. KFD_CIK_HIQ_PIPE/get_pipes_per_mec(dqm)+1,
  1518. KFD_CIK_HIQ_PIPE%get_pipes_per_mec(dqm),
  1519. KFD_CIK_HIQ_QUEUE);
  1520. seq_reg_dump(m, dump, n_regs);
  1521. kfree(dump);
  1522. }
  1523. for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
  1524. int pipe_offset = pipe * get_queues_per_pipe(dqm);
  1525. for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) {
  1526. if (!test_bit(pipe_offset + queue,
  1527. dqm->dev->shared_resources.queue_bitmap))
  1528. continue;
  1529. r = dqm->dev->kfd2kgd->hqd_dump(
  1530. dqm->dev->kgd, pipe, queue, &dump, &n_regs);
  1531. if (r)
  1532. break;
  1533. seq_printf(m, " CP Pipe %d, Queue %d\n",
  1534. pipe, queue);
  1535. seq_reg_dump(m, dump, n_regs);
  1536. kfree(dump);
  1537. }
  1538. }
  1539. for (pipe = 0; pipe < get_num_sdma_engines(dqm); pipe++) {
  1540. for (queue = 0;
  1541. queue < dqm->dev->device_info->num_sdma_queues_per_engine;
  1542. queue++) {
  1543. r = dqm->dev->kfd2kgd->hqd_sdma_dump(
  1544. dqm->dev->kgd, pipe, queue, &dump, &n_regs);
  1545. if (r)
  1546. break;
  1547. seq_printf(m, " SDMA Engine %d, RLC %d\n",
  1548. pipe, queue);
  1549. seq_reg_dump(m, dump, n_regs);
  1550. kfree(dump);
  1551. }
  1552. }
  1553. return r;
  1554. }
  1555. int dqm_debugfs_execute_queues(struct device_queue_manager *dqm)
  1556. {
  1557. int r = 0;
  1558. dqm_lock(dqm);
  1559. dqm->active_runlist = true;
  1560. r = execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
  1561. dqm_unlock(dqm);
  1562. return r;
  1563. }
  1564. #endif