cc_buffer_mgr.c 49 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* Copyright (C) 2012-2018 ARM Limited or its affiliates. */
  3. #include <crypto/internal/aead.h>
  4. #include <crypto/authenc.h>
  5. #include <crypto/scatterwalk.h>
  6. #include <linux/dmapool.h>
  7. #include <linux/dma-mapping.h>
  8. #include "cc_buffer_mgr.h"
  9. #include "cc_lli_defs.h"
  10. #include "cc_cipher.h"
  11. #include "cc_hash.h"
  12. #include "cc_aead.h"
  13. enum dma_buffer_type {
  14. DMA_NULL_TYPE = -1,
  15. DMA_SGL_TYPE = 1,
  16. DMA_BUFF_TYPE = 2,
  17. };
  18. struct buff_mgr_handle {
  19. struct dma_pool *mlli_buffs_pool;
  20. };
  21. union buffer_array_entry {
  22. struct scatterlist *sgl;
  23. dma_addr_t buffer_dma;
  24. };
  25. struct buffer_array {
  26. unsigned int num_of_buffers;
  27. union buffer_array_entry entry[MAX_NUM_OF_BUFFERS_IN_MLLI];
  28. unsigned int offset[MAX_NUM_OF_BUFFERS_IN_MLLI];
  29. int nents[MAX_NUM_OF_BUFFERS_IN_MLLI];
  30. int total_data_len[MAX_NUM_OF_BUFFERS_IN_MLLI];
  31. enum dma_buffer_type type[MAX_NUM_OF_BUFFERS_IN_MLLI];
  32. bool is_last[MAX_NUM_OF_BUFFERS_IN_MLLI];
  33. u32 *mlli_nents[MAX_NUM_OF_BUFFERS_IN_MLLI];
  34. };
  35. static inline char *cc_dma_buf_type(enum cc_req_dma_buf_type type)
  36. {
  37. switch (type) {
  38. case CC_DMA_BUF_NULL:
  39. return "BUF_NULL";
  40. case CC_DMA_BUF_DLLI:
  41. return "BUF_DLLI";
  42. case CC_DMA_BUF_MLLI:
  43. return "BUF_MLLI";
  44. default:
  45. return "BUF_INVALID";
  46. }
  47. }
  48. /**
  49. * cc_copy_mac() - Copy MAC to temporary location
  50. *
  51. * @dev: device object
  52. * @req: aead request object
  53. * @dir: [IN] copy from/to sgl
  54. */
  55. static void cc_copy_mac(struct device *dev, struct aead_request *req,
  56. enum cc_sg_cpy_direct dir)
  57. {
  58. struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
  59. struct crypto_aead *tfm = crypto_aead_reqtfm(req);
  60. u32 skip = req->assoclen + req->cryptlen;
  61. if (areq_ctx->is_gcm4543)
  62. skip += crypto_aead_ivsize(tfm);
  63. cc_copy_sg_portion(dev, areq_ctx->backup_mac, req->src,
  64. (skip - areq_ctx->req_authsize), skip, dir);
  65. }
  66. /**
  67. * cc_get_sgl_nents() - Get scatterlist number of entries.
  68. *
  69. * @sg_list: SG list
  70. * @nbytes: [IN] Total SGL data bytes.
  71. * @lbytes: [OUT] Returns the amount of bytes at the last entry
  72. */
  73. static unsigned int cc_get_sgl_nents(struct device *dev,
  74. struct scatterlist *sg_list,
  75. unsigned int nbytes, u32 *lbytes,
  76. bool *is_chained)
  77. {
  78. unsigned int nents = 0;
  79. while (nbytes && sg_list) {
  80. if (sg_list->length) {
  81. nents++;
  82. /* get the number of bytes in the last entry */
  83. *lbytes = nbytes;
  84. nbytes -= (sg_list->length > nbytes) ?
  85. nbytes : sg_list->length;
  86. sg_list = sg_next(sg_list);
  87. } else {
  88. sg_list = (struct scatterlist *)sg_page(sg_list);
  89. if (is_chained)
  90. *is_chained = true;
  91. }
  92. }
  93. dev_dbg(dev, "nents %d last bytes %d\n", nents, *lbytes);
  94. return nents;
  95. }
  96. /**
  97. * cc_zero_sgl() - Zero scatter scatter list data.
  98. *
  99. * @sgl:
  100. */
  101. void cc_zero_sgl(struct scatterlist *sgl, u32 data_len)
  102. {
  103. struct scatterlist *current_sg = sgl;
  104. int sg_index = 0;
  105. while (sg_index <= data_len) {
  106. if (!current_sg) {
  107. /* reached the end of the sgl --> just return back */
  108. return;
  109. }
  110. memset(sg_virt(current_sg), 0, current_sg->length);
  111. sg_index += current_sg->length;
  112. current_sg = sg_next(current_sg);
  113. }
  114. }
  115. /**
  116. * cc_copy_sg_portion() - Copy scatter list data,
  117. * from to_skip to end, to dest and vice versa
  118. *
  119. * @dest:
  120. * @sg:
  121. * @to_skip:
  122. * @end:
  123. * @direct:
  124. */
  125. void cc_copy_sg_portion(struct device *dev, u8 *dest, struct scatterlist *sg,
  126. u32 to_skip, u32 end, enum cc_sg_cpy_direct direct)
  127. {
  128. u32 nents, lbytes;
  129. nents = cc_get_sgl_nents(dev, sg, end, &lbytes, NULL);
  130. sg_copy_buffer(sg, nents, (void *)dest, (end - to_skip + 1), to_skip,
  131. (direct == CC_SG_TO_BUF));
  132. }
  133. static int cc_render_buff_to_mlli(struct device *dev, dma_addr_t buff_dma,
  134. u32 buff_size, u32 *curr_nents,
  135. u32 **mlli_entry_pp)
  136. {
  137. u32 *mlli_entry_p = *mlli_entry_pp;
  138. u32 new_nents;
  139. /* Verify there is no memory overflow*/
  140. new_nents = (*curr_nents + buff_size / CC_MAX_MLLI_ENTRY_SIZE + 1);
  141. if (new_nents > MAX_NUM_OF_TOTAL_MLLI_ENTRIES)
  142. return -ENOMEM;
  143. /*handle buffer longer than 64 kbytes */
  144. while (buff_size > CC_MAX_MLLI_ENTRY_SIZE) {
  145. cc_lli_set_addr(mlli_entry_p, buff_dma);
  146. cc_lli_set_size(mlli_entry_p, CC_MAX_MLLI_ENTRY_SIZE);
  147. dev_dbg(dev, "entry[%d]: single_buff=0x%08X size=%08X\n",
  148. *curr_nents, mlli_entry_p[LLI_WORD0_OFFSET],
  149. mlli_entry_p[LLI_WORD1_OFFSET]);
  150. buff_dma += CC_MAX_MLLI_ENTRY_SIZE;
  151. buff_size -= CC_MAX_MLLI_ENTRY_SIZE;
  152. mlli_entry_p = mlli_entry_p + 2;
  153. (*curr_nents)++;
  154. }
  155. /*Last entry */
  156. cc_lli_set_addr(mlli_entry_p, buff_dma);
  157. cc_lli_set_size(mlli_entry_p, buff_size);
  158. dev_dbg(dev, "entry[%d]: single_buff=0x%08X size=%08X\n",
  159. *curr_nents, mlli_entry_p[LLI_WORD0_OFFSET],
  160. mlli_entry_p[LLI_WORD1_OFFSET]);
  161. mlli_entry_p = mlli_entry_p + 2;
  162. *mlli_entry_pp = mlli_entry_p;
  163. (*curr_nents)++;
  164. return 0;
  165. }
  166. static int cc_render_sg_to_mlli(struct device *dev, struct scatterlist *sgl,
  167. u32 sgl_data_len, u32 sgl_offset,
  168. u32 *curr_nents, u32 **mlli_entry_pp)
  169. {
  170. struct scatterlist *curr_sgl = sgl;
  171. u32 *mlli_entry_p = *mlli_entry_pp;
  172. s32 rc = 0;
  173. for ( ; (curr_sgl && sgl_data_len);
  174. curr_sgl = sg_next(curr_sgl)) {
  175. u32 entry_data_len =
  176. (sgl_data_len > sg_dma_len(curr_sgl) - sgl_offset) ?
  177. sg_dma_len(curr_sgl) - sgl_offset :
  178. sgl_data_len;
  179. sgl_data_len -= entry_data_len;
  180. rc = cc_render_buff_to_mlli(dev, sg_dma_address(curr_sgl) +
  181. sgl_offset, entry_data_len,
  182. curr_nents, &mlli_entry_p);
  183. if (rc)
  184. return rc;
  185. sgl_offset = 0;
  186. }
  187. *mlli_entry_pp = mlli_entry_p;
  188. return 0;
  189. }
  190. static int cc_generate_mlli(struct device *dev, struct buffer_array *sg_data,
  191. struct mlli_params *mlli_params, gfp_t flags)
  192. {
  193. u32 *mlli_p;
  194. u32 total_nents = 0, prev_total_nents = 0;
  195. int rc = 0, i;
  196. dev_dbg(dev, "NUM of SG's = %d\n", sg_data->num_of_buffers);
  197. /* Allocate memory from the pointed pool */
  198. mlli_params->mlli_virt_addr =
  199. dma_pool_alloc(mlli_params->curr_pool, flags,
  200. &mlli_params->mlli_dma_addr);
  201. if (!mlli_params->mlli_virt_addr) {
  202. dev_err(dev, "dma_pool_alloc() failed\n");
  203. rc = -ENOMEM;
  204. goto build_mlli_exit;
  205. }
  206. /* Point to start of MLLI */
  207. mlli_p = (u32 *)mlli_params->mlli_virt_addr;
  208. /* go over all SG's and link it to one MLLI table */
  209. for (i = 0; i < sg_data->num_of_buffers; i++) {
  210. union buffer_array_entry *entry = &sg_data->entry[i];
  211. u32 tot_len = sg_data->total_data_len[i];
  212. u32 offset = sg_data->offset[i];
  213. if (sg_data->type[i] == DMA_SGL_TYPE)
  214. rc = cc_render_sg_to_mlli(dev, entry->sgl, tot_len,
  215. offset, &total_nents,
  216. &mlli_p);
  217. else /*DMA_BUFF_TYPE*/
  218. rc = cc_render_buff_to_mlli(dev, entry->buffer_dma,
  219. tot_len, &total_nents,
  220. &mlli_p);
  221. if (rc)
  222. return rc;
  223. /* set last bit in the current table */
  224. if (sg_data->mlli_nents[i]) {
  225. /*Calculate the current MLLI table length for the
  226. *length field in the descriptor
  227. */
  228. *sg_data->mlli_nents[i] +=
  229. (total_nents - prev_total_nents);
  230. prev_total_nents = total_nents;
  231. }
  232. }
  233. /* Set MLLI size for the bypass operation */
  234. mlli_params->mlli_len = (total_nents * LLI_ENTRY_BYTE_SIZE);
  235. dev_dbg(dev, "MLLI params: virt_addr=%pK dma_addr=%pad mlli_len=0x%X\n",
  236. mlli_params->mlli_virt_addr, &mlli_params->mlli_dma_addr,
  237. mlli_params->mlli_len);
  238. build_mlli_exit:
  239. return rc;
  240. }
  241. static void cc_add_buffer_entry(struct device *dev,
  242. struct buffer_array *sgl_data,
  243. dma_addr_t buffer_dma, unsigned int buffer_len,
  244. bool is_last_entry, u32 *mlli_nents)
  245. {
  246. unsigned int index = sgl_data->num_of_buffers;
  247. dev_dbg(dev, "index=%u single_buff=%pad buffer_len=0x%08X is_last=%d\n",
  248. index, &buffer_dma, buffer_len, is_last_entry);
  249. sgl_data->nents[index] = 1;
  250. sgl_data->entry[index].buffer_dma = buffer_dma;
  251. sgl_data->offset[index] = 0;
  252. sgl_data->total_data_len[index] = buffer_len;
  253. sgl_data->type[index] = DMA_BUFF_TYPE;
  254. sgl_data->is_last[index] = is_last_entry;
  255. sgl_data->mlli_nents[index] = mlli_nents;
  256. if (sgl_data->mlli_nents[index])
  257. *sgl_data->mlli_nents[index] = 0;
  258. sgl_data->num_of_buffers++;
  259. }
  260. static void cc_add_sg_entry(struct device *dev, struct buffer_array *sgl_data,
  261. unsigned int nents, struct scatterlist *sgl,
  262. unsigned int data_len, unsigned int data_offset,
  263. bool is_last_table, u32 *mlli_nents)
  264. {
  265. unsigned int index = sgl_data->num_of_buffers;
  266. dev_dbg(dev, "index=%u nents=%u sgl=%pK data_len=0x%08X is_last=%d\n",
  267. index, nents, sgl, data_len, is_last_table);
  268. sgl_data->nents[index] = nents;
  269. sgl_data->entry[index].sgl = sgl;
  270. sgl_data->offset[index] = data_offset;
  271. sgl_data->total_data_len[index] = data_len;
  272. sgl_data->type[index] = DMA_SGL_TYPE;
  273. sgl_data->is_last[index] = is_last_table;
  274. sgl_data->mlli_nents[index] = mlli_nents;
  275. if (sgl_data->mlli_nents[index])
  276. *sgl_data->mlli_nents[index] = 0;
  277. sgl_data->num_of_buffers++;
  278. }
  279. static int cc_dma_map_sg(struct device *dev, struct scatterlist *sg, u32 nents,
  280. enum dma_data_direction direction)
  281. {
  282. u32 i, j;
  283. struct scatterlist *l_sg = sg;
  284. for (i = 0; i < nents; i++) {
  285. if (!l_sg)
  286. break;
  287. if (dma_map_sg(dev, l_sg, 1, direction) != 1) {
  288. dev_err(dev, "dma_map_page() sg buffer failed\n");
  289. goto err;
  290. }
  291. l_sg = sg_next(l_sg);
  292. }
  293. return nents;
  294. err:
  295. /* Restore mapped parts */
  296. for (j = 0; j < i; j++) {
  297. if (!sg)
  298. break;
  299. dma_unmap_sg(dev, sg, 1, direction);
  300. sg = sg_next(sg);
  301. }
  302. return 0;
  303. }
  304. static int cc_map_sg(struct device *dev, struct scatterlist *sg,
  305. unsigned int nbytes, int direction, u32 *nents,
  306. u32 max_sg_nents, u32 *lbytes, u32 *mapped_nents)
  307. {
  308. bool is_chained = false;
  309. if (sg_is_last(sg)) {
  310. /* One entry only case -set to DLLI */
  311. if (dma_map_sg(dev, sg, 1, direction) != 1) {
  312. dev_err(dev, "dma_map_sg() single buffer failed\n");
  313. return -ENOMEM;
  314. }
  315. dev_dbg(dev, "Mapped sg: dma_address=%pad page=%p addr=%pK offset=%u length=%u\n",
  316. &sg_dma_address(sg), sg_page(sg), sg_virt(sg),
  317. sg->offset, sg->length);
  318. *lbytes = nbytes;
  319. *nents = 1;
  320. *mapped_nents = 1;
  321. } else { /*sg_is_last*/
  322. *nents = cc_get_sgl_nents(dev, sg, nbytes, lbytes,
  323. &is_chained);
  324. if (*nents > max_sg_nents) {
  325. *nents = 0;
  326. dev_err(dev, "Too many fragments. current %d max %d\n",
  327. *nents, max_sg_nents);
  328. return -ENOMEM;
  329. }
  330. if (!is_chained) {
  331. /* In case of mmu the number of mapped nents might
  332. * be changed from the original sgl nents
  333. */
  334. *mapped_nents = dma_map_sg(dev, sg, *nents, direction);
  335. if (*mapped_nents == 0) {
  336. *nents = 0;
  337. dev_err(dev, "dma_map_sg() sg buffer failed\n");
  338. return -ENOMEM;
  339. }
  340. } else {
  341. /*In this case the driver maps entry by entry so it
  342. * must have the same nents before and after map
  343. */
  344. *mapped_nents = cc_dma_map_sg(dev, sg, *nents,
  345. direction);
  346. if (*mapped_nents != *nents) {
  347. *nents = *mapped_nents;
  348. dev_err(dev, "dma_map_sg() sg buffer failed\n");
  349. return -ENOMEM;
  350. }
  351. }
  352. }
  353. return 0;
  354. }
  355. static int
  356. cc_set_aead_conf_buf(struct device *dev, struct aead_req_ctx *areq_ctx,
  357. u8 *config_data, struct buffer_array *sg_data,
  358. unsigned int assoclen)
  359. {
  360. dev_dbg(dev, " handle additional data config set to DLLI\n");
  361. /* create sg for the current buffer */
  362. sg_init_one(&areq_ctx->ccm_adata_sg, config_data,
  363. AES_BLOCK_SIZE + areq_ctx->ccm_hdr_size);
  364. if (dma_map_sg(dev, &areq_ctx->ccm_adata_sg, 1, DMA_TO_DEVICE) != 1) {
  365. dev_err(dev, "dma_map_sg() config buffer failed\n");
  366. return -ENOMEM;
  367. }
  368. dev_dbg(dev, "Mapped curr_buff: dma_address=%pad page=%p addr=%pK offset=%u length=%u\n",
  369. &sg_dma_address(&areq_ctx->ccm_adata_sg),
  370. sg_page(&areq_ctx->ccm_adata_sg),
  371. sg_virt(&areq_ctx->ccm_adata_sg),
  372. areq_ctx->ccm_adata_sg.offset, areq_ctx->ccm_adata_sg.length);
  373. /* prepare for case of MLLI */
  374. if (assoclen > 0) {
  375. cc_add_sg_entry(dev, sg_data, 1, &areq_ctx->ccm_adata_sg,
  376. (AES_BLOCK_SIZE + areq_ctx->ccm_hdr_size),
  377. 0, false, NULL);
  378. }
  379. return 0;
  380. }
  381. static int cc_set_hash_buf(struct device *dev, struct ahash_req_ctx *areq_ctx,
  382. u8 *curr_buff, u32 curr_buff_cnt,
  383. struct buffer_array *sg_data)
  384. {
  385. dev_dbg(dev, " handle curr buff %x set to DLLI\n", curr_buff_cnt);
  386. /* create sg for the current buffer */
  387. sg_init_one(areq_ctx->buff_sg, curr_buff, curr_buff_cnt);
  388. if (dma_map_sg(dev, areq_ctx->buff_sg, 1, DMA_TO_DEVICE) != 1) {
  389. dev_err(dev, "dma_map_sg() src buffer failed\n");
  390. return -ENOMEM;
  391. }
  392. dev_dbg(dev, "Mapped curr_buff: dma_address=%pad page=%p addr=%pK offset=%u length=%u\n",
  393. &sg_dma_address(areq_ctx->buff_sg), sg_page(areq_ctx->buff_sg),
  394. sg_virt(areq_ctx->buff_sg), areq_ctx->buff_sg->offset,
  395. areq_ctx->buff_sg->length);
  396. areq_ctx->data_dma_buf_type = CC_DMA_BUF_DLLI;
  397. areq_ctx->curr_sg = areq_ctx->buff_sg;
  398. areq_ctx->in_nents = 0;
  399. /* prepare for case of MLLI */
  400. cc_add_sg_entry(dev, sg_data, 1, areq_ctx->buff_sg, curr_buff_cnt, 0,
  401. false, NULL);
  402. return 0;
  403. }
  404. void cc_unmap_cipher_request(struct device *dev, void *ctx,
  405. unsigned int ivsize, struct scatterlist *src,
  406. struct scatterlist *dst)
  407. {
  408. struct cipher_req_ctx *req_ctx = (struct cipher_req_ctx *)ctx;
  409. if (req_ctx->gen_ctx.iv_dma_addr) {
  410. dev_dbg(dev, "Unmapped iv: iv_dma_addr=%pad iv_size=%u\n",
  411. &req_ctx->gen_ctx.iv_dma_addr, ivsize);
  412. dma_unmap_single(dev, req_ctx->gen_ctx.iv_dma_addr,
  413. ivsize, DMA_TO_DEVICE);
  414. }
  415. /* Release pool */
  416. if (req_ctx->dma_buf_type == CC_DMA_BUF_MLLI &&
  417. req_ctx->mlli_params.mlli_virt_addr) {
  418. dma_pool_free(req_ctx->mlli_params.curr_pool,
  419. req_ctx->mlli_params.mlli_virt_addr,
  420. req_ctx->mlli_params.mlli_dma_addr);
  421. }
  422. dma_unmap_sg(dev, src, req_ctx->in_nents, DMA_BIDIRECTIONAL);
  423. dev_dbg(dev, "Unmapped req->src=%pK\n", sg_virt(src));
  424. if (src != dst) {
  425. dma_unmap_sg(dev, dst, req_ctx->out_nents, DMA_BIDIRECTIONAL);
  426. dev_dbg(dev, "Unmapped req->dst=%pK\n", sg_virt(dst));
  427. }
  428. }
  429. int cc_map_cipher_request(struct cc_drvdata *drvdata, void *ctx,
  430. unsigned int ivsize, unsigned int nbytes,
  431. void *info, struct scatterlist *src,
  432. struct scatterlist *dst, gfp_t flags)
  433. {
  434. struct cipher_req_ctx *req_ctx = (struct cipher_req_ctx *)ctx;
  435. struct mlli_params *mlli_params = &req_ctx->mlli_params;
  436. struct buff_mgr_handle *buff_mgr = drvdata->buff_mgr_handle;
  437. struct device *dev = drvdata_to_dev(drvdata);
  438. struct buffer_array sg_data;
  439. u32 dummy = 0;
  440. int rc = 0;
  441. u32 mapped_nents = 0;
  442. req_ctx->dma_buf_type = CC_DMA_BUF_DLLI;
  443. mlli_params->curr_pool = NULL;
  444. sg_data.num_of_buffers = 0;
  445. /* Map IV buffer */
  446. if (ivsize) {
  447. dump_byte_array("iv", (u8 *)info, ivsize);
  448. req_ctx->gen_ctx.iv_dma_addr =
  449. dma_map_single(dev, (void *)info,
  450. ivsize, DMA_TO_DEVICE);
  451. if (dma_mapping_error(dev, req_ctx->gen_ctx.iv_dma_addr)) {
  452. dev_err(dev, "Mapping iv %u B at va=%pK for DMA failed\n",
  453. ivsize, info);
  454. return -ENOMEM;
  455. }
  456. dev_dbg(dev, "Mapped iv %u B at va=%pK to dma=%pad\n",
  457. ivsize, info, &req_ctx->gen_ctx.iv_dma_addr);
  458. } else {
  459. req_ctx->gen_ctx.iv_dma_addr = 0;
  460. }
  461. /* Map the src SGL */
  462. rc = cc_map_sg(dev, src, nbytes, DMA_BIDIRECTIONAL, &req_ctx->in_nents,
  463. LLI_MAX_NUM_OF_DATA_ENTRIES, &dummy, &mapped_nents);
  464. if (rc) {
  465. rc = -ENOMEM;
  466. goto cipher_exit;
  467. }
  468. if (mapped_nents > 1)
  469. req_ctx->dma_buf_type = CC_DMA_BUF_MLLI;
  470. if (src == dst) {
  471. /* Handle inplace operation */
  472. if (req_ctx->dma_buf_type == CC_DMA_BUF_MLLI) {
  473. req_ctx->out_nents = 0;
  474. cc_add_sg_entry(dev, &sg_data, req_ctx->in_nents, src,
  475. nbytes, 0, true,
  476. &req_ctx->in_mlli_nents);
  477. }
  478. } else {
  479. /* Map the dst sg */
  480. if (cc_map_sg(dev, dst, nbytes, DMA_BIDIRECTIONAL,
  481. &req_ctx->out_nents, LLI_MAX_NUM_OF_DATA_ENTRIES,
  482. &dummy, &mapped_nents)) {
  483. rc = -ENOMEM;
  484. goto cipher_exit;
  485. }
  486. if (mapped_nents > 1)
  487. req_ctx->dma_buf_type = CC_DMA_BUF_MLLI;
  488. if (req_ctx->dma_buf_type == CC_DMA_BUF_MLLI) {
  489. cc_add_sg_entry(dev, &sg_data, req_ctx->in_nents, src,
  490. nbytes, 0, true,
  491. &req_ctx->in_mlli_nents);
  492. cc_add_sg_entry(dev, &sg_data, req_ctx->out_nents, dst,
  493. nbytes, 0, true,
  494. &req_ctx->out_mlli_nents);
  495. }
  496. }
  497. if (req_ctx->dma_buf_type == CC_DMA_BUF_MLLI) {
  498. mlli_params->curr_pool = buff_mgr->mlli_buffs_pool;
  499. rc = cc_generate_mlli(dev, &sg_data, mlli_params, flags);
  500. if (rc)
  501. goto cipher_exit;
  502. }
  503. dev_dbg(dev, "areq_ctx->dma_buf_type = %s\n",
  504. cc_dma_buf_type(req_ctx->dma_buf_type));
  505. return 0;
  506. cipher_exit:
  507. cc_unmap_cipher_request(dev, req_ctx, ivsize, src, dst);
  508. return rc;
  509. }
  510. void cc_unmap_aead_request(struct device *dev, struct aead_request *req)
  511. {
  512. struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
  513. unsigned int hw_iv_size = areq_ctx->hw_iv_size;
  514. struct crypto_aead *tfm = crypto_aead_reqtfm(req);
  515. struct cc_drvdata *drvdata = dev_get_drvdata(dev);
  516. u32 dummy;
  517. bool chained;
  518. u32 size_to_unmap = 0;
  519. if (areq_ctx->mac_buf_dma_addr) {
  520. dma_unmap_single(dev, areq_ctx->mac_buf_dma_addr,
  521. MAX_MAC_SIZE, DMA_BIDIRECTIONAL);
  522. }
  523. if (areq_ctx->cipher_mode == DRV_CIPHER_GCTR) {
  524. if (areq_ctx->hkey_dma_addr) {
  525. dma_unmap_single(dev, areq_ctx->hkey_dma_addr,
  526. AES_BLOCK_SIZE, DMA_BIDIRECTIONAL);
  527. }
  528. if (areq_ctx->gcm_block_len_dma_addr) {
  529. dma_unmap_single(dev, areq_ctx->gcm_block_len_dma_addr,
  530. AES_BLOCK_SIZE, DMA_TO_DEVICE);
  531. }
  532. if (areq_ctx->gcm_iv_inc1_dma_addr) {
  533. dma_unmap_single(dev, areq_ctx->gcm_iv_inc1_dma_addr,
  534. AES_BLOCK_SIZE, DMA_TO_DEVICE);
  535. }
  536. if (areq_ctx->gcm_iv_inc2_dma_addr) {
  537. dma_unmap_single(dev, areq_ctx->gcm_iv_inc2_dma_addr,
  538. AES_BLOCK_SIZE, DMA_TO_DEVICE);
  539. }
  540. }
  541. if (areq_ctx->ccm_hdr_size != ccm_header_size_null) {
  542. if (areq_ctx->ccm_iv0_dma_addr) {
  543. dma_unmap_single(dev, areq_ctx->ccm_iv0_dma_addr,
  544. AES_BLOCK_SIZE, DMA_TO_DEVICE);
  545. }
  546. dma_unmap_sg(dev, &areq_ctx->ccm_adata_sg, 1, DMA_TO_DEVICE);
  547. }
  548. if (areq_ctx->gen_ctx.iv_dma_addr) {
  549. dma_unmap_single(dev, areq_ctx->gen_ctx.iv_dma_addr,
  550. hw_iv_size, DMA_BIDIRECTIONAL);
  551. }
  552. /*In case a pool was set, a table was
  553. *allocated and should be released
  554. */
  555. if (areq_ctx->mlli_params.curr_pool) {
  556. dev_dbg(dev, "free MLLI buffer: dma=%pad virt=%pK\n",
  557. &areq_ctx->mlli_params.mlli_dma_addr,
  558. areq_ctx->mlli_params.mlli_virt_addr);
  559. dma_pool_free(areq_ctx->mlli_params.curr_pool,
  560. areq_ctx->mlli_params.mlli_virt_addr,
  561. areq_ctx->mlli_params.mlli_dma_addr);
  562. }
  563. dev_dbg(dev, "Unmapping src sgl: req->src=%pK areq_ctx->src.nents=%u areq_ctx->assoc.nents=%u assoclen:%u cryptlen=%u\n",
  564. sg_virt(req->src), areq_ctx->src.nents, areq_ctx->assoc.nents,
  565. req->assoclen, req->cryptlen);
  566. size_to_unmap = req->assoclen + req->cryptlen;
  567. if (areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_ENCRYPT)
  568. size_to_unmap += areq_ctx->req_authsize;
  569. if (areq_ctx->is_gcm4543)
  570. size_to_unmap += crypto_aead_ivsize(tfm);
  571. dma_unmap_sg(dev, req->src,
  572. cc_get_sgl_nents(dev, req->src, size_to_unmap,
  573. &dummy, &chained),
  574. DMA_BIDIRECTIONAL);
  575. if (req->src != req->dst) {
  576. dev_dbg(dev, "Unmapping dst sgl: req->dst=%pK\n",
  577. sg_virt(req->dst));
  578. dma_unmap_sg(dev, req->dst,
  579. cc_get_sgl_nents(dev, req->dst, size_to_unmap,
  580. &dummy, &chained),
  581. DMA_BIDIRECTIONAL);
  582. }
  583. if (drvdata->coherent &&
  584. areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT &&
  585. req->src == req->dst) {
  586. /* copy back mac from temporary location to deal with possible
  587. * data memory overriding that caused by cache coherence
  588. * problem.
  589. */
  590. cc_copy_mac(dev, req, CC_SG_FROM_BUF);
  591. }
  592. }
  593. static int cc_get_aead_icv_nents(struct device *dev, struct scatterlist *sgl,
  594. unsigned int sgl_nents, unsigned int authsize,
  595. u32 last_entry_data_size,
  596. bool *is_icv_fragmented)
  597. {
  598. unsigned int icv_max_size = 0;
  599. unsigned int icv_required_size = authsize > last_entry_data_size ?
  600. (authsize - last_entry_data_size) :
  601. authsize;
  602. unsigned int nents;
  603. unsigned int i;
  604. if (sgl_nents < MAX_ICV_NENTS_SUPPORTED) {
  605. *is_icv_fragmented = false;
  606. return 0;
  607. }
  608. for (i = 0 ; i < (sgl_nents - MAX_ICV_NENTS_SUPPORTED) ; i++) {
  609. if (!sgl)
  610. break;
  611. sgl = sg_next(sgl);
  612. }
  613. if (sgl)
  614. icv_max_size = sgl->length;
  615. if (last_entry_data_size > authsize) {
  616. /* ICV attached to data in last entry (not fragmented!) */
  617. nents = 0;
  618. *is_icv_fragmented = false;
  619. } else if (last_entry_data_size == authsize) {
  620. /* ICV placed in whole last entry (not fragmented!) */
  621. nents = 1;
  622. *is_icv_fragmented = false;
  623. } else if (icv_max_size > icv_required_size) {
  624. nents = 1;
  625. *is_icv_fragmented = true;
  626. } else if (icv_max_size == icv_required_size) {
  627. nents = 2;
  628. *is_icv_fragmented = true;
  629. } else {
  630. dev_err(dev, "Unsupported num. of ICV fragments (> %d)\n",
  631. MAX_ICV_NENTS_SUPPORTED);
  632. nents = -1; /*unsupported*/
  633. }
  634. dev_dbg(dev, "is_frag=%s icv_nents=%u\n",
  635. (*is_icv_fragmented ? "true" : "false"), nents);
  636. return nents;
  637. }
  638. static int cc_aead_chain_iv(struct cc_drvdata *drvdata,
  639. struct aead_request *req,
  640. struct buffer_array *sg_data,
  641. bool is_last, bool do_chain)
  642. {
  643. struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
  644. unsigned int hw_iv_size = areq_ctx->hw_iv_size;
  645. struct device *dev = drvdata_to_dev(drvdata);
  646. int rc = 0;
  647. if (!req->iv) {
  648. areq_ctx->gen_ctx.iv_dma_addr = 0;
  649. goto chain_iv_exit;
  650. }
  651. areq_ctx->gen_ctx.iv_dma_addr = dma_map_single(dev, req->iv,
  652. hw_iv_size,
  653. DMA_BIDIRECTIONAL);
  654. if (dma_mapping_error(dev, areq_ctx->gen_ctx.iv_dma_addr)) {
  655. dev_err(dev, "Mapping iv %u B at va=%pK for DMA failed\n",
  656. hw_iv_size, req->iv);
  657. rc = -ENOMEM;
  658. goto chain_iv_exit;
  659. }
  660. dev_dbg(dev, "Mapped iv %u B at va=%pK to dma=%pad\n",
  661. hw_iv_size, req->iv, &areq_ctx->gen_ctx.iv_dma_addr);
  662. // TODO: what about CTR?? ask Ron
  663. if (do_chain && areq_ctx->plaintext_authenticate_only) {
  664. struct crypto_aead *tfm = crypto_aead_reqtfm(req);
  665. unsigned int iv_size_to_authenc = crypto_aead_ivsize(tfm);
  666. unsigned int iv_ofs = GCM_BLOCK_RFC4_IV_OFFSET;
  667. /* Chain to given list */
  668. cc_add_buffer_entry(dev, sg_data,
  669. (areq_ctx->gen_ctx.iv_dma_addr + iv_ofs),
  670. iv_size_to_authenc, is_last,
  671. &areq_ctx->assoc.mlli_nents);
  672. areq_ctx->assoc_buff_type = CC_DMA_BUF_MLLI;
  673. }
  674. chain_iv_exit:
  675. return rc;
  676. }
  677. static int cc_aead_chain_assoc(struct cc_drvdata *drvdata,
  678. struct aead_request *req,
  679. struct buffer_array *sg_data,
  680. bool is_last, bool do_chain)
  681. {
  682. struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
  683. int rc = 0;
  684. u32 mapped_nents = 0;
  685. struct scatterlist *current_sg = req->src;
  686. struct crypto_aead *tfm = crypto_aead_reqtfm(req);
  687. unsigned int sg_index = 0;
  688. u32 size_of_assoc = req->assoclen;
  689. struct device *dev = drvdata_to_dev(drvdata);
  690. if (areq_ctx->is_gcm4543)
  691. size_of_assoc += crypto_aead_ivsize(tfm);
  692. if (!sg_data) {
  693. rc = -EINVAL;
  694. goto chain_assoc_exit;
  695. }
  696. if (req->assoclen == 0) {
  697. areq_ctx->assoc_buff_type = CC_DMA_BUF_NULL;
  698. areq_ctx->assoc.nents = 0;
  699. areq_ctx->assoc.mlli_nents = 0;
  700. dev_dbg(dev, "Chain assoc of length 0: buff_type=%s nents=%u\n",
  701. cc_dma_buf_type(areq_ctx->assoc_buff_type),
  702. areq_ctx->assoc.nents);
  703. goto chain_assoc_exit;
  704. }
  705. //iterate over the sgl to see how many entries are for associated data
  706. //it is assumed that if we reach here , the sgl is already mapped
  707. sg_index = current_sg->length;
  708. //the first entry in the scatter list contains all the associated data
  709. if (sg_index > size_of_assoc) {
  710. mapped_nents++;
  711. } else {
  712. while (sg_index <= size_of_assoc) {
  713. current_sg = sg_next(current_sg);
  714. /* if have reached the end of the sgl, then this is
  715. * unexpected
  716. */
  717. if (!current_sg) {
  718. dev_err(dev, "reached end of sg list. unexpected\n");
  719. return -EINVAL;
  720. }
  721. sg_index += current_sg->length;
  722. mapped_nents++;
  723. }
  724. }
  725. if (mapped_nents > LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES) {
  726. dev_err(dev, "Too many fragments. current %d max %d\n",
  727. mapped_nents, LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES);
  728. return -ENOMEM;
  729. }
  730. areq_ctx->assoc.nents = mapped_nents;
  731. /* in CCM case we have additional entry for
  732. * ccm header configurations
  733. */
  734. if (areq_ctx->ccm_hdr_size != ccm_header_size_null) {
  735. if ((mapped_nents + 1) > LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES) {
  736. dev_err(dev, "CCM case.Too many fragments. Current %d max %d\n",
  737. (areq_ctx->assoc.nents + 1),
  738. LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES);
  739. rc = -ENOMEM;
  740. goto chain_assoc_exit;
  741. }
  742. }
  743. if (mapped_nents == 1 && areq_ctx->ccm_hdr_size == ccm_header_size_null)
  744. areq_ctx->assoc_buff_type = CC_DMA_BUF_DLLI;
  745. else
  746. areq_ctx->assoc_buff_type = CC_DMA_BUF_MLLI;
  747. if (do_chain || areq_ctx->assoc_buff_type == CC_DMA_BUF_MLLI) {
  748. dev_dbg(dev, "Chain assoc: buff_type=%s nents=%u\n",
  749. cc_dma_buf_type(areq_ctx->assoc_buff_type),
  750. areq_ctx->assoc.nents);
  751. cc_add_sg_entry(dev, sg_data, areq_ctx->assoc.nents, req->src,
  752. req->assoclen, 0, is_last,
  753. &areq_ctx->assoc.mlli_nents);
  754. areq_ctx->assoc_buff_type = CC_DMA_BUF_MLLI;
  755. }
  756. chain_assoc_exit:
  757. return rc;
  758. }
  759. static void cc_prepare_aead_data_dlli(struct aead_request *req,
  760. u32 *src_last_bytes, u32 *dst_last_bytes)
  761. {
  762. struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
  763. enum drv_crypto_direction direct = areq_ctx->gen_ctx.op_type;
  764. unsigned int authsize = areq_ctx->req_authsize;
  765. areq_ctx->is_icv_fragmented = false;
  766. if (req->src == req->dst) {
  767. /*INPLACE*/
  768. areq_ctx->icv_dma_addr = sg_dma_address(areq_ctx->src_sgl) +
  769. (*src_last_bytes - authsize);
  770. areq_ctx->icv_virt_addr = sg_virt(areq_ctx->src_sgl) +
  771. (*src_last_bytes - authsize);
  772. } else if (direct == DRV_CRYPTO_DIRECTION_DECRYPT) {
  773. /*NON-INPLACE and DECRYPT*/
  774. areq_ctx->icv_dma_addr = sg_dma_address(areq_ctx->src_sgl) +
  775. (*src_last_bytes - authsize);
  776. areq_ctx->icv_virt_addr = sg_virt(areq_ctx->src_sgl) +
  777. (*src_last_bytes - authsize);
  778. } else {
  779. /*NON-INPLACE and ENCRYPT*/
  780. areq_ctx->icv_dma_addr = sg_dma_address(areq_ctx->dst_sgl) +
  781. (*dst_last_bytes - authsize);
  782. areq_ctx->icv_virt_addr = sg_virt(areq_ctx->dst_sgl) +
  783. (*dst_last_bytes - authsize);
  784. }
  785. }
  786. static int cc_prepare_aead_data_mlli(struct cc_drvdata *drvdata,
  787. struct aead_request *req,
  788. struct buffer_array *sg_data,
  789. u32 *src_last_bytes, u32 *dst_last_bytes,
  790. bool is_last_table)
  791. {
  792. struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
  793. enum drv_crypto_direction direct = areq_ctx->gen_ctx.op_type;
  794. unsigned int authsize = areq_ctx->req_authsize;
  795. int rc = 0, icv_nents;
  796. struct device *dev = drvdata_to_dev(drvdata);
  797. struct scatterlist *sg;
  798. if (req->src == req->dst) {
  799. /*INPLACE*/
  800. cc_add_sg_entry(dev, sg_data, areq_ctx->src.nents,
  801. areq_ctx->src_sgl, areq_ctx->cryptlen,
  802. areq_ctx->src_offset, is_last_table,
  803. &areq_ctx->src.mlli_nents);
  804. icv_nents = cc_get_aead_icv_nents(dev, areq_ctx->src_sgl,
  805. areq_ctx->src.nents,
  806. authsize, *src_last_bytes,
  807. &areq_ctx->is_icv_fragmented);
  808. if (icv_nents < 0) {
  809. rc = -ENOTSUPP;
  810. goto prepare_data_mlli_exit;
  811. }
  812. if (areq_ctx->is_icv_fragmented) {
  813. /* Backup happens only when ICV is fragmented, ICV
  814. * verification is made by CPU compare in order to
  815. * simplify MAC verification upon request completion
  816. */
  817. if (direct == DRV_CRYPTO_DIRECTION_DECRYPT) {
  818. /* In coherent platforms (e.g. ACP)
  819. * already copying ICV for any
  820. * INPLACE-DECRYPT operation, hence
  821. * we must neglect this code.
  822. */
  823. if (!drvdata->coherent)
  824. cc_copy_mac(dev, req, CC_SG_TO_BUF);
  825. areq_ctx->icv_virt_addr = areq_ctx->backup_mac;
  826. } else {
  827. areq_ctx->icv_virt_addr = areq_ctx->mac_buf;
  828. areq_ctx->icv_dma_addr =
  829. areq_ctx->mac_buf_dma_addr;
  830. }
  831. } else { /* Contig. ICV */
  832. sg = &areq_ctx->src_sgl[areq_ctx->src.nents - 1];
  833. /*Should hanlde if the sg is not contig.*/
  834. areq_ctx->icv_dma_addr = sg_dma_address(sg) +
  835. (*src_last_bytes - authsize);
  836. areq_ctx->icv_virt_addr = sg_virt(sg) +
  837. (*src_last_bytes - authsize);
  838. }
  839. } else if (direct == DRV_CRYPTO_DIRECTION_DECRYPT) {
  840. /*NON-INPLACE and DECRYPT*/
  841. cc_add_sg_entry(dev, sg_data, areq_ctx->src.nents,
  842. areq_ctx->src_sgl, areq_ctx->cryptlen,
  843. areq_ctx->src_offset, is_last_table,
  844. &areq_ctx->src.mlli_nents);
  845. cc_add_sg_entry(dev, sg_data, areq_ctx->dst.nents,
  846. areq_ctx->dst_sgl, areq_ctx->cryptlen,
  847. areq_ctx->dst_offset, is_last_table,
  848. &areq_ctx->dst.mlli_nents);
  849. icv_nents = cc_get_aead_icv_nents(dev, areq_ctx->src_sgl,
  850. areq_ctx->src.nents,
  851. authsize, *src_last_bytes,
  852. &areq_ctx->is_icv_fragmented);
  853. if (icv_nents < 0) {
  854. rc = -ENOTSUPP;
  855. goto prepare_data_mlli_exit;
  856. }
  857. /* Backup happens only when ICV is fragmented, ICV
  858. * verification is made by CPU compare in order to simplify
  859. * MAC verification upon request completion
  860. */
  861. if (areq_ctx->is_icv_fragmented) {
  862. cc_copy_mac(dev, req, CC_SG_TO_BUF);
  863. areq_ctx->icv_virt_addr = areq_ctx->backup_mac;
  864. } else { /* Contig. ICV */
  865. sg = &areq_ctx->src_sgl[areq_ctx->src.nents - 1];
  866. /*Should hanlde if the sg is not contig.*/
  867. areq_ctx->icv_dma_addr = sg_dma_address(sg) +
  868. (*src_last_bytes - authsize);
  869. areq_ctx->icv_virt_addr = sg_virt(sg) +
  870. (*src_last_bytes - authsize);
  871. }
  872. } else {
  873. /*NON-INPLACE and ENCRYPT*/
  874. cc_add_sg_entry(dev, sg_data, areq_ctx->dst.nents,
  875. areq_ctx->dst_sgl, areq_ctx->cryptlen,
  876. areq_ctx->dst_offset, is_last_table,
  877. &areq_ctx->dst.mlli_nents);
  878. cc_add_sg_entry(dev, sg_data, areq_ctx->src.nents,
  879. areq_ctx->src_sgl, areq_ctx->cryptlen,
  880. areq_ctx->src_offset, is_last_table,
  881. &areq_ctx->src.mlli_nents);
  882. icv_nents = cc_get_aead_icv_nents(dev, areq_ctx->dst_sgl,
  883. areq_ctx->dst.nents,
  884. authsize, *dst_last_bytes,
  885. &areq_ctx->is_icv_fragmented);
  886. if (icv_nents < 0) {
  887. rc = -ENOTSUPP;
  888. goto prepare_data_mlli_exit;
  889. }
  890. if (!areq_ctx->is_icv_fragmented) {
  891. sg = &areq_ctx->dst_sgl[areq_ctx->dst.nents - 1];
  892. /* Contig. ICV */
  893. areq_ctx->icv_dma_addr = sg_dma_address(sg) +
  894. (*dst_last_bytes - authsize);
  895. areq_ctx->icv_virt_addr = sg_virt(sg) +
  896. (*dst_last_bytes - authsize);
  897. } else {
  898. areq_ctx->icv_dma_addr = areq_ctx->mac_buf_dma_addr;
  899. areq_ctx->icv_virt_addr = areq_ctx->mac_buf;
  900. }
  901. }
  902. prepare_data_mlli_exit:
  903. return rc;
  904. }
  905. static int cc_aead_chain_data(struct cc_drvdata *drvdata,
  906. struct aead_request *req,
  907. struct buffer_array *sg_data,
  908. bool is_last_table, bool do_chain)
  909. {
  910. struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
  911. struct device *dev = drvdata_to_dev(drvdata);
  912. enum drv_crypto_direction direct = areq_ctx->gen_ctx.op_type;
  913. unsigned int authsize = areq_ctx->req_authsize;
  914. unsigned int src_last_bytes = 0, dst_last_bytes = 0;
  915. int rc = 0;
  916. u32 src_mapped_nents = 0, dst_mapped_nents = 0;
  917. u32 offset = 0;
  918. /* non-inplace mode */
  919. unsigned int size_for_map = req->assoclen + req->cryptlen;
  920. struct crypto_aead *tfm = crypto_aead_reqtfm(req);
  921. u32 sg_index = 0;
  922. bool chained = false;
  923. bool is_gcm4543 = areq_ctx->is_gcm4543;
  924. u32 size_to_skip = req->assoclen;
  925. if (is_gcm4543)
  926. size_to_skip += crypto_aead_ivsize(tfm);
  927. offset = size_to_skip;
  928. if (!sg_data)
  929. return -EINVAL;
  930. areq_ctx->src_sgl = req->src;
  931. areq_ctx->dst_sgl = req->dst;
  932. if (is_gcm4543)
  933. size_for_map += crypto_aead_ivsize(tfm);
  934. size_for_map += (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) ?
  935. authsize : 0;
  936. src_mapped_nents = cc_get_sgl_nents(dev, req->src, size_for_map,
  937. &src_last_bytes, &chained);
  938. sg_index = areq_ctx->src_sgl->length;
  939. //check where the data starts
  940. while (sg_index <= size_to_skip) {
  941. offset -= areq_ctx->src_sgl->length;
  942. areq_ctx->src_sgl = sg_next(areq_ctx->src_sgl);
  943. //if have reached the end of the sgl, then this is unexpected
  944. if (!areq_ctx->src_sgl) {
  945. dev_err(dev, "reached end of sg list. unexpected\n");
  946. return -EINVAL;
  947. }
  948. sg_index += areq_ctx->src_sgl->length;
  949. src_mapped_nents--;
  950. }
  951. if (src_mapped_nents > LLI_MAX_NUM_OF_DATA_ENTRIES) {
  952. dev_err(dev, "Too many fragments. current %d max %d\n",
  953. src_mapped_nents, LLI_MAX_NUM_OF_DATA_ENTRIES);
  954. return -ENOMEM;
  955. }
  956. areq_ctx->src.nents = src_mapped_nents;
  957. areq_ctx->src_offset = offset;
  958. if (req->src != req->dst) {
  959. size_for_map = req->assoclen + req->cryptlen;
  960. size_for_map += (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) ?
  961. authsize : 0;
  962. if (is_gcm4543)
  963. size_for_map += crypto_aead_ivsize(tfm);
  964. rc = cc_map_sg(dev, req->dst, size_for_map, DMA_BIDIRECTIONAL,
  965. &areq_ctx->dst.nents,
  966. LLI_MAX_NUM_OF_DATA_ENTRIES, &dst_last_bytes,
  967. &dst_mapped_nents);
  968. if (rc) {
  969. rc = -ENOMEM;
  970. goto chain_data_exit;
  971. }
  972. }
  973. dst_mapped_nents = cc_get_sgl_nents(dev, req->dst, size_for_map,
  974. &dst_last_bytes, &chained);
  975. sg_index = areq_ctx->dst_sgl->length;
  976. offset = size_to_skip;
  977. //check where the data starts
  978. while (sg_index <= size_to_skip) {
  979. offset -= areq_ctx->dst_sgl->length;
  980. areq_ctx->dst_sgl = sg_next(areq_ctx->dst_sgl);
  981. //if have reached the end of the sgl, then this is unexpected
  982. if (!areq_ctx->dst_sgl) {
  983. dev_err(dev, "reached end of sg list. unexpected\n");
  984. return -EINVAL;
  985. }
  986. sg_index += areq_ctx->dst_sgl->length;
  987. dst_mapped_nents--;
  988. }
  989. if (dst_mapped_nents > LLI_MAX_NUM_OF_DATA_ENTRIES) {
  990. dev_err(dev, "Too many fragments. current %d max %d\n",
  991. dst_mapped_nents, LLI_MAX_NUM_OF_DATA_ENTRIES);
  992. return -ENOMEM;
  993. }
  994. areq_ctx->dst.nents = dst_mapped_nents;
  995. areq_ctx->dst_offset = offset;
  996. if (src_mapped_nents > 1 ||
  997. dst_mapped_nents > 1 ||
  998. do_chain) {
  999. areq_ctx->data_buff_type = CC_DMA_BUF_MLLI;
  1000. rc = cc_prepare_aead_data_mlli(drvdata, req, sg_data,
  1001. &src_last_bytes,
  1002. &dst_last_bytes, is_last_table);
  1003. } else {
  1004. areq_ctx->data_buff_type = CC_DMA_BUF_DLLI;
  1005. cc_prepare_aead_data_dlli(req, &src_last_bytes,
  1006. &dst_last_bytes);
  1007. }
  1008. chain_data_exit:
  1009. return rc;
  1010. }
  1011. static void cc_update_aead_mlli_nents(struct cc_drvdata *drvdata,
  1012. struct aead_request *req)
  1013. {
  1014. struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
  1015. u32 curr_mlli_size = 0;
  1016. if (areq_ctx->assoc_buff_type == CC_DMA_BUF_MLLI) {
  1017. areq_ctx->assoc.sram_addr = drvdata->mlli_sram_addr;
  1018. curr_mlli_size = areq_ctx->assoc.mlli_nents *
  1019. LLI_ENTRY_BYTE_SIZE;
  1020. }
  1021. if (areq_ctx->data_buff_type == CC_DMA_BUF_MLLI) {
  1022. /*Inplace case dst nents equal to src nents*/
  1023. if (req->src == req->dst) {
  1024. areq_ctx->dst.mlli_nents = areq_ctx->src.mlli_nents;
  1025. areq_ctx->src.sram_addr = drvdata->mlli_sram_addr +
  1026. curr_mlli_size;
  1027. areq_ctx->dst.sram_addr = areq_ctx->src.sram_addr;
  1028. if (!areq_ctx->is_single_pass)
  1029. areq_ctx->assoc.mlli_nents +=
  1030. areq_ctx->src.mlli_nents;
  1031. } else {
  1032. if (areq_ctx->gen_ctx.op_type ==
  1033. DRV_CRYPTO_DIRECTION_DECRYPT) {
  1034. areq_ctx->src.sram_addr =
  1035. drvdata->mlli_sram_addr +
  1036. curr_mlli_size;
  1037. areq_ctx->dst.sram_addr =
  1038. areq_ctx->src.sram_addr +
  1039. areq_ctx->src.mlli_nents *
  1040. LLI_ENTRY_BYTE_SIZE;
  1041. if (!areq_ctx->is_single_pass)
  1042. areq_ctx->assoc.mlli_nents +=
  1043. areq_ctx->src.mlli_nents;
  1044. } else {
  1045. areq_ctx->dst.sram_addr =
  1046. drvdata->mlli_sram_addr +
  1047. curr_mlli_size;
  1048. areq_ctx->src.sram_addr =
  1049. areq_ctx->dst.sram_addr +
  1050. areq_ctx->dst.mlli_nents *
  1051. LLI_ENTRY_BYTE_SIZE;
  1052. if (!areq_ctx->is_single_pass)
  1053. areq_ctx->assoc.mlli_nents +=
  1054. areq_ctx->dst.mlli_nents;
  1055. }
  1056. }
  1057. }
  1058. }
  1059. int cc_map_aead_request(struct cc_drvdata *drvdata, struct aead_request *req)
  1060. {
  1061. struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
  1062. struct mlli_params *mlli_params = &areq_ctx->mlli_params;
  1063. struct device *dev = drvdata_to_dev(drvdata);
  1064. struct buffer_array sg_data;
  1065. unsigned int authsize = areq_ctx->req_authsize;
  1066. struct buff_mgr_handle *buff_mgr = drvdata->buff_mgr_handle;
  1067. int rc = 0;
  1068. struct crypto_aead *tfm = crypto_aead_reqtfm(req);
  1069. bool is_gcm4543 = areq_ctx->is_gcm4543;
  1070. dma_addr_t dma_addr;
  1071. u32 mapped_nents = 0;
  1072. u32 dummy = 0; /*used for the assoc data fragments */
  1073. u32 size_to_map = 0;
  1074. gfp_t flags = cc_gfp_flags(&req->base);
  1075. mlli_params->curr_pool = NULL;
  1076. sg_data.num_of_buffers = 0;
  1077. /* copy mac to a temporary location to deal with possible
  1078. * data memory overriding that caused by cache coherence problem.
  1079. */
  1080. if (drvdata->coherent &&
  1081. areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT &&
  1082. req->src == req->dst)
  1083. cc_copy_mac(dev, req, CC_SG_TO_BUF);
  1084. /* cacluate the size for cipher remove ICV in decrypt*/
  1085. areq_ctx->cryptlen = (areq_ctx->gen_ctx.op_type ==
  1086. DRV_CRYPTO_DIRECTION_ENCRYPT) ?
  1087. req->cryptlen :
  1088. (req->cryptlen - authsize);
  1089. dma_addr = dma_map_single(dev, areq_ctx->mac_buf, MAX_MAC_SIZE,
  1090. DMA_BIDIRECTIONAL);
  1091. if (dma_mapping_error(dev, dma_addr)) {
  1092. dev_err(dev, "Mapping mac_buf %u B at va=%pK for DMA failed\n",
  1093. MAX_MAC_SIZE, areq_ctx->mac_buf);
  1094. rc = -ENOMEM;
  1095. goto aead_map_failure;
  1096. }
  1097. areq_ctx->mac_buf_dma_addr = dma_addr;
  1098. if (areq_ctx->ccm_hdr_size != ccm_header_size_null) {
  1099. void *addr = areq_ctx->ccm_config + CCM_CTR_COUNT_0_OFFSET;
  1100. dma_addr = dma_map_single(dev, addr, AES_BLOCK_SIZE,
  1101. DMA_TO_DEVICE);
  1102. if (dma_mapping_error(dev, dma_addr)) {
  1103. dev_err(dev, "Mapping mac_buf %u B at va=%pK for DMA failed\n",
  1104. AES_BLOCK_SIZE, addr);
  1105. areq_ctx->ccm_iv0_dma_addr = 0;
  1106. rc = -ENOMEM;
  1107. goto aead_map_failure;
  1108. }
  1109. areq_ctx->ccm_iv0_dma_addr = dma_addr;
  1110. if (cc_set_aead_conf_buf(dev, areq_ctx, areq_ctx->ccm_config,
  1111. &sg_data, req->assoclen)) {
  1112. rc = -ENOMEM;
  1113. goto aead_map_failure;
  1114. }
  1115. }
  1116. if (areq_ctx->cipher_mode == DRV_CIPHER_GCTR) {
  1117. dma_addr = dma_map_single(dev, areq_ctx->hkey, AES_BLOCK_SIZE,
  1118. DMA_BIDIRECTIONAL);
  1119. if (dma_mapping_error(dev, dma_addr)) {
  1120. dev_err(dev, "Mapping hkey %u B at va=%pK for DMA failed\n",
  1121. AES_BLOCK_SIZE, areq_ctx->hkey);
  1122. rc = -ENOMEM;
  1123. goto aead_map_failure;
  1124. }
  1125. areq_ctx->hkey_dma_addr = dma_addr;
  1126. dma_addr = dma_map_single(dev, &areq_ctx->gcm_len_block,
  1127. AES_BLOCK_SIZE, DMA_TO_DEVICE);
  1128. if (dma_mapping_error(dev, dma_addr)) {
  1129. dev_err(dev, "Mapping gcm_len_block %u B at va=%pK for DMA failed\n",
  1130. AES_BLOCK_SIZE, &areq_ctx->gcm_len_block);
  1131. rc = -ENOMEM;
  1132. goto aead_map_failure;
  1133. }
  1134. areq_ctx->gcm_block_len_dma_addr = dma_addr;
  1135. dma_addr = dma_map_single(dev, areq_ctx->gcm_iv_inc1,
  1136. AES_BLOCK_SIZE, DMA_TO_DEVICE);
  1137. if (dma_mapping_error(dev, dma_addr)) {
  1138. dev_err(dev, "Mapping gcm_iv_inc1 %u B at va=%pK for DMA failed\n",
  1139. AES_BLOCK_SIZE, (areq_ctx->gcm_iv_inc1));
  1140. areq_ctx->gcm_iv_inc1_dma_addr = 0;
  1141. rc = -ENOMEM;
  1142. goto aead_map_failure;
  1143. }
  1144. areq_ctx->gcm_iv_inc1_dma_addr = dma_addr;
  1145. dma_addr = dma_map_single(dev, areq_ctx->gcm_iv_inc2,
  1146. AES_BLOCK_SIZE, DMA_TO_DEVICE);
  1147. if (dma_mapping_error(dev, dma_addr)) {
  1148. dev_err(dev, "Mapping gcm_iv_inc2 %u B at va=%pK for DMA failed\n",
  1149. AES_BLOCK_SIZE, (areq_ctx->gcm_iv_inc2));
  1150. areq_ctx->gcm_iv_inc2_dma_addr = 0;
  1151. rc = -ENOMEM;
  1152. goto aead_map_failure;
  1153. }
  1154. areq_ctx->gcm_iv_inc2_dma_addr = dma_addr;
  1155. }
  1156. size_to_map = req->cryptlen + req->assoclen;
  1157. if (areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_ENCRYPT)
  1158. size_to_map += authsize;
  1159. if (is_gcm4543)
  1160. size_to_map += crypto_aead_ivsize(tfm);
  1161. rc = cc_map_sg(dev, req->src, size_to_map, DMA_BIDIRECTIONAL,
  1162. &areq_ctx->src.nents,
  1163. (LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES +
  1164. LLI_MAX_NUM_OF_DATA_ENTRIES),
  1165. &dummy, &mapped_nents);
  1166. if (rc) {
  1167. rc = -ENOMEM;
  1168. goto aead_map_failure;
  1169. }
  1170. if (areq_ctx->is_single_pass) {
  1171. /*
  1172. * Create MLLI table for:
  1173. * (1) Assoc. data
  1174. * (2) Src/Dst SGLs
  1175. * Note: IV is contg. buffer (not an SGL)
  1176. */
  1177. rc = cc_aead_chain_assoc(drvdata, req, &sg_data, true, false);
  1178. if (rc)
  1179. goto aead_map_failure;
  1180. rc = cc_aead_chain_iv(drvdata, req, &sg_data, true, false);
  1181. if (rc)
  1182. goto aead_map_failure;
  1183. rc = cc_aead_chain_data(drvdata, req, &sg_data, true, false);
  1184. if (rc)
  1185. goto aead_map_failure;
  1186. } else { /* DOUBLE-PASS flow */
  1187. /*
  1188. * Prepare MLLI table(s) in this order:
  1189. *
  1190. * If ENCRYPT/DECRYPT (inplace):
  1191. * (1) MLLI table for assoc
  1192. * (2) IV entry (chained right after end of assoc)
  1193. * (3) MLLI for src/dst (inplace operation)
  1194. *
  1195. * If ENCRYPT (non-inplace)
  1196. * (1) MLLI table for assoc
  1197. * (2) IV entry (chained right after end of assoc)
  1198. * (3) MLLI for dst
  1199. * (4) MLLI for src
  1200. *
  1201. * If DECRYPT (non-inplace)
  1202. * (1) MLLI table for assoc
  1203. * (2) IV entry (chained right after end of assoc)
  1204. * (3) MLLI for src
  1205. * (4) MLLI for dst
  1206. */
  1207. rc = cc_aead_chain_assoc(drvdata, req, &sg_data, false, true);
  1208. if (rc)
  1209. goto aead_map_failure;
  1210. rc = cc_aead_chain_iv(drvdata, req, &sg_data, false, true);
  1211. if (rc)
  1212. goto aead_map_failure;
  1213. rc = cc_aead_chain_data(drvdata, req, &sg_data, true, true);
  1214. if (rc)
  1215. goto aead_map_failure;
  1216. }
  1217. /* Mlli support -start building the MLLI according to the above
  1218. * results
  1219. */
  1220. if (areq_ctx->assoc_buff_type == CC_DMA_BUF_MLLI ||
  1221. areq_ctx->data_buff_type == CC_DMA_BUF_MLLI) {
  1222. mlli_params->curr_pool = buff_mgr->mlli_buffs_pool;
  1223. rc = cc_generate_mlli(dev, &sg_data, mlli_params, flags);
  1224. if (rc)
  1225. goto aead_map_failure;
  1226. cc_update_aead_mlli_nents(drvdata, req);
  1227. dev_dbg(dev, "assoc params mn %d\n",
  1228. areq_ctx->assoc.mlli_nents);
  1229. dev_dbg(dev, "src params mn %d\n", areq_ctx->src.mlli_nents);
  1230. dev_dbg(dev, "dst params mn %d\n", areq_ctx->dst.mlli_nents);
  1231. }
  1232. return 0;
  1233. aead_map_failure:
  1234. cc_unmap_aead_request(dev, req);
  1235. return rc;
  1236. }
  1237. int cc_map_hash_request_final(struct cc_drvdata *drvdata, void *ctx,
  1238. struct scatterlist *src, unsigned int nbytes,
  1239. bool do_update, gfp_t flags)
  1240. {
  1241. struct ahash_req_ctx *areq_ctx = (struct ahash_req_ctx *)ctx;
  1242. struct device *dev = drvdata_to_dev(drvdata);
  1243. u8 *curr_buff = cc_hash_buf(areq_ctx);
  1244. u32 *curr_buff_cnt = cc_hash_buf_cnt(areq_ctx);
  1245. struct mlli_params *mlli_params = &areq_ctx->mlli_params;
  1246. struct buffer_array sg_data;
  1247. struct buff_mgr_handle *buff_mgr = drvdata->buff_mgr_handle;
  1248. u32 dummy = 0;
  1249. u32 mapped_nents = 0;
  1250. dev_dbg(dev, "final params : curr_buff=%pK curr_buff_cnt=0x%X nbytes = 0x%X src=%pK curr_index=%u\n",
  1251. curr_buff, *curr_buff_cnt, nbytes, src, areq_ctx->buff_index);
  1252. /* Init the type of the dma buffer */
  1253. areq_ctx->data_dma_buf_type = CC_DMA_BUF_NULL;
  1254. mlli_params->curr_pool = NULL;
  1255. sg_data.num_of_buffers = 0;
  1256. areq_ctx->in_nents = 0;
  1257. if (nbytes == 0 && *curr_buff_cnt == 0) {
  1258. /* nothing to do */
  1259. return 0;
  1260. }
  1261. /*TODO: copy data in case that buffer is enough for operation */
  1262. /* map the previous buffer */
  1263. if (*curr_buff_cnt) {
  1264. if (cc_set_hash_buf(dev, areq_ctx, curr_buff, *curr_buff_cnt,
  1265. &sg_data)) {
  1266. return -ENOMEM;
  1267. }
  1268. }
  1269. if (src && nbytes > 0 && do_update) {
  1270. if (cc_map_sg(dev, src, nbytes, DMA_TO_DEVICE,
  1271. &areq_ctx->in_nents, LLI_MAX_NUM_OF_DATA_ENTRIES,
  1272. &dummy, &mapped_nents)) {
  1273. goto unmap_curr_buff;
  1274. }
  1275. if (src && mapped_nents == 1 &&
  1276. areq_ctx->data_dma_buf_type == CC_DMA_BUF_NULL) {
  1277. memcpy(areq_ctx->buff_sg, src,
  1278. sizeof(struct scatterlist));
  1279. areq_ctx->buff_sg->length = nbytes;
  1280. areq_ctx->curr_sg = areq_ctx->buff_sg;
  1281. areq_ctx->data_dma_buf_type = CC_DMA_BUF_DLLI;
  1282. } else {
  1283. areq_ctx->data_dma_buf_type = CC_DMA_BUF_MLLI;
  1284. }
  1285. }
  1286. /*build mlli */
  1287. if (areq_ctx->data_dma_buf_type == CC_DMA_BUF_MLLI) {
  1288. mlli_params->curr_pool = buff_mgr->mlli_buffs_pool;
  1289. /* add the src data to the sg_data */
  1290. cc_add_sg_entry(dev, &sg_data, areq_ctx->in_nents, src, nbytes,
  1291. 0, true, &areq_ctx->mlli_nents);
  1292. if (cc_generate_mlli(dev, &sg_data, mlli_params, flags))
  1293. goto fail_unmap_din;
  1294. }
  1295. /* change the buffer index for the unmap function */
  1296. areq_ctx->buff_index = (areq_ctx->buff_index ^ 1);
  1297. dev_dbg(dev, "areq_ctx->data_dma_buf_type = %s\n",
  1298. cc_dma_buf_type(areq_ctx->data_dma_buf_type));
  1299. return 0;
  1300. fail_unmap_din:
  1301. dma_unmap_sg(dev, src, areq_ctx->in_nents, DMA_TO_DEVICE);
  1302. unmap_curr_buff:
  1303. if (*curr_buff_cnt)
  1304. dma_unmap_sg(dev, areq_ctx->buff_sg, 1, DMA_TO_DEVICE);
  1305. return -ENOMEM;
  1306. }
  1307. int cc_map_hash_request_update(struct cc_drvdata *drvdata, void *ctx,
  1308. struct scatterlist *src, unsigned int nbytes,
  1309. unsigned int block_size, gfp_t flags)
  1310. {
  1311. struct ahash_req_ctx *areq_ctx = (struct ahash_req_ctx *)ctx;
  1312. struct device *dev = drvdata_to_dev(drvdata);
  1313. u8 *curr_buff = cc_hash_buf(areq_ctx);
  1314. u32 *curr_buff_cnt = cc_hash_buf_cnt(areq_ctx);
  1315. u8 *next_buff = cc_next_buf(areq_ctx);
  1316. u32 *next_buff_cnt = cc_next_buf_cnt(areq_ctx);
  1317. struct mlli_params *mlli_params = &areq_ctx->mlli_params;
  1318. unsigned int update_data_len;
  1319. u32 total_in_len = nbytes + *curr_buff_cnt;
  1320. struct buffer_array sg_data;
  1321. struct buff_mgr_handle *buff_mgr = drvdata->buff_mgr_handle;
  1322. unsigned int swap_index = 0;
  1323. u32 dummy = 0;
  1324. u32 mapped_nents = 0;
  1325. dev_dbg(dev, " update params : curr_buff=%pK curr_buff_cnt=0x%X nbytes=0x%X src=%pK curr_index=%u\n",
  1326. curr_buff, *curr_buff_cnt, nbytes, src, areq_ctx->buff_index);
  1327. /* Init the type of the dma buffer */
  1328. areq_ctx->data_dma_buf_type = CC_DMA_BUF_NULL;
  1329. mlli_params->curr_pool = NULL;
  1330. areq_ctx->curr_sg = NULL;
  1331. sg_data.num_of_buffers = 0;
  1332. areq_ctx->in_nents = 0;
  1333. if (total_in_len < block_size) {
  1334. dev_dbg(dev, " less than one block: curr_buff=%pK *curr_buff_cnt=0x%X copy_to=%pK\n",
  1335. curr_buff, *curr_buff_cnt, &curr_buff[*curr_buff_cnt]);
  1336. areq_ctx->in_nents =
  1337. cc_get_sgl_nents(dev, src, nbytes, &dummy, NULL);
  1338. sg_copy_to_buffer(src, areq_ctx->in_nents,
  1339. &curr_buff[*curr_buff_cnt], nbytes);
  1340. *curr_buff_cnt += nbytes;
  1341. return 1;
  1342. }
  1343. /* Calculate the residue size*/
  1344. *next_buff_cnt = total_in_len & (block_size - 1);
  1345. /* update data len */
  1346. update_data_len = total_in_len - *next_buff_cnt;
  1347. dev_dbg(dev, " temp length : *next_buff_cnt=0x%X update_data_len=0x%X\n",
  1348. *next_buff_cnt, update_data_len);
  1349. /* Copy the new residue to next buffer */
  1350. if (*next_buff_cnt) {
  1351. dev_dbg(dev, " handle residue: next buff %pK skip data %u residue %u\n",
  1352. next_buff, (update_data_len - *curr_buff_cnt),
  1353. *next_buff_cnt);
  1354. cc_copy_sg_portion(dev, next_buff, src,
  1355. (update_data_len - *curr_buff_cnt),
  1356. nbytes, CC_SG_TO_BUF);
  1357. /* change the buffer index for next operation */
  1358. swap_index = 1;
  1359. }
  1360. if (*curr_buff_cnt) {
  1361. if (cc_set_hash_buf(dev, areq_ctx, curr_buff, *curr_buff_cnt,
  1362. &sg_data)) {
  1363. return -ENOMEM;
  1364. }
  1365. /* change the buffer index for next operation */
  1366. swap_index = 1;
  1367. }
  1368. if (update_data_len > *curr_buff_cnt) {
  1369. if (cc_map_sg(dev, src, (update_data_len - *curr_buff_cnt),
  1370. DMA_TO_DEVICE, &areq_ctx->in_nents,
  1371. LLI_MAX_NUM_OF_DATA_ENTRIES, &dummy,
  1372. &mapped_nents)) {
  1373. goto unmap_curr_buff;
  1374. }
  1375. if (mapped_nents == 1 &&
  1376. areq_ctx->data_dma_buf_type == CC_DMA_BUF_NULL) {
  1377. /* only one entry in the SG and no previous data */
  1378. memcpy(areq_ctx->buff_sg, src,
  1379. sizeof(struct scatterlist));
  1380. areq_ctx->buff_sg->length = update_data_len;
  1381. areq_ctx->data_dma_buf_type = CC_DMA_BUF_DLLI;
  1382. areq_ctx->curr_sg = areq_ctx->buff_sg;
  1383. } else {
  1384. areq_ctx->data_dma_buf_type = CC_DMA_BUF_MLLI;
  1385. }
  1386. }
  1387. if (areq_ctx->data_dma_buf_type == CC_DMA_BUF_MLLI) {
  1388. mlli_params->curr_pool = buff_mgr->mlli_buffs_pool;
  1389. /* add the src data to the sg_data */
  1390. cc_add_sg_entry(dev, &sg_data, areq_ctx->in_nents, src,
  1391. (update_data_len - *curr_buff_cnt), 0, true,
  1392. &areq_ctx->mlli_nents);
  1393. if (cc_generate_mlli(dev, &sg_data, mlli_params, flags))
  1394. goto fail_unmap_din;
  1395. }
  1396. areq_ctx->buff_index = (areq_ctx->buff_index ^ swap_index);
  1397. return 0;
  1398. fail_unmap_din:
  1399. dma_unmap_sg(dev, src, areq_ctx->in_nents, DMA_TO_DEVICE);
  1400. unmap_curr_buff:
  1401. if (*curr_buff_cnt)
  1402. dma_unmap_sg(dev, areq_ctx->buff_sg, 1, DMA_TO_DEVICE);
  1403. return -ENOMEM;
  1404. }
  1405. void cc_unmap_hash_request(struct device *dev, void *ctx,
  1406. struct scatterlist *src, bool do_revert)
  1407. {
  1408. struct ahash_req_ctx *areq_ctx = (struct ahash_req_ctx *)ctx;
  1409. u32 *prev_len = cc_next_buf_cnt(areq_ctx);
  1410. /*In case a pool was set, a table was
  1411. *allocated and should be released
  1412. */
  1413. if (areq_ctx->mlli_params.curr_pool) {
  1414. dev_dbg(dev, "free MLLI buffer: dma=%pad virt=%pK\n",
  1415. &areq_ctx->mlli_params.mlli_dma_addr,
  1416. areq_ctx->mlli_params.mlli_virt_addr);
  1417. dma_pool_free(areq_ctx->mlli_params.curr_pool,
  1418. areq_ctx->mlli_params.mlli_virt_addr,
  1419. areq_ctx->mlli_params.mlli_dma_addr);
  1420. }
  1421. if (src && areq_ctx->in_nents) {
  1422. dev_dbg(dev, "Unmapped sg src: virt=%pK dma=%pad len=0x%X\n",
  1423. sg_virt(src), &sg_dma_address(src), sg_dma_len(src));
  1424. dma_unmap_sg(dev, src,
  1425. areq_ctx->in_nents, DMA_TO_DEVICE);
  1426. }
  1427. if (*prev_len) {
  1428. dev_dbg(dev, "Unmapped buffer: areq_ctx->buff_sg=%pK dma=%pad len 0x%X\n",
  1429. sg_virt(areq_ctx->buff_sg),
  1430. &sg_dma_address(areq_ctx->buff_sg),
  1431. sg_dma_len(areq_ctx->buff_sg));
  1432. dma_unmap_sg(dev, areq_ctx->buff_sg, 1, DMA_TO_DEVICE);
  1433. if (!do_revert) {
  1434. /* clean the previous data length for update
  1435. * operation
  1436. */
  1437. *prev_len = 0;
  1438. } else {
  1439. areq_ctx->buff_index ^= 1;
  1440. }
  1441. }
  1442. }
  1443. int cc_buffer_mgr_init(struct cc_drvdata *drvdata)
  1444. {
  1445. struct buff_mgr_handle *buff_mgr_handle;
  1446. struct device *dev = drvdata_to_dev(drvdata);
  1447. buff_mgr_handle = kmalloc(sizeof(*buff_mgr_handle), GFP_KERNEL);
  1448. if (!buff_mgr_handle)
  1449. return -ENOMEM;
  1450. drvdata->buff_mgr_handle = buff_mgr_handle;
  1451. buff_mgr_handle->mlli_buffs_pool =
  1452. dma_pool_create("dx_single_mlli_tables", dev,
  1453. MAX_NUM_OF_TOTAL_MLLI_ENTRIES *
  1454. LLI_ENTRY_BYTE_SIZE,
  1455. MLLI_TABLE_MIN_ALIGNMENT, 0);
  1456. if (!buff_mgr_handle->mlli_buffs_pool)
  1457. goto error;
  1458. return 0;
  1459. error:
  1460. cc_buffer_mgr_fini(drvdata);
  1461. return -ENOMEM;
  1462. }
  1463. int cc_buffer_mgr_fini(struct cc_drvdata *drvdata)
  1464. {
  1465. struct buff_mgr_handle *buff_mgr_handle = drvdata->buff_mgr_handle;
  1466. if (buff_mgr_handle) {
  1467. dma_pool_destroy(buff_mgr_handle->mlli_buffs_pool);
  1468. kfree(drvdata->buff_mgr_handle);
  1469. drvdata->buff_mgr_handle = NULL;
  1470. }
  1471. return 0;
  1472. }