ccp-dmaengine.c 18 KB

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  1. /*
  2. * AMD Cryptographic Coprocessor (CCP) driver
  3. *
  4. * Copyright (C) 2016,2017 Advanced Micro Devices, Inc.
  5. *
  6. * Author: Gary R Hook <gary.hook@amd.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/dmaengine.h>
  15. #include <linux/spinlock.h>
  16. #include <linux/mutex.h>
  17. #include <linux/ccp.h>
  18. #include "ccp-dev.h"
  19. #include "../../dma/dmaengine.h"
  20. #define CCP_DMA_WIDTH(_mask) \
  21. ({ \
  22. u64 mask = _mask + 1; \
  23. (mask == 0) ? 64 : fls64(mask); \
  24. })
  25. /* The CCP as a DMA provider can be configured for public or private
  26. * channels. Default is specified in the vdata for the device (PCI ID).
  27. * This module parameter will override for all channels on all devices:
  28. * dma_chan_attr = 0x2 to force all channels public
  29. * = 0x1 to force all channels private
  30. * = 0x0 to defer to the vdata setting
  31. * = any other value: warning, revert to 0x0
  32. */
  33. static unsigned int dma_chan_attr = CCP_DMA_DFLT;
  34. module_param(dma_chan_attr, uint, 0444);
  35. MODULE_PARM_DESC(dma_chan_attr, "Set DMA channel visibility: 0 (default) = device defaults, 1 = make private, 2 = make public");
  36. static unsigned int ccp_get_dma_chan_attr(struct ccp_device *ccp)
  37. {
  38. switch (dma_chan_attr) {
  39. case CCP_DMA_DFLT:
  40. return ccp->vdata->dma_chan_attr;
  41. case CCP_DMA_PRIV:
  42. return DMA_PRIVATE;
  43. case CCP_DMA_PUB:
  44. return 0;
  45. default:
  46. dev_info_once(ccp->dev, "Invalid value for dma_chan_attr: %d\n",
  47. dma_chan_attr);
  48. return ccp->vdata->dma_chan_attr;
  49. }
  50. }
  51. static void ccp_free_cmd_resources(struct ccp_device *ccp,
  52. struct list_head *list)
  53. {
  54. struct ccp_dma_cmd *cmd, *ctmp;
  55. list_for_each_entry_safe(cmd, ctmp, list, entry) {
  56. list_del(&cmd->entry);
  57. kmem_cache_free(ccp->dma_cmd_cache, cmd);
  58. }
  59. }
  60. static void ccp_free_desc_resources(struct ccp_device *ccp,
  61. struct list_head *list)
  62. {
  63. struct ccp_dma_desc *desc, *dtmp;
  64. list_for_each_entry_safe(desc, dtmp, list, entry) {
  65. ccp_free_cmd_resources(ccp, &desc->active);
  66. ccp_free_cmd_resources(ccp, &desc->pending);
  67. list_del(&desc->entry);
  68. kmem_cache_free(ccp->dma_desc_cache, desc);
  69. }
  70. }
  71. static void ccp_free_chan_resources(struct dma_chan *dma_chan)
  72. {
  73. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  74. dma_chan);
  75. unsigned long flags;
  76. dev_dbg(chan->ccp->dev, "%s - chan=%p\n", __func__, chan);
  77. spin_lock_irqsave(&chan->lock, flags);
  78. ccp_free_desc_resources(chan->ccp, &chan->complete);
  79. ccp_free_desc_resources(chan->ccp, &chan->active);
  80. ccp_free_desc_resources(chan->ccp, &chan->pending);
  81. ccp_free_desc_resources(chan->ccp, &chan->created);
  82. spin_unlock_irqrestore(&chan->lock, flags);
  83. }
  84. static void ccp_cleanup_desc_resources(struct ccp_device *ccp,
  85. struct list_head *list)
  86. {
  87. struct ccp_dma_desc *desc, *dtmp;
  88. list_for_each_entry_safe_reverse(desc, dtmp, list, entry) {
  89. if (!async_tx_test_ack(&desc->tx_desc))
  90. continue;
  91. dev_dbg(ccp->dev, "%s - desc=%p\n", __func__, desc);
  92. ccp_free_cmd_resources(ccp, &desc->active);
  93. ccp_free_cmd_resources(ccp, &desc->pending);
  94. list_del(&desc->entry);
  95. kmem_cache_free(ccp->dma_desc_cache, desc);
  96. }
  97. }
  98. static void ccp_do_cleanup(unsigned long data)
  99. {
  100. struct ccp_dma_chan *chan = (struct ccp_dma_chan *)data;
  101. unsigned long flags;
  102. dev_dbg(chan->ccp->dev, "%s - chan=%s\n", __func__,
  103. dma_chan_name(&chan->dma_chan));
  104. spin_lock_irqsave(&chan->lock, flags);
  105. ccp_cleanup_desc_resources(chan->ccp, &chan->complete);
  106. spin_unlock_irqrestore(&chan->lock, flags);
  107. }
  108. static int ccp_issue_next_cmd(struct ccp_dma_desc *desc)
  109. {
  110. struct ccp_dma_cmd *cmd;
  111. int ret;
  112. cmd = list_first_entry(&desc->pending, struct ccp_dma_cmd, entry);
  113. list_move(&cmd->entry, &desc->active);
  114. dev_dbg(desc->ccp->dev, "%s - tx %d, cmd=%p\n", __func__,
  115. desc->tx_desc.cookie, cmd);
  116. ret = ccp_enqueue_cmd(&cmd->ccp_cmd);
  117. if (!ret || (ret == -EINPROGRESS) || (ret == -EBUSY))
  118. return 0;
  119. dev_dbg(desc->ccp->dev, "%s - error: ret=%d, tx %d, cmd=%p\n", __func__,
  120. ret, desc->tx_desc.cookie, cmd);
  121. return ret;
  122. }
  123. static void ccp_free_active_cmd(struct ccp_dma_desc *desc)
  124. {
  125. struct ccp_dma_cmd *cmd;
  126. cmd = list_first_entry_or_null(&desc->active, struct ccp_dma_cmd,
  127. entry);
  128. if (!cmd)
  129. return;
  130. dev_dbg(desc->ccp->dev, "%s - freeing tx %d cmd=%p\n",
  131. __func__, desc->tx_desc.cookie, cmd);
  132. list_del(&cmd->entry);
  133. kmem_cache_free(desc->ccp->dma_cmd_cache, cmd);
  134. }
  135. static struct ccp_dma_desc *__ccp_next_dma_desc(struct ccp_dma_chan *chan,
  136. struct ccp_dma_desc *desc)
  137. {
  138. /* Move current DMA descriptor to the complete list */
  139. if (desc)
  140. list_move(&desc->entry, &chan->complete);
  141. /* Get the next DMA descriptor on the active list */
  142. desc = list_first_entry_or_null(&chan->active, struct ccp_dma_desc,
  143. entry);
  144. return desc;
  145. }
  146. static struct ccp_dma_desc *ccp_handle_active_desc(struct ccp_dma_chan *chan,
  147. struct ccp_dma_desc *desc)
  148. {
  149. struct dma_async_tx_descriptor *tx_desc;
  150. unsigned long flags;
  151. /* Loop over descriptors until one is found with commands */
  152. do {
  153. if (desc) {
  154. /* Remove the DMA command from the list and free it */
  155. ccp_free_active_cmd(desc);
  156. if (!list_empty(&desc->pending)) {
  157. /* No errors, keep going */
  158. if (desc->status != DMA_ERROR)
  159. return desc;
  160. /* Error, free remaining commands and move on */
  161. ccp_free_cmd_resources(desc->ccp,
  162. &desc->pending);
  163. }
  164. tx_desc = &desc->tx_desc;
  165. } else {
  166. tx_desc = NULL;
  167. }
  168. spin_lock_irqsave(&chan->lock, flags);
  169. if (desc) {
  170. if (desc->status != DMA_ERROR)
  171. desc->status = DMA_COMPLETE;
  172. dev_dbg(desc->ccp->dev,
  173. "%s - tx %d complete, status=%u\n", __func__,
  174. desc->tx_desc.cookie, desc->status);
  175. dma_cookie_complete(tx_desc);
  176. dma_descriptor_unmap(tx_desc);
  177. }
  178. desc = __ccp_next_dma_desc(chan, desc);
  179. spin_unlock_irqrestore(&chan->lock, flags);
  180. if (tx_desc) {
  181. dmaengine_desc_get_callback_invoke(tx_desc, NULL);
  182. dma_run_dependencies(tx_desc);
  183. }
  184. } while (desc);
  185. return NULL;
  186. }
  187. static struct ccp_dma_desc *__ccp_pending_to_active(struct ccp_dma_chan *chan)
  188. {
  189. struct ccp_dma_desc *desc;
  190. if (list_empty(&chan->pending))
  191. return NULL;
  192. desc = list_empty(&chan->active)
  193. ? list_first_entry(&chan->pending, struct ccp_dma_desc, entry)
  194. : NULL;
  195. list_splice_tail_init(&chan->pending, &chan->active);
  196. return desc;
  197. }
  198. static void ccp_cmd_callback(void *data, int err)
  199. {
  200. struct ccp_dma_desc *desc = data;
  201. struct ccp_dma_chan *chan;
  202. int ret;
  203. if (err == -EINPROGRESS)
  204. return;
  205. chan = container_of(desc->tx_desc.chan, struct ccp_dma_chan,
  206. dma_chan);
  207. dev_dbg(chan->ccp->dev, "%s - tx %d callback, err=%d\n",
  208. __func__, desc->tx_desc.cookie, err);
  209. if (err)
  210. desc->status = DMA_ERROR;
  211. while (true) {
  212. /* Check for DMA descriptor completion */
  213. desc = ccp_handle_active_desc(chan, desc);
  214. /* Don't submit cmd if no descriptor or DMA is paused */
  215. if (!desc || (chan->status == DMA_PAUSED))
  216. break;
  217. ret = ccp_issue_next_cmd(desc);
  218. if (!ret)
  219. break;
  220. desc->status = DMA_ERROR;
  221. }
  222. tasklet_schedule(&chan->cleanup_tasklet);
  223. }
  224. static dma_cookie_t ccp_tx_submit(struct dma_async_tx_descriptor *tx_desc)
  225. {
  226. struct ccp_dma_desc *desc = container_of(tx_desc, struct ccp_dma_desc,
  227. tx_desc);
  228. struct ccp_dma_chan *chan;
  229. dma_cookie_t cookie;
  230. unsigned long flags;
  231. chan = container_of(tx_desc->chan, struct ccp_dma_chan, dma_chan);
  232. spin_lock_irqsave(&chan->lock, flags);
  233. cookie = dma_cookie_assign(tx_desc);
  234. list_del(&desc->entry);
  235. list_add_tail(&desc->entry, &chan->pending);
  236. spin_unlock_irqrestore(&chan->lock, flags);
  237. dev_dbg(chan->ccp->dev, "%s - added tx descriptor %d to pending list\n",
  238. __func__, cookie);
  239. return cookie;
  240. }
  241. static struct ccp_dma_cmd *ccp_alloc_dma_cmd(struct ccp_dma_chan *chan)
  242. {
  243. struct ccp_dma_cmd *cmd;
  244. cmd = kmem_cache_alloc(chan->ccp->dma_cmd_cache, GFP_NOWAIT);
  245. if (cmd)
  246. memset(cmd, 0, sizeof(*cmd));
  247. return cmd;
  248. }
  249. static struct ccp_dma_desc *ccp_alloc_dma_desc(struct ccp_dma_chan *chan,
  250. unsigned long flags)
  251. {
  252. struct ccp_dma_desc *desc;
  253. desc = kmem_cache_zalloc(chan->ccp->dma_desc_cache, GFP_NOWAIT);
  254. if (!desc)
  255. return NULL;
  256. dma_async_tx_descriptor_init(&desc->tx_desc, &chan->dma_chan);
  257. desc->tx_desc.flags = flags;
  258. desc->tx_desc.tx_submit = ccp_tx_submit;
  259. desc->ccp = chan->ccp;
  260. INIT_LIST_HEAD(&desc->pending);
  261. INIT_LIST_HEAD(&desc->active);
  262. desc->status = DMA_IN_PROGRESS;
  263. return desc;
  264. }
  265. static struct ccp_dma_desc *ccp_create_desc(struct dma_chan *dma_chan,
  266. struct scatterlist *dst_sg,
  267. unsigned int dst_nents,
  268. struct scatterlist *src_sg,
  269. unsigned int src_nents,
  270. unsigned long flags)
  271. {
  272. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  273. dma_chan);
  274. struct ccp_device *ccp = chan->ccp;
  275. struct ccp_dma_desc *desc;
  276. struct ccp_dma_cmd *cmd;
  277. struct ccp_cmd *ccp_cmd;
  278. struct ccp_passthru_nomap_engine *ccp_pt;
  279. unsigned int src_offset, src_len;
  280. unsigned int dst_offset, dst_len;
  281. unsigned int len;
  282. unsigned long sflags;
  283. size_t total_len;
  284. if (!dst_sg || !src_sg)
  285. return NULL;
  286. if (!dst_nents || !src_nents)
  287. return NULL;
  288. desc = ccp_alloc_dma_desc(chan, flags);
  289. if (!desc)
  290. return NULL;
  291. total_len = 0;
  292. src_len = sg_dma_len(src_sg);
  293. src_offset = 0;
  294. dst_len = sg_dma_len(dst_sg);
  295. dst_offset = 0;
  296. while (true) {
  297. if (!src_len) {
  298. src_nents--;
  299. if (!src_nents)
  300. break;
  301. src_sg = sg_next(src_sg);
  302. if (!src_sg)
  303. break;
  304. src_len = sg_dma_len(src_sg);
  305. src_offset = 0;
  306. continue;
  307. }
  308. if (!dst_len) {
  309. dst_nents--;
  310. if (!dst_nents)
  311. break;
  312. dst_sg = sg_next(dst_sg);
  313. if (!dst_sg)
  314. break;
  315. dst_len = sg_dma_len(dst_sg);
  316. dst_offset = 0;
  317. continue;
  318. }
  319. len = min(dst_len, src_len);
  320. cmd = ccp_alloc_dma_cmd(chan);
  321. if (!cmd)
  322. goto err;
  323. ccp_cmd = &cmd->ccp_cmd;
  324. ccp_cmd->ccp = chan->ccp;
  325. ccp_pt = &ccp_cmd->u.passthru_nomap;
  326. ccp_cmd->flags = CCP_CMD_MAY_BACKLOG;
  327. ccp_cmd->flags |= CCP_CMD_PASSTHRU_NO_DMA_MAP;
  328. ccp_cmd->engine = CCP_ENGINE_PASSTHRU;
  329. ccp_pt->bit_mod = CCP_PASSTHRU_BITWISE_NOOP;
  330. ccp_pt->byte_swap = CCP_PASSTHRU_BYTESWAP_NOOP;
  331. ccp_pt->src_dma = sg_dma_address(src_sg) + src_offset;
  332. ccp_pt->dst_dma = sg_dma_address(dst_sg) + dst_offset;
  333. ccp_pt->src_len = len;
  334. ccp_pt->final = 1;
  335. ccp_cmd->callback = ccp_cmd_callback;
  336. ccp_cmd->data = desc;
  337. list_add_tail(&cmd->entry, &desc->pending);
  338. dev_dbg(ccp->dev,
  339. "%s - cmd=%p, src=%pad, dst=%pad, len=%llu\n", __func__,
  340. cmd, &ccp_pt->src_dma,
  341. &ccp_pt->dst_dma, ccp_pt->src_len);
  342. total_len += len;
  343. src_len -= len;
  344. src_offset += len;
  345. dst_len -= len;
  346. dst_offset += len;
  347. }
  348. desc->len = total_len;
  349. if (list_empty(&desc->pending))
  350. goto err;
  351. dev_dbg(ccp->dev, "%s - desc=%p\n", __func__, desc);
  352. spin_lock_irqsave(&chan->lock, sflags);
  353. list_add_tail(&desc->entry, &chan->created);
  354. spin_unlock_irqrestore(&chan->lock, sflags);
  355. return desc;
  356. err:
  357. ccp_free_cmd_resources(ccp, &desc->pending);
  358. kmem_cache_free(ccp->dma_desc_cache, desc);
  359. return NULL;
  360. }
  361. static struct dma_async_tx_descriptor *ccp_prep_dma_memcpy(
  362. struct dma_chan *dma_chan, dma_addr_t dst, dma_addr_t src, size_t len,
  363. unsigned long flags)
  364. {
  365. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  366. dma_chan);
  367. struct ccp_dma_desc *desc;
  368. struct scatterlist dst_sg, src_sg;
  369. dev_dbg(chan->ccp->dev,
  370. "%s - src=%pad, dst=%pad, len=%zu, flags=%#lx\n",
  371. __func__, &src, &dst, len, flags);
  372. sg_init_table(&dst_sg, 1);
  373. sg_dma_address(&dst_sg) = dst;
  374. sg_dma_len(&dst_sg) = len;
  375. sg_init_table(&src_sg, 1);
  376. sg_dma_address(&src_sg) = src;
  377. sg_dma_len(&src_sg) = len;
  378. desc = ccp_create_desc(dma_chan, &dst_sg, 1, &src_sg, 1, flags);
  379. if (!desc)
  380. return NULL;
  381. return &desc->tx_desc;
  382. }
  383. static struct dma_async_tx_descriptor *ccp_prep_dma_interrupt(
  384. struct dma_chan *dma_chan, unsigned long flags)
  385. {
  386. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  387. dma_chan);
  388. struct ccp_dma_desc *desc;
  389. desc = ccp_alloc_dma_desc(chan, flags);
  390. if (!desc)
  391. return NULL;
  392. return &desc->tx_desc;
  393. }
  394. static void ccp_issue_pending(struct dma_chan *dma_chan)
  395. {
  396. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  397. dma_chan);
  398. struct ccp_dma_desc *desc;
  399. unsigned long flags;
  400. dev_dbg(chan->ccp->dev, "%s\n", __func__);
  401. spin_lock_irqsave(&chan->lock, flags);
  402. desc = __ccp_pending_to_active(chan);
  403. spin_unlock_irqrestore(&chan->lock, flags);
  404. /* If there was nothing active, start processing */
  405. if (desc)
  406. ccp_cmd_callback(desc, 0);
  407. }
  408. static enum dma_status ccp_tx_status(struct dma_chan *dma_chan,
  409. dma_cookie_t cookie,
  410. struct dma_tx_state *state)
  411. {
  412. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  413. dma_chan);
  414. struct ccp_dma_desc *desc;
  415. enum dma_status ret;
  416. unsigned long flags;
  417. if (chan->status == DMA_PAUSED) {
  418. ret = DMA_PAUSED;
  419. goto out;
  420. }
  421. ret = dma_cookie_status(dma_chan, cookie, state);
  422. if (ret == DMA_COMPLETE) {
  423. spin_lock_irqsave(&chan->lock, flags);
  424. /* Get status from complete chain, if still there */
  425. list_for_each_entry(desc, &chan->complete, entry) {
  426. if (desc->tx_desc.cookie != cookie)
  427. continue;
  428. ret = desc->status;
  429. break;
  430. }
  431. spin_unlock_irqrestore(&chan->lock, flags);
  432. }
  433. out:
  434. dev_dbg(chan->ccp->dev, "%s - %u\n", __func__, ret);
  435. return ret;
  436. }
  437. static int ccp_pause(struct dma_chan *dma_chan)
  438. {
  439. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  440. dma_chan);
  441. chan->status = DMA_PAUSED;
  442. /*TODO: Wait for active DMA to complete before returning? */
  443. return 0;
  444. }
  445. static int ccp_resume(struct dma_chan *dma_chan)
  446. {
  447. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  448. dma_chan);
  449. struct ccp_dma_desc *desc;
  450. unsigned long flags;
  451. spin_lock_irqsave(&chan->lock, flags);
  452. desc = list_first_entry_or_null(&chan->active, struct ccp_dma_desc,
  453. entry);
  454. spin_unlock_irqrestore(&chan->lock, flags);
  455. /* Indicate the channel is running again */
  456. chan->status = DMA_IN_PROGRESS;
  457. /* If there was something active, re-start */
  458. if (desc)
  459. ccp_cmd_callback(desc, 0);
  460. return 0;
  461. }
  462. static int ccp_terminate_all(struct dma_chan *dma_chan)
  463. {
  464. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  465. dma_chan);
  466. unsigned long flags;
  467. dev_dbg(chan->ccp->dev, "%s\n", __func__);
  468. /*TODO: Wait for active DMA to complete before continuing */
  469. spin_lock_irqsave(&chan->lock, flags);
  470. /*TODO: Purge the complete list? */
  471. ccp_free_desc_resources(chan->ccp, &chan->active);
  472. ccp_free_desc_resources(chan->ccp, &chan->pending);
  473. ccp_free_desc_resources(chan->ccp, &chan->created);
  474. spin_unlock_irqrestore(&chan->lock, flags);
  475. return 0;
  476. }
  477. int ccp_dmaengine_register(struct ccp_device *ccp)
  478. {
  479. struct ccp_dma_chan *chan;
  480. struct dma_device *dma_dev = &ccp->dma_dev;
  481. struct dma_chan *dma_chan;
  482. char *dma_cmd_cache_name;
  483. char *dma_desc_cache_name;
  484. unsigned int i;
  485. int ret;
  486. ccp->ccp_dma_chan = devm_kcalloc(ccp->dev, ccp->cmd_q_count,
  487. sizeof(*(ccp->ccp_dma_chan)),
  488. GFP_KERNEL);
  489. if (!ccp->ccp_dma_chan)
  490. return -ENOMEM;
  491. dma_cmd_cache_name = devm_kasprintf(ccp->dev, GFP_KERNEL,
  492. "%s-dmaengine-cmd-cache",
  493. ccp->name);
  494. if (!dma_cmd_cache_name)
  495. return -ENOMEM;
  496. ccp->dma_cmd_cache = kmem_cache_create(dma_cmd_cache_name,
  497. sizeof(struct ccp_dma_cmd),
  498. sizeof(void *),
  499. SLAB_HWCACHE_ALIGN, NULL);
  500. if (!ccp->dma_cmd_cache)
  501. return -ENOMEM;
  502. dma_desc_cache_name = devm_kasprintf(ccp->dev, GFP_KERNEL,
  503. "%s-dmaengine-desc-cache",
  504. ccp->name);
  505. if (!dma_desc_cache_name) {
  506. ret = -ENOMEM;
  507. goto err_cache;
  508. }
  509. ccp->dma_desc_cache = kmem_cache_create(dma_desc_cache_name,
  510. sizeof(struct ccp_dma_desc),
  511. sizeof(void *),
  512. SLAB_HWCACHE_ALIGN, NULL);
  513. if (!ccp->dma_desc_cache) {
  514. ret = -ENOMEM;
  515. goto err_cache;
  516. }
  517. dma_dev->dev = ccp->dev;
  518. dma_dev->src_addr_widths = CCP_DMA_WIDTH(dma_get_mask(ccp->dev));
  519. dma_dev->dst_addr_widths = CCP_DMA_WIDTH(dma_get_mask(ccp->dev));
  520. dma_dev->directions = DMA_MEM_TO_MEM;
  521. dma_dev->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
  522. dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
  523. dma_cap_set(DMA_INTERRUPT, dma_dev->cap_mask);
  524. /* The DMA channels for this device can be set to public or private,
  525. * and overridden by the module parameter dma_chan_attr.
  526. * Default: according to the value in vdata (dma_chan_attr=0)
  527. * dma_chan_attr=0x1: all channels private (override vdata)
  528. * dma_chan_attr=0x2: all channels public (override vdata)
  529. */
  530. if (ccp_get_dma_chan_attr(ccp) == DMA_PRIVATE)
  531. dma_cap_set(DMA_PRIVATE, dma_dev->cap_mask);
  532. INIT_LIST_HEAD(&dma_dev->channels);
  533. for (i = 0; i < ccp->cmd_q_count; i++) {
  534. chan = ccp->ccp_dma_chan + i;
  535. dma_chan = &chan->dma_chan;
  536. chan->ccp = ccp;
  537. spin_lock_init(&chan->lock);
  538. INIT_LIST_HEAD(&chan->created);
  539. INIT_LIST_HEAD(&chan->pending);
  540. INIT_LIST_HEAD(&chan->active);
  541. INIT_LIST_HEAD(&chan->complete);
  542. tasklet_init(&chan->cleanup_tasklet, ccp_do_cleanup,
  543. (unsigned long)chan);
  544. dma_chan->device = dma_dev;
  545. dma_cookie_init(dma_chan);
  546. list_add_tail(&dma_chan->device_node, &dma_dev->channels);
  547. }
  548. dma_dev->device_free_chan_resources = ccp_free_chan_resources;
  549. dma_dev->device_prep_dma_memcpy = ccp_prep_dma_memcpy;
  550. dma_dev->device_prep_dma_interrupt = ccp_prep_dma_interrupt;
  551. dma_dev->device_issue_pending = ccp_issue_pending;
  552. dma_dev->device_tx_status = ccp_tx_status;
  553. dma_dev->device_pause = ccp_pause;
  554. dma_dev->device_resume = ccp_resume;
  555. dma_dev->device_terminate_all = ccp_terminate_all;
  556. ret = dma_async_device_register(dma_dev);
  557. if (ret)
  558. goto err_reg;
  559. return 0;
  560. err_reg:
  561. kmem_cache_destroy(ccp->dma_desc_cache);
  562. err_cache:
  563. kmem_cache_destroy(ccp->dma_cmd_cache);
  564. return ret;
  565. }
  566. void ccp_dmaengine_unregister(struct ccp_device *ccp)
  567. {
  568. struct dma_device *dma_dev = &ccp->dma_dev;
  569. dma_async_device_unregister(dma_dev);
  570. kmem_cache_destroy(ccp->dma_desc_cache);
  571. kmem_cache_destroy(ccp->dma_cmd_cache);
  572. }