clk-hi655x.c 3.2 KB

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  1. /*
  2. * Clock driver for Hi655x
  3. *
  4. * Copyright (c) 2017, Linaro Ltd.
  5. *
  6. * Author: Daniel Lezcano <daniel.lezcano@linaro.org>
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms and conditions of the GNU General Public License,
  10. * version 2, as published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. */
  17. #include <linux/clk-provider.h>
  18. #include <linux/module.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/regmap.h>
  21. #include <linux/slab.h>
  22. #include <linux/mfd/core.h>
  23. #include <linux/mfd/hi655x-pmic.h>
  24. #define HI655X_CLK_BASE HI655X_BUS_ADDR(0x1c)
  25. #define HI655X_CLK_SET BIT(6)
  26. struct hi655x_clk {
  27. struct hi655x_pmic *hi655x;
  28. struct clk_hw clk_hw;
  29. };
  30. static unsigned long hi655x_clk_recalc_rate(struct clk_hw *hw,
  31. unsigned long parent_rate)
  32. {
  33. return 32768;
  34. }
  35. static int hi655x_clk_enable(struct clk_hw *hw, bool enable)
  36. {
  37. struct hi655x_clk *hi655x_clk =
  38. container_of(hw, struct hi655x_clk, clk_hw);
  39. struct hi655x_pmic *hi655x = hi655x_clk->hi655x;
  40. return regmap_update_bits(hi655x->regmap, HI655X_CLK_BASE,
  41. HI655X_CLK_SET, enable ? HI655X_CLK_SET : 0);
  42. }
  43. static int hi655x_clk_prepare(struct clk_hw *hw)
  44. {
  45. return hi655x_clk_enable(hw, true);
  46. }
  47. static void hi655x_clk_unprepare(struct clk_hw *hw)
  48. {
  49. hi655x_clk_enable(hw, false);
  50. }
  51. static int hi655x_clk_is_prepared(struct clk_hw *hw)
  52. {
  53. struct hi655x_clk *hi655x_clk =
  54. container_of(hw, struct hi655x_clk, clk_hw);
  55. struct hi655x_pmic *hi655x = hi655x_clk->hi655x;
  56. int ret;
  57. uint32_t val;
  58. ret = regmap_read(hi655x->regmap, HI655X_CLK_BASE, &val);
  59. if (ret < 0)
  60. return ret;
  61. return val & HI655X_CLK_BASE;
  62. }
  63. static const struct clk_ops hi655x_clk_ops = {
  64. .prepare = hi655x_clk_prepare,
  65. .unprepare = hi655x_clk_unprepare,
  66. .is_prepared = hi655x_clk_is_prepared,
  67. .recalc_rate = hi655x_clk_recalc_rate,
  68. };
  69. static int hi655x_clk_probe(struct platform_device *pdev)
  70. {
  71. struct device *parent = pdev->dev.parent;
  72. struct hi655x_pmic *hi655x = dev_get_drvdata(parent);
  73. struct hi655x_clk *hi655x_clk;
  74. const char *clk_name = "hi655x-clk";
  75. struct clk_init_data init = {
  76. .name = clk_name,
  77. .ops = &hi655x_clk_ops
  78. };
  79. int ret;
  80. hi655x_clk = devm_kzalloc(&pdev->dev, sizeof(*hi655x_clk), GFP_KERNEL);
  81. if (!hi655x_clk)
  82. return -ENOMEM;
  83. of_property_read_string_index(parent->of_node, "clock-output-names",
  84. 0, &clk_name);
  85. hi655x_clk->clk_hw.init = &init;
  86. hi655x_clk->hi655x = hi655x;
  87. platform_set_drvdata(pdev, hi655x_clk);
  88. ret = devm_clk_hw_register(&pdev->dev, &hi655x_clk->clk_hw);
  89. if (ret)
  90. return ret;
  91. return of_clk_add_hw_provider(parent->of_node, of_clk_hw_simple_get,
  92. &hi655x_clk->clk_hw);
  93. }
  94. static struct platform_driver hi655x_clk_driver = {
  95. .probe = hi655x_clk_probe,
  96. .driver = {
  97. .name = "hi655x-clk",
  98. },
  99. };
  100. module_platform_driver(hi655x_clk_driver);
  101. MODULE_DESCRIPTION("Clk driver for the hi655x series PMICs");
  102. MODULE_AUTHOR("Daniel Lezcano <daniel.lezcano@linaro.org>");
  103. MODULE_LICENSE("GPL");
  104. MODULE_ALIAS("platform:hi655x-clk");