sama5d4.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <linux/clk-provider.h>
  3. #include <linux/mfd/syscon.h>
  4. #include <linux/slab.h>
  5. #include <dt-bindings/clock/at91.h>
  6. #include "pmc.h"
  7. static const struct clk_master_characteristics mck_characteristics = {
  8. .output = { .min = 125000000, .max = 200000000 },
  9. .divisors = { 1, 2, 4, 3 },
  10. };
  11. static u8 plla_out[] = { 0 };
  12. static u16 plla_icpll[] = { 0 };
  13. static struct clk_range plla_outputs[] = {
  14. { .min = 600000000, .max = 1200000000 },
  15. };
  16. static const struct clk_pll_characteristics plla_characteristics = {
  17. .input = { .min = 12000000, .max = 12000000 },
  18. .num_output = ARRAY_SIZE(plla_outputs),
  19. .output = plla_outputs,
  20. .icpll = plla_icpll,
  21. .out = plla_out,
  22. };
  23. static const struct {
  24. char *n;
  25. char *p;
  26. u8 id;
  27. } sama5d4_systemck[] = {
  28. { .n = "ddrck", .p = "masterck", .id = 2 },
  29. { .n = "lcdck", .p = "masterck", .id = 3 },
  30. { .n = "smdck", .p = "smdclk", .id = 4 },
  31. { .n = "uhpck", .p = "usbck", .id = 6 },
  32. { .n = "udpck", .p = "usbck", .id = 7 },
  33. { .n = "pck0", .p = "prog0", .id = 8 },
  34. { .n = "pck1", .p = "prog1", .id = 9 },
  35. { .n = "pck2", .p = "prog2", .id = 10 },
  36. };
  37. static const struct {
  38. char *n;
  39. u8 id;
  40. } sama5d4_periph32ck[] = {
  41. { .n = "pioD_clk", .id = 5 },
  42. { .n = "usart0_clk", .id = 6 },
  43. { .n = "usart1_clk", .id = 7 },
  44. { .n = "icm_clk", .id = 9 },
  45. { .n = "aes_clk", .id = 12 },
  46. { .n = "tdes_clk", .id = 14 },
  47. { .n = "sha_clk", .id = 15 },
  48. { .n = "matrix1_clk", .id = 17 },
  49. { .n = "hsmc_clk", .id = 22 },
  50. { .n = "pioA_clk", .id = 23 },
  51. { .n = "pioB_clk", .id = 24 },
  52. { .n = "pioC_clk", .id = 25 },
  53. { .n = "pioE_clk", .id = 26 },
  54. { .n = "uart0_clk", .id = 27 },
  55. { .n = "uart1_clk", .id = 28 },
  56. { .n = "usart2_clk", .id = 29 },
  57. { .n = "usart3_clk", .id = 30 },
  58. { .n = "usart4_clk", .id = 31 },
  59. { .n = "twi0_clk", .id = 32 },
  60. { .n = "twi1_clk", .id = 33 },
  61. { .n = "twi2_clk", .id = 34 },
  62. { .n = "mci0_clk", .id = 35 },
  63. { .n = "mci1_clk", .id = 36 },
  64. { .n = "spi0_clk", .id = 37 },
  65. { .n = "spi1_clk", .id = 38 },
  66. { .n = "spi2_clk", .id = 39 },
  67. { .n = "tcb0_clk", .id = 40 },
  68. { .n = "tcb1_clk", .id = 41 },
  69. { .n = "tcb2_clk", .id = 42 },
  70. { .n = "pwm_clk", .id = 43 },
  71. { .n = "adc_clk", .id = 44 },
  72. { .n = "dbgu_clk", .id = 45 },
  73. { .n = "uhphs_clk", .id = 46 },
  74. { .n = "udphs_clk", .id = 47 },
  75. { .n = "ssc0_clk", .id = 48 },
  76. { .n = "ssc1_clk", .id = 49 },
  77. { .n = "trng_clk", .id = 53 },
  78. { .n = "macb0_clk", .id = 54 },
  79. { .n = "macb1_clk", .id = 55 },
  80. { .n = "fuse_clk", .id = 57 },
  81. { .n = "securam_clk", .id = 59 },
  82. { .n = "smd_clk", .id = 61 },
  83. { .n = "twi3_clk", .id = 62 },
  84. { .n = "catb_clk", .id = 63 },
  85. };
  86. static const struct {
  87. char *n;
  88. u8 id;
  89. } sama5d4_periphck[] = {
  90. { .n = "dma0_clk", .id = 8 },
  91. { .n = "cpkcc_clk", .id = 10 },
  92. { .n = "aesb_clk", .id = 13 },
  93. { .n = "mpddr_clk", .id = 16 },
  94. { .n = "matrix0_clk", .id = 18 },
  95. { .n = "vdec_clk", .id = 19 },
  96. { .n = "dma1_clk", .id = 50 },
  97. { .n = "lcdc_clk", .id = 51 },
  98. { .n = "isi_clk", .id = 52 },
  99. };
  100. static void __init sama5d4_pmc_setup(struct device_node *np)
  101. {
  102. struct clk_range range = CLK_RANGE(0, 0);
  103. const char *slck_name, *mainxtal_name;
  104. struct pmc_data *sama5d4_pmc;
  105. const char *parent_names[5];
  106. struct regmap *regmap;
  107. struct clk_hw *hw;
  108. int i;
  109. bool bypass;
  110. i = of_property_match_string(np, "clock-names", "slow_clk");
  111. if (i < 0)
  112. return;
  113. slck_name = of_clk_get_parent_name(np, i);
  114. i = of_property_match_string(np, "clock-names", "main_xtal");
  115. if (i < 0)
  116. return;
  117. mainxtal_name = of_clk_get_parent_name(np, i);
  118. regmap = syscon_node_to_regmap(np);
  119. if (IS_ERR(regmap))
  120. return;
  121. sama5d4_pmc = pmc_data_allocate(PMC_MCK2 + 1,
  122. nck(sama5d4_systemck),
  123. nck(sama5d4_periph32ck), 0);
  124. if (!sama5d4_pmc)
  125. return;
  126. hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
  127. 100000000);
  128. if (IS_ERR(hw))
  129. goto err_free;
  130. bypass = of_property_read_bool(np, "atmel,osc-bypass");
  131. hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
  132. bypass);
  133. if (IS_ERR(hw))
  134. goto err_free;
  135. parent_names[0] = "main_rc_osc";
  136. parent_names[1] = "main_osc";
  137. hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
  138. if (IS_ERR(hw))
  139. goto err_free;
  140. hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
  141. &sama5d3_pll_layout, &plla_characteristics);
  142. if (IS_ERR(hw))
  143. goto err_free;
  144. hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
  145. if (IS_ERR(hw))
  146. goto err_free;
  147. hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
  148. if (IS_ERR(hw))
  149. goto err_free;
  150. sama5d4_pmc->chws[PMC_UTMI] = hw;
  151. parent_names[0] = slck_name;
  152. parent_names[1] = "mainck";
  153. parent_names[2] = "plladivck";
  154. parent_names[3] = "utmick";
  155. hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
  156. &at91sam9x5_master_layout,
  157. &mck_characteristics);
  158. if (IS_ERR(hw))
  159. goto err_free;
  160. sama5d4_pmc->chws[PMC_MCK] = hw;
  161. hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck");
  162. if (IS_ERR(hw))
  163. goto err_free;
  164. sama5d4_pmc->chws[PMC_MCK2] = hw;
  165. parent_names[0] = "plladivck";
  166. parent_names[1] = "utmick";
  167. hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
  168. if (IS_ERR(hw))
  169. goto err_free;
  170. parent_names[0] = "plladivck";
  171. parent_names[1] = "utmick";
  172. hw = at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2);
  173. if (IS_ERR(hw))
  174. goto err_free;
  175. parent_names[0] = slck_name;
  176. parent_names[1] = "mainck";
  177. parent_names[2] = "plladivck";
  178. parent_names[3] = "utmick";
  179. parent_names[4] = "mck";
  180. for (i = 0; i < 3; i++) {
  181. char name[6];
  182. snprintf(name, sizeof(name), "prog%d", i);
  183. hw = at91_clk_register_programmable(regmap, name,
  184. parent_names, 5, i,
  185. &at91sam9x5_programmable_layout);
  186. if (IS_ERR(hw))
  187. goto err_free;
  188. }
  189. for (i = 0; i < ARRAY_SIZE(sama5d4_systemck); i++) {
  190. hw = at91_clk_register_system(regmap, sama5d4_systemck[i].n,
  191. sama5d4_systemck[i].p,
  192. sama5d4_systemck[i].id);
  193. if (IS_ERR(hw))
  194. goto err_free;
  195. sama5d4_pmc->shws[sama5d4_systemck[i].id] = hw;
  196. }
  197. for (i = 0; i < ARRAY_SIZE(sama5d4_periphck); i++) {
  198. hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
  199. sama5d4_periphck[i].n,
  200. "masterck",
  201. sama5d4_periphck[i].id,
  202. &range);
  203. if (IS_ERR(hw))
  204. goto err_free;
  205. sama5d4_pmc->phws[sama5d4_periphck[i].id] = hw;
  206. }
  207. for (i = 0; i < ARRAY_SIZE(sama5d4_periph32ck); i++) {
  208. hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
  209. sama5d4_periph32ck[i].n,
  210. "h32mxck",
  211. sama5d4_periph32ck[i].id,
  212. &range);
  213. if (IS_ERR(hw))
  214. goto err_free;
  215. sama5d4_pmc->phws[sama5d4_periph32ck[i].id] = hw;
  216. }
  217. of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama5d4_pmc);
  218. return;
  219. err_free:
  220. pmc_data_free(sama5d4_pmc);
  221. }
  222. CLK_OF_DECLARE_DRIVER(sama5d4_pmc, "atmel,sama5d4-pmc", sama5d4_pmc_setup);