clk-smd.c 3.3 KB

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  1. /*
  2. * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. */
  10. #include <linux/clk-provider.h>
  11. #include <linux/clkdev.h>
  12. #include <linux/clk/at91_pmc.h>
  13. #include <linux/of.h>
  14. #include <linux/mfd/syscon.h>
  15. #include <linux/regmap.h>
  16. #include "pmc.h"
  17. #define SMD_DIV_SHIFT 8
  18. #define SMD_MAX_DIV 0xf
  19. struct at91sam9x5_clk_smd {
  20. struct clk_hw hw;
  21. struct regmap *regmap;
  22. };
  23. #define to_at91sam9x5_clk_smd(hw) \
  24. container_of(hw, struct at91sam9x5_clk_smd, hw)
  25. static unsigned long at91sam9x5_clk_smd_recalc_rate(struct clk_hw *hw,
  26. unsigned long parent_rate)
  27. {
  28. struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw);
  29. unsigned int smdr;
  30. u8 smddiv;
  31. regmap_read(smd->regmap, AT91_PMC_SMD, &smdr);
  32. smddiv = (smdr & AT91_PMC_SMD_DIV) >> SMD_DIV_SHIFT;
  33. return parent_rate / (smddiv + 1);
  34. }
  35. static long at91sam9x5_clk_smd_round_rate(struct clk_hw *hw, unsigned long rate,
  36. unsigned long *parent_rate)
  37. {
  38. unsigned long div;
  39. unsigned long bestrate;
  40. unsigned long tmp;
  41. if (rate >= *parent_rate)
  42. return *parent_rate;
  43. div = *parent_rate / rate;
  44. if (div > SMD_MAX_DIV)
  45. return *parent_rate / (SMD_MAX_DIV + 1);
  46. bestrate = *parent_rate / div;
  47. tmp = *parent_rate / (div + 1);
  48. if (bestrate - rate > rate - tmp)
  49. bestrate = tmp;
  50. return bestrate;
  51. }
  52. static int at91sam9x5_clk_smd_set_parent(struct clk_hw *hw, u8 index)
  53. {
  54. struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw);
  55. if (index > 1)
  56. return -EINVAL;
  57. regmap_update_bits(smd->regmap, AT91_PMC_SMD, AT91_PMC_SMDS,
  58. index ? AT91_PMC_SMDS : 0);
  59. return 0;
  60. }
  61. static u8 at91sam9x5_clk_smd_get_parent(struct clk_hw *hw)
  62. {
  63. struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw);
  64. unsigned int smdr;
  65. regmap_read(smd->regmap, AT91_PMC_SMD, &smdr);
  66. return smdr & AT91_PMC_SMDS;
  67. }
  68. static int at91sam9x5_clk_smd_set_rate(struct clk_hw *hw, unsigned long rate,
  69. unsigned long parent_rate)
  70. {
  71. struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw);
  72. unsigned long div = parent_rate / rate;
  73. if (parent_rate % rate || div < 1 || div > (SMD_MAX_DIV + 1))
  74. return -EINVAL;
  75. regmap_update_bits(smd->regmap, AT91_PMC_SMD, AT91_PMC_SMD_DIV,
  76. (div - 1) << SMD_DIV_SHIFT);
  77. return 0;
  78. }
  79. static const struct clk_ops at91sam9x5_smd_ops = {
  80. .recalc_rate = at91sam9x5_clk_smd_recalc_rate,
  81. .round_rate = at91sam9x5_clk_smd_round_rate,
  82. .get_parent = at91sam9x5_clk_smd_get_parent,
  83. .set_parent = at91sam9x5_clk_smd_set_parent,
  84. .set_rate = at91sam9x5_clk_smd_set_rate,
  85. };
  86. struct clk_hw * __init
  87. at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name,
  88. const char **parent_names, u8 num_parents)
  89. {
  90. struct at91sam9x5_clk_smd *smd;
  91. struct clk_hw *hw;
  92. struct clk_init_data init;
  93. int ret;
  94. smd = kzalloc(sizeof(*smd), GFP_KERNEL);
  95. if (!smd)
  96. return ERR_PTR(-ENOMEM);
  97. init.name = name;
  98. init.ops = &at91sam9x5_smd_ops;
  99. init.parent_names = parent_names;
  100. init.num_parents = num_parents;
  101. init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
  102. smd->hw.init = &init;
  103. smd->regmap = regmap;
  104. hw = &smd->hw;
  105. ret = clk_hw_register(NULL, &smd->hw);
  106. if (ret) {
  107. kfree(smd);
  108. hw = ERR_PTR(ret);
  109. }
  110. return hw;
  111. }