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unicore32
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include
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mach
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regs-nand.h

regs-nand.h 1.7 KB
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  1. /* SPDX-License-Identifier: GPL-2.0 */
    2. 

  2. /*
    3. 

  3.  * PKUnity NAND Controller Registers
    4. 

  4.  */
    5. 

  5. /*
    6. 

  6.  * ID Reg. 0 NAND_IDR0
    7. 

  7.  */
    8. 

  8. #define NAND_IDR0	(PKUNITY_NAND_BASE + 0x0000)
    9. 

  9. /*
    10. 

  10.  * ID Reg. 1 NAND_IDR1
    11. 

  11.  */
    12. 

  12. #define NAND_IDR1	(PKUNITY_NAND_BASE + 0x0004)
    13. 

  13. /*
    14. 

  14.  * ID Reg. 2 NAND_IDR2
    15. 

  15.  */
    16. 

  16. #define NAND_IDR2	(PKUNITY_NAND_BASE + 0x0008)
    17. 

  17. /*
    18. 

  18.  * ID Reg. 3 NAND_IDR3
    19. 

  19.  */
    20. 

  20. #define NAND_IDR3	(PKUNITY_NAND_BASE + 0x000C)
    21. 

  21. /*
    22. 

  22.  * Page Address Reg 0 NAND_PAR0
    23. 

  23.  */
    24. 

  24. #define NAND_PAR0	(PKUNITY_NAND_BASE + 0x0010)
    25. 

  25. /*
    26. 

  26.  * Page Address Reg 1 NAND_PAR1
    27. 

  27.  */
    28. 

  28. #define NAND_PAR1	(PKUNITY_NAND_BASE + 0x0014)
    29. 

  29. /*
    30. 

  30.  * Page Address Reg 2 NAND_PAR2
    31. 

  31.  */
    32. 

  32. #define NAND_PAR2	(PKUNITY_NAND_BASE + 0x0018)
    33. 

  33. /*
    34. 

  34.  * ECC Enable Reg NAND_ECCEN
    35. 

  35.  */
    36. 

  36. #define NAND_ECCEN	(PKUNITY_NAND_BASE + 0x001C)
    37. 

  37. /*
    38. 

  38.  * Buffer Reg NAND_BUF
    39. 

  39.  */
    40. 

  40. #define NAND_BUF	(PKUNITY_NAND_BASE + 0x0020)
    41. 

  41. /*
    42. 

  42.  * ECC Status Reg NAND_ECCSR
    43. 

  43.  */
    44. 

  44. #define NAND_ECCSR	(PKUNITY_NAND_BASE + 0x0024)
    45. 

  45. /*
    46. 

  46.  * Command Reg NAND_CMD
    47. 

  47.  */
    48. 

  48. #define NAND_CMD	(PKUNITY_NAND_BASE + 0x0028)
    49. 

  49. /*
    50. 

  50.  * DMA Configure Reg NAND_DMACR
    51. 

  51.  */
    52. 

  52. #define NAND_DMACR	(PKUNITY_NAND_BASE + 0x002C)
    53. 

  53. /*
    54. 

  54.  * Interrupt Reg NAND_IR
    55. 

  55.  */
    56. 

  56. #define NAND_IR		(PKUNITY_NAND_BASE + 0x0030)
    57. 

  57. /*
    58. 

  58.  * Interrupt Mask Reg NAND_IMR
    59. 

  59.  */
    60. 

  60. #define NAND_IMR	(PKUNITY_NAND_BASE + 0x0034)
    61. 

  61. /*
    62. 

  62.  * Chip Enable Reg NAND_CHIPEN
    63. 

  63.  */
    64. 

  64. #define NAND_CHIPEN	(PKUNITY_NAND_BASE + 0x0038)
    65. 

  65. /*
    66. 

  66.  * Address Reg NAND_ADDR
    67. 

  67.  */
    68. 

  68. #define NAND_ADDR	(PKUNITY_NAND_BASE + 0x003C)
    69. 

  69. 

  70. /*
    71. 

  71.  * Command bits NAND_CMD_CMD_MASK
    72. 

  72.  */
    73. 

  73. #define NAND_CMD_CMD_MASK		FMASK(4, 4)
    74. 

  74. #define NAND_CMD_CMD_READPAGE		FIELD(0x0, 4, 4)
    75. 

  75. #define NAND_CMD_CMD_ERASEBLOCK		FIELD(0x6, 4, 4)
    76. 

  76. #define NAND_CMD_CMD_READSTATUS		FIELD(0x7, 4, 4)
    77. 

  77. #define NAND_CMD_CMD_WRITEPAGE		FIELD(0x8, 4, 4)
    78. 

  78. #define NAND_CMD_CMD_READID		FIELD(0x9, 4, 4)
    79. 

  79. #define NAND_CMD_CMD_RESET		FIELD(0xf, 4, 4)
    80. 

  80.