setup-sh770x.c 6.4 KB

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  1. /*
  2. * SH3 Setup code for SH7706, SH7707, SH7708, SH7709
  3. *
  4. * Copyright (C) 2007 Magnus Damm
  5. * Copyright (C) 2009 Paul Mundt
  6. *
  7. * Based on setup-sh7709.c
  8. *
  9. * Copyright (C) 2006 Paul Mundt
  10. *
  11. * This file is subject to the terms and conditions of the GNU General Public
  12. * License. See the file "COPYING" in the main directory of this archive
  13. * for more details.
  14. */
  15. #include <linux/init.h>
  16. #include <linux/io.h>
  17. #include <linux/irq.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/serial.h>
  20. #include <linux/serial_sci.h>
  21. #include <linux/sh_timer.h>
  22. #include <linux/sh_intc.h>
  23. #include <cpu/serial.h>
  24. enum {
  25. UNUSED = 0,
  26. /* interrupt sources */
  27. IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
  28. PINT07, PINT815,
  29. DMAC, SCIF0, SCIF2, SCI, ADC_ADI,
  30. LCDC, PCC0, PCC1,
  31. TMU0, TMU1, TMU2,
  32. RTC, WDT, REF,
  33. };
  34. static struct intc_vect vectors[] __initdata = {
  35. INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
  36. INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
  37. INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
  38. INTC_VECT(RTC, 0x4c0),
  39. INTC_VECT(SCI, 0x4e0), INTC_VECT(SCI, 0x500),
  40. INTC_VECT(SCI, 0x520), INTC_VECT(SCI, 0x540),
  41. INTC_VECT(WDT, 0x560),
  42. INTC_VECT(REF, 0x580),
  43. INTC_VECT(REF, 0x5a0),
  44. #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  45. defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  46. defined(CONFIG_CPU_SUBTYPE_SH7709)
  47. /* IRQ0->5 are handled in setup-sh3.c */
  48. INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820),
  49. INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860),
  50. INTC_VECT(ADC_ADI, 0x980),
  51. INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920),
  52. INTC_VECT(SCIF2, 0x940), INTC_VECT(SCIF2, 0x960),
  53. #endif
  54. #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  55. defined(CONFIG_CPU_SUBTYPE_SH7709)
  56. INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
  57. INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
  58. INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0),
  59. #endif
  60. #if defined(CONFIG_CPU_SUBTYPE_SH7707)
  61. INTC_VECT(LCDC, 0x9a0),
  62. INTC_VECT(PCC0, 0x9c0), INTC_VECT(PCC1, 0x9e0),
  63. #endif
  64. };
  65. static struct intc_prio_reg prio_registers[] __initdata = {
  66. { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
  67. { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },
  68. #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  69. defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  70. defined(CONFIG_CPU_SUBTYPE_SH7709)
  71. { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
  72. { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
  73. { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } },
  74. #endif
  75. #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  76. defined(CONFIG_CPU_SUBTYPE_SH7709)
  77. { 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, } },
  78. { 0xa400001a, 0, 16, 4, /* IPRE */ { 0, SCIF0 } },
  79. #endif
  80. #if defined(CONFIG_CPU_SUBTYPE_SH7707)
  81. { 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } },
  82. #endif
  83. };
  84. static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, NULL,
  85. NULL, prio_registers, NULL);
  86. static struct resource rtc_resources[] = {
  87. [0] = {
  88. .start = 0xfffffec0,
  89. .end = 0xfffffec0 + 0x1e,
  90. .flags = IORESOURCE_IO,
  91. },
  92. [1] = {
  93. .start = evt2irq(0x480),
  94. .flags = IORESOURCE_IRQ,
  95. },
  96. };
  97. static struct platform_device rtc_device = {
  98. .name = "sh-rtc",
  99. .id = -1,
  100. .num_resources = ARRAY_SIZE(rtc_resources),
  101. .resource = rtc_resources,
  102. };
  103. static struct plat_sci_port scif0_platform_data = {
  104. .type = PORT_SCI,
  105. .ops = &sh770x_sci_port_ops,
  106. };
  107. static struct resource scif0_resources[] = {
  108. DEFINE_RES_MEM(0xfffffe80, 0x10),
  109. DEFINE_RES_IRQ(evt2irq(0x4e0)),
  110. };
  111. static struct platform_device scif0_device = {
  112. .name = "sh-sci",
  113. .id = 0,
  114. .resource = scif0_resources,
  115. .num_resources = ARRAY_SIZE(scif0_resources),
  116. .dev = {
  117. .platform_data = &scif0_platform_data,
  118. },
  119. };
  120. #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  121. defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  122. defined(CONFIG_CPU_SUBTYPE_SH7709)
  123. static struct plat_sci_port scif1_platform_data = {
  124. .type = PORT_SCIF,
  125. .ops = &sh770x_sci_port_ops,
  126. .regtype = SCIx_SH3_SCIF_REGTYPE,
  127. };
  128. static struct resource scif1_resources[] = {
  129. DEFINE_RES_MEM(0xa4000150, 0x10),
  130. DEFINE_RES_IRQ(evt2irq(0x900)),
  131. };
  132. static struct platform_device scif1_device = {
  133. .name = "sh-sci",
  134. .id = 1,
  135. .resource = scif1_resources,
  136. .num_resources = ARRAY_SIZE(scif1_resources),
  137. .dev = {
  138. .platform_data = &scif1_platform_data,
  139. },
  140. };
  141. #endif
  142. #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  143. defined(CONFIG_CPU_SUBTYPE_SH7709)
  144. static struct plat_sci_port scif2_platform_data = {
  145. .type = PORT_IRDA,
  146. .ops = &sh770x_sci_port_ops,
  147. };
  148. static struct resource scif2_resources[] = {
  149. DEFINE_RES_MEM(0xa4000140, 0x10),
  150. DEFINE_RES_IRQ(evt2irq(0x880)),
  151. };
  152. static struct platform_device scif2_device = {
  153. .name = "sh-sci",
  154. .id = 2,
  155. .resource = scif2_resources,
  156. .num_resources = ARRAY_SIZE(scif2_resources),
  157. .dev = {
  158. .platform_data = &scif2_platform_data,
  159. },
  160. };
  161. #endif
  162. static struct sh_timer_config tmu0_platform_data = {
  163. .channels_mask = 7,
  164. };
  165. static struct resource tmu0_resources[] = {
  166. DEFINE_RES_MEM(0xfffffe90, 0x2c),
  167. DEFINE_RES_IRQ(evt2irq(0x400)),
  168. DEFINE_RES_IRQ(evt2irq(0x420)),
  169. DEFINE_RES_IRQ(evt2irq(0x440)),
  170. };
  171. static struct platform_device tmu0_device = {
  172. .name = "sh-tmu-sh3",
  173. .id = 0,
  174. .dev = {
  175. .platform_data = &tmu0_platform_data,
  176. },
  177. .resource = tmu0_resources,
  178. .num_resources = ARRAY_SIZE(tmu0_resources),
  179. };
  180. static struct platform_device *sh770x_devices[] __initdata = {
  181. &scif0_device,
  182. #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  183. defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  184. defined(CONFIG_CPU_SUBTYPE_SH7709)
  185. &scif1_device,
  186. #endif
  187. #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  188. defined(CONFIG_CPU_SUBTYPE_SH7709)
  189. &scif2_device,
  190. #endif
  191. &tmu0_device,
  192. &rtc_device,
  193. };
  194. static int __init sh770x_devices_setup(void)
  195. {
  196. return platform_add_devices(sh770x_devices,
  197. ARRAY_SIZE(sh770x_devices));
  198. }
  199. arch_initcall(sh770x_devices_setup);
  200. static struct platform_device *sh770x_early_devices[] __initdata = {
  201. &scif0_device,
  202. #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  203. defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  204. defined(CONFIG_CPU_SUBTYPE_SH7709)
  205. &scif1_device,
  206. #endif
  207. #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  208. defined(CONFIG_CPU_SUBTYPE_SH7709)
  209. &scif2_device,
  210. #endif
  211. &tmu0_device,
  212. };
  213. void __init plat_early_device_setup(void)
  214. {
  215. early_platform_add_devices(sh770x_early_devices,
  216. ARRAY_SIZE(sh770x_early_devices));
  217. }
  218. void __init plat_irq_setup(void)
  219. {
  220. register_intc_controller(&intc_desc);
  221. #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  222. defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  223. defined(CONFIG_CPU_SUBTYPE_SH7709)
  224. plat_irq_setup_sh3();
  225. #endif
  226. }