Kconfig 9.2 KB

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  1. # SPDX-License-Identifier: GPL-2.0
  2. menu "Platform support"
  3. source "arch/powerpc/platforms/powernv/Kconfig"
  4. source "arch/powerpc/platforms/pseries/Kconfig"
  5. source "arch/powerpc/platforms/chrp/Kconfig"
  6. source "arch/powerpc/platforms/512x/Kconfig"
  7. source "arch/powerpc/platforms/52xx/Kconfig"
  8. source "arch/powerpc/platforms/powermac/Kconfig"
  9. source "arch/powerpc/platforms/maple/Kconfig"
  10. source "arch/powerpc/platforms/pasemi/Kconfig"
  11. source "arch/powerpc/platforms/ps3/Kconfig"
  12. source "arch/powerpc/platforms/cell/Kconfig"
  13. source "arch/powerpc/platforms/8xx/Kconfig"
  14. source "arch/powerpc/platforms/82xx/Kconfig"
  15. source "arch/powerpc/platforms/83xx/Kconfig"
  16. source "arch/powerpc/platforms/85xx/Kconfig"
  17. source "arch/powerpc/platforms/86xx/Kconfig"
  18. source "arch/powerpc/platforms/embedded6xx/Kconfig"
  19. source "arch/powerpc/platforms/44x/Kconfig"
  20. source "arch/powerpc/platforms/40x/Kconfig"
  21. source "arch/powerpc/platforms/amigaone/Kconfig"
  22. config KVM_GUEST
  23. bool "KVM Guest support"
  24. select EPAPR_PARAVIRT
  25. ---help---
  26. This option enables various optimizations for running under the KVM
  27. hypervisor. Overhead for the kernel when not running inside KVM should
  28. be minimal.
  29. In case of doubt, say Y
  30. config EPAPR_PARAVIRT
  31. bool "ePAPR para-virtualization support"
  32. help
  33. Enables ePAPR para-virtualization support for guests.
  34. In case of doubt, say Y
  35. config PPC_NATIVE
  36. bool
  37. depends on 6xx || PPC64
  38. help
  39. Support for running natively on the hardware, i.e. without
  40. a hypervisor. This option is not user-selectable but should
  41. be selected by all platforms that need it.
  42. config PPC_OF_BOOT_TRAMPOLINE
  43. bool "Support booting from Open Firmware or yaboot"
  44. depends on 6xx || PPC64
  45. default y
  46. help
  47. Support from booting from Open Firmware or yaboot using an
  48. Open Firmware client interface. This enables the kernel to
  49. communicate with open firmware to retrieve system information
  50. such as the device tree.
  51. In case of doubt, say Y
  52. config PPC_DT_CPU_FTRS
  53. bool "Device-tree based CPU feature discovery & setup"
  54. depends on PPC_BOOK3S_64
  55. default y
  56. help
  57. This enables code to use a new device tree binding for describing CPU
  58. compatibility and features. Saying Y here will attempt to use the new
  59. binding if the firmware provides it. Currently only the skiboot
  60. firmware provides this binding.
  61. If you're not sure say Y.
  62. config UDBG_RTAS_CONSOLE
  63. bool "RTAS based debug console"
  64. depends on PPC_RTAS
  65. config PPC_SMP_MUXED_IPI
  66. bool
  67. help
  68. Select this option if your platform supports SMP and your
  69. interrupt controller provides less than 4 interrupts to each
  70. cpu. This will enable the generic code to multiplex the 4
  71. messages on to one ipi.
  72. config IPIC
  73. bool
  74. config MPIC
  75. bool
  76. config MPIC_TIMER
  77. bool "MPIC Global Timer"
  78. depends on MPIC && FSL_SOC
  79. help
  80. The MPIC global timer is a hardware timer inside the
  81. Freescale PIC complying with OpenPIC standard. When the
  82. specified interval times out, the hardware timer generates
  83. an interrupt. The driver currently is only tested on fsl
  84. chip, but it can potentially support other global timers
  85. complying with the OpenPIC standard.
  86. config FSL_MPIC_TIMER_WAKEUP
  87. tristate "Freescale MPIC global timer wakeup driver"
  88. depends on FSL_SOC && MPIC_TIMER && PM
  89. help
  90. The driver provides a way to wake up the system by MPIC
  91. timer.
  92. e.g. "echo 5 > /sys/devices/system/mpic/timer_wakeup"
  93. config PPC_EPAPR_HV_PIC
  94. bool
  95. select EPAPR_PARAVIRT
  96. config MPIC_WEIRD
  97. bool
  98. config MPIC_MSGR
  99. bool "MPIC message register support"
  100. depends on MPIC
  101. help
  102. Enables support for the MPIC message registers. These
  103. registers are used for inter-processor communication.
  104. config PPC_I8259
  105. bool
  106. config U3_DART
  107. bool
  108. depends on PPC64
  109. config PPC_RTAS
  110. bool
  111. config RTAS_ERROR_LOGGING
  112. bool
  113. depends on PPC_RTAS
  114. config PPC_RTAS_DAEMON
  115. bool
  116. depends on PPC_RTAS
  117. config RTAS_PROC
  118. bool "Proc interface to RTAS"
  119. depends on PPC_RTAS && PROC_FS
  120. default y
  121. config RTAS_FLASH
  122. tristate "Firmware flash interface"
  123. depends on PPC64 && RTAS_PROC
  124. config MMIO_NVRAM
  125. bool
  126. config MPIC_U3_HT_IRQS
  127. bool
  128. config MPIC_BROKEN_REGREAD
  129. bool
  130. depends on MPIC
  131. help
  132. This option enables a MPIC driver workaround for some chips
  133. that have a bug that causes some interrupt source information
  134. to not read back properly. It is safe to use on other chips as
  135. well, but enabling it uses about 8KB of memory to keep copies
  136. of the register contents in software.
  137. config EEH
  138. bool
  139. depends on (PPC_POWERNV || PPC_PSERIES) && PCI
  140. default y
  141. config PPC_MPC106
  142. bool
  143. config PPC_970_NAP
  144. bool
  145. config PPC_P7_NAP
  146. bool
  147. config PPC_INDIRECT_PIO
  148. bool
  149. select GENERIC_IOMAP
  150. config PPC_INDIRECT_MMIO
  151. bool
  152. config PPC_IO_WORKAROUNDS
  153. bool
  154. source "drivers/cpufreq/Kconfig"
  155. menu "CPUIdle driver"
  156. source "drivers/cpuidle/Kconfig"
  157. endmenu
  158. config PPC601_SYNC_FIX
  159. bool "Workarounds for PPC601 bugs"
  160. depends on 6xx && PPC_PMAC
  161. help
  162. Some versions of the PPC601 (the first PowerPC chip) have bugs which
  163. mean that extra synchronization instructions are required near
  164. certain instructions, typically those that make major changes to the
  165. CPU state. These extra instructions reduce performance slightly.
  166. If you say N here, these extra instructions will not be included,
  167. resulting in a kernel which will run faster but may not run at all
  168. on some systems with the PPC601 chip.
  169. If in doubt, say Y here.
  170. config TAU
  171. bool "On-chip CPU temperature sensor support"
  172. depends on 6xx
  173. help
  174. G3 and G4 processors have an on-chip temperature sensor called the
  175. 'Thermal Assist Unit (TAU)', which, in theory, can measure the on-die
  176. temperature within 2-4 degrees Celsius. This option shows the current
  177. on-die temperature in /proc/cpuinfo if the cpu supports it.
  178. Unfortunately, on some chip revisions, this sensor is very inaccurate
  179. and in many cases, does not work at all, so don't assume the cpu
  180. temp is actually what /proc/cpuinfo says it is.
  181. config TAU_INT
  182. bool "Interrupt driven TAU driver (DANGEROUS)"
  183. depends on TAU
  184. ---help---
  185. The TAU supports an interrupt driven mode which causes an interrupt
  186. whenever the temperature goes out of range. This is the fastest way
  187. to get notified the temp has exceeded a range. With this option off,
  188. a timer is used to re-check the temperature periodically.
  189. However, on some cpus it appears that the TAU interrupt hardware
  190. is buggy and can cause a situation which would lead unexplained hard
  191. lockups.
  192. Unless you are extending the TAU driver, or enjoy kernel/hardware
  193. debugging, leave this option off.
  194. config TAU_AVERAGE
  195. bool "Average high and low temp"
  196. depends on TAU
  197. ---help---
  198. The TAU hardware can compare the temperature to an upper and lower
  199. bound. The default behavior is to show both the upper and lower
  200. bound in /proc/cpuinfo. If the range is large, the temperature is
  201. either changing a lot, or the TAU hardware is broken (likely on some
  202. G4's). If the range is small (around 4 degrees), the temperature is
  203. relatively stable. If you say Y here, a single temperature value,
  204. halfway between the upper and lower bounds, will be reported in
  205. /proc/cpuinfo.
  206. If in doubt, say N here.
  207. config QE_GPIO
  208. bool "QE GPIO support"
  209. depends on QUICC_ENGINE
  210. select GPIOLIB
  211. help
  212. Say Y here if you're going to use hardware that connects to the
  213. QE GPIOs.
  214. config CPM2
  215. bool "Enable support for the CPM2 (Communications Processor Module)"
  216. depends on (FSL_SOC_BOOKE && PPC32) || 8260
  217. select CPM
  218. select PPC_PCI_CHOICE
  219. select GPIOLIB
  220. help
  221. The CPM2 (Communications Processor Module) is a coprocessor on
  222. embedded CPUs made by Freescale. Selecting this option means that
  223. you wish to build a kernel for a machine with a CPM2 coprocessor
  224. on it (826x, 827x, 8560).
  225. config FSL_ULI1575
  226. bool
  227. select GENERIC_ISA_DMA
  228. help
  229. Supports for the ULI1575 PCIe south bridge that exists on some
  230. Freescale reference boards. The boards all use the ULI in pretty
  231. much the same way.
  232. config CPM
  233. bool
  234. select GENERIC_ALLOCATOR
  235. config OF_RTC
  236. bool
  237. help
  238. Uses information from the OF or flattened device tree to instantiate
  239. platform devices for direct mapped RTC chips like the DS1742 or DS1743.
  240. config GEN_RTC
  241. bool "Use the platform RTC operations from user space"
  242. select RTC_CLASS
  243. select RTC_DRV_GENERIC
  244. help
  245. This option provides backwards compatibility with the old gen_rtc.ko
  246. module that was traditionally used for old PowerPC machines.
  247. Platforms should migrate to enabling the RTC_DRV_GENERIC by hand
  248. replacing their get_rtc_time/set_rtc_time callbacks with
  249. a proper RTC device driver.
  250. config SIMPLE_GPIO
  251. bool "Support for simple, memory-mapped GPIO controllers"
  252. depends on PPC
  253. select GPIOLIB
  254. help
  255. Say Y here to support simple, memory-mapped GPIO controllers.
  256. These are usually BCSRs used to control board's switches, LEDs,
  257. chip-selects, Ethernet/USB PHY's power and various other small
  258. on-board peripherals.
  259. config MCU_MPC8349EMITX
  260. bool "MPC8349E-mITX MCU driver"
  261. depends on I2C=y && PPC_83xx
  262. select GPIOLIB
  263. help
  264. Say Y here to enable soft power-off functionality on the Freescale
  265. boards with the MPC8349E-mITX-compatible MCU chips. This driver will
  266. also register MCU GPIOs with the generic GPIO API, so you'll able
  267. to use MCU pins as GPIOs.
  268. config XILINX_PCI
  269. bool "Xilinx PCI host bridge support"
  270. depends on PCI && XILINX_VIRTEX
  271. endmenu