cputable.c 69 KB

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  1. /*
  2. * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
  3. *
  4. * Modifications for ppc64:
  5. * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. #include <linux/string.h>
  13. #include <linux/sched.h>
  14. #include <linux/threads.h>
  15. #include <linux/init.h>
  16. #include <linux/export.h>
  17. #include <linux/jump_label.h>
  18. #include <asm/oprofile_impl.h>
  19. #include <asm/cputable.h>
  20. #include <asm/prom.h> /* for PTRRELOC on ARCH=ppc */
  21. #include <asm/mmu.h>
  22. #include <asm/setup.h>
  23. static struct cpu_spec the_cpu_spec __read_mostly;
  24. struct cpu_spec* cur_cpu_spec __read_mostly = NULL;
  25. EXPORT_SYMBOL(cur_cpu_spec);
  26. /* The platform string corresponding to the real PVR */
  27. const char *powerpc_base_platform;
  28. /* NOTE:
  29. * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
  30. * the responsibility of the appropriate CPU save/restore functions to
  31. * eventually copy these settings over. Those save/restore aren't yet
  32. * part of the cputable though. That has to be fixed for both ppc32
  33. * and ppc64
  34. */
  35. #ifdef CONFIG_PPC32
  36. extern void __setup_cpu_e200(unsigned long offset, struct cpu_spec* spec);
  37. extern void __setup_cpu_e500v1(unsigned long offset, struct cpu_spec* spec);
  38. extern void __setup_cpu_e500v2(unsigned long offset, struct cpu_spec* spec);
  39. extern void __setup_cpu_e500mc(unsigned long offset, struct cpu_spec* spec);
  40. extern void __setup_cpu_440ep(unsigned long offset, struct cpu_spec* spec);
  41. extern void __setup_cpu_440epx(unsigned long offset, struct cpu_spec* spec);
  42. extern void __setup_cpu_440gx(unsigned long offset, struct cpu_spec* spec);
  43. extern void __setup_cpu_440grx(unsigned long offset, struct cpu_spec* spec);
  44. extern void __setup_cpu_440spe(unsigned long offset, struct cpu_spec* spec);
  45. extern void __setup_cpu_440x5(unsigned long offset, struct cpu_spec* spec);
  46. extern void __setup_cpu_460ex(unsigned long offset, struct cpu_spec* spec);
  47. extern void __setup_cpu_460gt(unsigned long offset, struct cpu_spec* spec);
  48. extern void __setup_cpu_460sx(unsigned long offset, struct cpu_spec *spec);
  49. extern void __setup_cpu_apm821xx(unsigned long offset, struct cpu_spec *spec);
  50. extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec);
  51. extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec);
  52. extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec);
  53. extern void __setup_cpu_750cx(unsigned long offset, struct cpu_spec* spec);
  54. extern void __setup_cpu_750fx(unsigned long offset, struct cpu_spec* spec);
  55. extern void __setup_cpu_7400(unsigned long offset, struct cpu_spec* spec);
  56. extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec);
  57. extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
  58. #endif /* CONFIG_PPC32 */
  59. #ifdef CONFIG_PPC64
  60. extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
  61. extern void __setup_cpu_ppc970MP(unsigned long offset, struct cpu_spec* spec);
  62. extern void __setup_cpu_pa6t(unsigned long offset, struct cpu_spec* spec);
  63. extern void __restore_cpu_pa6t(void);
  64. extern void __restore_cpu_ppc970(void);
  65. extern void __setup_cpu_power7(unsigned long offset, struct cpu_spec* spec);
  66. extern void __restore_cpu_power7(void);
  67. extern void __setup_cpu_power8(unsigned long offset, struct cpu_spec* spec);
  68. extern void __restore_cpu_power8(void);
  69. extern void __setup_cpu_power9(unsigned long offset, struct cpu_spec* spec);
  70. extern void __restore_cpu_power9(void);
  71. extern long __machine_check_early_realmode_p7(struct pt_regs *regs);
  72. extern long __machine_check_early_realmode_p8(struct pt_regs *regs);
  73. extern long __machine_check_early_realmode_p9(struct pt_regs *regs);
  74. #endif /* CONFIG_PPC64 */
  75. #if defined(CONFIG_E500)
  76. extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec);
  77. extern void __setup_cpu_e6500(unsigned long offset, struct cpu_spec* spec);
  78. extern void __restore_cpu_e5500(void);
  79. extern void __restore_cpu_e6500(void);
  80. #endif /* CONFIG_E500 */
  81. /* This table only contains "desktop" CPUs, it need to be filled with embedded
  82. * ones as well...
  83. */
  84. #define COMMON_USER (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
  85. PPC_FEATURE_HAS_MMU)
  86. #define COMMON_USER_PPC64 (COMMON_USER | PPC_FEATURE_64)
  87. #define COMMON_USER_POWER4 (COMMON_USER_PPC64 | PPC_FEATURE_POWER4)
  88. #define COMMON_USER_POWER5 (COMMON_USER_PPC64 | PPC_FEATURE_POWER5 |\
  89. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  90. #define COMMON_USER_POWER5_PLUS (COMMON_USER_PPC64 | PPC_FEATURE_POWER5_PLUS|\
  91. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  92. #define COMMON_USER_POWER6 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_05 |\
  93. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  94. PPC_FEATURE_TRUE_LE | \
  95. PPC_FEATURE_PSERIES_PERFMON_COMPAT)
  96. #define COMMON_USER_POWER7 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\
  97. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  98. PPC_FEATURE_TRUE_LE | \
  99. PPC_FEATURE_PSERIES_PERFMON_COMPAT)
  100. #define COMMON_USER2_POWER7 (PPC_FEATURE2_DSCR)
  101. #define COMMON_USER_POWER8 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\
  102. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  103. PPC_FEATURE_TRUE_LE | \
  104. PPC_FEATURE_PSERIES_PERFMON_COMPAT)
  105. #define COMMON_USER2_POWER8 (PPC_FEATURE2_ARCH_2_07 | \
  106. PPC_FEATURE2_HTM_COMP | \
  107. PPC_FEATURE2_HTM_NOSC_COMP | \
  108. PPC_FEATURE2_DSCR | \
  109. PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR | \
  110. PPC_FEATURE2_VEC_CRYPTO)
  111. #define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\
  112. PPC_FEATURE_TRUE_LE | \
  113. PPC_FEATURE_HAS_ALTIVEC_COMP)
  114. #define COMMON_USER_POWER9 COMMON_USER_POWER8
  115. #define COMMON_USER2_POWER9 (COMMON_USER2_POWER8 | \
  116. PPC_FEATURE2_ARCH_3_00 | \
  117. PPC_FEATURE2_HAS_IEEE128 | \
  118. PPC_FEATURE2_DARN )
  119. #ifdef CONFIG_PPC_BOOK3E_64
  120. #define COMMON_USER_BOOKE (COMMON_USER_PPC64 | PPC_FEATURE_BOOKE)
  121. #else
  122. #define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \
  123. PPC_FEATURE_BOOKE)
  124. #endif
  125. static struct cpu_spec __initdata cpu_specs[] = {
  126. #ifdef CONFIG_PPC_BOOK3S_64
  127. { /* PPC970 */
  128. .pvr_mask = 0xffff0000,
  129. .pvr_value = 0x00390000,
  130. .cpu_name = "PPC970",
  131. .cpu_features = CPU_FTRS_PPC970,
  132. .cpu_user_features = COMMON_USER_POWER4 |
  133. PPC_FEATURE_HAS_ALTIVEC_COMP,
  134. .mmu_features = MMU_FTRS_PPC970,
  135. .icache_bsize = 128,
  136. .dcache_bsize = 128,
  137. .num_pmcs = 8,
  138. .pmc_type = PPC_PMC_IBM,
  139. .cpu_setup = __setup_cpu_ppc970,
  140. .cpu_restore = __restore_cpu_ppc970,
  141. .oprofile_cpu_type = "ppc64/970",
  142. .oprofile_type = PPC_OPROFILE_POWER4,
  143. .platform = "ppc970",
  144. },
  145. { /* PPC970FX */
  146. .pvr_mask = 0xffff0000,
  147. .pvr_value = 0x003c0000,
  148. .cpu_name = "PPC970FX",
  149. .cpu_features = CPU_FTRS_PPC970,
  150. .cpu_user_features = COMMON_USER_POWER4 |
  151. PPC_FEATURE_HAS_ALTIVEC_COMP,
  152. .mmu_features = MMU_FTRS_PPC970,
  153. .icache_bsize = 128,
  154. .dcache_bsize = 128,
  155. .num_pmcs = 8,
  156. .pmc_type = PPC_PMC_IBM,
  157. .cpu_setup = __setup_cpu_ppc970,
  158. .cpu_restore = __restore_cpu_ppc970,
  159. .oprofile_cpu_type = "ppc64/970",
  160. .oprofile_type = PPC_OPROFILE_POWER4,
  161. .platform = "ppc970",
  162. },
  163. { /* PPC970MP DD1.0 - no DEEPNAP, use regular 970 init */
  164. .pvr_mask = 0xffffffff,
  165. .pvr_value = 0x00440100,
  166. .cpu_name = "PPC970MP",
  167. .cpu_features = CPU_FTRS_PPC970,
  168. .cpu_user_features = COMMON_USER_POWER4 |
  169. PPC_FEATURE_HAS_ALTIVEC_COMP,
  170. .mmu_features = MMU_FTRS_PPC970,
  171. .icache_bsize = 128,
  172. .dcache_bsize = 128,
  173. .num_pmcs = 8,
  174. .pmc_type = PPC_PMC_IBM,
  175. .cpu_setup = __setup_cpu_ppc970,
  176. .cpu_restore = __restore_cpu_ppc970,
  177. .oprofile_cpu_type = "ppc64/970MP",
  178. .oprofile_type = PPC_OPROFILE_POWER4,
  179. .platform = "ppc970",
  180. },
  181. { /* PPC970MP */
  182. .pvr_mask = 0xffff0000,
  183. .pvr_value = 0x00440000,
  184. .cpu_name = "PPC970MP",
  185. .cpu_features = CPU_FTRS_PPC970,
  186. .cpu_user_features = COMMON_USER_POWER4 |
  187. PPC_FEATURE_HAS_ALTIVEC_COMP,
  188. .mmu_features = MMU_FTRS_PPC970,
  189. .icache_bsize = 128,
  190. .dcache_bsize = 128,
  191. .num_pmcs = 8,
  192. .pmc_type = PPC_PMC_IBM,
  193. .cpu_setup = __setup_cpu_ppc970MP,
  194. .cpu_restore = __restore_cpu_ppc970,
  195. .oprofile_cpu_type = "ppc64/970MP",
  196. .oprofile_type = PPC_OPROFILE_POWER4,
  197. .platform = "ppc970",
  198. },
  199. { /* PPC970GX */
  200. .pvr_mask = 0xffff0000,
  201. .pvr_value = 0x00450000,
  202. .cpu_name = "PPC970GX",
  203. .cpu_features = CPU_FTRS_PPC970,
  204. .cpu_user_features = COMMON_USER_POWER4 |
  205. PPC_FEATURE_HAS_ALTIVEC_COMP,
  206. .mmu_features = MMU_FTRS_PPC970,
  207. .icache_bsize = 128,
  208. .dcache_bsize = 128,
  209. .num_pmcs = 8,
  210. .pmc_type = PPC_PMC_IBM,
  211. .cpu_setup = __setup_cpu_ppc970,
  212. .oprofile_cpu_type = "ppc64/970",
  213. .oprofile_type = PPC_OPROFILE_POWER4,
  214. .platform = "ppc970",
  215. },
  216. { /* Power5 GR */
  217. .pvr_mask = 0xffff0000,
  218. .pvr_value = 0x003a0000,
  219. .cpu_name = "POWER5 (gr)",
  220. .cpu_features = CPU_FTRS_POWER5,
  221. .cpu_user_features = COMMON_USER_POWER5,
  222. .mmu_features = MMU_FTRS_POWER5,
  223. .icache_bsize = 128,
  224. .dcache_bsize = 128,
  225. .num_pmcs = 6,
  226. .pmc_type = PPC_PMC_IBM,
  227. .oprofile_cpu_type = "ppc64/power5",
  228. .oprofile_type = PPC_OPROFILE_POWER4,
  229. /* SIHV / SIPR bits are implemented on POWER4+ (GQ)
  230. * and above but only works on POWER5 and above
  231. */
  232. .oprofile_mmcra_sihv = MMCRA_SIHV,
  233. .oprofile_mmcra_sipr = MMCRA_SIPR,
  234. .platform = "power5",
  235. },
  236. { /* Power5++ */
  237. .pvr_mask = 0xffffff00,
  238. .pvr_value = 0x003b0300,
  239. .cpu_name = "POWER5+ (gs)",
  240. .cpu_features = CPU_FTRS_POWER5,
  241. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  242. .mmu_features = MMU_FTRS_POWER5,
  243. .icache_bsize = 128,
  244. .dcache_bsize = 128,
  245. .num_pmcs = 6,
  246. .oprofile_cpu_type = "ppc64/power5++",
  247. .oprofile_type = PPC_OPROFILE_POWER4,
  248. .oprofile_mmcra_sihv = MMCRA_SIHV,
  249. .oprofile_mmcra_sipr = MMCRA_SIPR,
  250. .platform = "power5+",
  251. },
  252. { /* Power5 GS */
  253. .pvr_mask = 0xffff0000,
  254. .pvr_value = 0x003b0000,
  255. .cpu_name = "POWER5+ (gs)",
  256. .cpu_features = CPU_FTRS_POWER5,
  257. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  258. .mmu_features = MMU_FTRS_POWER5,
  259. .icache_bsize = 128,
  260. .dcache_bsize = 128,
  261. .num_pmcs = 6,
  262. .pmc_type = PPC_PMC_IBM,
  263. .oprofile_cpu_type = "ppc64/power5+",
  264. .oprofile_type = PPC_OPROFILE_POWER4,
  265. .oprofile_mmcra_sihv = MMCRA_SIHV,
  266. .oprofile_mmcra_sipr = MMCRA_SIPR,
  267. .platform = "power5+",
  268. },
  269. { /* POWER6 in P5+ mode; 2.04-compliant processor */
  270. .pvr_mask = 0xffffffff,
  271. .pvr_value = 0x0f000001,
  272. .cpu_name = "POWER5+",
  273. .cpu_features = CPU_FTRS_POWER5,
  274. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  275. .mmu_features = MMU_FTRS_POWER5,
  276. .icache_bsize = 128,
  277. .dcache_bsize = 128,
  278. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  279. .oprofile_type = PPC_OPROFILE_POWER4,
  280. .platform = "power5+",
  281. },
  282. { /* Power6 */
  283. .pvr_mask = 0xffff0000,
  284. .pvr_value = 0x003e0000,
  285. .cpu_name = "POWER6 (raw)",
  286. .cpu_features = CPU_FTRS_POWER6,
  287. .cpu_user_features = COMMON_USER_POWER6 |
  288. PPC_FEATURE_POWER6_EXT,
  289. .mmu_features = MMU_FTRS_POWER6,
  290. .icache_bsize = 128,
  291. .dcache_bsize = 128,
  292. .num_pmcs = 6,
  293. .pmc_type = PPC_PMC_IBM,
  294. .oprofile_cpu_type = "ppc64/power6",
  295. .oprofile_type = PPC_OPROFILE_POWER4,
  296. .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
  297. .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
  298. .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
  299. POWER6_MMCRA_OTHER,
  300. .platform = "power6x",
  301. },
  302. { /* 2.05-compliant processor, i.e. Power6 "architected" mode */
  303. .pvr_mask = 0xffffffff,
  304. .pvr_value = 0x0f000002,
  305. .cpu_name = "POWER6 (architected)",
  306. .cpu_features = CPU_FTRS_POWER6,
  307. .cpu_user_features = COMMON_USER_POWER6,
  308. .mmu_features = MMU_FTRS_POWER6,
  309. .icache_bsize = 128,
  310. .dcache_bsize = 128,
  311. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  312. .oprofile_type = PPC_OPROFILE_POWER4,
  313. .platform = "power6",
  314. },
  315. { /* 2.06-compliant processor, i.e. Power7 "architected" mode */
  316. .pvr_mask = 0xffffffff,
  317. .pvr_value = 0x0f000003,
  318. .cpu_name = "POWER7 (architected)",
  319. .cpu_features = CPU_FTRS_POWER7,
  320. .cpu_user_features = COMMON_USER_POWER7,
  321. .cpu_user_features2 = COMMON_USER2_POWER7,
  322. .mmu_features = MMU_FTRS_POWER7,
  323. .icache_bsize = 128,
  324. .dcache_bsize = 128,
  325. .oprofile_type = PPC_OPROFILE_POWER4,
  326. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  327. .cpu_setup = __setup_cpu_power7,
  328. .cpu_restore = __restore_cpu_power7,
  329. .machine_check_early = __machine_check_early_realmode_p7,
  330. .platform = "power7",
  331. },
  332. { /* 2.07-compliant processor, i.e. Power8 "architected" mode */
  333. .pvr_mask = 0xffffffff,
  334. .pvr_value = 0x0f000004,
  335. .cpu_name = "POWER8 (architected)",
  336. .cpu_features = CPU_FTRS_POWER8,
  337. .cpu_user_features = COMMON_USER_POWER8,
  338. .cpu_user_features2 = COMMON_USER2_POWER8,
  339. .mmu_features = MMU_FTRS_POWER8,
  340. .icache_bsize = 128,
  341. .dcache_bsize = 128,
  342. .oprofile_type = PPC_OPROFILE_INVALID,
  343. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  344. .cpu_setup = __setup_cpu_power8,
  345. .cpu_restore = __restore_cpu_power8,
  346. .machine_check_early = __machine_check_early_realmode_p8,
  347. .platform = "power8",
  348. },
  349. { /* 3.00-compliant processor, i.e. Power9 "architected" mode */
  350. .pvr_mask = 0xffffffff,
  351. .pvr_value = 0x0f000005,
  352. .cpu_name = "POWER9 (architected)",
  353. .cpu_features = CPU_FTRS_POWER9,
  354. .cpu_user_features = COMMON_USER_POWER9,
  355. .cpu_user_features2 = COMMON_USER2_POWER9,
  356. .mmu_features = MMU_FTRS_POWER9,
  357. .icache_bsize = 128,
  358. .dcache_bsize = 128,
  359. .oprofile_type = PPC_OPROFILE_INVALID,
  360. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  361. .cpu_setup = __setup_cpu_power9,
  362. .cpu_restore = __restore_cpu_power9,
  363. .platform = "power9",
  364. },
  365. { /* Power7 */
  366. .pvr_mask = 0xffff0000,
  367. .pvr_value = 0x003f0000,
  368. .cpu_name = "POWER7 (raw)",
  369. .cpu_features = CPU_FTRS_POWER7,
  370. .cpu_user_features = COMMON_USER_POWER7,
  371. .cpu_user_features2 = COMMON_USER2_POWER7,
  372. .mmu_features = MMU_FTRS_POWER7,
  373. .icache_bsize = 128,
  374. .dcache_bsize = 128,
  375. .num_pmcs = 6,
  376. .pmc_type = PPC_PMC_IBM,
  377. .oprofile_cpu_type = "ppc64/power7",
  378. .oprofile_type = PPC_OPROFILE_POWER4,
  379. .cpu_setup = __setup_cpu_power7,
  380. .cpu_restore = __restore_cpu_power7,
  381. .machine_check_early = __machine_check_early_realmode_p7,
  382. .platform = "power7",
  383. },
  384. { /* Power7+ */
  385. .pvr_mask = 0xffff0000,
  386. .pvr_value = 0x004A0000,
  387. .cpu_name = "POWER7+ (raw)",
  388. .cpu_features = CPU_FTRS_POWER7,
  389. .cpu_user_features = COMMON_USER_POWER7,
  390. .cpu_user_features2 = COMMON_USER2_POWER7,
  391. .mmu_features = MMU_FTRS_POWER7,
  392. .icache_bsize = 128,
  393. .dcache_bsize = 128,
  394. .num_pmcs = 6,
  395. .pmc_type = PPC_PMC_IBM,
  396. .oprofile_cpu_type = "ppc64/power7",
  397. .oprofile_type = PPC_OPROFILE_POWER4,
  398. .cpu_setup = __setup_cpu_power7,
  399. .cpu_restore = __restore_cpu_power7,
  400. .machine_check_early = __machine_check_early_realmode_p7,
  401. .platform = "power7+",
  402. },
  403. { /* Power8E */
  404. .pvr_mask = 0xffff0000,
  405. .pvr_value = 0x004b0000,
  406. .cpu_name = "POWER8E (raw)",
  407. .cpu_features = CPU_FTRS_POWER8E,
  408. .cpu_user_features = COMMON_USER_POWER8,
  409. .cpu_user_features2 = COMMON_USER2_POWER8,
  410. .mmu_features = MMU_FTRS_POWER8,
  411. .icache_bsize = 128,
  412. .dcache_bsize = 128,
  413. .num_pmcs = 6,
  414. .pmc_type = PPC_PMC_IBM,
  415. .oprofile_cpu_type = "ppc64/power8",
  416. .oprofile_type = PPC_OPROFILE_INVALID,
  417. .cpu_setup = __setup_cpu_power8,
  418. .cpu_restore = __restore_cpu_power8,
  419. .machine_check_early = __machine_check_early_realmode_p8,
  420. .platform = "power8",
  421. },
  422. { /* Power8NVL */
  423. .pvr_mask = 0xffff0000,
  424. .pvr_value = 0x004c0000,
  425. .cpu_name = "POWER8NVL (raw)",
  426. .cpu_features = CPU_FTRS_POWER8,
  427. .cpu_user_features = COMMON_USER_POWER8,
  428. .cpu_user_features2 = COMMON_USER2_POWER8,
  429. .mmu_features = MMU_FTRS_POWER8,
  430. .icache_bsize = 128,
  431. .dcache_bsize = 128,
  432. .num_pmcs = 6,
  433. .pmc_type = PPC_PMC_IBM,
  434. .oprofile_cpu_type = "ppc64/power8",
  435. .oprofile_type = PPC_OPROFILE_INVALID,
  436. .cpu_setup = __setup_cpu_power8,
  437. .cpu_restore = __restore_cpu_power8,
  438. .machine_check_early = __machine_check_early_realmode_p8,
  439. .platform = "power8",
  440. },
  441. { /* Power8 */
  442. .pvr_mask = 0xffff0000,
  443. .pvr_value = 0x004d0000,
  444. .cpu_name = "POWER8 (raw)",
  445. .cpu_features = CPU_FTRS_POWER8,
  446. .cpu_user_features = COMMON_USER_POWER8,
  447. .cpu_user_features2 = COMMON_USER2_POWER8,
  448. .mmu_features = MMU_FTRS_POWER8,
  449. .icache_bsize = 128,
  450. .dcache_bsize = 128,
  451. .num_pmcs = 6,
  452. .pmc_type = PPC_PMC_IBM,
  453. .oprofile_cpu_type = "ppc64/power8",
  454. .oprofile_type = PPC_OPROFILE_INVALID,
  455. .cpu_setup = __setup_cpu_power8,
  456. .cpu_restore = __restore_cpu_power8,
  457. .machine_check_early = __machine_check_early_realmode_p8,
  458. .platform = "power8",
  459. },
  460. { /* Power9 DD2.0 */
  461. .pvr_mask = 0xffffefff,
  462. .pvr_value = 0x004e0200,
  463. .cpu_name = "POWER9 (raw)",
  464. .cpu_features = CPU_FTRS_POWER9_DD2_0,
  465. .cpu_user_features = COMMON_USER_POWER9,
  466. .cpu_user_features2 = COMMON_USER2_POWER9,
  467. .mmu_features = MMU_FTRS_POWER9,
  468. .icache_bsize = 128,
  469. .dcache_bsize = 128,
  470. .num_pmcs = 6,
  471. .pmc_type = PPC_PMC_IBM,
  472. .oprofile_cpu_type = "ppc64/power9",
  473. .oprofile_type = PPC_OPROFILE_INVALID,
  474. .cpu_setup = __setup_cpu_power9,
  475. .cpu_restore = __restore_cpu_power9,
  476. .machine_check_early = __machine_check_early_realmode_p9,
  477. .platform = "power9",
  478. },
  479. { /* Power9 DD 2.1 */
  480. .pvr_mask = 0xffffefff,
  481. .pvr_value = 0x004e0201,
  482. .cpu_name = "POWER9 (raw)",
  483. .cpu_features = CPU_FTRS_POWER9_DD2_1,
  484. .cpu_user_features = COMMON_USER_POWER9,
  485. .cpu_user_features2 = COMMON_USER2_POWER9,
  486. .mmu_features = MMU_FTRS_POWER9,
  487. .icache_bsize = 128,
  488. .dcache_bsize = 128,
  489. .num_pmcs = 6,
  490. .pmc_type = PPC_PMC_IBM,
  491. .oprofile_cpu_type = "ppc64/power9",
  492. .oprofile_type = PPC_OPROFILE_INVALID,
  493. .cpu_setup = __setup_cpu_power9,
  494. .cpu_restore = __restore_cpu_power9,
  495. .machine_check_early = __machine_check_early_realmode_p9,
  496. .platform = "power9",
  497. },
  498. { /* Power9 DD2.2 or later */
  499. .pvr_mask = 0xffff0000,
  500. .pvr_value = 0x004e0000,
  501. .cpu_name = "POWER9 (raw)",
  502. .cpu_features = CPU_FTRS_POWER9_DD2_2,
  503. .cpu_user_features = COMMON_USER_POWER9,
  504. .cpu_user_features2 = COMMON_USER2_POWER9,
  505. .mmu_features = MMU_FTRS_POWER9,
  506. .icache_bsize = 128,
  507. .dcache_bsize = 128,
  508. .num_pmcs = 6,
  509. .pmc_type = PPC_PMC_IBM,
  510. .oprofile_cpu_type = "ppc64/power9",
  511. .oprofile_type = PPC_OPROFILE_INVALID,
  512. .cpu_setup = __setup_cpu_power9,
  513. .cpu_restore = __restore_cpu_power9,
  514. .machine_check_early = __machine_check_early_realmode_p9,
  515. .platform = "power9",
  516. },
  517. { /* Cell Broadband Engine */
  518. .pvr_mask = 0xffff0000,
  519. .pvr_value = 0x00700000,
  520. .cpu_name = "Cell Broadband Engine",
  521. .cpu_features = CPU_FTRS_CELL,
  522. .cpu_user_features = COMMON_USER_PPC64 |
  523. PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP |
  524. PPC_FEATURE_SMT,
  525. .mmu_features = MMU_FTRS_CELL,
  526. .icache_bsize = 128,
  527. .dcache_bsize = 128,
  528. .num_pmcs = 4,
  529. .pmc_type = PPC_PMC_IBM,
  530. .oprofile_cpu_type = "ppc64/cell-be",
  531. .oprofile_type = PPC_OPROFILE_CELL,
  532. .platform = "ppc-cell-be",
  533. },
  534. { /* PA Semi PA6T */
  535. .pvr_mask = 0x7fff0000,
  536. .pvr_value = 0x00900000,
  537. .cpu_name = "PA6T",
  538. .cpu_features = CPU_FTRS_PA6T,
  539. .cpu_user_features = COMMON_USER_PA6T,
  540. .mmu_features = MMU_FTRS_PA6T,
  541. .icache_bsize = 64,
  542. .dcache_bsize = 64,
  543. .num_pmcs = 6,
  544. .pmc_type = PPC_PMC_PA6T,
  545. .cpu_setup = __setup_cpu_pa6t,
  546. .cpu_restore = __restore_cpu_pa6t,
  547. .oprofile_cpu_type = "ppc64/pa6t",
  548. .oprofile_type = PPC_OPROFILE_PA6T,
  549. .platform = "pa6t",
  550. },
  551. { /* default match */
  552. .pvr_mask = 0x00000000,
  553. .pvr_value = 0x00000000,
  554. .cpu_name = "POWER5 (compatible)",
  555. .cpu_features = CPU_FTRS_COMPATIBLE,
  556. .cpu_user_features = COMMON_USER_PPC64,
  557. .mmu_features = MMU_FTRS_POWER,
  558. .icache_bsize = 128,
  559. .dcache_bsize = 128,
  560. .num_pmcs = 6,
  561. .pmc_type = PPC_PMC_IBM,
  562. .platform = "power5",
  563. }
  564. #endif /* CONFIG_PPC_BOOK3S_64 */
  565. #ifdef CONFIG_PPC32
  566. #ifdef CONFIG_PPC_BOOK3S_32
  567. { /* 601 */
  568. .pvr_mask = 0xffff0000,
  569. .pvr_value = 0x00010000,
  570. .cpu_name = "601",
  571. .cpu_features = CPU_FTRS_PPC601,
  572. .cpu_user_features = COMMON_USER | PPC_FEATURE_601_INSTR |
  573. PPC_FEATURE_UNIFIED_CACHE | PPC_FEATURE_NO_TB,
  574. .mmu_features = MMU_FTR_HPTE_TABLE,
  575. .icache_bsize = 32,
  576. .dcache_bsize = 32,
  577. .machine_check = machine_check_generic,
  578. .platform = "ppc601",
  579. },
  580. { /* 603 */
  581. .pvr_mask = 0xffff0000,
  582. .pvr_value = 0x00030000,
  583. .cpu_name = "603",
  584. .cpu_features = CPU_FTRS_603,
  585. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  586. .mmu_features = 0,
  587. .icache_bsize = 32,
  588. .dcache_bsize = 32,
  589. .cpu_setup = __setup_cpu_603,
  590. .machine_check = machine_check_generic,
  591. .platform = "ppc603",
  592. },
  593. { /* 603e */
  594. .pvr_mask = 0xffff0000,
  595. .pvr_value = 0x00060000,
  596. .cpu_name = "603e",
  597. .cpu_features = CPU_FTRS_603,
  598. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  599. .mmu_features = 0,
  600. .icache_bsize = 32,
  601. .dcache_bsize = 32,
  602. .cpu_setup = __setup_cpu_603,
  603. .machine_check = machine_check_generic,
  604. .platform = "ppc603",
  605. },
  606. { /* 603ev */
  607. .pvr_mask = 0xffff0000,
  608. .pvr_value = 0x00070000,
  609. .cpu_name = "603ev",
  610. .cpu_features = CPU_FTRS_603,
  611. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  612. .mmu_features = 0,
  613. .icache_bsize = 32,
  614. .dcache_bsize = 32,
  615. .cpu_setup = __setup_cpu_603,
  616. .machine_check = machine_check_generic,
  617. .platform = "ppc603",
  618. },
  619. { /* 604 */
  620. .pvr_mask = 0xffff0000,
  621. .pvr_value = 0x00040000,
  622. .cpu_name = "604",
  623. .cpu_features = CPU_FTRS_604,
  624. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  625. .mmu_features = MMU_FTR_HPTE_TABLE,
  626. .icache_bsize = 32,
  627. .dcache_bsize = 32,
  628. .num_pmcs = 2,
  629. .cpu_setup = __setup_cpu_604,
  630. .machine_check = machine_check_generic,
  631. .platform = "ppc604",
  632. },
  633. { /* 604e */
  634. .pvr_mask = 0xfffff000,
  635. .pvr_value = 0x00090000,
  636. .cpu_name = "604e",
  637. .cpu_features = CPU_FTRS_604,
  638. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  639. .mmu_features = MMU_FTR_HPTE_TABLE,
  640. .icache_bsize = 32,
  641. .dcache_bsize = 32,
  642. .num_pmcs = 4,
  643. .cpu_setup = __setup_cpu_604,
  644. .machine_check = machine_check_generic,
  645. .platform = "ppc604",
  646. },
  647. { /* 604r */
  648. .pvr_mask = 0xffff0000,
  649. .pvr_value = 0x00090000,
  650. .cpu_name = "604r",
  651. .cpu_features = CPU_FTRS_604,
  652. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  653. .mmu_features = MMU_FTR_HPTE_TABLE,
  654. .icache_bsize = 32,
  655. .dcache_bsize = 32,
  656. .num_pmcs = 4,
  657. .cpu_setup = __setup_cpu_604,
  658. .machine_check = machine_check_generic,
  659. .platform = "ppc604",
  660. },
  661. { /* 604ev */
  662. .pvr_mask = 0xffff0000,
  663. .pvr_value = 0x000a0000,
  664. .cpu_name = "604ev",
  665. .cpu_features = CPU_FTRS_604,
  666. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  667. .mmu_features = MMU_FTR_HPTE_TABLE,
  668. .icache_bsize = 32,
  669. .dcache_bsize = 32,
  670. .num_pmcs = 4,
  671. .cpu_setup = __setup_cpu_604,
  672. .machine_check = machine_check_generic,
  673. .platform = "ppc604",
  674. },
  675. { /* 740/750 (0x4202, don't support TAU ?) */
  676. .pvr_mask = 0xffffffff,
  677. .pvr_value = 0x00084202,
  678. .cpu_name = "740/750",
  679. .cpu_features = CPU_FTRS_740_NOTAU,
  680. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  681. .mmu_features = MMU_FTR_HPTE_TABLE,
  682. .icache_bsize = 32,
  683. .dcache_bsize = 32,
  684. .num_pmcs = 4,
  685. .cpu_setup = __setup_cpu_750,
  686. .machine_check = machine_check_generic,
  687. .platform = "ppc750",
  688. },
  689. { /* 750CX (80100 and 8010x?) */
  690. .pvr_mask = 0xfffffff0,
  691. .pvr_value = 0x00080100,
  692. .cpu_name = "750CX",
  693. .cpu_features = CPU_FTRS_750,
  694. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  695. .mmu_features = MMU_FTR_HPTE_TABLE,
  696. .icache_bsize = 32,
  697. .dcache_bsize = 32,
  698. .num_pmcs = 4,
  699. .cpu_setup = __setup_cpu_750cx,
  700. .machine_check = machine_check_generic,
  701. .platform = "ppc750",
  702. },
  703. { /* 750CX (82201 and 82202) */
  704. .pvr_mask = 0xfffffff0,
  705. .pvr_value = 0x00082200,
  706. .cpu_name = "750CX",
  707. .cpu_features = CPU_FTRS_750,
  708. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  709. .mmu_features = MMU_FTR_HPTE_TABLE,
  710. .icache_bsize = 32,
  711. .dcache_bsize = 32,
  712. .num_pmcs = 4,
  713. .pmc_type = PPC_PMC_IBM,
  714. .cpu_setup = __setup_cpu_750cx,
  715. .machine_check = machine_check_generic,
  716. .platform = "ppc750",
  717. },
  718. { /* 750CXe (82214) */
  719. .pvr_mask = 0xfffffff0,
  720. .pvr_value = 0x00082210,
  721. .cpu_name = "750CXe",
  722. .cpu_features = CPU_FTRS_750,
  723. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  724. .mmu_features = MMU_FTR_HPTE_TABLE,
  725. .icache_bsize = 32,
  726. .dcache_bsize = 32,
  727. .num_pmcs = 4,
  728. .pmc_type = PPC_PMC_IBM,
  729. .cpu_setup = __setup_cpu_750cx,
  730. .machine_check = machine_check_generic,
  731. .platform = "ppc750",
  732. },
  733. { /* 750CXe "Gekko" (83214) */
  734. .pvr_mask = 0xffffffff,
  735. .pvr_value = 0x00083214,
  736. .cpu_name = "750CXe",
  737. .cpu_features = CPU_FTRS_750,
  738. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  739. .mmu_features = MMU_FTR_HPTE_TABLE,
  740. .icache_bsize = 32,
  741. .dcache_bsize = 32,
  742. .num_pmcs = 4,
  743. .pmc_type = PPC_PMC_IBM,
  744. .cpu_setup = __setup_cpu_750cx,
  745. .machine_check = machine_check_generic,
  746. .platform = "ppc750",
  747. },
  748. { /* 750CL (and "Broadway") */
  749. .pvr_mask = 0xfffff0e0,
  750. .pvr_value = 0x00087000,
  751. .cpu_name = "750CL",
  752. .cpu_features = CPU_FTRS_750CL,
  753. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  754. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  755. .icache_bsize = 32,
  756. .dcache_bsize = 32,
  757. .num_pmcs = 4,
  758. .pmc_type = PPC_PMC_IBM,
  759. .cpu_setup = __setup_cpu_750,
  760. .machine_check = machine_check_generic,
  761. .platform = "ppc750",
  762. .oprofile_cpu_type = "ppc/750",
  763. .oprofile_type = PPC_OPROFILE_G4,
  764. },
  765. { /* 745/755 */
  766. .pvr_mask = 0xfffff000,
  767. .pvr_value = 0x00083000,
  768. .cpu_name = "745/755",
  769. .cpu_features = CPU_FTRS_750,
  770. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  771. .mmu_features = MMU_FTR_HPTE_TABLE,
  772. .icache_bsize = 32,
  773. .dcache_bsize = 32,
  774. .num_pmcs = 4,
  775. .pmc_type = PPC_PMC_IBM,
  776. .cpu_setup = __setup_cpu_750,
  777. .machine_check = machine_check_generic,
  778. .platform = "ppc750",
  779. },
  780. { /* 750FX rev 1.x */
  781. .pvr_mask = 0xffffff00,
  782. .pvr_value = 0x70000100,
  783. .cpu_name = "750FX",
  784. .cpu_features = CPU_FTRS_750FX1,
  785. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  786. .mmu_features = MMU_FTR_HPTE_TABLE,
  787. .icache_bsize = 32,
  788. .dcache_bsize = 32,
  789. .num_pmcs = 4,
  790. .pmc_type = PPC_PMC_IBM,
  791. .cpu_setup = __setup_cpu_750,
  792. .machine_check = machine_check_generic,
  793. .platform = "ppc750",
  794. .oprofile_cpu_type = "ppc/750",
  795. .oprofile_type = PPC_OPROFILE_G4,
  796. },
  797. { /* 750FX rev 2.0 must disable HID0[DPM] */
  798. .pvr_mask = 0xffffffff,
  799. .pvr_value = 0x70000200,
  800. .cpu_name = "750FX",
  801. .cpu_features = CPU_FTRS_750FX2,
  802. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  803. .mmu_features = MMU_FTR_HPTE_TABLE,
  804. .icache_bsize = 32,
  805. .dcache_bsize = 32,
  806. .num_pmcs = 4,
  807. .pmc_type = PPC_PMC_IBM,
  808. .cpu_setup = __setup_cpu_750,
  809. .machine_check = machine_check_generic,
  810. .platform = "ppc750",
  811. .oprofile_cpu_type = "ppc/750",
  812. .oprofile_type = PPC_OPROFILE_G4,
  813. },
  814. { /* 750FX (All revs except 2.0) */
  815. .pvr_mask = 0xffff0000,
  816. .pvr_value = 0x70000000,
  817. .cpu_name = "750FX",
  818. .cpu_features = CPU_FTRS_750FX,
  819. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  820. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  821. .icache_bsize = 32,
  822. .dcache_bsize = 32,
  823. .num_pmcs = 4,
  824. .pmc_type = PPC_PMC_IBM,
  825. .cpu_setup = __setup_cpu_750fx,
  826. .machine_check = machine_check_generic,
  827. .platform = "ppc750",
  828. .oprofile_cpu_type = "ppc/750",
  829. .oprofile_type = PPC_OPROFILE_G4,
  830. },
  831. { /* 750GX */
  832. .pvr_mask = 0xffff0000,
  833. .pvr_value = 0x70020000,
  834. .cpu_name = "750GX",
  835. .cpu_features = CPU_FTRS_750GX,
  836. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  837. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  838. .icache_bsize = 32,
  839. .dcache_bsize = 32,
  840. .num_pmcs = 4,
  841. .pmc_type = PPC_PMC_IBM,
  842. .cpu_setup = __setup_cpu_750fx,
  843. .machine_check = machine_check_generic,
  844. .platform = "ppc750",
  845. .oprofile_cpu_type = "ppc/750",
  846. .oprofile_type = PPC_OPROFILE_G4,
  847. },
  848. { /* 740/750 (L2CR bit need fixup for 740) */
  849. .pvr_mask = 0xffff0000,
  850. .pvr_value = 0x00080000,
  851. .cpu_name = "740/750",
  852. .cpu_features = CPU_FTRS_740,
  853. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  854. .mmu_features = MMU_FTR_HPTE_TABLE,
  855. .icache_bsize = 32,
  856. .dcache_bsize = 32,
  857. .num_pmcs = 4,
  858. .pmc_type = PPC_PMC_IBM,
  859. .cpu_setup = __setup_cpu_750,
  860. .machine_check = machine_check_generic,
  861. .platform = "ppc750",
  862. },
  863. { /* 7400 rev 1.1 ? (no TAU) */
  864. .pvr_mask = 0xffffffff,
  865. .pvr_value = 0x000c1101,
  866. .cpu_name = "7400 (1.1)",
  867. .cpu_features = CPU_FTRS_7400_NOTAU,
  868. .cpu_user_features = COMMON_USER |
  869. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  870. .mmu_features = MMU_FTR_HPTE_TABLE,
  871. .icache_bsize = 32,
  872. .dcache_bsize = 32,
  873. .num_pmcs = 4,
  874. .pmc_type = PPC_PMC_G4,
  875. .cpu_setup = __setup_cpu_7400,
  876. .machine_check = machine_check_generic,
  877. .platform = "ppc7400",
  878. },
  879. { /* 7400 */
  880. .pvr_mask = 0xffff0000,
  881. .pvr_value = 0x000c0000,
  882. .cpu_name = "7400",
  883. .cpu_features = CPU_FTRS_7400,
  884. .cpu_user_features = COMMON_USER |
  885. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  886. .mmu_features = MMU_FTR_HPTE_TABLE,
  887. .icache_bsize = 32,
  888. .dcache_bsize = 32,
  889. .num_pmcs = 4,
  890. .pmc_type = PPC_PMC_G4,
  891. .cpu_setup = __setup_cpu_7400,
  892. .machine_check = machine_check_generic,
  893. .platform = "ppc7400",
  894. },
  895. { /* 7410 */
  896. .pvr_mask = 0xffff0000,
  897. .pvr_value = 0x800c0000,
  898. .cpu_name = "7410",
  899. .cpu_features = CPU_FTRS_7400,
  900. .cpu_user_features = COMMON_USER |
  901. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  902. .mmu_features = MMU_FTR_HPTE_TABLE,
  903. .icache_bsize = 32,
  904. .dcache_bsize = 32,
  905. .num_pmcs = 4,
  906. .pmc_type = PPC_PMC_G4,
  907. .cpu_setup = __setup_cpu_7410,
  908. .machine_check = machine_check_generic,
  909. .platform = "ppc7400",
  910. },
  911. { /* 7450 2.0 - no doze/nap */
  912. .pvr_mask = 0xffffffff,
  913. .pvr_value = 0x80000200,
  914. .cpu_name = "7450",
  915. .cpu_features = CPU_FTRS_7450_20,
  916. .cpu_user_features = COMMON_USER |
  917. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  918. .mmu_features = MMU_FTR_HPTE_TABLE,
  919. .icache_bsize = 32,
  920. .dcache_bsize = 32,
  921. .num_pmcs = 6,
  922. .pmc_type = PPC_PMC_G4,
  923. .cpu_setup = __setup_cpu_745x,
  924. .oprofile_cpu_type = "ppc/7450",
  925. .oprofile_type = PPC_OPROFILE_G4,
  926. .machine_check = machine_check_generic,
  927. .platform = "ppc7450",
  928. },
  929. { /* 7450 2.1 */
  930. .pvr_mask = 0xffffffff,
  931. .pvr_value = 0x80000201,
  932. .cpu_name = "7450",
  933. .cpu_features = CPU_FTRS_7450_21,
  934. .cpu_user_features = COMMON_USER |
  935. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  936. .mmu_features = MMU_FTR_HPTE_TABLE,
  937. .icache_bsize = 32,
  938. .dcache_bsize = 32,
  939. .num_pmcs = 6,
  940. .pmc_type = PPC_PMC_G4,
  941. .cpu_setup = __setup_cpu_745x,
  942. .oprofile_cpu_type = "ppc/7450",
  943. .oprofile_type = PPC_OPROFILE_G4,
  944. .machine_check = machine_check_generic,
  945. .platform = "ppc7450",
  946. },
  947. { /* 7450 2.3 and newer */
  948. .pvr_mask = 0xffff0000,
  949. .pvr_value = 0x80000000,
  950. .cpu_name = "7450",
  951. .cpu_features = CPU_FTRS_7450_23,
  952. .cpu_user_features = COMMON_USER |
  953. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  954. .mmu_features = MMU_FTR_HPTE_TABLE,
  955. .icache_bsize = 32,
  956. .dcache_bsize = 32,
  957. .num_pmcs = 6,
  958. .pmc_type = PPC_PMC_G4,
  959. .cpu_setup = __setup_cpu_745x,
  960. .oprofile_cpu_type = "ppc/7450",
  961. .oprofile_type = PPC_OPROFILE_G4,
  962. .machine_check = machine_check_generic,
  963. .platform = "ppc7450",
  964. },
  965. { /* 7455 rev 1.x */
  966. .pvr_mask = 0xffffff00,
  967. .pvr_value = 0x80010100,
  968. .cpu_name = "7455",
  969. .cpu_features = CPU_FTRS_7455_1,
  970. .cpu_user_features = COMMON_USER |
  971. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  972. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  973. .icache_bsize = 32,
  974. .dcache_bsize = 32,
  975. .num_pmcs = 6,
  976. .pmc_type = PPC_PMC_G4,
  977. .cpu_setup = __setup_cpu_745x,
  978. .oprofile_cpu_type = "ppc/7450",
  979. .oprofile_type = PPC_OPROFILE_G4,
  980. .machine_check = machine_check_generic,
  981. .platform = "ppc7450",
  982. },
  983. { /* 7455 rev 2.0 */
  984. .pvr_mask = 0xffffffff,
  985. .pvr_value = 0x80010200,
  986. .cpu_name = "7455",
  987. .cpu_features = CPU_FTRS_7455_20,
  988. .cpu_user_features = COMMON_USER |
  989. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  990. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  991. .icache_bsize = 32,
  992. .dcache_bsize = 32,
  993. .num_pmcs = 6,
  994. .pmc_type = PPC_PMC_G4,
  995. .cpu_setup = __setup_cpu_745x,
  996. .oprofile_cpu_type = "ppc/7450",
  997. .oprofile_type = PPC_OPROFILE_G4,
  998. .machine_check = machine_check_generic,
  999. .platform = "ppc7450",
  1000. },
  1001. { /* 7455 others */
  1002. .pvr_mask = 0xffff0000,
  1003. .pvr_value = 0x80010000,
  1004. .cpu_name = "7455",
  1005. .cpu_features = CPU_FTRS_7455,
  1006. .cpu_user_features = COMMON_USER |
  1007. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1008. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1009. .icache_bsize = 32,
  1010. .dcache_bsize = 32,
  1011. .num_pmcs = 6,
  1012. .pmc_type = PPC_PMC_G4,
  1013. .cpu_setup = __setup_cpu_745x,
  1014. .oprofile_cpu_type = "ppc/7450",
  1015. .oprofile_type = PPC_OPROFILE_G4,
  1016. .machine_check = machine_check_generic,
  1017. .platform = "ppc7450",
  1018. },
  1019. { /* 7447/7457 Rev 1.0 */
  1020. .pvr_mask = 0xffffffff,
  1021. .pvr_value = 0x80020100,
  1022. .cpu_name = "7447/7457",
  1023. .cpu_features = CPU_FTRS_7447_10,
  1024. .cpu_user_features = COMMON_USER |
  1025. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1026. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1027. .icache_bsize = 32,
  1028. .dcache_bsize = 32,
  1029. .num_pmcs = 6,
  1030. .pmc_type = PPC_PMC_G4,
  1031. .cpu_setup = __setup_cpu_745x,
  1032. .oprofile_cpu_type = "ppc/7450",
  1033. .oprofile_type = PPC_OPROFILE_G4,
  1034. .machine_check = machine_check_generic,
  1035. .platform = "ppc7450",
  1036. },
  1037. { /* 7447/7457 Rev 1.1 */
  1038. .pvr_mask = 0xffffffff,
  1039. .pvr_value = 0x80020101,
  1040. .cpu_name = "7447/7457",
  1041. .cpu_features = CPU_FTRS_7447_10,
  1042. .cpu_user_features = COMMON_USER |
  1043. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1044. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1045. .icache_bsize = 32,
  1046. .dcache_bsize = 32,
  1047. .num_pmcs = 6,
  1048. .pmc_type = PPC_PMC_G4,
  1049. .cpu_setup = __setup_cpu_745x,
  1050. .oprofile_cpu_type = "ppc/7450",
  1051. .oprofile_type = PPC_OPROFILE_G4,
  1052. .machine_check = machine_check_generic,
  1053. .platform = "ppc7450",
  1054. },
  1055. { /* 7447/7457 Rev 1.2 and later */
  1056. .pvr_mask = 0xffff0000,
  1057. .pvr_value = 0x80020000,
  1058. .cpu_name = "7447/7457",
  1059. .cpu_features = CPU_FTRS_7447,
  1060. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1061. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1062. .icache_bsize = 32,
  1063. .dcache_bsize = 32,
  1064. .num_pmcs = 6,
  1065. .pmc_type = PPC_PMC_G4,
  1066. .cpu_setup = __setup_cpu_745x,
  1067. .oprofile_cpu_type = "ppc/7450",
  1068. .oprofile_type = PPC_OPROFILE_G4,
  1069. .machine_check = machine_check_generic,
  1070. .platform = "ppc7450",
  1071. },
  1072. { /* 7447A */
  1073. .pvr_mask = 0xffff0000,
  1074. .pvr_value = 0x80030000,
  1075. .cpu_name = "7447A",
  1076. .cpu_features = CPU_FTRS_7447A,
  1077. .cpu_user_features = COMMON_USER |
  1078. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1079. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1080. .icache_bsize = 32,
  1081. .dcache_bsize = 32,
  1082. .num_pmcs = 6,
  1083. .pmc_type = PPC_PMC_G4,
  1084. .cpu_setup = __setup_cpu_745x,
  1085. .oprofile_cpu_type = "ppc/7450",
  1086. .oprofile_type = PPC_OPROFILE_G4,
  1087. .machine_check = machine_check_generic,
  1088. .platform = "ppc7450",
  1089. },
  1090. { /* 7448 */
  1091. .pvr_mask = 0xffff0000,
  1092. .pvr_value = 0x80040000,
  1093. .cpu_name = "7448",
  1094. .cpu_features = CPU_FTRS_7448,
  1095. .cpu_user_features = COMMON_USER |
  1096. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1097. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1098. .icache_bsize = 32,
  1099. .dcache_bsize = 32,
  1100. .num_pmcs = 6,
  1101. .pmc_type = PPC_PMC_G4,
  1102. .cpu_setup = __setup_cpu_745x,
  1103. .oprofile_cpu_type = "ppc/7450",
  1104. .oprofile_type = PPC_OPROFILE_G4,
  1105. .machine_check = machine_check_generic,
  1106. .platform = "ppc7450",
  1107. },
  1108. { /* 82xx (8240, 8245, 8260 are all 603e cores) */
  1109. .pvr_mask = 0x7fff0000,
  1110. .pvr_value = 0x00810000,
  1111. .cpu_name = "82xx",
  1112. .cpu_features = CPU_FTRS_82XX,
  1113. .cpu_user_features = COMMON_USER,
  1114. .mmu_features = 0,
  1115. .icache_bsize = 32,
  1116. .dcache_bsize = 32,
  1117. .cpu_setup = __setup_cpu_603,
  1118. .machine_check = machine_check_generic,
  1119. .platform = "ppc603",
  1120. },
  1121. { /* All G2_LE (603e core, plus some) have the same pvr */
  1122. .pvr_mask = 0x7fff0000,
  1123. .pvr_value = 0x00820000,
  1124. .cpu_name = "G2_LE",
  1125. .cpu_features = CPU_FTRS_G2_LE,
  1126. .cpu_user_features = COMMON_USER,
  1127. .mmu_features = MMU_FTR_USE_HIGH_BATS,
  1128. .icache_bsize = 32,
  1129. .dcache_bsize = 32,
  1130. .cpu_setup = __setup_cpu_603,
  1131. .machine_check = machine_check_generic,
  1132. .platform = "ppc603",
  1133. },
  1134. { /* e300c1 (a 603e core, plus some) on 83xx */
  1135. .pvr_mask = 0x7fff0000,
  1136. .pvr_value = 0x00830000,
  1137. .cpu_name = "e300c1",
  1138. .cpu_features = CPU_FTRS_E300,
  1139. .cpu_user_features = COMMON_USER,
  1140. .mmu_features = MMU_FTR_USE_HIGH_BATS,
  1141. .icache_bsize = 32,
  1142. .dcache_bsize = 32,
  1143. .cpu_setup = __setup_cpu_603,
  1144. .machine_check = machine_check_generic,
  1145. .platform = "ppc603",
  1146. },
  1147. { /* e300c2 (an e300c1 core, plus some, minus FPU) on 83xx */
  1148. .pvr_mask = 0x7fff0000,
  1149. .pvr_value = 0x00840000,
  1150. .cpu_name = "e300c2",
  1151. .cpu_features = CPU_FTRS_E300C2,
  1152. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1153. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1154. MMU_FTR_NEED_DTLB_SW_LRU,
  1155. .icache_bsize = 32,
  1156. .dcache_bsize = 32,
  1157. .cpu_setup = __setup_cpu_603,
  1158. .machine_check = machine_check_generic,
  1159. .platform = "ppc603",
  1160. },
  1161. { /* e300c3 (e300c1, plus one IU, half cache size) on 83xx */
  1162. .pvr_mask = 0x7fff0000,
  1163. .pvr_value = 0x00850000,
  1164. .cpu_name = "e300c3",
  1165. .cpu_features = CPU_FTRS_E300,
  1166. .cpu_user_features = COMMON_USER,
  1167. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1168. MMU_FTR_NEED_DTLB_SW_LRU,
  1169. .icache_bsize = 32,
  1170. .dcache_bsize = 32,
  1171. .cpu_setup = __setup_cpu_603,
  1172. .machine_check = machine_check_generic,
  1173. .num_pmcs = 4,
  1174. .oprofile_cpu_type = "ppc/e300",
  1175. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1176. .platform = "ppc603",
  1177. },
  1178. { /* e300c4 (e300c1, plus one IU) */
  1179. .pvr_mask = 0x7fff0000,
  1180. .pvr_value = 0x00860000,
  1181. .cpu_name = "e300c4",
  1182. .cpu_features = CPU_FTRS_E300,
  1183. .cpu_user_features = COMMON_USER,
  1184. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1185. MMU_FTR_NEED_DTLB_SW_LRU,
  1186. .icache_bsize = 32,
  1187. .dcache_bsize = 32,
  1188. .cpu_setup = __setup_cpu_603,
  1189. .machine_check = machine_check_generic,
  1190. .num_pmcs = 4,
  1191. .oprofile_cpu_type = "ppc/e300",
  1192. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1193. .platform = "ppc603",
  1194. },
  1195. { /* default match, we assume split I/D cache & TB (non-601)... */
  1196. .pvr_mask = 0x00000000,
  1197. .pvr_value = 0x00000000,
  1198. .cpu_name = "(generic PPC)",
  1199. .cpu_features = CPU_FTRS_CLASSIC32,
  1200. .cpu_user_features = COMMON_USER,
  1201. .mmu_features = MMU_FTR_HPTE_TABLE,
  1202. .icache_bsize = 32,
  1203. .dcache_bsize = 32,
  1204. .machine_check = machine_check_generic,
  1205. .platform = "ppc603",
  1206. },
  1207. #endif /* CONFIG_PPC_BOOK3S_32 */
  1208. #ifdef CONFIG_PPC_8xx
  1209. { /* 8xx */
  1210. .pvr_mask = 0xffff0000,
  1211. .pvr_value = PVR_8xx,
  1212. .cpu_name = "8xx",
  1213. /* CPU_FTR_MAYBE_CAN_DOZE is possible,
  1214. * if the 8xx code is there.... */
  1215. .cpu_features = CPU_FTRS_8XX,
  1216. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1217. .mmu_features = MMU_FTR_TYPE_8xx,
  1218. .icache_bsize = 16,
  1219. .dcache_bsize = 16,
  1220. .machine_check = machine_check_8xx,
  1221. .platform = "ppc823",
  1222. },
  1223. #endif /* CONFIG_PPC_8xx */
  1224. #ifdef CONFIG_40x
  1225. { /* 403GC */
  1226. .pvr_mask = 0xffffff00,
  1227. .pvr_value = 0x00200200,
  1228. .cpu_name = "403GC",
  1229. .cpu_features = CPU_FTRS_40X,
  1230. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1231. .mmu_features = MMU_FTR_TYPE_40x,
  1232. .icache_bsize = 16,
  1233. .dcache_bsize = 16,
  1234. .machine_check = machine_check_4xx,
  1235. .platform = "ppc403",
  1236. },
  1237. { /* 403GCX */
  1238. .pvr_mask = 0xffffff00,
  1239. .pvr_value = 0x00201400,
  1240. .cpu_name = "403GCX",
  1241. .cpu_features = CPU_FTRS_40X,
  1242. .cpu_user_features = PPC_FEATURE_32 |
  1243. PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB,
  1244. .mmu_features = MMU_FTR_TYPE_40x,
  1245. .icache_bsize = 16,
  1246. .dcache_bsize = 16,
  1247. .machine_check = machine_check_4xx,
  1248. .platform = "ppc403",
  1249. },
  1250. { /* 403G ?? */
  1251. .pvr_mask = 0xffff0000,
  1252. .pvr_value = 0x00200000,
  1253. .cpu_name = "403G ??",
  1254. .cpu_features = CPU_FTRS_40X,
  1255. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1256. .mmu_features = MMU_FTR_TYPE_40x,
  1257. .icache_bsize = 16,
  1258. .dcache_bsize = 16,
  1259. .machine_check = machine_check_4xx,
  1260. .platform = "ppc403",
  1261. },
  1262. { /* 405GP */
  1263. .pvr_mask = 0xffff0000,
  1264. .pvr_value = 0x40110000,
  1265. .cpu_name = "405GP",
  1266. .cpu_features = CPU_FTRS_40X,
  1267. .cpu_user_features = PPC_FEATURE_32 |
  1268. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1269. .mmu_features = MMU_FTR_TYPE_40x,
  1270. .icache_bsize = 32,
  1271. .dcache_bsize = 32,
  1272. .machine_check = machine_check_4xx,
  1273. .platform = "ppc405",
  1274. },
  1275. { /* STB 03xxx */
  1276. .pvr_mask = 0xffff0000,
  1277. .pvr_value = 0x40130000,
  1278. .cpu_name = "STB03xxx",
  1279. .cpu_features = CPU_FTRS_40X,
  1280. .cpu_user_features = PPC_FEATURE_32 |
  1281. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1282. .mmu_features = MMU_FTR_TYPE_40x,
  1283. .icache_bsize = 32,
  1284. .dcache_bsize = 32,
  1285. .machine_check = machine_check_4xx,
  1286. .platform = "ppc405",
  1287. },
  1288. { /* STB 04xxx */
  1289. .pvr_mask = 0xffff0000,
  1290. .pvr_value = 0x41810000,
  1291. .cpu_name = "STB04xxx",
  1292. .cpu_features = CPU_FTRS_40X,
  1293. .cpu_user_features = PPC_FEATURE_32 |
  1294. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1295. .mmu_features = MMU_FTR_TYPE_40x,
  1296. .icache_bsize = 32,
  1297. .dcache_bsize = 32,
  1298. .machine_check = machine_check_4xx,
  1299. .platform = "ppc405",
  1300. },
  1301. { /* NP405L */
  1302. .pvr_mask = 0xffff0000,
  1303. .pvr_value = 0x41610000,
  1304. .cpu_name = "NP405L",
  1305. .cpu_features = CPU_FTRS_40X,
  1306. .cpu_user_features = PPC_FEATURE_32 |
  1307. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1308. .mmu_features = MMU_FTR_TYPE_40x,
  1309. .icache_bsize = 32,
  1310. .dcache_bsize = 32,
  1311. .machine_check = machine_check_4xx,
  1312. .platform = "ppc405",
  1313. },
  1314. { /* NP4GS3 */
  1315. .pvr_mask = 0xffff0000,
  1316. .pvr_value = 0x40B10000,
  1317. .cpu_name = "NP4GS3",
  1318. .cpu_features = CPU_FTRS_40X,
  1319. .cpu_user_features = PPC_FEATURE_32 |
  1320. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1321. .mmu_features = MMU_FTR_TYPE_40x,
  1322. .icache_bsize = 32,
  1323. .dcache_bsize = 32,
  1324. .machine_check = machine_check_4xx,
  1325. .platform = "ppc405",
  1326. },
  1327. { /* NP405H */
  1328. .pvr_mask = 0xffff0000,
  1329. .pvr_value = 0x41410000,
  1330. .cpu_name = "NP405H",
  1331. .cpu_features = CPU_FTRS_40X,
  1332. .cpu_user_features = PPC_FEATURE_32 |
  1333. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1334. .mmu_features = MMU_FTR_TYPE_40x,
  1335. .icache_bsize = 32,
  1336. .dcache_bsize = 32,
  1337. .machine_check = machine_check_4xx,
  1338. .platform = "ppc405",
  1339. },
  1340. { /* 405GPr */
  1341. .pvr_mask = 0xffff0000,
  1342. .pvr_value = 0x50910000,
  1343. .cpu_name = "405GPr",
  1344. .cpu_features = CPU_FTRS_40X,
  1345. .cpu_user_features = PPC_FEATURE_32 |
  1346. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1347. .mmu_features = MMU_FTR_TYPE_40x,
  1348. .icache_bsize = 32,
  1349. .dcache_bsize = 32,
  1350. .machine_check = machine_check_4xx,
  1351. .platform = "ppc405",
  1352. },
  1353. { /* STBx25xx */
  1354. .pvr_mask = 0xffff0000,
  1355. .pvr_value = 0x51510000,
  1356. .cpu_name = "STBx25xx",
  1357. .cpu_features = CPU_FTRS_40X,
  1358. .cpu_user_features = PPC_FEATURE_32 |
  1359. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1360. .mmu_features = MMU_FTR_TYPE_40x,
  1361. .icache_bsize = 32,
  1362. .dcache_bsize = 32,
  1363. .machine_check = machine_check_4xx,
  1364. .platform = "ppc405",
  1365. },
  1366. { /* 405LP */
  1367. .pvr_mask = 0xffff0000,
  1368. .pvr_value = 0x41F10000,
  1369. .cpu_name = "405LP",
  1370. .cpu_features = CPU_FTRS_40X,
  1371. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1372. .mmu_features = MMU_FTR_TYPE_40x,
  1373. .icache_bsize = 32,
  1374. .dcache_bsize = 32,
  1375. .machine_check = machine_check_4xx,
  1376. .platform = "ppc405",
  1377. },
  1378. { /* Xilinx Virtex-II Pro */
  1379. .pvr_mask = 0xfffff000,
  1380. .pvr_value = 0x20010000,
  1381. .cpu_name = "Virtex-II Pro",
  1382. .cpu_features = CPU_FTRS_40X,
  1383. .cpu_user_features = PPC_FEATURE_32 |
  1384. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1385. .mmu_features = MMU_FTR_TYPE_40x,
  1386. .icache_bsize = 32,
  1387. .dcache_bsize = 32,
  1388. .machine_check = machine_check_4xx,
  1389. .platform = "ppc405",
  1390. },
  1391. { /* Xilinx Virtex-4 FX */
  1392. .pvr_mask = 0xfffff000,
  1393. .pvr_value = 0x20011000,
  1394. .cpu_name = "Virtex-4 FX",
  1395. .cpu_features = CPU_FTRS_40X,
  1396. .cpu_user_features = PPC_FEATURE_32 |
  1397. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1398. .mmu_features = MMU_FTR_TYPE_40x,
  1399. .icache_bsize = 32,
  1400. .dcache_bsize = 32,
  1401. .machine_check = machine_check_4xx,
  1402. .platform = "ppc405",
  1403. },
  1404. { /* 405EP */
  1405. .pvr_mask = 0xffff0000,
  1406. .pvr_value = 0x51210000,
  1407. .cpu_name = "405EP",
  1408. .cpu_features = CPU_FTRS_40X,
  1409. .cpu_user_features = PPC_FEATURE_32 |
  1410. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1411. .mmu_features = MMU_FTR_TYPE_40x,
  1412. .icache_bsize = 32,
  1413. .dcache_bsize = 32,
  1414. .machine_check = machine_check_4xx,
  1415. .platform = "ppc405",
  1416. },
  1417. { /* 405EX Rev. A/B with Security */
  1418. .pvr_mask = 0xffff000f,
  1419. .pvr_value = 0x12910007,
  1420. .cpu_name = "405EX Rev. A/B",
  1421. .cpu_features = CPU_FTRS_40X,
  1422. .cpu_user_features = PPC_FEATURE_32 |
  1423. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1424. .mmu_features = MMU_FTR_TYPE_40x,
  1425. .icache_bsize = 32,
  1426. .dcache_bsize = 32,
  1427. .machine_check = machine_check_4xx,
  1428. .platform = "ppc405",
  1429. },
  1430. { /* 405EX Rev. C without Security */
  1431. .pvr_mask = 0xffff000f,
  1432. .pvr_value = 0x1291000d,
  1433. .cpu_name = "405EX Rev. C",
  1434. .cpu_features = CPU_FTRS_40X,
  1435. .cpu_user_features = PPC_FEATURE_32 |
  1436. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1437. .mmu_features = MMU_FTR_TYPE_40x,
  1438. .icache_bsize = 32,
  1439. .dcache_bsize = 32,
  1440. .machine_check = machine_check_4xx,
  1441. .platform = "ppc405",
  1442. },
  1443. { /* 405EX Rev. C with Security */
  1444. .pvr_mask = 0xffff000f,
  1445. .pvr_value = 0x1291000f,
  1446. .cpu_name = "405EX Rev. C",
  1447. .cpu_features = CPU_FTRS_40X,
  1448. .cpu_user_features = PPC_FEATURE_32 |
  1449. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1450. .mmu_features = MMU_FTR_TYPE_40x,
  1451. .icache_bsize = 32,
  1452. .dcache_bsize = 32,
  1453. .machine_check = machine_check_4xx,
  1454. .platform = "ppc405",
  1455. },
  1456. { /* 405EX Rev. D without Security */
  1457. .pvr_mask = 0xffff000f,
  1458. .pvr_value = 0x12910003,
  1459. .cpu_name = "405EX Rev. D",
  1460. .cpu_features = CPU_FTRS_40X,
  1461. .cpu_user_features = PPC_FEATURE_32 |
  1462. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1463. .mmu_features = MMU_FTR_TYPE_40x,
  1464. .icache_bsize = 32,
  1465. .dcache_bsize = 32,
  1466. .machine_check = machine_check_4xx,
  1467. .platform = "ppc405",
  1468. },
  1469. { /* 405EX Rev. D with Security */
  1470. .pvr_mask = 0xffff000f,
  1471. .pvr_value = 0x12910005,
  1472. .cpu_name = "405EX Rev. D",
  1473. .cpu_features = CPU_FTRS_40X,
  1474. .cpu_user_features = PPC_FEATURE_32 |
  1475. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1476. .mmu_features = MMU_FTR_TYPE_40x,
  1477. .icache_bsize = 32,
  1478. .dcache_bsize = 32,
  1479. .machine_check = machine_check_4xx,
  1480. .platform = "ppc405",
  1481. },
  1482. { /* 405EXr Rev. A/B without Security */
  1483. .pvr_mask = 0xffff000f,
  1484. .pvr_value = 0x12910001,
  1485. .cpu_name = "405EXr Rev. A/B",
  1486. .cpu_features = CPU_FTRS_40X,
  1487. .cpu_user_features = PPC_FEATURE_32 |
  1488. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1489. .mmu_features = MMU_FTR_TYPE_40x,
  1490. .icache_bsize = 32,
  1491. .dcache_bsize = 32,
  1492. .machine_check = machine_check_4xx,
  1493. .platform = "ppc405",
  1494. },
  1495. { /* 405EXr Rev. C without Security */
  1496. .pvr_mask = 0xffff000f,
  1497. .pvr_value = 0x12910009,
  1498. .cpu_name = "405EXr Rev. C",
  1499. .cpu_features = CPU_FTRS_40X,
  1500. .cpu_user_features = PPC_FEATURE_32 |
  1501. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1502. .mmu_features = MMU_FTR_TYPE_40x,
  1503. .icache_bsize = 32,
  1504. .dcache_bsize = 32,
  1505. .machine_check = machine_check_4xx,
  1506. .platform = "ppc405",
  1507. },
  1508. { /* 405EXr Rev. C with Security */
  1509. .pvr_mask = 0xffff000f,
  1510. .pvr_value = 0x1291000b,
  1511. .cpu_name = "405EXr Rev. C",
  1512. .cpu_features = CPU_FTRS_40X,
  1513. .cpu_user_features = PPC_FEATURE_32 |
  1514. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1515. .mmu_features = MMU_FTR_TYPE_40x,
  1516. .icache_bsize = 32,
  1517. .dcache_bsize = 32,
  1518. .machine_check = machine_check_4xx,
  1519. .platform = "ppc405",
  1520. },
  1521. { /* 405EXr Rev. D without Security */
  1522. .pvr_mask = 0xffff000f,
  1523. .pvr_value = 0x12910000,
  1524. .cpu_name = "405EXr Rev. D",
  1525. .cpu_features = CPU_FTRS_40X,
  1526. .cpu_user_features = PPC_FEATURE_32 |
  1527. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1528. .mmu_features = MMU_FTR_TYPE_40x,
  1529. .icache_bsize = 32,
  1530. .dcache_bsize = 32,
  1531. .machine_check = machine_check_4xx,
  1532. .platform = "ppc405",
  1533. },
  1534. { /* 405EXr Rev. D with Security */
  1535. .pvr_mask = 0xffff000f,
  1536. .pvr_value = 0x12910002,
  1537. .cpu_name = "405EXr Rev. D",
  1538. .cpu_features = CPU_FTRS_40X,
  1539. .cpu_user_features = PPC_FEATURE_32 |
  1540. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1541. .mmu_features = MMU_FTR_TYPE_40x,
  1542. .icache_bsize = 32,
  1543. .dcache_bsize = 32,
  1544. .machine_check = machine_check_4xx,
  1545. .platform = "ppc405",
  1546. },
  1547. {
  1548. /* 405EZ */
  1549. .pvr_mask = 0xffff0000,
  1550. .pvr_value = 0x41510000,
  1551. .cpu_name = "405EZ",
  1552. .cpu_features = CPU_FTRS_40X,
  1553. .cpu_user_features = PPC_FEATURE_32 |
  1554. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1555. .mmu_features = MMU_FTR_TYPE_40x,
  1556. .icache_bsize = 32,
  1557. .dcache_bsize = 32,
  1558. .machine_check = machine_check_4xx,
  1559. .platform = "ppc405",
  1560. },
  1561. { /* APM8018X */
  1562. .pvr_mask = 0xffff0000,
  1563. .pvr_value = 0x7ff11432,
  1564. .cpu_name = "APM8018X",
  1565. .cpu_features = CPU_FTRS_40X,
  1566. .cpu_user_features = PPC_FEATURE_32 |
  1567. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1568. .mmu_features = MMU_FTR_TYPE_40x,
  1569. .icache_bsize = 32,
  1570. .dcache_bsize = 32,
  1571. .machine_check = machine_check_4xx,
  1572. .platform = "ppc405",
  1573. },
  1574. { /* default match */
  1575. .pvr_mask = 0x00000000,
  1576. .pvr_value = 0x00000000,
  1577. .cpu_name = "(generic 40x PPC)",
  1578. .cpu_features = CPU_FTRS_40X,
  1579. .cpu_user_features = PPC_FEATURE_32 |
  1580. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1581. .mmu_features = MMU_FTR_TYPE_40x,
  1582. .icache_bsize = 32,
  1583. .dcache_bsize = 32,
  1584. .machine_check = machine_check_4xx,
  1585. .platform = "ppc405",
  1586. }
  1587. #endif /* CONFIG_40x */
  1588. #ifdef CONFIG_44x
  1589. {
  1590. .pvr_mask = 0xf0000fff,
  1591. .pvr_value = 0x40000850,
  1592. .cpu_name = "440GR Rev. A",
  1593. .cpu_features = CPU_FTRS_44X,
  1594. .cpu_user_features = COMMON_USER_BOOKE,
  1595. .mmu_features = MMU_FTR_TYPE_44x,
  1596. .icache_bsize = 32,
  1597. .dcache_bsize = 32,
  1598. .machine_check = machine_check_4xx,
  1599. .platform = "ppc440",
  1600. },
  1601. { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1602. .pvr_mask = 0xf0000fff,
  1603. .pvr_value = 0x40000858,
  1604. .cpu_name = "440EP Rev. A",
  1605. .cpu_features = CPU_FTRS_44X,
  1606. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1607. .mmu_features = MMU_FTR_TYPE_44x,
  1608. .icache_bsize = 32,
  1609. .dcache_bsize = 32,
  1610. .cpu_setup = __setup_cpu_440ep,
  1611. .machine_check = machine_check_4xx,
  1612. .platform = "ppc440",
  1613. },
  1614. {
  1615. .pvr_mask = 0xf0000fff,
  1616. .pvr_value = 0x400008d3,
  1617. .cpu_name = "440GR Rev. B",
  1618. .cpu_features = CPU_FTRS_44X,
  1619. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1620. .mmu_features = MMU_FTR_TYPE_44x,
  1621. .icache_bsize = 32,
  1622. .dcache_bsize = 32,
  1623. .machine_check = machine_check_4xx,
  1624. .platform = "ppc440",
  1625. },
  1626. { /* Matches both physical and logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1627. .pvr_mask = 0xf0000ff7,
  1628. .pvr_value = 0x400008d4,
  1629. .cpu_name = "440EP Rev. C",
  1630. .cpu_features = CPU_FTRS_44X,
  1631. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1632. .mmu_features = MMU_FTR_TYPE_44x,
  1633. .icache_bsize = 32,
  1634. .dcache_bsize = 32,
  1635. .cpu_setup = __setup_cpu_440ep,
  1636. .machine_check = machine_check_4xx,
  1637. .platform = "ppc440",
  1638. },
  1639. { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1640. .pvr_mask = 0xf0000fff,
  1641. .pvr_value = 0x400008db,
  1642. .cpu_name = "440EP Rev. B",
  1643. .cpu_features = CPU_FTRS_44X,
  1644. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1645. .mmu_features = MMU_FTR_TYPE_44x,
  1646. .icache_bsize = 32,
  1647. .dcache_bsize = 32,
  1648. .cpu_setup = __setup_cpu_440ep,
  1649. .machine_check = machine_check_4xx,
  1650. .platform = "ppc440",
  1651. },
  1652. { /* 440GRX */
  1653. .pvr_mask = 0xf0000ffb,
  1654. .pvr_value = 0x200008D0,
  1655. .cpu_name = "440GRX",
  1656. .cpu_features = CPU_FTRS_44X,
  1657. .cpu_user_features = COMMON_USER_BOOKE,
  1658. .mmu_features = MMU_FTR_TYPE_44x,
  1659. .icache_bsize = 32,
  1660. .dcache_bsize = 32,
  1661. .cpu_setup = __setup_cpu_440grx,
  1662. .machine_check = machine_check_440A,
  1663. .platform = "ppc440",
  1664. },
  1665. { /* Use logical PVR for 440EPx (logical pvr = pvr | 0x8) */
  1666. .pvr_mask = 0xf0000ffb,
  1667. .pvr_value = 0x200008D8,
  1668. .cpu_name = "440EPX",
  1669. .cpu_features = CPU_FTRS_44X,
  1670. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1671. .mmu_features = MMU_FTR_TYPE_44x,
  1672. .icache_bsize = 32,
  1673. .dcache_bsize = 32,
  1674. .cpu_setup = __setup_cpu_440epx,
  1675. .machine_check = machine_check_440A,
  1676. .platform = "ppc440",
  1677. },
  1678. { /* 440GP Rev. B */
  1679. .pvr_mask = 0xf0000fff,
  1680. .pvr_value = 0x40000440,
  1681. .cpu_name = "440GP Rev. B",
  1682. .cpu_features = CPU_FTRS_44X,
  1683. .cpu_user_features = COMMON_USER_BOOKE,
  1684. .mmu_features = MMU_FTR_TYPE_44x,
  1685. .icache_bsize = 32,
  1686. .dcache_bsize = 32,
  1687. .machine_check = machine_check_4xx,
  1688. .platform = "ppc440gp",
  1689. },
  1690. { /* 440GP Rev. C */
  1691. .pvr_mask = 0xf0000fff,
  1692. .pvr_value = 0x40000481,
  1693. .cpu_name = "440GP Rev. C",
  1694. .cpu_features = CPU_FTRS_44X,
  1695. .cpu_user_features = COMMON_USER_BOOKE,
  1696. .mmu_features = MMU_FTR_TYPE_44x,
  1697. .icache_bsize = 32,
  1698. .dcache_bsize = 32,
  1699. .machine_check = machine_check_4xx,
  1700. .platform = "ppc440gp",
  1701. },
  1702. { /* 440GX Rev. A */
  1703. .pvr_mask = 0xf0000fff,
  1704. .pvr_value = 0x50000850,
  1705. .cpu_name = "440GX Rev. A",
  1706. .cpu_features = CPU_FTRS_44X,
  1707. .cpu_user_features = COMMON_USER_BOOKE,
  1708. .mmu_features = MMU_FTR_TYPE_44x,
  1709. .icache_bsize = 32,
  1710. .dcache_bsize = 32,
  1711. .cpu_setup = __setup_cpu_440gx,
  1712. .machine_check = machine_check_440A,
  1713. .platform = "ppc440",
  1714. },
  1715. { /* 440GX Rev. B */
  1716. .pvr_mask = 0xf0000fff,
  1717. .pvr_value = 0x50000851,
  1718. .cpu_name = "440GX Rev. B",
  1719. .cpu_features = CPU_FTRS_44X,
  1720. .cpu_user_features = COMMON_USER_BOOKE,
  1721. .mmu_features = MMU_FTR_TYPE_44x,
  1722. .icache_bsize = 32,
  1723. .dcache_bsize = 32,
  1724. .cpu_setup = __setup_cpu_440gx,
  1725. .machine_check = machine_check_440A,
  1726. .platform = "ppc440",
  1727. },
  1728. { /* 440GX Rev. C */
  1729. .pvr_mask = 0xf0000fff,
  1730. .pvr_value = 0x50000892,
  1731. .cpu_name = "440GX Rev. C",
  1732. .cpu_features = CPU_FTRS_44X,
  1733. .cpu_user_features = COMMON_USER_BOOKE,
  1734. .mmu_features = MMU_FTR_TYPE_44x,
  1735. .icache_bsize = 32,
  1736. .dcache_bsize = 32,
  1737. .cpu_setup = __setup_cpu_440gx,
  1738. .machine_check = machine_check_440A,
  1739. .platform = "ppc440",
  1740. },
  1741. { /* 440GX Rev. F */
  1742. .pvr_mask = 0xf0000fff,
  1743. .pvr_value = 0x50000894,
  1744. .cpu_name = "440GX Rev. F",
  1745. .cpu_features = CPU_FTRS_44X,
  1746. .cpu_user_features = COMMON_USER_BOOKE,
  1747. .mmu_features = MMU_FTR_TYPE_44x,
  1748. .icache_bsize = 32,
  1749. .dcache_bsize = 32,
  1750. .cpu_setup = __setup_cpu_440gx,
  1751. .machine_check = machine_check_440A,
  1752. .platform = "ppc440",
  1753. },
  1754. { /* 440SP Rev. A */
  1755. .pvr_mask = 0xfff00fff,
  1756. .pvr_value = 0x53200891,
  1757. .cpu_name = "440SP Rev. A",
  1758. .cpu_features = CPU_FTRS_44X,
  1759. .cpu_user_features = COMMON_USER_BOOKE,
  1760. .mmu_features = MMU_FTR_TYPE_44x,
  1761. .icache_bsize = 32,
  1762. .dcache_bsize = 32,
  1763. .machine_check = machine_check_4xx,
  1764. .platform = "ppc440",
  1765. },
  1766. { /* 440SPe Rev. A */
  1767. .pvr_mask = 0xfff00fff,
  1768. .pvr_value = 0x53400890,
  1769. .cpu_name = "440SPe Rev. A",
  1770. .cpu_features = CPU_FTRS_44X,
  1771. .cpu_user_features = COMMON_USER_BOOKE,
  1772. .mmu_features = MMU_FTR_TYPE_44x,
  1773. .icache_bsize = 32,
  1774. .dcache_bsize = 32,
  1775. .cpu_setup = __setup_cpu_440spe,
  1776. .machine_check = machine_check_440A,
  1777. .platform = "ppc440",
  1778. },
  1779. { /* 440SPe Rev. B */
  1780. .pvr_mask = 0xfff00fff,
  1781. .pvr_value = 0x53400891,
  1782. .cpu_name = "440SPe Rev. B",
  1783. .cpu_features = CPU_FTRS_44X,
  1784. .cpu_user_features = COMMON_USER_BOOKE,
  1785. .mmu_features = MMU_FTR_TYPE_44x,
  1786. .icache_bsize = 32,
  1787. .dcache_bsize = 32,
  1788. .cpu_setup = __setup_cpu_440spe,
  1789. .machine_check = machine_check_440A,
  1790. .platform = "ppc440",
  1791. },
  1792. { /* 440 in Xilinx Virtex-5 FXT */
  1793. .pvr_mask = 0xfffffff0,
  1794. .pvr_value = 0x7ff21910,
  1795. .cpu_name = "440 in Virtex-5 FXT",
  1796. .cpu_features = CPU_FTRS_44X,
  1797. .cpu_user_features = COMMON_USER_BOOKE,
  1798. .mmu_features = MMU_FTR_TYPE_44x,
  1799. .icache_bsize = 32,
  1800. .dcache_bsize = 32,
  1801. .cpu_setup = __setup_cpu_440x5,
  1802. .machine_check = machine_check_440A,
  1803. .platform = "ppc440",
  1804. },
  1805. { /* 460EX */
  1806. .pvr_mask = 0xffff0006,
  1807. .pvr_value = 0x13020002,
  1808. .cpu_name = "460EX",
  1809. .cpu_features = CPU_FTRS_440x6,
  1810. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1811. .mmu_features = MMU_FTR_TYPE_44x,
  1812. .icache_bsize = 32,
  1813. .dcache_bsize = 32,
  1814. .cpu_setup = __setup_cpu_460ex,
  1815. .machine_check = machine_check_440A,
  1816. .platform = "ppc440",
  1817. },
  1818. { /* 460EX Rev B */
  1819. .pvr_mask = 0xffff0007,
  1820. .pvr_value = 0x13020004,
  1821. .cpu_name = "460EX Rev. B",
  1822. .cpu_features = CPU_FTRS_440x6,
  1823. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1824. .mmu_features = MMU_FTR_TYPE_44x,
  1825. .icache_bsize = 32,
  1826. .dcache_bsize = 32,
  1827. .cpu_setup = __setup_cpu_460ex,
  1828. .machine_check = machine_check_440A,
  1829. .platform = "ppc440",
  1830. },
  1831. { /* 460GT */
  1832. .pvr_mask = 0xffff0006,
  1833. .pvr_value = 0x13020000,
  1834. .cpu_name = "460GT",
  1835. .cpu_features = CPU_FTRS_440x6,
  1836. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1837. .mmu_features = MMU_FTR_TYPE_44x,
  1838. .icache_bsize = 32,
  1839. .dcache_bsize = 32,
  1840. .cpu_setup = __setup_cpu_460gt,
  1841. .machine_check = machine_check_440A,
  1842. .platform = "ppc440",
  1843. },
  1844. { /* 460GT Rev B */
  1845. .pvr_mask = 0xffff0007,
  1846. .pvr_value = 0x13020005,
  1847. .cpu_name = "460GT Rev. B",
  1848. .cpu_features = CPU_FTRS_440x6,
  1849. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1850. .mmu_features = MMU_FTR_TYPE_44x,
  1851. .icache_bsize = 32,
  1852. .dcache_bsize = 32,
  1853. .cpu_setup = __setup_cpu_460gt,
  1854. .machine_check = machine_check_440A,
  1855. .platform = "ppc440",
  1856. },
  1857. { /* 460SX */
  1858. .pvr_mask = 0xffffff00,
  1859. .pvr_value = 0x13541800,
  1860. .cpu_name = "460SX",
  1861. .cpu_features = CPU_FTRS_44X,
  1862. .cpu_user_features = COMMON_USER_BOOKE,
  1863. .mmu_features = MMU_FTR_TYPE_44x,
  1864. .icache_bsize = 32,
  1865. .dcache_bsize = 32,
  1866. .cpu_setup = __setup_cpu_460sx,
  1867. .machine_check = machine_check_440A,
  1868. .platform = "ppc440",
  1869. },
  1870. { /* 464 in APM821xx */
  1871. .pvr_mask = 0xfffffff0,
  1872. .pvr_value = 0x12C41C80,
  1873. .cpu_name = "APM821XX",
  1874. .cpu_features = CPU_FTRS_44X,
  1875. .cpu_user_features = COMMON_USER_BOOKE |
  1876. PPC_FEATURE_HAS_FPU,
  1877. .mmu_features = MMU_FTR_TYPE_44x,
  1878. .icache_bsize = 32,
  1879. .dcache_bsize = 32,
  1880. .cpu_setup = __setup_cpu_apm821xx,
  1881. .machine_check = machine_check_440A,
  1882. .platform = "ppc440",
  1883. },
  1884. #ifdef CONFIG_PPC_47x
  1885. { /* 476 DD2 core */
  1886. .pvr_mask = 0xffffffff,
  1887. .pvr_value = 0x11a52080,
  1888. .cpu_name = "476",
  1889. .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD2,
  1890. .cpu_user_features = COMMON_USER_BOOKE |
  1891. PPC_FEATURE_HAS_FPU,
  1892. .mmu_features = MMU_FTR_TYPE_47x |
  1893. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1894. .icache_bsize = 32,
  1895. .dcache_bsize = 128,
  1896. .machine_check = machine_check_47x,
  1897. .platform = "ppc470",
  1898. },
  1899. { /* 476fpe */
  1900. .pvr_mask = 0xffff0000,
  1901. .pvr_value = 0x7ff50000,
  1902. .cpu_name = "476fpe",
  1903. .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD2,
  1904. .cpu_user_features = COMMON_USER_BOOKE |
  1905. PPC_FEATURE_HAS_FPU,
  1906. .mmu_features = MMU_FTR_TYPE_47x |
  1907. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1908. .icache_bsize = 32,
  1909. .dcache_bsize = 128,
  1910. .machine_check = machine_check_47x,
  1911. .platform = "ppc470",
  1912. },
  1913. { /* 476 iss */
  1914. .pvr_mask = 0xffff0000,
  1915. .pvr_value = 0x00050000,
  1916. .cpu_name = "476",
  1917. .cpu_features = CPU_FTRS_47X,
  1918. .cpu_user_features = COMMON_USER_BOOKE |
  1919. PPC_FEATURE_HAS_FPU,
  1920. .mmu_features = MMU_FTR_TYPE_47x |
  1921. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1922. .icache_bsize = 32,
  1923. .dcache_bsize = 128,
  1924. .machine_check = machine_check_47x,
  1925. .platform = "ppc470",
  1926. },
  1927. { /* 476 others */
  1928. .pvr_mask = 0xffff0000,
  1929. .pvr_value = 0x11a50000,
  1930. .cpu_name = "476",
  1931. .cpu_features = CPU_FTRS_47X,
  1932. .cpu_user_features = COMMON_USER_BOOKE |
  1933. PPC_FEATURE_HAS_FPU,
  1934. .mmu_features = MMU_FTR_TYPE_47x |
  1935. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1936. .icache_bsize = 32,
  1937. .dcache_bsize = 128,
  1938. .machine_check = machine_check_47x,
  1939. .platform = "ppc470",
  1940. },
  1941. #endif /* CONFIG_PPC_47x */
  1942. { /* default match */
  1943. .pvr_mask = 0x00000000,
  1944. .pvr_value = 0x00000000,
  1945. .cpu_name = "(generic 44x PPC)",
  1946. .cpu_features = CPU_FTRS_44X,
  1947. .cpu_user_features = COMMON_USER_BOOKE,
  1948. .mmu_features = MMU_FTR_TYPE_44x,
  1949. .icache_bsize = 32,
  1950. .dcache_bsize = 32,
  1951. .machine_check = machine_check_4xx,
  1952. .platform = "ppc440",
  1953. }
  1954. #endif /* CONFIG_44x */
  1955. #ifdef CONFIG_E200
  1956. { /* e200z5 */
  1957. .pvr_mask = 0xfff00000,
  1958. .pvr_value = 0x81000000,
  1959. .cpu_name = "e200z5",
  1960. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1961. .cpu_features = CPU_FTRS_E200,
  1962. .cpu_user_features = COMMON_USER_BOOKE |
  1963. PPC_FEATURE_HAS_EFP_SINGLE |
  1964. PPC_FEATURE_UNIFIED_CACHE,
  1965. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1966. .dcache_bsize = 32,
  1967. .machine_check = machine_check_e200,
  1968. .platform = "ppc5554",
  1969. },
  1970. { /* e200z6 */
  1971. .pvr_mask = 0xfff00000,
  1972. .pvr_value = 0x81100000,
  1973. .cpu_name = "e200z6",
  1974. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1975. .cpu_features = CPU_FTRS_E200,
  1976. .cpu_user_features = COMMON_USER_BOOKE |
  1977. PPC_FEATURE_HAS_SPE_COMP |
  1978. PPC_FEATURE_HAS_EFP_SINGLE_COMP |
  1979. PPC_FEATURE_UNIFIED_CACHE,
  1980. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1981. .dcache_bsize = 32,
  1982. .machine_check = machine_check_e200,
  1983. .platform = "ppc5554",
  1984. },
  1985. { /* default match */
  1986. .pvr_mask = 0x00000000,
  1987. .pvr_value = 0x00000000,
  1988. .cpu_name = "(generic E200 PPC)",
  1989. .cpu_features = CPU_FTRS_E200,
  1990. .cpu_user_features = COMMON_USER_BOOKE |
  1991. PPC_FEATURE_HAS_EFP_SINGLE |
  1992. PPC_FEATURE_UNIFIED_CACHE,
  1993. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1994. .dcache_bsize = 32,
  1995. .cpu_setup = __setup_cpu_e200,
  1996. .machine_check = machine_check_e200,
  1997. .platform = "ppc5554",
  1998. }
  1999. #endif /* CONFIG_E200 */
  2000. #endif /* CONFIG_PPC32 */
  2001. #ifdef CONFIG_E500
  2002. #ifdef CONFIG_PPC32
  2003. #ifndef CONFIG_PPC_E500MC
  2004. { /* e500 */
  2005. .pvr_mask = 0xffff0000,
  2006. .pvr_value = 0x80200000,
  2007. .cpu_name = "e500",
  2008. .cpu_features = CPU_FTRS_E500,
  2009. .cpu_user_features = COMMON_USER_BOOKE |
  2010. PPC_FEATURE_HAS_SPE_COMP |
  2011. PPC_FEATURE_HAS_EFP_SINGLE_COMP,
  2012. .cpu_user_features2 = PPC_FEATURE2_ISEL,
  2013. .mmu_features = MMU_FTR_TYPE_FSL_E,
  2014. .icache_bsize = 32,
  2015. .dcache_bsize = 32,
  2016. .num_pmcs = 4,
  2017. .oprofile_cpu_type = "ppc/e500",
  2018. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  2019. .cpu_setup = __setup_cpu_e500v1,
  2020. .machine_check = machine_check_e500,
  2021. .platform = "ppc8540",
  2022. },
  2023. { /* e500v2 */
  2024. .pvr_mask = 0xffff0000,
  2025. .pvr_value = 0x80210000,
  2026. .cpu_name = "e500v2",
  2027. .cpu_features = CPU_FTRS_E500_2,
  2028. .cpu_user_features = COMMON_USER_BOOKE |
  2029. PPC_FEATURE_HAS_SPE_COMP |
  2030. PPC_FEATURE_HAS_EFP_SINGLE_COMP |
  2031. PPC_FEATURE_HAS_EFP_DOUBLE_COMP,
  2032. .cpu_user_features2 = PPC_FEATURE2_ISEL,
  2033. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS,
  2034. .icache_bsize = 32,
  2035. .dcache_bsize = 32,
  2036. .num_pmcs = 4,
  2037. .oprofile_cpu_type = "ppc/e500",
  2038. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  2039. .cpu_setup = __setup_cpu_e500v2,
  2040. .machine_check = machine_check_e500,
  2041. .platform = "ppc8548",
  2042. .cpu_down_flush = cpu_down_flush_e500v2,
  2043. },
  2044. #else
  2045. { /* e500mc */
  2046. .pvr_mask = 0xffff0000,
  2047. .pvr_value = 0x80230000,
  2048. .cpu_name = "e500mc",
  2049. .cpu_features = CPU_FTRS_E500MC,
  2050. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  2051. .cpu_user_features2 = PPC_FEATURE2_ISEL,
  2052. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
  2053. MMU_FTR_USE_TLBILX,
  2054. .icache_bsize = 64,
  2055. .dcache_bsize = 64,
  2056. .num_pmcs = 4,
  2057. .oprofile_cpu_type = "ppc/e500mc",
  2058. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  2059. .cpu_setup = __setup_cpu_e500mc,
  2060. .machine_check = machine_check_e500mc,
  2061. .platform = "ppce500mc",
  2062. .cpu_down_flush = cpu_down_flush_e500mc,
  2063. },
  2064. #endif /* CONFIG_PPC_E500MC */
  2065. #endif /* CONFIG_PPC32 */
  2066. #ifdef CONFIG_PPC_E500MC
  2067. { /* e5500 */
  2068. .pvr_mask = 0xffff0000,
  2069. .pvr_value = 0x80240000,
  2070. .cpu_name = "e5500",
  2071. .cpu_features = CPU_FTRS_E5500,
  2072. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  2073. .cpu_user_features2 = PPC_FEATURE2_ISEL,
  2074. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
  2075. MMU_FTR_USE_TLBILX,
  2076. .icache_bsize = 64,
  2077. .dcache_bsize = 64,
  2078. .num_pmcs = 4,
  2079. .oprofile_cpu_type = "ppc/e500mc",
  2080. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  2081. .cpu_setup = __setup_cpu_e5500,
  2082. #ifndef CONFIG_PPC32
  2083. .cpu_restore = __restore_cpu_e5500,
  2084. #endif
  2085. .machine_check = machine_check_e500mc,
  2086. .platform = "ppce5500",
  2087. .cpu_down_flush = cpu_down_flush_e5500,
  2088. },
  2089. { /* e6500 */
  2090. .pvr_mask = 0xffff0000,
  2091. .pvr_value = 0x80400000,
  2092. .cpu_name = "e6500",
  2093. .cpu_features = CPU_FTRS_E6500,
  2094. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU |
  2095. PPC_FEATURE_HAS_ALTIVEC_COMP,
  2096. .cpu_user_features2 = PPC_FEATURE2_ISEL,
  2097. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
  2098. MMU_FTR_USE_TLBILX,
  2099. .icache_bsize = 64,
  2100. .dcache_bsize = 64,
  2101. .num_pmcs = 6,
  2102. .oprofile_cpu_type = "ppc/e6500",
  2103. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  2104. .cpu_setup = __setup_cpu_e6500,
  2105. #ifndef CONFIG_PPC32
  2106. .cpu_restore = __restore_cpu_e6500,
  2107. #endif
  2108. .machine_check = machine_check_e500mc,
  2109. .platform = "ppce6500",
  2110. .cpu_down_flush = cpu_down_flush_e6500,
  2111. },
  2112. #endif /* CONFIG_PPC_E500MC */
  2113. #ifdef CONFIG_PPC32
  2114. { /* default match */
  2115. .pvr_mask = 0x00000000,
  2116. .pvr_value = 0x00000000,
  2117. .cpu_name = "(generic E500 PPC)",
  2118. .cpu_features = CPU_FTRS_E500,
  2119. .cpu_user_features = COMMON_USER_BOOKE |
  2120. PPC_FEATURE_HAS_SPE_COMP |
  2121. PPC_FEATURE_HAS_EFP_SINGLE_COMP,
  2122. .mmu_features = MMU_FTR_TYPE_FSL_E,
  2123. .icache_bsize = 32,
  2124. .dcache_bsize = 32,
  2125. .machine_check = machine_check_e500,
  2126. .platform = "powerpc",
  2127. }
  2128. #endif /* CONFIG_PPC32 */
  2129. #endif /* CONFIG_E500 */
  2130. };
  2131. void __init set_cur_cpu_spec(struct cpu_spec *s)
  2132. {
  2133. struct cpu_spec *t = &the_cpu_spec;
  2134. t = PTRRELOC(t);
  2135. *t = *s;
  2136. *PTRRELOC(&cur_cpu_spec) = &the_cpu_spec;
  2137. }
  2138. static struct cpu_spec * __init setup_cpu_spec(unsigned long offset,
  2139. struct cpu_spec *s)
  2140. {
  2141. struct cpu_spec *t = &the_cpu_spec;
  2142. struct cpu_spec old;
  2143. t = PTRRELOC(t);
  2144. old = *t;
  2145. /* Copy everything, then do fixups */
  2146. *t = *s;
  2147. /*
  2148. * If we are overriding a previous value derived from the real
  2149. * PVR with a new value obtained using a logical PVR value,
  2150. * don't modify the performance monitor fields.
  2151. */
  2152. if (old.num_pmcs && !s->num_pmcs) {
  2153. t->num_pmcs = old.num_pmcs;
  2154. t->pmc_type = old.pmc_type;
  2155. t->oprofile_type = old.oprofile_type;
  2156. t->oprofile_mmcra_sihv = old.oprofile_mmcra_sihv;
  2157. t->oprofile_mmcra_sipr = old.oprofile_mmcra_sipr;
  2158. t->oprofile_mmcra_clear = old.oprofile_mmcra_clear;
  2159. /*
  2160. * If we have passed through this logic once before and
  2161. * have pulled the default case because the real PVR was
  2162. * not found inside cpu_specs[], then we are possibly
  2163. * running in compatibility mode. In that case, let the
  2164. * oprofiler know which set of compatibility counters to
  2165. * pull from by making sure the oprofile_cpu_type string
  2166. * is set to that of compatibility mode. If the
  2167. * oprofile_cpu_type already has a value, then we are
  2168. * possibly overriding a real PVR with a logical one,
  2169. * and, in that case, keep the current value for
  2170. * oprofile_cpu_type.
  2171. */
  2172. if (old.oprofile_cpu_type != NULL) {
  2173. t->oprofile_cpu_type = old.oprofile_cpu_type;
  2174. t->oprofile_type = old.oprofile_type;
  2175. }
  2176. }
  2177. *PTRRELOC(&cur_cpu_spec) = &the_cpu_spec;
  2178. /*
  2179. * Set the base platform string once; assumes
  2180. * we're called with real pvr first.
  2181. */
  2182. if (*PTRRELOC(&powerpc_base_platform) == NULL)
  2183. *PTRRELOC(&powerpc_base_platform) = t->platform;
  2184. #if defined(CONFIG_PPC64) || defined(CONFIG_BOOKE)
  2185. /* ppc64 and booke expect identify_cpu to also call setup_cpu for
  2186. * that processor. I will consolidate that at a later time, for now,
  2187. * just use #ifdef. We also don't need to PTRRELOC the function
  2188. * pointer on ppc64 and booke as we are running at 0 in real mode
  2189. * on ppc64 and reloc_offset is always 0 on booke.
  2190. */
  2191. if (t->cpu_setup) {
  2192. t->cpu_setup(offset, t);
  2193. }
  2194. #endif /* CONFIG_PPC64 || CONFIG_BOOKE */
  2195. return t;
  2196. }
  2197. struct cpu_spec * __init identify_cpu(unsigned long offset, unsigned int pvr)
  2198. {
  2199. struct cpu_spec *s = cpu_specs;
  2200. int i;
  2201. s = PTRRELOC(s);
  2202. for (i = 0; i < ARRAY_SIZE(cpu_specs); i++,s++) {
  2203. if ((pvr & s->pvr_mask) == s->pvr_value)
  2204. return setup_cpu_spec(offset, s);
  2205. }
  2206. BUG();
  2207. return NULL;
  2208. }
  2209. /*
  2210. * Used by cpufeatures to get the name for CPUs with a PVR table.
  2211. * If they don't hae a PVR table, cpufeatures gets the name from
  2212. * cpu device-tree node.
  2213. */
  2214. void __init identify_cpu_name(unsigned int pvr)
  2215. {
  2216. struct cpu_spec *s = cpu_specs;
  2217. struct cpu_spec *t = &the_cpu_spec;
  2218. int i;
  2219. s = PTRRELOC(s);
  2220. t = PTRRELOC(t);
  2221. for (i = 0; i < ARRAY_SIZE(cpu_specs); i++,s++) {
  2222. if ((pvr & s->pvr_mask) == s->pvr_value) {
  2223. t->cpu_name = s->cpu_name;
  2224. return;
  2225. }
  2226. }
  2227. }
  2228. #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
  2229. struct static_key_true cpu_feature_keys[NUM_CPU_FTR_KEYS] = {
  2230. [0 ... NUM_CPU_FTR_KEYS - 1] = STATIC_KEY_TRUE_INIT
  2231. };
  2232. EXPORT_SYMBOL_GPL(cpu_feature_keys);
  2233. void __init cpu_feature_keys_init(void)
  2234. {
  2235. int i;
  2236. for (i = 0; i < NUM_CPU_FTR_KEYS; i++) {
  2237. unsigned long f = 1ul << i;
  2238. if (!(cur_cpu_spec->cpu_features & f))
  2239. static_branch_disable(&cpu_feature_keys[i]);
  2240. }
  2241. }
  2242. struct static_key_true mmu_feature_keys[NUM_MMU_FTR_KEYS] = {
  2243. [0 ... NUM_MMU_FTR_KEYS - 1] = STATIC_KEY_TRUE_INIT
  2244. };
  2245. EXPORT_SYMBOL_GPL(mmu_feature_keys);
  2246. void __init mmu_feature_keys_init(void)
  2247. {
  2248. int i;
  2249. for (i = 0; i < NUM_MMU_FTR_KEYS; i++) {
  2250. unsigned long f = 1ul << i;
  2251. if (!(cur_cpu_spec->mmu_features & f))
  2252. static_branch_disable(&mmu_feature_keys[i]);
  2253. }
  2254. }
  2255. #endif