setup.c 22 KB

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  1. /*
  2. * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
  3. * and RBTX49xx patch from CELF patch archive.
  4. *
  5. * 2003-2005 (c) MontaVista Software, Inc.
  6. * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
  7. *
  8. * This file is subject to the terms and conditions of the GNU General Public
  9. * License. See the file "COPYING" in the main directory of this archive
  10. * for more details.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/kernel.h>
  14. #include <linux/types.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/string.h>
  17. #include <linux/export.h>
  18. #include <linux/clk-provider.h>
  19. #include <linux/clkdev.h>
  20. #include <linux/err.h>
  21. #include <linux/gpio/driver.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/platform_data/txx9/ndfmc.h>
  24. #include <linux/serial_core.h>
  25. #include <linux/mtd/physmap.h>
  26. #include <linux/leds.h>
  27. #include <linux/device.h>
  28. #include <linux/slab.h>
  29. #include <linux/irq.h>
  30. #include <asm/bootinfo.h>
  31. #include <asm/idle.h>
  32. #include <asm/time.h>
  33. #include <asm/reboot.h>
  34. #include <asm/r4kcache.h>
  35. #include <asm/sections.h>
  36. #include <asm/setup.h>
  37. #include <asm/txx9/generic.h>
  38. #include <asm/txx9/pci.h>
  39. #include <asm/txx9tmr.h>
  40. #include <asm/txx9/dmac.h>
  41. #ifdef CONFIG_CPU_TX49XX
  42. #include <asm/txx9/tx4938.h>
  43. #endif
  44. /* EBUSC settings of TX4927, etc. */
  45. struct resource txx9_ce_res[8];
  46. static char txx9_ce_res_name[8][4]; /* "CEn" */
  47. /* pcode, internal register */
  48. unsigned int txx9_pcode;
  49. char txx9_pcode_str[8];
  50. static struct resource txx9_reg_res = {
  51. .name = txx9_pcode_str,
  52. .flags = IORESOURCE_MEM,
  53. };
  54. void __init
  55. txx9_reg_res_init(unsigned int pcode, unsigned long base, unsigned long size)
  56. {
  57. int i;
  58. for (i = 0; i < ARRAY_SIZE(txx9_ce_res); i++) {
  59. sprintf(txx9_ce_res_name[i], "CE%d", i);
  60. txx9_ce_res[i].flags = IORESOURCE_MEM;
  61. txx9_ce_res[i].name = txx9_ce_res_name[i];
  62. }
  63. txx9_pcode = pcode;
  64. sprintf(txx9_pcode_str, "TX%x", pcode);
  65. if (base) {
  66. txx9_reg_res.start = base & 0xfffffffffULL;
  67. txx9_reg_res.end = (base & 0xfffffffffULL) + (size - 1);
  68. request_resource(&iomem_resource, &txx9_reg_res);
  69. }
  70. }
  71. /* clocks */
  72. unsigned int txx9_master_clock;
  73. unsigned int txx9_cpu_clock;
  74. unsigned int txx9_gbus_clock;
  75. #ifdef CONFIG_CPU_TX39XX
  76. /* don't enable by default - see errata */
  77. int txx9_ccfg_toeon __initdata;
  78. #else
  79. int txx9_ccfg_toeon __initdata = 1;
  80. #endif
  81. #define BOARD_VEC(board) extern struct txx9_board_vec board;
  82. #include <asm/txx9/boards.h>
  83. #undef BOARD_VEC
  84. struct txx9_board_vec *txx9_board_vec __initdata;
  85. static char txx9_system_type[32];
  86. static struct txx9_board_vec *board_vecs[] __initdata = {
  87. #define BOARD_VEC(board) &board,
  88. #include <asm/txx9/boards.h>
  89. #undef BOARD_VEC
  90. };
  91. static struct txx9_board_vec *__init find_board_byname(const char *name)
  92. {
  93. int i;
  94. /* search board_vecs table */
  95. for (i = 0; i < ARRAY_SIZE(board_vecs); i++) {
  96. if (strstr(board_vecs[i]->system, name))
  97. return board_vecs[i];
  98. }
  99. return NULL;
  100. }
  101. static void __init prom_init_cmdline(void)
  102. {
  103. int argc;
  104. int *argv32;
  105. int i; /* Always ignore the "-c" at argv[0] */
  106. if (fw_arg0 >= CKSEG0 || fw_arg1 < CKSEG0) {
  107. /*
  108. * argc is not a valid number, or argv32 is not a valid
  109. * pointer
  110. */
  111. argc = 0;
  112. argv32 = NULL;
  113. } else {
  114. argc = (int)fw_arg0;
  115. argv32 = (int *)fw_arg1;
  116. }
  117. arcs_cmdline[0] = '\0';
  118. for (i = 1; i < argc; i++) {
  119. char *str = (char *)(long)argv32[i];
  120. if (i != 1)
  121. strcat(arcs_cmdline, " ");
  122. if (strchr(str, ' ')) {
  123. strcat(arcs_cmdline, "\"");
  124. strcat(arcs_cmdline, str);
  125. strcat(arcs_cmdline, "\"");
  126. } else
  127. strcat(arcs_cmdline, str);
  128. }
  129. }
  130. static int txx9_ic_disable __initdata;
  131. static int txx9_dc_disable __initdata;
  132. #if defined(CONFIG_CPU_TX49XX)
  133. /* flush all cache on very early stage (before 4k_cache_init) */
  134. static void __init early_flush_dcache(void)
  135. {
  136. unsigned int conf = read_c0_config();
  137. unsigned int dc_size = 1 << (12 + ((conf & CONF_DC) >> 6));
  138. unsigned int linesz = 32;
  139. unsigned long addr, end;
  140. end = INDEX_BASE + dc_size / 4;
  141. /* 4way, waybit=0 */
  142. for (addr = INDEX_BASE; addr < end; addr += linesz) {
  143. cache_op(Index_Writeback_Inv_D, addr | 0);
  144. cache_op(Index_Writeback_Inv_D, addr | 1);
  145. cache_op(Index_Writeback_Inv_D, addr | 2);
  146. cache_op(Index_Writeback_Inv_D, addr | 3);
  147. }
  148. }
  149. static void __init txx9_cache_fixup(void)
  150. {
  151. unsigned int conf;
  152. conf = read_c0_config();
  153. /* flush and disable */
  154. if (txx9_ic_disable) {
  155. conf |= TX49_CONF_IC;
  156. write_c0_config(conf);
  157. }
  158. if (txx9_dc_disable) {
  159. early_flush_dcache();
  160. conf |= TX49_CONF_DC;
  161. write_c0_config(conf);
  162. }
  163. /* enable cache */
  164. conf = read_c0_config();
  165. if (!txx9_ic_disable)
  166. conf &= ~TX49_CONF_IC;
  167. if (!txx9_dc_disable)
  168. conf &= ~TX49_CONF_DC;
  169. write_c0_config(conf);
  170. if (conf & TX49_CONF_IC)
  171. pr_info("TX49XX I-Cache disabled.\n");
  172. if (conf & TX49_CONF_DC)
  173. pr_info("TX49XX D-Cache disabled.\n");
  174. }
  175. #elif defined(CONFIG_CPU_TX39XX)
  176. /* flush all cache on very early stage (before tx39_cache_init) */
  177. static void __init early_flush_dcache(void)
  178. {
  179. unsigned int conf = read_c0_config();
  180. unsigned int dc_size = 1 << (10 + ((conf & TX39_CONF_DCS_MASK) >>
  181. TX39_CONF_DCS_SHIFT));
  182. unsigned int linesz = 16;
  183. unsigned long addr, end;
  184. end = INDEX_BASE + dc_size / 2;
  185. /* 2way, waybit=0 */
  186. for (addr = INDEX_BASE; addr < end; addr += linesz) {
  187. cache_op(Index_Writeback_Inv_D, addr | 0);
  188. cache_op(Index_Writeback_Inv_D, addr | 1);
  189. }
  190. }
  191. static void __init txx9_cache_fixup(void)
  192. {
  193. unsigned int conf;
  194. conf = read_c0_config();
  195. /* flush and disable */
  196. if (txx9_ic_disable) {
  197. conf &= ~TX39_CONF_ICE;
  198. write_c0_config(conf);
  199. }
  200. if (txx9_dc_disable) {
  201. early_flush_dcache();
  202. conf &= ~TX39_CONF_DCE;
  203. write_c0_config(conf);
  204. }
  205. /* enable cache */
  206. conf = read_c0_config();
  207. if (!txx9_ic_disable)
  208. conf |= TX39_CONF_ICE;
  209. if (!txx9_dc_disable)
  210. conf |= TX39_CONF_DCE;
  211. write_c0_config(conf);
  212. if (!(conf & TX39_CONF_ICE))
  213. pr_info("TX39XX I-Cache disabled.\n");
  214. if (!(conf & TX39_CONF_DCE))
  215. pr_info("TX39XX D-Cache disabled.\n");
  216. }
  217. #else
  218. static inline void txx9_cache_fixup(void)
  219. {
  220. }
  221. #endif
  222. static void __init preprocess_cmdline(void)
  223. {
  224. static char cmdline[COMMAND_LINE_SIZE] __initdata;
  225. char *s;
  226. strcpy(cmdline, arcs_cmdline);
  227. s = cmdline;
  228. arcs_cmdline[0] = '\0';
  229. while (s && *s) {
  230. char *str = strsep(&s, " ");
  231. if (strncmp(str, "board=", 6) == 0) {
  232. txx9_board_vec = find_board_byname(str + 6);
  233. continue;
  234. } else if (strncmp(str, "masterclk=", 10) == 0) {
  235. unsigned int val;
  236. if (kstrtouint(str + 10, 10, &val) == 0)
  237. txx9_master_clock = val;
  238. continue;
  239. } else if (strcmp(str, "icdisable") == 0) {
  240. txx9_ic_disable = 1;
  241. continue;
  242. } else if (strcmp(str, "dcdisable") == 0) {
  243. txx9_dc_disable = 1;
  244. continue;
  245. } else if (strcmp(str, "toeoff") == 0) {
  246. txx9_ccfg_toeon = 0;
  247. continue;
  248. } else if (strcmp(str, "toeon") == 0) {
  249. txx9_ccfg_toeon = 1;
  250. continue;
  251. }
  252. if (arcs_cmdline[0])
  253. strcat(arcs_cmdline, " ");
  254. strcat(arcs_cmdline, str);
  255. }
  256. txx9_cache_fixup();
  257. }
  258. static void __init select_board(void)
  259. {
  260. const char *envstr;
  261. /* first, determine by "board=" argument in preprocess_cmdline() */
  262. if (txx9_board_vec)
  263. return;
  264. /* next, determine by "board" envvar */
  265. envstr = prom_getenv("board");
  266. if (envstr) {
  267. txx9_board_vec = find_board_byname(envstr);
  268. if (txx9_board_vec)
  269. return;
  270. }
  271. /* select "default" board */
  272. #ifdef CONFIG_TOSHIBA_JMR3927
  273. txx9_board_vec = &jmr3927_vec;
  274. #endif
  275. #ifdef CONFIG_CPU_TX49XX
  276. switch (TX4938_REV_PCODE()) {
  277. #ifdef CONFIG_TOSHIBA_RBTX4927
  278. case 0x4927:
  279. txx9_board_vec = &rbtx4927_vec;
  280. break;
  281. case 0x4937:
  282. txx9_board_vec = &rbtx4937_vec;
  283. break;
  284. #endif
  285. #ifdef CONFIG_TOSHIBA_RBTX4938
  286. case 0x4938:
  287. txx9_board_vec = &rbtx4938_vec;
  288. break;
  289. #endif
  290. #ifdef CONFIG_TOSHIBA_RBTX4939
  291. case 0x4939:
  292. txx9_board_vec = &rbtx4939_vec;
  293. break;
  294. #endif
  295. }
  296. #endif
  297. }
  298. void __init prom_init(void)
  299. {
  300. prom_init_cmdline();
  301. preprocess_cmdline();
  302. select_board();
  303. strcpy(txx9_system_type, txx9_board_vec->system);
  304. txx9_board_vec->prom_init();
  305. }
  306. void __init prom_free_prom_memory(void)
  307. {
  308. unsigned long saddr = PAGE_SIZE;
  309. unsigned long eaddr = __pa_symbol(&_text);
  310. if (saddr < eaddr)
  311. free_init_pages("prom memory", saddr, eaddr);
  312. }
  313. const char *get_system_type(void)
  314. {
  315. return txx9_system_type;
  316. }
  317. const char *__init prom_getenv(const char *name)
  318. {
  319. const s32 *str;
  320. if (fw_arg2 < CKSEG0)
  321. return NULL;
  322. str = (const s32 *)fw_arg2;
  323. /* YAMON style ("name", "value" pairs) */
  324. while (str[0] && str[1]) {
  325. if (!strcmp((const char *)(unsigned long)str[0], name))
  326. return (const char *)(unsigned long)str[1];
  327. str += 2;
  328. }
  329. return NULL;
  330. }
  331. static void __noreturn txx9_machine_halt(void)
  332. {
  333. local_irq_disable();
  334. clear_c0_status(ST0_IM);
  335. while (1) {
  336. if (cpu_wait) {
  337. (*cpu_wait)();
  338. if (cpu_has_counter) {
  339. /*
  340. * Clear counter interrupt while it
  341. * breaks WAIT instruction even if
  342. * masked.
  343. */
  344. write_c0_compare(0);
  345. }
  346. }
  347. }
  348. }
  349. /* Watchdog support */
  350. void __init txx9_wdt_init(unsigned long base)
  351. {
  352. struct resource res = {
  353. .start = base,
  354. .end = base + 0x100 - 1,
  355. .flags = IORESOURCE_MEM,
  356. };
  357. platform_device_register_simple("txx9wdt", -1, &res, 1);
  358. }
  359. void txx9_wdt_now(unsigned long base)
  360. {
  361. struct txx9_tmr_reg __iomem *tmrptr =
  362. ioremap(base, sizeof(struct txx9_tmr_reg));
  363. /* disable watch dog timer */
  364. __raw_writel(TXx9_TMWTMR_WDIS | TXx9_TMWTMR_TWC, &tmrptr->wtmr);
  365. __raw_writel(0, &tmrptr->tcr);
  366. /* kick watchdog */
  367. __raw_writel(TXx9_TMWTMR_TWIE, &tmrptr->wtmr);
  368. __raw_writel(1, &tmrptr->cpra); /* immediate */
  369. __raw_writel(TXx9_TMTCR_TCE | TXx9_TMTCR_CCDE | TXx9_TMTCR_TMODE_WDOG,
  370. &tmrptr->tcr);
  371. }
  372. /* SPI support */
  373. void __init txx9_spi_init(int busid, unsigned long base, int irq)
  374. {
  375. struct resource res[] = {
  376. {
  377. .start = base,
  378. .end = base + 0x20 - 1,
  379. .flags = IORESOURCE_MEM,
  380. }, {
  381. .start = irq,
  382. .flags = IORESOURCE_IRQ,
  383. },
  384. };
  385. platform_device_register_simple("spi_txx9", busid,
  386. res, ARRAY_SIZE(res));
  387. }
  388. void __init txx9_ethaddr_init(unsigned int id, unsigned char *ethaddr)
  389. {
  390. struct platform_device *pdev =
  391. platform_device_alloc("tc35815-mac", id);
  392. if (!pdev ||
  393. platform_device_add_data(pdev, ethaddr, 6) ||
  394. platform_device_add(pdev))
  395. platform_device_put(pdev);
  396. }
  397. void __init txx9_sio_init(unsigned long baseaddr, int irq,
  398. unsigned int line, unsigned int sclk, int nocts)
  399. {
  400. #ifdef CONFIG_SERIAL_TXX9
  401. struct uart_port req;
  402. memset(&req, 0, sizeof(req));
  403. req.line = line;
  404. req.iotype = UPIO_MEM;
  405. req.membase = ioremap(baseaddr, 0x24);
  406. req.mapbase = baseaddr;
  407. req.irq = irq;
  408. if (!nocts)
  409. req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
  410. if (sclk) {
  411. req.flags |= UPF_MAGIC_MULTIPLIER /*USE_SCLK*/;
  412. req.uartclk = sclk;
  413. } else
  414. req.uartclk = TXX9_IMCLK;
  415. early_serial_txx9_setup(&req);
  416. #endif /* CONFIG_SERIAL_TXX9 */
  417. }
  418. #ifdef CONFIG_EARLY_PRINTK
  419. static void null_prom_putchar(char c)
  420. {
  421. }
  422. void (*txx9_prom_putchar)(char c) = null_prom_putchar;
  423. void prom_putchar(char c)
  424. {
  425. txx9_prom_putchar(c);
  426. }
  427. static void __iomem *early_txx9_sio_port;
  428. static void early_txx9_sio_putchar(char c)
  429. {
  430. #define TXX9_SICISR 0x0c
  431. #define TXX9_SITFIFO 0x1c
  432. #define TXX9_SICISR_TXALS 0x00000002
  433. while (!(__raw_readl(early_txx9_sio_port + TXX9_SICISR) &
  434. TXX9_SICISR_TXALS))
  435. ;
  436. __raw_writel(c, early_txx9_sio_port + TXX9_SITFIFO);
  437. }
  438. void __init txx9_sio_putchar_init(unsigned long baseaddr)
  439. {
  440. early_txx9_sio_port = ioremap(baseaddr, 0x24);
  441. txx9_prom_putchar = early_txx9_sio_putchar;
  442. }
  443. #endif /* CONFIG_EARLY_PRINTK */
  444. /* wrappers */
  445. void __init plat_mem_setup(void)
  446. {
  447. ioport_resource.start = 0;
  448. ioport_resource.end = ~0UL; /* no limit */
  449. iomem_resource.start = 0;
  450. iomem_resource.end = ~0UL; /* no limit */
  451. /* fallback restart/halt routines */
  452. _machine_restart = (void (*)(char *))txx9_machine_halt;
  453. _machine_halt = txx9_machine_halt;
  454. pm_power_off = txx9_machine_halt;
  455. #ifdef CONFIG_PCI
  456. pcibios_plat_setup = txx9_pcibios_setup;
  457. #endif
  458. txx9_board_vec->mem_setup();
  459. }
  460. void __init arch_init_irq(void)
  461. {
  462. txx9_board_vec->irq_setup();
  463. }
  464. void __init plat_time_init(void)
  465. {
  466. #ifdef CONFIG_CPU_TX49XX
  467. mips_hpt_frequency = txx9_cpu_clock / 2;
  468. #endif
  469. txx9_board_vec->time_init();
  470. }
  471. static void txx9_clk_init(void)
  472. {
  473. struct clk_hw *hw;
  474. int error;
  475. hw = clk_hw_register_fixed_rate(NULL, "gbus", NULL, 0, txx9_gbus_clock);
  476. if (IS_ERR(hw)) {
  477. error = PTR_ERR(hw);
  478. goto fail;
  479. }
  480. hw = clk_hw_register_fixed_factor(NULL, "imbus", "gbus", 0, 1, 2);
  481. error = clk_hw_register_clkdev(hw, "imbus_clk", NULL);
  482. if (error)
  483. goto fail;
  484. #ifdef CONFIG_CPU_TX49XX
  485. if (TX4938_REV_PCODE() == 0x4938) {
  486. hw = clk_hw_register_fixed_factor(NULL, "spi", "gbus", 0, 1, 4);
  487. error = clk_hw_register_clkdev(hw, "spi-baseclk", NULL);
  488. if (error)
  489. goto fail;
  490. }
  491. #endif
  492. return;
  493. fail:
  494. pr_err("Failed to register clocks: %d\n", error);
  495. }
  496. static int __init _txx9_arch_init(void)
  497. {
  498. txx9_clk_init();
  499. if (txx9_board_vec->arch_init)
  500. txx9_board_vec->arch_init();
  501. return 0;
  502. }
  503. arch_initcall(_txx9_arch_init);
  504. static int __init _txx9_device_init(void)
  505. {
  506. if (txx9_board_vec->device_init)
  507. txx9_board_vec->device_init();
  508. return 0;
  509. }
  510. device_initcall(_txx9_device_init);
  511. int (*txx9_irq_dispatch)(int pending);
  512. asmlinkage void plat_irq_dispatch(void)
  513. {
  514. int pending = read_c0_status() & read_c0_cause() & ST0_IM;
  515. int irq = txx9_irq_dispatch(pending);
  516. if (likely(irq >= 0))
  517. do_IRQ(irq);
  518. else
  519. spurious_interrupt();
  520. }
  521. /* see include/asm-mips/mach-tx39xx/mangle-port.h, for example. */
  522. #ifdef NEEDS_TXX9_SWIZZLE_ADDR_B
  523. static unsigned long __swizzle_addr_none(unsigned long port)
  524. {
  525. return port;
  526. }
  527. unsigned long (*__swizzle_addr_b)(unsigned long port) = __swizzle_addr_none;
  528. EXPORT_SYMBOL(__swizzle_addr_b);
  529. #endif
  530. #ifdef NEEDS_TXX9_IOSWABW
  531. static u16 ioswabw_default(volatile u16 *a, u16 x)
  532. {
  533. return le16_to_cpu(x);
  534. }
  535. static u16 __mem_ioswabw_default(volatile u16 *a, u16 x)
  536. {
  537. return x;
  538. }
  539. u16 (*ioswabw)(volatile u16 *a, u16 x) = ioswabw_default;
  540. EXPORT_SYMBOL(ioswabw);
  541. u16 (*__mem_ioswabw)(volatile u16 *a, u16 x) = __mem_ioswabw_default;
  542. EXPORT_SYMBOL(__mem_ioswabw);
  543. #endif
  544. void __init txx9_physmap_flash_init(int no, unsigned long addr,
  545. unsigned long size,
  546. const struct physmap_flash_data *pdata)
  547. {
  548. #if IS_ENABLED(CONFIG_MTD_PHYSMAP)
  549. struct resource res = {
  550. .start = addr,
  551. .end = addr + size - 1,
  552. .flags = IORESOURCE_MEM,
  553. };
  554. struct platform_device *pdev;
  555. static struct mtd_partition parts[2];
  556. struct physmap_flash_data pdata_part;
  557. /* If this area contained boot area, make separate partition */
  558. if (pdata->nr_parts == 0 && !pdata->parts &&
  559. addr < 0x1fc00000 && addr + size > 0x1fc00000 &&
  560. !parts[0].name) {
  561. parts[0].name = "boot";
  562. parts[0].offset = 0x1fc00000 - addr;
  563. parts[0].size = addr + size - 0x1fc00000;
  564. parts[1].name = "user";
  565. parts[1].offset = 0;
  566. parts[1].size = 0x1fc00000 - addr;
  567. pdata_part = *pdata;
  568. pdata_part.nr_parts = ARRAY_SIZE(parts);
  569. pdata_part.parts = parts;
  570. pdata = &pdata_part;
  571. }
  572. pdev = platform_device_alloc("physmap-flash", no);
  573. if (!pdev ||
  574. platform_device_add_resources(pdev, &res, 1) ||
  575. platform_device_add_data(pdev, pdata, sizeof(*pdata)) ||
  576. platform_device_add(pdev))
  577. platform_device_put(pdev);
  578. #endif
  579. }
  580. void __init txx9_ndfmc_init(unsigned long baseaddr,
  581. const struct txx9ndfmc_platform_data *pdata)
  582. {
  583. #if IS_ENABLED(CONFIG_MTD_NAND_TXX9NDFMC)
  584. struct resource res = {
  585. .start = baseaddr,
  586. .end = baseaddr + 0x1000 - 1,
  587. .flags = IORESOURCE_MEM,
  588. };
  589. struct platform_device *pdev = platform_device_alloc("txx9ndfmc", -1);
  590. if (!pdev ||
  591. platform_device_add_resources(pdev, &res, 1) ||
  592. platform_device_add_data(pdev, pdata, sizeof(*pdata)) ||
  593. platform_device_add(pdev))
  594. platform_device_put(pdev);
  595. #endif
  596. }
  597. #if IS_ENABLED(CONFIG_LEDS_GPIO)
  598. static DEFINE_SPINLOCK(txx9_iocled_lock);
  599. #define TXX9_IOCLED_MAXLEDS 8
  600. struct txx9_iocled_data {
  601. struct gpio_chip chip;
  602. u8 cur_val;
  603. void __iomem *mmioaddr;
  604. struct gpio_led_platform_data pdata;
  605. struct gpio_led leds[TXX9_IOCLED_MAXLEDS];
  606. char names[TXX9_IOCLED_MAXLEDS][32];
  607. };
  608. static int txx9_iocled_get(struct gpio_chip *chip, unsigned int offset)
  609. {
  610. struct txx9_iocled_data *data = gpiochip_get_data(chip);
  611. return !!(data->cur_val & (1 << offset));
  612. }
  613. static void txx9_iocled_set(struct gpio_chip *chip, unsigned int offset,
  614. int value)
  615. {
  616. struct txx9_iocled_data *data = gpiochip_get_data(chip);
  617. unsigned long flags;
  618. spin_lock_irqsave(&txx9_iocled_lock, flags);
  619. if (value)
  620. data->cur_val |= 1 << offset;
  621. else
  622. data->cur_val &= ~(1 << offset);
  623. writeb(data->cur_val, data->mmioaddr);
  624. mmiowb();
  625. spin_unlock_irqrestore(&txx9_iocled_lock, flags);
  626. }
  627. static int txx9_iocled_dir_in(struct gpio_chip *chip, unsigned int offset)
  628. {
  629. return 0;
  630. }
  631. static int txx9_iocled_dir_out(struct gpio_chip *chip, unsigned int offset,
  632. int value)
  633. {
  634. txx9_iocled_set(chip, offset, value);
  635. return 0;
  636. }
  637. void __init txx9_iocled_init(unsigned long baseaddr,
  638. int basenum, unsigned int num, int lowactive,
  639. const char *color, char **deftriggers)
  640. {
  641. struct txx9_iocled_data *iocled;
  642. struct platform_device *pdev;
  643. int i;
  644. static char *default_triggers[] __initdata = {
  645. "heartbeat",
  646. "disk-activity",
  647. "nand-disk",
  648. NULL,
  649. };
  650. if (!deftriggers)
  651. deftriggers = default_triggers;
  652. iocled = kzalloc(sizeof(*iocled), GFP_KERNEL);
  653. if (!iocled)
  654. return;
  655. iocled->mmioaddr = ioremap(baseaddr, 1);
  656. if (!iocled->mmioaddr)
  657. goto out_free;
  658. iocled->chip.get = txx9_iocled_get;
  659. iocled->chip.set = txx9_iocled_set;
  660. iocled->chip.direction_input = txx9_iocled_dir_in;
  661. iocled->chip.direction_output = txx9_iocled_dir_out;
  662. iocled->chip.label = "iocled";
  663. iocled->chip.base = basenum;
  664. iocled->chip.ngpio = num;
  665. if (gpiochip_add_data(&iocled->chip, iocled))
  666. goto out_unmap;
  667. if (basenum < 0)
  668. basenum = iocled->chip.base;
  669. pdev = platform_device_alloc("leds-gpio", basenum);
  670. if (!pdev)
  671. goto out_gpio;
  672. iocled->pdata.num_leds = num;
  673. iocled->pdata.leds = iocled->leds;
  674. for (i = 0; i < num; i++) {
  675. struct gpio_led *led = &iocled->leds[i];
  676. snprintf(iocled->names[i], sizeof(iocled->names[i]),
  677. "iocled:%s:%u", color, i);
  678. led->name = iocled->names[i];
  679. led->gpio = basenum + i;
  680. led->active_low = lowactive;
  681. if (deftriggers && *deftriggers)
  682. led->default_trigger = *deftriggers++;
  683. }
  684. pdev->dev.platform_data = &iocled->pdata;
  685. if (platform_device_add(pdev))
  686. goto out_pdev;
  687. return;
  688. out_pdev:
  689. platform_device_put(pdev);
  690. out_gpio:
  691. gpiochip_remove(&iocled->chip);
  692. out_unmap:
  693. iounmap(iocled->mmioaddr);
  694. out_free:
  695. kfree(iocled);
  696. }
  697. #else /* CONFIG_LEDS_GPIO */
  698. void __init txx9_iocled_init(unsigned long baseaddr,
  699. int basenum, unsigned int num, int lowactive,
  700. const char *color, char **deftriggers)
  701. {
  702. }
  703. #endif /* CONFIG_LEDS_GPIO */
  704. void __init txx9_dmac_init(int id, unsigned long baseaddr, int irq,
  705. const struct txx9dmac_platform_data *pdata)
  706. {
  707. #if IS_ENABLED(CONFIG_TXX9_DMAC)
  708. struct resource res[] = {
  709. {
  710. .start = baseaddr,
  711. .end = baseaddr + 0x800 - 1,
  712. .flags = IORESOURCE_MEM,
  713. #ifndef CONFIG_MACH_TX49XX
  714. }, {
  715. .start = irq,
  716. .flags = IORESOURCE_IRQ,
  717. #endif
  718. }
  719. };
  720. #ifdef CONFIG_MACH_TX49XX
  721. struct resource chan_res[] = {
  722. {
  723. .flags = IORESOURCE_IRQ,
  724. }
  725. };
  726. #endif
  727. struct platform_device *pdev = platform_device_alloc("txx9dmac", id);
  728. struct txx9dmac_chan_platform_data cpdata;
  729. int i;
  730. if (!pdev ||
  731. platform_device_add_resources(pdev, res, ARRAY_SIZE(res)) ||
  732. platform_device_add_data(pdev, pdata, sizeof(*pdata)) ||
  733. platform_device_add(pdev)) {
  734. platform_device_put(pdev);
  735. return;
  736. }
  737. memset(&cpdata, 0, sizeof(cpdata));
  738. cpdata.dmac_dev = pdev;
  739. for (i = 0; i < TXX9_DMA_MAX_NR_CHANNELS; i++) {
  740. #ifdef CONFIG_MACH_TX49XX
  741. chan_res[0].start = irq + i;
  742. #endif
  743. pdev = platform_device_alloc("txx9dmac-chan",
  744. id * TXX9_DMA_MAX_NR_CHANNELS + i);
  745. if (!pdev ||
  746. #ifdef CONFIG_MACH_TX49XX
  747. platform_device_add_resources(pdev, chan_res,
  748. ARRAY_SIZE(chan_res)) ||
  749. #endif
  750. platform_device_add_data(pdev, &cpdata, sizeof(cpdata)) ||
  751. platform_device_add(pdev))
  752. platform_device_put(pdev);
  753. }
  754. #endif
  755. }
  756. void __init txx9_aclc_init(unsigned long baseaddr, int irq,
  757. unsigned int dmac_id,
  758. unsigned int dma_chan_out,
  759. unsigned int dma_chan_in)
  760. {
  761. #if IS_ENABLED(CONFIG_SND_SOC_TXX9ACLC)
  762. unsigned int dma_base = dmac_id * TXX9_DMA_MAX_NR_CHANNELS;
  763. struct resource res[] = {
  764. {
  765. .start = baseaddr,
  766. .end = baseaddr + 0x100 - 1,
  767. .flags = IORESOURCE_MEM,
  768. }, {
  769. .start = irq,
  770. .flags = IORESOURCE_IRQ,
  771. }, {
  772. .name = "txx9dmac-chan",
  773. .start = dma_base + dma_chan_out,
  774. .flags = IORESOURCE_DMA,
  775. }, {
  776. .name = "txx9dmac-chan",
  777. .start = dma_base + dma_chan_in,
  778. .flags = IORESOURCE_DMA,
  779. }
  780. };
  781. struct platform_device *pdev =
  782. platform_device_alloc("txx9aclc-ac97", -1);
  783. if (!pdev ||
  784. platform_device_add_resources(pdev, res, ARRAY_SIZE(res)) ||
  785. platform_device_add(pdev))
  786. platform_device_put(pdev);
  787. #endif
  788. }
  789. static struct bus_type txx9_sramc_subsys = {
  790. .name = "txx9_sram",
  791. .dev_name = "txx9_sram",
  792. };
  793. struct txx9_sramc_dev {
  794. struct device dev;
  795. struct bin_attribute bindata_attr;
  796. void __iomem *base;
  797. };
  798. static ssize_t txx9_sram_read(struct file *filp, struct kobject *kobj,
  799. struct bin_attribute *bin_attr,
  800. char *buf, loff_t pos, size_t size)
  801. {
  802. struct txx9_sramc_dev *dev = bin_attr->private;
  803. size_t ramsize = bin_attr->size;
  804. if (pos >= ramsize)
  805. return 0;
  806. if (pos + size > ramsize)
  807. size = ramsize - pos;
  808. memcpy_fromio(buf, dev->base + pos, size);
  809. return size;
  810. }
  811. static ssize_t txx9_sram_write(struct file *filp, struct kobject *kobj,
  812. struct bin_attribute *bin_attr,
  813. char *buf, loff_t pos, size_t size)
  814. {
  815. struct txx9_sramc_dev *dev = bin_attr->private;
  816. size_t ramsize = bin_attr->size;
  817. if (pos >= ramsize)
  818. return 0;
  819. if (pos + size > ramsize)
  820. size = ramsize - pos;
  821. memcpy_toio(dev->base + pos, buf, size);
  822. return size;
  823. }
  824. static void txx9_device_release(struct device *dev)
  825. {
  826. struct txx9_sramc_dev *tdev;
  827. tdev = container_of(dev, struct txx9_sramc_dev, dev);
  828. kfree(tdev);
  829. }
  830. void __init txx9_sramc_init(struct resource *r)
  831. {
  832. struct txx9_sramc_dev *dev;
  833. size_t size;
  834. int err;
  835. err = subsys_system_register(&txx9_sramc_subsys, NULL);
  836. if (err)
  837. return;
  838. dev = kzalloc(sizeof(*dev), GFP_KERNEL);
  839. if (!dev)
  840. return;
  841. size = resource_size(r);
  842. dev->base = ioremap(r->start, size);
  843. if (!dev->base) {
  844. kfree(dev);
  845. return;
  846. }
  847. dev->dev.release = &txx9_device_release;
  848. dev->dev.bus = &txx9_sramc_subsys;
  849. sysfs_bin_attr_init(&dev->bindata_attr);
  850. dev->bindata_attr.attr.name = "bindata";
  851. dev->bindata_attr.attr.mode = S_IRUSR | S_IWUSR;
  852. dev->bindata_attr.read = txx9_sram_read;
  853. dev->bindata_attr.write = txx9_sram_write;
  854. dev->bindata_attr.size = size;
  855. dev->bindata_attr.private = dev;
  856. err = device_register(&dev->dev);
  857. if (err)
  858. goto exit_put;
  859. err = sysfs_create_bin_file(&dev->dev.kobj, &dev->bindata_attr);
  860. if (err) {
  861. iounmap(dev->base);
  862. device_unregister(&dev->dev);
  863. }
  864. return;
  865. exit_put:
  866. iounmap(dev->base);
  867. put_device(&dev->dev);
  868. }