fixup.c 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
  4. * Derived from fixup.c of i386 tree.
  5. */
  6. #include <linux/pci.h>
  7. #include <linux/init.h>
  8. #include <linux/vgaarb.h>
  9. #include <linux/screen_info.h>
  10. #include <asm/machvec.h>
  11. /*
  12. * Fixup to mark boot BIOS video selected by BIOS before it changes
  13. *
  14. * From information provided by "Jon Smirl" <jonsmirl@gmail.com>
  15. *
  16. * The standard boot ROM sequence for an x86 machine uses the BIOS
  17. * to select an initial video card for boot display. This boot video
  18. * card will have its BIOS copied to 0xC0000 in system RAM.
  19. * IORESOURCE_ROM_SHADOW is used to associate the boot video
  20. * card with this copy. On laptops this copy has to be used since
  21. * the main ROM may be compressed or combined with another image.
  22. * See pci_map_rom() for use of this flag. Before marking the device
  23. * with IORESOURCE_ROM_SHADOW check if a vga_default_device is already set
  24. * by either arch code or vga-arbitration; if so only apply the fixup to this
  25. * already-determined primary video card.
  26. */
  27. static void pci_fixup_video(struct pci_dev *pdev)
  28. {
  29. struct pci_dev *bridge;
  30. struct pci_bus *bus;
  31. u16 config;
  32. struct resource *res;
  33. if ((strcmp(ia64_platform_name, "dig") != 0)
  34. && (strcmp(ia64_platform_name, "hpzx1") != 0))
  35. return;
  36. /* Maybe, this machine supports legacy memory map. */
  37. /* Is VGA routed to us? */
  38. bus = pdev->bus;
  39. while (bus) {
  40. bridge = bus->self;
  41. /*
  42. * From information provided by
  43. * "David Miller" <davem@davemloft.net>
  44. * The bridge control register is valid for PCI header
  45. * type BRIDGE, or CARDBUS. Host to PCI controllers use
  46. * PCI header type NORMAL.
  47. */
  48. if (bridge && (pci_is_bridge(bridge))) {
  49. pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
  50. &config);
  51. if (!(config & PCI_BRIDGE_CTL_VGA))
  52. return;
  53. }
  54. bus = bus->parent;
  55. }
  56. if (!vga_default_device() || pdev == vga_default_device()) {
  57. pci_read_config_word(pdev, PCI_COMMAND, &config);
  58. if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
  59. res = &pdev->resource[PCI_ROM_RESOURCE];
  60. pci_disable_rom(pdev);
  61. if (res->parent)
  62. release_resource(res);
  63. res->start = 0xC0000;
  64. res->end = res->start + 0x20000 - 1;
  65. res->flags = IORESOURCE_MEM | IORESOURCE_ROM_SHADOW |
  66. IORESOURCE_PCI_FIXED;
  67. dev_info(&pdev->dev, "Video device with shadowed ROM at %pR\n",
  68. res);
  69. }
  70. }
  71. }
  72. DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
  73. PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_video);