edosk2674.dts 2.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /dts-v1/;
  3. / {
  4. compatible = "renesas,edosk2674";
  5. #address-cells = <1>;
  6. #size-cells = <1>;
  7. interrupt-parent = <&h8intc>;
  8. chosen {
  9. bootargs = "console=ttySC2,38400";
  10. stdout-path = &sci2;
  11. };
  12. aliases {
  13. serial0 = &sci0;
  14. serial1 = &sci1;
  15. serial2 = &sci2;
  16. };
  17. xclk: oscillator {
  18. #clock-cells = <0>;
  19. compatible = "fixed-clock";
  20. clock-frequency = <33333333>;
  21. clock-output-names = "xtal";
  22. };
  23. pllclk: pllclk {
  24. compatible = "renesas,h8s2678-pll-clock";
  25. clocks = <&xclk>;
  26. #clock-cells = <0>;
  27. reg = <0xffff3b 1>, <0xffff45 1>;
  28. };
  29. core_clk: core_clk {
  30. compatible = "renesas,h8300-div-clock";
  31. clocks = <&pllclk>;
  32. #clock-cells = <0>;
  33. reg = <0xffff3b 1>;
  34. renesas,width = <3>;
  35. };
  36. fclk: fclk {
  37. compatible = "fixed-factor-clock";
  38. clocks = <&core_clk>;
  39. #clock-cells = <0>;
  40. clock-div = <1>;
  41. clock-mult = <1>;
  42. };
  43. memory@400000 {
  44. device_type = "memory";
  45. reg = <0x400000 0x800000>;
  46. };
  47. cpus {
  48. #address-cells = <1>;
  49. #size-cells = <0>;
  50. cpu@0 {
  51. compatible = "renesas,h8300";
  52. clock-frequency = <33333333>;
  53. };
  54. };
  55. h8intc: interrupt-controller@fffe00 {
  56. compatible = "renesas,h8s-intc", "renesas,h8300-intc";
  57. #interrupt-cells = <2>;
  58. interrupt-controller;
  59. reg = <0xfffe00 24>;
  60. };
  61. bsc: memory-controller@fffec0 {
  62. compatible = "renesas,h8s-bsc", "renesas,h8300-bsc";
  63. reg = <0xfffec0 24>;
  64. };
  65. tpu: timer@ffffe0 {
  66. compatible = "renesas,tpu";
  67. reg = <0xffffe0 16>, <0xfffff0 12>;
  68. clocks = <&fclk>;
  69. clock-names = "fck";
  70. };
  71. timer8: timer@ffffb0 {
  72. compatible = "renesas,8bit-timer";
  73. reg = <0xffffb0 10>;
  74. interrupts = <72 0>;
  75. clocks = <&fclk>;
  76. clock-names = "fck";
  77. };
  78. sci0: serial@ffff78 {
  79. compatible = "renesas,sci";
  80. reg = <0xffff78 8>;
  81. interrupts = <88 0>, <89 0>, <90 0>, <91 0>;
  82. clocks = <&fclk>;
  83. clock-names = "fck";
  84. };
  85. sci1: serial@ffff80 {
  86. compatible = "renesas,sci";
  87. reg = <0xffff80 8>;
  88. interrupts = <92 0>, <93 0>, <94 0>, <95 0>;
  89. clocks = <&fclk>;
  90. clock-names = "fck";
  91. };
  92. sci2: serial@ffff88 {
  93. compatible = "renesas,sci";
  94. reg = <0xffff88 8>;
  95. interrupts = <96 0>, <97 0>, <98 0>, <99 0>;
  96. clocks = <&fclk>;
  97. clock-names = "fck";
  98. };
  99. };