entry.h 2.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
  3. #ifndef __ASM_CSKY_ENTRY_H
  4. #define __ASM_CSKY_ENTRY_H
  5. #include <asm/setup.h>
  6. #include <abi/regdef.h>
  7. #define LSAVE_PC 8
  8. #define LSAVE_PSR 12
  9. #define LSAVE_A0 24
  10. #define LSAVE_A1 28
  11. #define LSAVE_A2 32
  12. #define LSAVE_A3 36
  13. #define LSAVE_A4 40
  14. #define LSAVE_A5 44
  15. #define EPC_INCREASE 2
  16. #define EPC_KEEP 0
  17. .macro USPTOKSP
  18. mtcr sp, ss1
  19. mfcr sp, ss0
  20. .endm
  21. .macro KSPTOUSP
  22. mtcr sp, ss0
  23. mfcr sp, ss1
  24. .endm
  25. .macro INCTRAP rx
  26. addi \rx, EPC_INCREASE
  27. .endm
  28. .macro SAVE_ALL epc_inc
  29. mtcr r13, ss2
  30. mfcr r13, epsr
  31. btsti r13, 31
  32. bt 1f
  33. USPTOKSP
  34. 1:
  35. subi sp, 32
  36. subi sp, 32
  37. subi sp, 16
  38. stw r13, (sp, 12)
  39. stw lr, (sp, 4)
  40. mfcr lr, epc
  41. movi r13, \epc_inc
  42. add lr, r13
  43. stw lr, (sp, 8)
  44. mfcr lr, ss1
  45. stw lr, (sp, 16)
  46. stw a0, (sp, 20)
  47. stw a0, (sp, 24)
  48. stw a1, (sp, 28)
  49. stw a2, (sp, 32)
  50. stw a3, (sp, 36)
  51. addi sp, 32
  52. addi sp, 8
  53. mfcr r13, ss2
  54. stw r6, (sp)
  55. stw r7, (sp, 4)
  56. stw r8, (sp, 8)
  57. stw r9, (sp, 12)
  58. stw r10, (sp, 16)
  59. stw r11, (sp, 20)
  60. stw r12, (sp, 24)
  61. stw r13, (sp, 28)
  62. stw r14, (sp, 32)
  63. stw r1, (sp, 36)
  64. subi sp, 32
  65. subi sp, 8
  66. .endm
  67. .macro RESTORE_ALL
  68. psrclr ie
  69. ldw lr, (sp, 4)
  70. ldw a0, (sp, 8)
  71. mtcr a0, epc
  72. ldw a0, (sp, 12)
  73. mtcr a0, epsr
  74. btsti a0, 31
  75. ldw a0, (sp, 16)
  76. mtcr a0, ss1
  77. ldw a0, (sp, 24)
  78. ldw a1, (sp, 28)
  79. ldw a2, (sp, 32)
  80. ldw a3, (sp, 36)
  81. addi sp, 32
  82. addi sp, 8
  83. ldw r6, (sp)
  84. ldw r7, (sp, 4)
  85. ldw r8, (sp, 8)
  86. ldw r9, (sp, 12)
  87. ldw r10, (sp, 16)
  88. ldw r11, (sp, 20)
  89. ldw r12, (sp, 24)
  90. ldw r13, (sp, 28)
  91. ldw r14, (sp, 32)
  92. ldw r1, (sp, 36)
  93. addi sp, 32
  94. addi sp, 8
  95. bt 1f
  96. KSPTOUSP
  97. 1:
  98. rte
  99. .endm
  100. .macro SAVE_SWITCH_STACK
  101. subi sp, 32
  102. stm r8-r15, (sp)
  103. .endm
  104. .macro RESTORE_SWITCH_STACK
  105. ldm r8-r15, (sp)
  106. addi sp, 32
  107. .endm
  108. /* MMU registers operators. */
  109. .macro RD_MIR rx
  110. cprcr \rx, cpcr0
  111. .endm
  112. .macro RD_MEH rx
  113. cprcr \rx, cpcr4
  114. .endm
  115. .macro RD_MCIR rx
  116. cprcr \rx, cpcr8
  117. .endm
  118. .macro RD_PGDR rx
  119. cprcr \rx, cpcr29
  120. .endm
  121. .macro WR_MEH rx
  122. cpwcr \rx, cpcr4
  123. .endm
  124. .macro WR_MCIR rx
  125. cpwcr \rx, cpcr8
  126. .endm
  127. .macro SETUP_MMU rx
  128. lrw \rx, PHYS_OFFSET | 0xe
  129. cpwcr \rx, cpcr30
  130. lrw \rx, (PHYS_OFFSET + 0x20000000) | 0xe
  131. cpwcr \rx, cpcr31
  132. .endm
  133. #endif /* __ASM_CSKY_ENTRY_H */