r8a77980-condor.dts 4.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Device Tree Source for the Condor board
  4. *
  5. * Copyright (C) 2018 Renesas Electronics Corp.
  6. * Copyright (C) 2018 Cogent Embedded, Inc.
  7. */
  8. /dts-v1/;
  9. #include "r8a77980.dtsi"
  10. / {
  11. model = "Renesas Condor board based on r8a77980";
  12. compatible = "renesas,condor", "renesas,r8a77980";
  13. aliases {
  14. serial0 = &scif0;
  15. ethernet0 = &gether;
  16. };
  17. chosen {
  18. stdout-path = "serial0:115200n8";
  19. };
  20. memory@48000000 {
  21. device_type = "memory";
  22. /* first 128MB is reserved for secure area. */
  23. reg = <0 0x48000000 0 0x78000000>;
  24. };
  25. d3_3v: regulator-0 {
  26. compatible = "regulator-fixed";
  27. regulator-name = "D3.3V";
  28. regulator-min-microvolt = <3300000>;
  29. regulator-max-microvolt = <3300000>;
  30. regulator-boot-on;
  31. regulator-always-on;
  32. };
  33. vddq_vin01: regulator-1 {
  34. compatible = "regulator-fixed";
  35. regulator-name = "VDDQ_VIN01";
  36. regulator-min-microvolt = <1800000>;
  37. regulator-max-microvolt = <1800000>;
  38. regulator-boot-on;
  39. regulator-always-on;
  40. };
  41. d1_8v: regulator-2 {
  42. compatible = "regulator-fixed";
  43. regulator-name = "D1.8V";
  44. regulator-min-microvolt = <1800000>;
  45. regulator-max-microvolt = <1800000>;
  46. regulator-boot-on;
  47. regulator-always-on;
  48. };
  49. hdmi-out {
  50. compatible = "hdmi-connector";
  51. type = "a";
  52. port {
  53. hdmi_con: endpoint {
  54. remote-endpoint = <&adv7511_out>;
  55. };
  56. };
  57. };
  58. lvds-decoder {
  59. compatible = "thine,thc63lvd1024";
  60. vcc-supply = <&d3_3v>;
  61. ports {
  62. #address-cells = <1>;
  63. #size-cells = <0>;
  64. port@0 {
  65. reg = <0>;
  66. thc63lvd1024_in: endpoint {
  67. remote-endpoint = <&lvds0_out>;
  68. };
  69. };
  70. port@2 {
  71. reg = <2>;
  72. thc63lvd1024_out: endpoint {
  73. remote-endpoint = <&adv7511_in>;
  74. };
  75. };
  76. };
  77. };
  78. x1_clk: x1-clock {
  79. compatible = "fixed-clock";
  80. #clock-cells = <0>;
  81. clock-frequency = <148500000>;
  82. };
  83. };
  84. &canfd {
  85. pinctrl-0 = <&canfd0_pins>;
  86. pinctrl-names = "default";
  87. status = "okay";
  88. channel0 {
  89. status = "okay";
  90. };
  91. };
  92. &du {
  93. clocks = <&cpg CPG_MOD 724>,
  94. <&x1_clk>;
  95. clock-names = "du.0", "dclkin.0";
  96. status = "okay";
  97. };
  98. &extal_clk {
  99. clock-frequency = <16666666>;
  100. };
  101. &extalr_clk {
  102. clock-frequency = <32768>;
  103. };
  104. &gether {
  105. pinctrl-0 = <&gether_pins>;
  106. pinctrl-names = "default";
  107. phy-mode = "rgmii-id";
  108. phy-handle = <&phy0>;
  109. renesas,no-ether-link;
  110. status = "okay";
  111. phy0: ethernet-phy@0 {
  112. rxc-skew-ps = <1500>;
  113. reg = <0>;
  114. interrupt-parent = <&gpio4>;
  115. interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
  116. };
  117. };
  118. &i2c0 {
  119. pinctrl-0 = <&i2c0_pins>;
  120. pinctrl-names = "default";
  121. status = "okay";
  122. clock-frequency = <400000>;
  123. io_expander0: gpio@20 {
  124. compatible = "onnn,pca9654";
  125. reg = <0x20>;
  126. gpio-controller;
  127. #gpio-cells = <2>;
  128. };
  129. io_expander1: gpio@21 {
  130. compatible = "onnn,pca9654";
  131. reg = <0x21>;
  132. gpio-controller;
  133. #gpio-cells = <2>;
  134. };
  135. hdmi@39 {
  136. compatible = "adi,adv7511w";
  137. reg = <0x39>;
  138. interrupt-parent = <&gpio1>;
  139. interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
  140. avdd-supply = <&d1_8v>;
  141. dvdd-supply = <&d1_8v>;
  142. pvdd-supply = <&d1_8v>;
  143. bgvdd-supply = <&d1_8v>;
  144. dvdd-3v-supply = <&d3_3v>;
  145. adi,input-depth = <8>;
  146. adi,input-colorspace = "rgb";
  147. adi,input-clock = "1x";
  148. adi,input-style = <1>;
  149. adi,input-justification = "evenly";
  150. ports {
  151. #address-cells = <1>;
  152. #size-cells = <0>;
  153. port@0 {
  154. reg = <0>;
  155. adv7511_in: endpoint {
  156. remote-endpoint = <&thc63lvd1024_out>;
  157. };
  158. };
  159. port@1 {
  160. reg = <1>;
  161. adv7511_out: endpoint {
  162. remote-endpoint = <&hdmi_con>;
  163. };
  164. };
  165. };
  166. };
  167. };
  168. &lvds0 {
  169. status = "okay";
  170. ports {
  171. port@1 {
  172. lvds0_out: endpoint {
  173. remote-endpoint = <&thc63lvd1024_in>;
  174. };
  175. };
  176. };
  177. };
  178. &mmc0 {
  179. pinctrl-0 = <&mmc_pins>;
  180. pinctrl-1 = <&mmc_pins_uhs>;
  181. pinctrl-names = "default", "state_uhs";
  182. vmmc-supply = <&d3_3v>;
  183. vqmmc-supply = <&vddq_vin01>;
  184. mmc-hs200-1_8v;
  185. bus-width = <8>;
  186. non-removable;
  187. status = "okay";
  188. };
  189. &pciec {
  190. status = "okay";
  191. };
  192. &pcie_bus_clk {
  193. clock-frequency = <100000000>;
  194. };
  195. &pcie_phy {
  196. status = "okay";
  197. };
  198. &pfc {
  199. canfd0_pins: canfd0 {
  200. groups = "canfd0_data_a";
  201. function = "canfd0";
  202. };
  203. gether_pins: gether {
  204. groups = "gether_mdio_a", "gether_rgmii",
  205. "gether_txcrefclk", "gether_txcrefclk_mega";
  206. function = "gether";
  207. };
  208. i2c0_pins: i2c0 {
  209. groups = "i2c0";
  210. function = "i2c0";
  211. };
  212. mmc_pins: mmc {
  213. groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
  214. function = "mmc";
  215. power-source = <3300>;
  216. };
  217. mmc_pins_uhs: mmc_uhs {
  218. groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
  219. function = "mmc";
  220. power-source = <1800>;
  221. };
  222. scif0_pins: scif0 {
  223. groups = "scif0_data";
  224. function = "scif0";
  225. };
  226. scif_clk_pins: scif_clk {
  227. groups = "scif_clk_b";
  228. function = "scif_clk";
  229. };
  230. };
  231. &rwdt {
  232. timeout-sec = <60>;
  233. status = "okay";
  234. };
  235. &scif0 {
  236. pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
  237. pinctrl-names = "default";
  238. status = "okay";
  239. };
  240. &scif_clk {
  241. clock-frequency = <14745600>;
  242. };