linux_kernel/arch/arm64/boot/dts/qcom/sdm845.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * SDM845 SoC device tree source
 *
 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
 */

#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>

/ {
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		i2c5 = &i2c5;
		i2c6 = &i2c6;
		i2c7 = &i2c7;
		i2c8 = &i2c8;
		i2c9 = &i2c9;
		i2c10 = &i2c10;
		i2c11 = &i2c11;
		i2c12 = &i2c12;
		i2c13 = &i2c13;
		i2c14 = &i2c14;
		i2c15 = &i2c15;
		spi0 = &spi0;
		spi1 = &spi1;
		spi2 = &spi2;
		spi3 = &spi3;
		spi4 = &spi4;
		spi5 = &spi5;
		spi6 = &spi6;
		spi7 = &spi7;
		spi8 = &spi8;
		spi9 = &spi9;
		spi10 = &spi10;
		spi11 = &spi11;
		spi12 = &spi12;
		spi13 = &spi13;
		spi14 = &spi14;
		spi15 = &spi15;
	};

	chosen { };

	memory@80000000 {
		device_type = "memory";
		/* We expect the bootloader to fill in the size */
		reg = <0 0x80000000 0 0>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		memory@85fc0000 {
			reg = <0 0x85fc0000 0 0x20000>;
			no-map;
		};

		memory@85fe0000 {
			compatible = "qcom,cmd-db";
			reg = <0x0 0x85fe0000 0x0 0x20000>;
			no-map;
		};

		smem_mem: memory@86000000 {
			reg = <0x0 0x86000000 0x0 0x200000>;
			no-map;
		};

		memory@86200000 {
			reg = <0 0x86200000 0 0x2d00000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
			L2_0: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
				L3_0: l3-cache {
				      compatible = "cache";
				};
			};
		};

		CPU1: cpu@100 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x100>;
			enable-method = "psci";
			next-level-cache = <&L2_100>;
			L2_100: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
			};
		};

		CPU2: cpu@200 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x200>;
			enable-method = "psci";
			next-level-cache = <&L2_200>;
			L2_200: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
			};
		};

		CPU3: cpu@300 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x300>;
			enable-method = "psci";
			next-level-cache = <&L2_300>;
			L2_300: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
			};
		};

		CPU4: cpu@400 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x400>;
			enable-method = "psci";
			next-level-cache = <&L2_400>;
			L2_400: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
			};
		};

		CPU5: cpu@500 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x500>;
			enable-method = "psci";
			next-level-cache = <&L2_500>;
			L2_500: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
			};
		};

		CPU6: cpu@600 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x600>;
			enable-method = "psci";
			next-level-cache = <&L2_600>;
			L2_600: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
			};
		};

		CPU7: cpu@700 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x700>;
			enable-method = "psci";
			next-level-cache = <&L2_700>;
			L2_700: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
			};
		};
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
	};

	clocks {
		xo_board: xo-board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <38400000>;
			clock-output-names = "xo_board";
		};

		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32764>;
		};
	};

	tcsr_mutex: hwlock {
		compatible = "qcom,tcsr-mutex";
		syscon = <&tcsr_mutex_regs 0 0x1000>;
		#hwlock-cells = <1>;
	};

	smem {
		compatible = "qcom,smem";
		memory-region = <&smem_mem>;
		hwlocks = <&tcsr_mutex 3>;
	};

	smp2p-cdsp {
		compatible = "qcom,smp2p";
		qcom,smem = <94>, <432>;

		interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;

		mboxes = <&apss_shared 6>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <5>;

		cdsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		cdsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smp2p-lpass {
		compatible = "qcom,smp2p";
		qcom,smem = <443>, <429>;

		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;

		mboxes = <&apss_shared 10>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <2>;

		adsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		adsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smp2p-mpss {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;
		interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
		mboxes = <&apss_shared 14>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <1>;

		modem_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		modem_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smp2p-slpi {
		compatible = "qcom,smp2p";
		qcom,smem = <481>, <430>;
		interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
		mboxes = <&apss_shared 26>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <3>;

		slpi_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		slpi_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;
		compatible = "simple-bus";

		gcc: clock-controller@100000 {
			compatible = "qcom,gcc-sdm845";
			reg = <0x100000 0x1f0000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
		};

		qfprom@784000 {
			compatible = "qcom,qfprom";
			reg = <0x784000 0x8ff>;
			#address-cells = <1>;
			#size-cells = <1>;

			qusb2p_hstx_trim: hstx-trim-primary@1eb {
				reg = <0x1eb 0x1>;
				bits = <1 4>;
			};

			qusb2s_hstx_trim: hstx-trim-secondary@1eb {
				reg = <0x1eb 0x2>;
				bits = <6 4>;
			};
		};

		qupv3_id_0: geniqup@8c0000 {
			compatible = "qcom,geni-se-qup";
			reg = <0x8c0000 0x6000>;
			clock-names = "m-ahb", "s-ahb";
			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			status = "disabled";

			i2c0: i2c@880000 {
				compatible = "qcom,geni-i2c";
				reg = <0x880000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c0_default>;
				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			spi0: spi@880000 {
				compatible = "qcom,geni-spi";
				reg = <0x880000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi0_default>;
				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c1: i2c@884000 {
				compatible = "qcom,geni-i2c";
				reg = <0x884000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c1_default>;
				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			spi1: spi@884000 {
				compatible = "qcom,geni-spi";
				reg = <0x884000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi1_default>;
				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c2: i2c@888000 {
				compatible = "qcom,geni-i2c";
				reg = <0x888000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c2_default>;
				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			spi2: spi@888000 {
				compatible = "qcom,geni-spi";
				reg = <0x888000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi2_default>;
				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c3: i2c@88c000 {
				compatible = "qcom,geni-i2c";
				reg = <0x88c000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c3_default>;
				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			spi3: spi@88c000 {
				compatible = "qcom,geni-spi";
				reg = <0x88c000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi3_default>;
				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c4: i2c@890000 {
				compatible = "qcom,geni-i2c";
				reg = <0x890000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c4_default>;
				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			spi4: spi@890000 {
				compatible = "qcom,geni-spi";
				reg = <0x890000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi4_default>;
				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c5: i2c@894000 {
				compatible = "qcom,geni-i2c";
				reg = <0x894000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c5_default>;
				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			spi5: spi@894000 {
				compatible = "qcom,geni-spi";
				reg = <0x894000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi5_default>;
				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c6: i2c@898000 {
				compatible = "qcom,geni-i2c";
				reg = <0x898000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c6_default>;
				interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			spi6: spi@898000 {
				compatible = "qcom,geni-spi";
				reg = <0x898000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi6_default>;
				interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c7: i2c@89c000 {
				compatible = "qcom,geni-i2c";
				reg = <0x89c000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c7_default>;
				interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			spi7: spi@89c000 {
				compatible = "qcom,geni-spi";
				reg = <0x89c000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi7_default>;
				interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};
		};

		qupv3_id_1: geniqup@ac0000 {
			compatible = "qcom,geni-se-qup";
			reg = <0xac0000 0x6000>;
			clock-names = "m-ahb", "s-ahb";
			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			status = "disabled";

			i2c8: i2c@a80000 {
				compatible = "qcom,geni-i2c";
				reg = <0xa80000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c8_default>;
				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			spi8: spi@a80000 {
				compatible = "qcom,geni-spi";
				reg = <0xa80000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi8_default>;
				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c9: i2c@a84000 {
				compatible = "qcom,geni-i2c";
				reg = <0xa84000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c9_default>;
				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			spi9: spi@a84000 {
				compatible = "qcom,geni-spi";
				reg = <0xa84000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi9_default>;
				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			uart9: serial@a84000 {
				compatible = "qcom,geni-debug-uart";
				reg = <0xa84000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_uart9_default>;
				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			i2c10: i2c@a88000 {
				compatible = "qcom,geni-i2c";
				reg = <0xa88000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c10_default>;
				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			spi10: spi@a88000 {
				compatible = "qcom,geni-spi";
				reg = <0xa88000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi10_default>;
				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c11: i2c@a8c000 {
				compatible = "qcom,geni-i2c";
				reg = <0xa8c000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c11_default>;
				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			spi11: spi@a8c000 {
				compatible = "qcom,geni-spi";
				reg = <0xa8c000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi11_default>;
				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c12: i2c@a90000 {
				compatible = "qcom,geni-i2c";
				reg = <0xa90000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c12_default>;
				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			spi12: spi@a90000 {
				compatible = "qcom,geni-spi";
				reg = <0xa90000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi12_default>;
				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c13: i2c@a94000 {
				compatible = "qcom,geni-i2c";
				reg = <0xa94000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c13_default>;
				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			spi13: spi@a94000 {
				compatible = "qcom,geni-spi";
				reg = <0xa94000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi13_default>;
				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c14: i2c@a98000 {
				compatible = "qcom,geni-i2c";
				reg = <0xa98000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c14_default>;
				interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			spi14: spi@a98000 {
				compatible = "qcom,geni-spi";
				reg = <0xa98000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi14_default>;
				interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c15: i2c@a9c000 {
				compatible = "qcom,geni-i2c";
				reg = <0xa9c000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c15_default>;
				interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			spi15: spi@a9c000 {
				compatible = "qcom,geni-spi";
				reg = <0xa9c000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi15_default>;
				interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};
		};

		tcsr_mutex_regs: syscon@1f40000 {
			compatible = "syscon";
			reg = <0x1f40000 0x40000>;
		};

		tlmm: pinctrl@3400000 {
			compatible = "qcom,sdm845-pinctrl";
			reg = <0x03400000 0xc00000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;

			qup_i2c0_default: qup-i2c0-default {
				pinmux {
					pins = "gpio0", "gpio1";
					function = "qup0";
				};
			};

			qup_i2c1_default: qup-i2c1-default {
				pinmux {
					pins = "gpio17", "gpio18";
					function = "qup1";
				};
			};

			qup_i2c2_default: qup-i2c2-default {
				pinmux {
					pins = "gpio27", "gpio28";
					function = "qup2";
				};
			};

			qup_i2c3_default: qup-i2c3-default {
				pinmux {
					pins = "gpio41", "gpio42";
					function = "qup3";
				};
			};

			qup_i2c4_default: qup-i2c4-default {
				pinmux {
					pins = "gpio89", "gpio90";
					function = "qup4";
				};
			};

			qup_i2c5_default: qup-i2c5-default {
				pinmux {
					pins = "gpio85", "gpio86";
					function = "qup5";
				};
			};

			qup_i2c6_default: qup-i2c6-default {
				pinmux {
					pins = "gpio45", "gpio46";
					function = "qup6";
				};
			};

			qup_i2c7_default: qup-i2c7-default {
				pinmux {
					pins = "gpio93", "gpio94";
					function = "qup7";
				};
			};

			qup_i2c8_default: qup-i2c8-default {
				pinmux {
					pins = "gpio65", "gpio66";
					function = "qup8";
				};
			};

			qup_i2c9_default: qup-i2c9-default {
				pinmux {
					pins = "gpio6", "gpio7";
					function = "qup9";
				};
			};

			qup_i2c10_default: qup-i2c10-default {
				pinmux {
					pins = "gpio55", "gpio56";
					function = "qup10";
				};
			};

			qup_i2c11_default: qup-i2c11-default {
				pinmux {
					pins = "gpio31", "gpio32";
					function = "qup11";
				};
			};

			qup_i2c12_default: qup-i2c12-default {
				pinmux {
					pins = "gpio49", "gpio50";
					function = "qup12";
				};
			};

			qup_i2c13_default: qup-i2c13-default {
				pinmux {
					pins = "gpio105", "gpio106";
					function = "qup13";
				};
			};

			qup_i2c14_default: qup-i2c14-default {
				pinmux {
					pins = "gpio33", "gpio34";
					function = "qup14";
				};
			};

			qup_i2c15_default: qup-i2c15-default {
				pinmux {
					pins = "gpio81", "gpio82";
					function = "qup15";
				};
			};

			qup_spi0_default: qup-spi0-default {
				pinmux {
					pins = "gpio0", "gpio1",
					       "gpio2", "gpio3";
					function = "qup0";
				};
			};

			qup_spi1_default: qup-spi1-default {
				pinmux {
					pins = "gpio17", "gpio18",
					       "gpio19", "gpio20";
					function = "qup1";
				};
			};

			qup_spi2_default: qup-spi2-default {
				pinmux {
					pins = "gpio27", "gpio28",
					       "gpio29", "gpio30";
					function = "qup2";
				};
			};

			qup_spi3_default: qup-spi3-default {
				pinmux {
					pins = "gpio41", "gpio42",
					       "gpio43", "gpio44";
					function = "qup3";
				};
			};

			qup_spi4_default: qup-spi4-default {
				pinmux {
					pins = "gpio89", "gpio90",
					       "gpio91", "gpio92";
					function = "qup4";
				};
			};

			qup_spi5_default: qup-spi5-default {
				pinmux {
					pins = "gpio85", "gpio86",
					       "gpio87", "gpio88";
					function = "qup5";
				};
			};

			qup_spi6_default: qup-spi6-default {
				pinmux {
					pins = "gpio45", "gpio46",
					       "gpio47", "gpio48";
					function = "qup6";
				};
			};

			qup_spi7_default: qup-spi7-default {
				pinmux {
					pins = "gpio93", "gpio94",
					       "gpio95", "gpio96";
					function = "qup7";
				};
			};

			qup_spi8_default: qup-spi8-default {
				pinmux {
					pins = "gpio65", "gpio66",
					       "gpio67", "gpio68";
					function = "qup8";
				};
			};

			qup_spi9_default: qup-spi9-default {
				pinmux {
					pins = "gpio6", "gpio7",
					       "gpio4", "gpio5";
					function = "qup9";
				};
			};

			qup_spi10_default: qup-spi10-default {
				pinmux {
					pins = "gpio55", "gpio56",
					       "gpio53", "gpio54";
					function = "qup10";
				};
			};

			qup_spi11_default: qup-spi11-default {
				pinmux {
					pins = "gpio31", "gpio32",
					       "gpio33", "gpio34";
					function = "qup11";
				};
			};

			qup_spi12_default: qup-spi12-default {
				pinmux {
					pins = "gpio49", "gpio50",
					       "gpio51", "gpio52";
					function = "qup12";
				};
			};

			qup_spi13_default: qup-spi13-default {
				pinmux {
					pins = "gpio105", "gpio106",
					       "gpio107", "gpio108";
					function = "qup13";
				};
			};

			qup_spi14_default: qup-spi14-default {
				pinmux {
					pins = "gpio33", "gpio34",
					       "gpio31", "gpio32";
					function = "qup14";
				};
			};

			qup_spi15_default: qup-spi15-default {
				pinmux {
					pins = "gpio81", "gpio82",
					       "gpio83", "gpio84";
					function = "qup15";
				};
			};

			qup_uart9_default: qup-uart9-default {
				pinmux {
					pins = "gpio4", "gpio5";
					function = "qup9";
				};
			};
		};

		usb_1_hsphy: phy@88e2000 {
			compatible = "qcom,sdm845-qusb2-phy";
			reg = <0x88e2000 0x400>;
			status = "disabled";
			#phy-cells = <0>;

			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
				 <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "cfg_ahb", "ref";

			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;

			nvmem-cells = <&qusb2p_hstx_trim>;
		};

		usb_2_hsphy: phy@88e3000 {
			compatible = "qcom,sdm845-qusb2-phy";
			reg = <0x88e3000 0x400>;
			status = "disabled";
			#phy-cells = <0>;

			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
				 <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "cfg_ahb", "ref";

			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;

			nvmem-cells = <&qusb2s_hstx_trim>;
		};

		usb_1_qmpphy: phy@88e9000 {
			compatible = "qcom,sdm845-qmp-usb3-phy";
			reg = <0x88e9000 0x18c>,
			      <0x88e8000 0x10>;
			reg-names = "reg-base", "dp_com";
			status = "disabled";
			#clock-cells = <1>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
				 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
				 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
			clock-names = "aux", "cfg_ahb", "ref", "com_aux";

			resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
				 <&gcc GCC_USB3_PHY_PRIM_BCR>;
			reset-names = "phy", "common";

			usb_1_ssphy: lane@88e9200 {
				reg = <0x88e9200 0x128>,
				      <0x88e9400 0x200>,
				      <0x88e9c00 0x218>,
				      <0x88e9a00 0x100>;
				#phy-cells = <0>;
				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
				clock-names = "pipe0";
				clock-output-names = "usb3_phy_pipe_clk_src";
			};
		};

		usb_2_qmpphy: phy@88eb000 {
			compatible = "qcom,sdm845-qmp-usb3-uni-phy";
			reg = <0x88eb000 0x18c>;
			status = "disabled";
			#clock-cells = <1>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
				 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
				 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
				 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
			clock-names = "aux", "cfg_ahb", "ref", "com_aux";

			resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
				 <&gcc GCC_USB3_PHY_SEC_BCR>;
			reset-names = "phy", "common";

			usb_2_ssphy: lane@88eb200 {
				reg = <0x88eb200 0x128>,
				      <0x88eb400 0x1fc>,
				      <0x88eb800 0x218>,
				      <0x88e9600 0x70>;
				#phy-cells = <0>;
				clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
				clock-names = "pipe0";
				clock-output-names = "usb3_uni_phy_pipe_clk_src";
			};
		};

		usb_1: usb@a6f8800 {
			compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
			reg = <0xa6f8800 0x400>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
			clock-names = "cfg_noc", "core", "iface", "mock_utmi",
				      "sleep";

			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
			assigned-clock-rates = <19200000>, <150000000>;

			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hs_phy_irq", "ss_phy_irq",
					  "dm_hs_phy_irq", "dp_hs_phy_irq";

			power-domains = <&gcc USB30_PRIM_GDSC>;

			resets = <&gcc GCC_USB30_PRIM_BCR>;

			usb_1_dwc3: dwc3@a600000 {
				compatible = "snps,dwc3";
				reg = <0xa600000 0xcd00>;
				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
				snps,dis_u2_susphy_quirk;
				snps,dis_enblslpm_quirk;
				phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
				phy-names = "usb2-phy", "usb3-phy";
			};
		};

		usb_2: usb@a8f8800 {
			compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
			reg = <0xa8f8800 0x400>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
				 <&gcc GCC_USB30_SEC_MASTER_CLK>,
				 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
				 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
				 <&gcc GCC_USB30_SEC_SLEEP_CLK>;
			clock-names = "cfg_noc", "core", "iface", "mock_utmi",
				      "sleep";

			assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
					  <&gcc GCC_USB30_SEC_MASTER_CLK>;
			assigned-clock-rates = <19200000>, <150000000>;

			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hs_phy_irq", "ss_phy_irq",
					  "dm_hs_phy_irq", "dp_hs_phy_irq";

			power-domains = <&gcc USB30_SEC_GDSC>;

			resets = <&gcc GCC_USB30_SEC_BCR>;

			usb_2_dwc3: dwc3@a800000 {
				compatible = "snps,dwc3";
				reg = <0xa800000 0xcd00>;
				interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
				snps,dis_u2_susphy_quirk;
				snps,dis_enblslpm_quirk;
				phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
				phy-names = "usb2-phy", "usb3-phy";
			};
		};

		dispcc: clock-controller@af00000 {
			compatible = "qcom,sdm845-dispcc";
			reg = <0xaf00000 0x10000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
		};

		tsens0: thermal-sensor@c263000 {
			compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
			reg = <0xc263000 0x1ff>, /* TM */
			      <0xc222000 0x1ff>; /* SROT */
			#qcom,sensors = <13>;
			#thermal-sensor-cells = <1>;
		};

		tsens1: thermal-sensor@c265000 {
			compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
			reg = <0xc265000 0x1ff>, /* TM */
			      <0xc223000 0x1ff>; /* SROT */
			#qcom,sensors = <8>;
			#thermal-sensor-cells = <1>;
		};

		aoss_reset: reset-controller@c2a0000 {
			compatible = "qcom,sdm845-aoss-cc";
			reg = <0xc2a0000 0x31000>;
			#reset-cells = <1>;
		};

		spmi_bus: spmi@c440000 {
			compatible = "qcom,spmi-pmic-arb";
			reg = <0xc440000 0x1100>,
			      <0xc600000 0x2000000>,
			      <0xe600000 0x100000>,
			      <0xe700000 0xa0000>,
			      <0xc40a000 0x26000>;
			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
			interrupt-names = "periph_irq";
			interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
			cell-index = <0>;
		};

		apss_shared: mailbox@17990000 {
			compatible = "qcom,sdm845-apss-shared";
			reg = <0x17990000 0x1000>;
			#mbox-cells = <1>;
		};

		apps_rsc: rsc@179c0000 {
			label = "apps_rsc";
			compatible = "qcom,rpmh-rsc";
			reg = <0x179c0000 0x10000>,
			      <0x179d0000 0x10000>,
			      <0x179e0000 0x10000>;
			reg-names = "drv-0", "drv-1", "drv-2";
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			qcom,tcs-offset = <0xd00>;
			qcom,drv-id = <2>;
			qcom,tcs-config = <ACTIVE_TCS  2>,
					  <SLEEP_TCS   3>,
					  <WAKE_TCS    3>,
					  <CONTROL_TCS 1>;

			rpmhcc: clock-controller {
				compatible = "qcom,sdm845-rpmh-clk";
				#clock-cells = <1>;
			};
		};

		intc: interrupt-controller@17a00000 {
			compatible = "arm,gic-v3";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x17a00000 0x10000>,     /* GICD */
			      <0x17a60000 0x100000>;    /* GICR * 8 */
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

			gic-its@17a40000 {
				compatible = "arm,gic-v3-its";
				msi-controller;
				#msi-cells = <1>;
				reg = <0x17a40000 0x20000>;
				status = "disabled";
			};
		};

		timer@17c90000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0x17c90000 0x1000>;

			frame@17ca0000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17ca0000 0x1000>,
				      <0x17cb0000 0x1000>;
			};

			frame@17cc0000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17cc0000 0x1000>;
				status = "disabled";
			};

			frame@17cd0000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17cd0000 0x1000>;
				status = "disabled";
			};

			frame@17ce0000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17ce0000 0x1000>;
				status = "disabled";
			};

			frame@17cf0000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17cf0000 0x1000>;
				status = "disabled";
			};

			frame@17d00000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17d00000 0x1000>;
				status = "disabled";
			};

			frame@17d10000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17d10000 0x1000>;
				status = "disabled";
			};
		};
	};
};