skeleton_hs_idu.dtsi 1.2 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364
  1. /*
  2. * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. / {
  9. compatible = "snps,arc";
  10. #address-cells = <1>;
  11. #size-cells = <1>;
  12. chosen { };
  13. aliases { };
  14. cpus {
  15. #address-cells = <1>;
  16. #size-cells = <0>;
  17. cpu@0 {
  18. device_type = "cpu";
  19. compatible = "snps,archs38";
  20. reg = <0>;
  21. clocks = <&core_clk>;
  22. };
  23. cpu@1 {
  24. device_type = "cpu";
  25. compatible = "snps,archs38";
  26. reg = <1>;
  27. clocks = <&core_clk>;
  28. };
  29. cpu@2 {
  30. device_type = "cpu";
  31. compatible = "snps,archs38";
  32. reg = <2>;
  33. clocks = <&core_clk>;
  34. };
  35. cpu@3 {
  36. device_type = "cpu";
  37. compatible = "snps,archs38";
  38. reg = <3>;
  39. clocks = <&core_clk>;
  40. };
  41. };
  42. /* TIMER0 with interrupt for clockevent */
  43. timer0 {
  44. compatible = "snps,arc-timer";
  45. interrupts = <16>;
  46. interrupt-parent = <&core_intc>;
  47. clocks = <&core_clk>;
  48. };
  49. /* 64-bit Global Free Running Counter */
  50. gfrc {
  51. compatible = "snps,archs-timer-gfrc";
  52. clocks = <&core_clk>;
  53. };
  54. memory {
  55. device_type = "memory";
  56. reg = <0x80000000 0x10000000>; /* 256M */
  57. };
  58. };