amdgpu_device.c 60 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391
  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include <linux/console.h>
  29. #include <linux/slab.h>
  30. #include <linux/debugfs.h>
  31. #include <drm/drmP.h>
  32. #include <drm/drm_crtc_helper.h>
  33. #include <drm/amdgpu_drm.h>
  34. #include <linux/vgaarb.h>
  35. #include <linux/vga_switcheroo.h>
  36. #include <linux/efi.h>
  37. #include "amdgpu.h"
  38. #include "amdgpu_i2c.h"
  39. #include "atom.h"
  40. #include "amdgpu_atombios.h"
  41. #include "amd_pcie.h"
  42. #ifdef CONFIG_DRM_AMDGPU_CIK
  43. #include "cik.h"
  44. #endif
  45. #include "vi.h"
  46. #include "bif/bif_4_1_d.h"
  47. static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
  48. static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
  49. static const char *amdgpu_asic_name[] = {
  50. "BONAIRE",
  51. "KAVERI",
  52. "KABINI",
  53. "HAWAII",
  54. "MULLINS",
  55. "TOPAZ",
  56. "TONGA",
  57. "FIJI",
  58. "CARRIZO",
  59. "STONEY",
  60. "POLARIS10",
  61. "POLARIS11",
  62. "LAST",
  63. };
  64. bool amdgpu_device_is_px(struct drm_device *dev)
  65. {
  66. struct amdgpu_device *adev = dev->dev_private;
  67. if (adev->flags & AMD_IS_PX)
  68. return true;
  69. return false;
  70. }
  71. /*
  72. * MMIO register access helper functions.
  73. */
  74. uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
  75. bool always_indirect)
  76. {
  77. if ((reg * 4) < adev->rmmio_size && !always_indirect)
  78. return readl(((void __iomem *)adev->rmmio) + (reg * 4));
  79. else {
  80. unsigned long flags;
  81. uint32_t ret;
  82. spin_lock_irqsave(&adev->mmio_idx_lock, flags);
  83. writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
  84. ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
  85. spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
  86. return ret;
  87. }
  88. }
  89. void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
  90. bool always_indirect)
  91. {
  92. if ((reg * 4) < adev->rmmio_size && !always_indirect)
  93. writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
  94. else {
  95. unsigned long flags;
  96. spin_lock_irqsave(&adev->mmio_idx_lock, flags);
  97. writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
  98. writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
  99. spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
  100. }
  101. }
  102. u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
  103. {
  104. if ((reg * 4) < adev->rio_mem_size)
  105. return ioread32(adev->rio_mem + (reg * 4));
  106. else {
  107. iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
  108. return ioread32(adev->rio_mem + (mmMM_DATA * 4));
  109. }
  110. }
  111. void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
  112. {
  113. if ((reg * 4) < adev->rio_mem_size)
  114. iowrite32(v, adev->rio_mem + (reg * 4));
  115. else {
  116. iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
  117. iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
  118. }
  119. }
  120. /**
  121. * amdgpu_mm_rdoorbell - read a doorbell dword
  122. *
  123. * @adev: amdgpu_device pointer
  124. * @index: doorbell index
  125. *
  126. * Returns the value in the doorbell aperture at the
  127. * requested doorbell index (CIK).
  128. */
  129. u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
  130. {
  131. if (index < adev->doorbell.num_doorbells) {
  132. return readl(adev->doorbell.ptr + index);
  133. } else {
  134. DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
  135. return 0;
  136. }
  137. }
  138. /**
  139. * amdgpu_mm_wdoorbell - write a doorbell dword
  140. *
  141. * @adev: amdgpu_device pointer
  142. * @index: doorbell index
  143. * @v: value to write
  144. *
  145. * Writes @v to the doorbell aperture at the
  146. * requested doorbell index (CIK).
  147. */
  148. void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
  149. {
  150. if (index < adev->doorbell.num_doorbells) {
  151. writel(v, adev->doorbell.ptr + index);
  152. } else {
  153. DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
  154. }
  155. }
  156. /**
  157. * amdgpu_invalid_rreg - dummy reg read function
  158. *
  159. * @adev: amdgpu device pointer
  160. * @reg: offset of register
  161. *
  162. * Dummy register read function. Used for register blocks
  163. * that certain asics don't have (all asics).
  164. * Returns the value in the register.
  165. */
  166. static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
  167. {
  168. DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
  169. BUG();
  170. return 0;
  171. }
  172. /**
  173. * amdgpu_invalid_wreg - dummy reg write function
  174. *
  175. * @adev: amdgpu device pointer
  176. * @reg: offset of register
  177. * @v: value to write to the register
  178. *
  179. * Dummy register read function. Used for register blocks
  180. * that certain asics don't have (all asics).
  181. */
  182. static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
  183. {
  184. DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
  185. reg, v);
  186. BUG();
  187. }
  188. /**
  189. * amdgpu_block_invalid_rreg - dummy reg read function
  190. *
  191. * @adev: amdgpu device pointer
  192. * @block: offset of instance
  193. * @reg: offset of register
  194. *
  195. * Dummy register read function. Used for register blocks
  196. * that certain asics don't have (all asics).
  197. * Returns the value in the register.
  198. */
  199. static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
  200. uint32_t block, uint32_t reg)
  201. {
  202. DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
  203. reg, block);
  204. BUG();
  205. return 0;
  206. }
  207. /**
  208. * amdgpu_block_invalid_wreg - dummy reg write function
  209. *
  210. * @adev: amdgpu device pointer
  211. * @block: offset of instance
  212. * @reg: offset of register
  213. * @v: value to write to the register
  214. *
  215. * Dummy register read function. Used for register blocks
  216. * that certain asics don't have (all asics).
  217. */
  218. static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
  219. uint32_t block,
  220. uint32_t reg, uint32_t v)
  221. {
  222. DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
  223. reg, block, v);
  224. BUG();
  225. }
  226. static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
  227. {
  228. int r;
  229. if (adev->vram_scratch.robj == NULL) {
  230. r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
  231. PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
  232. AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
  233. NULL, NULL, &adev->vram_scratch.robj);
  234. if (r) {
  235. return r;
  236. }
  237. }
  238. r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
  239. if (unlikely(r != 0))
  240. return r;
  241. r = amdgpu_bo_pin(adev->vram_scratch.robj,
  242. AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr);
  243. if (r) {
  244. amdgpu_bo_unreserve(adev->vram_scratch.robj);
  245. return r;
  246. }
  247. r = amdgpu_bo_kmap(adev->vram_scratch.robj,
  248. (void **)&adev->vram_scratch.ptr);
  249. if (r)
  250. amdgpu_bo_unpin(adev->vram_scratch.robj);
  251. amdgpu_bo_unreserve(adev->vram_scratch.robj);
  252. return r;
  253. }
  254. static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
  255. {
  256. int r;
  257. if (adev->vram_scratch.robj == NULL) {
  258. return;
  259. }
  260. r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
  261. if (likely(r == 0)) {
  262. amdgpu_bo_kunmap(adev->vram_scratch.robj);
  263. amdgpu_bo_unpin(adev->vram_scratch.robj);
  264. amdgpu_bo_unreserve(adev->vram_scratch.robj);
  265. }
  266. amdgpu_bo_unref(&adev->vram_scratch.robj);
  267. }
  268. /**
  269. * amdgpu_program_register_sequence - program an array of registers.
  270. *
  271. * @adev: amdgpu_device pointer
  272. * @registers: pointer to the register array
  273. * @array_size: size of the register array
  274. *
  275. * Programs an array or registers with and and or masks.
  276. * This is a helper for setting golden registers.
  277. */
  278. void amdgpu_program_register_sequence(struct amdgpu_device *adev,
  279. const u32 *registers,
  280. const u32 array_size)
  281. {
  282. u32 tmp, reg, and_mask, or_mask;
  283. int i;
  284. if (array_size % 3)
  285. return;
  286. for (i = 0; i < array_size; i +=3) {
  287. reg = registers[i + 0];
  288. and_mask = registers[i + 1];
  289. or_mask = registers[i + 2];
  290. if (and_mask == 0xffffffff) {
  291. tmp = or_mask;
  292. } else {
  293. tmp = RREG32(reg);
  294. tmp &= ~and_mask;
  295. tmp |= or_mask;
  296. }
  297. WREG32(reg, tmp);
  298. }
  299. }
  300. void amdgpu_pci_config_reset(struct amdgpu_device *adev)
  301. {
  302. pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
  303. }
  304. /*
  305. * GPU doorbell aperture helpers function.
  306. */
  307. /**
  308. * amdgpu_doorbell_init - Init doorbell driver information.
  309. *
  310. * @adev: amdgpu_device pointer
  311. *
  312. * Init doorbell driver information (CIK)
  313. * Returns 0 on success, error on failure.
  314. */
  315. static int amdgpu_doorbell_init(struct amdgpu_device *adev)
  316. {
  317. /* doorbell bar mapping */
  318. adev->doorbell.base = pci_resource_start(adev->pdev, 2);
  319. adev->doorbell.size = pci_resource_len(adev->pdev, 2);
  320. adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
  321. AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
  322. if (adev->doorbell.num_doorbells == 0)
  323. return -EINVAL;
  324. adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32));
  325. if (adev->doorbell.ptr == NULL) {
  326. return -ENOMEM;
  327. }
  328. DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base);
  329. DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size);
  330. return 0;
  331. }
  332. /**
  333. * amdgpu_doorbell_fini - Tear down doorbell driver information.
  334. *
  335. * @adev: amdgpu_device pointer
  336. *
  337. * Tear down doorbell driver information (CIK)
  338. */
  339. static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
  340. {
  341. iounmap(adev->doorbell.ptr);
  342. adev->doorbell.ptr = NULL;
  343. }
  344. /**
  345. * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
  346. * setup amdkfd
  347. *
  348. * @adev: amdgpu_device pointer
  349. * @aperture_base: output returning doorbell aperture base physical address
  350. * @aperture_size: output returning doorbell aperture size in bytes
  351. * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
  352. *
  353. * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
  354. * takes doorbells required for its own rings and reports the setup to amdkfd.
  355. * amdgpu reserved doorbells are at the start of the doorbell aperture.
  356. */
  357. void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
  358. phys_addr_t *aperture_base,
  359. size_t *aperture_size,
  360. size_t *start_offset)
  361. {
  362. /*
  363. * The first num_doorbells are used by amdgpu.
  364. * amdkfd takes whatever's left in the aperture.
  365. */
  366. if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
  367. *aperture_base = adev->doorbell.base;
  368. *aperture_size = adev->doorbell.size;
  369. *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
  370. } else {
  371. *aperture_base = 0;
  372. *aperture_size = 0;
  373. *start_offset = 0;
  374. }
  375. }
  376. /*
  377. * amdgpu_wb_*()
  378. * Writeback is the the method by which the the GPU updates special pages
  379. * in memory with the status of certain GPU events (fences, ring pointers,
  380. * etc.).
  381. */
  382. /**
  383. * amdgpu_wb_fini - Disable Writeback and free memory
  384. *
  385. * @adev: amdgpu_device pointer
  386. *
  387. * Disables Writeback and frees the Writeback memory (all asics).
  388. * Used at driver shutdown.
  389. */
  390. static void amdgpu_wb_fini(struct amdgpu_device *adev)
  391. {
  392. if (adev->wb.wb_obj) {
  393. if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) {
  394. amdgpu_bo_kunmap(adev->wb.wb_obj);
  395. amdgpu_bo_unpin(adev->wb.wb_obj);
  396. amdgpu_bo_unreserve(adev->wb.wb_obj);
  397. }
  398. amdgpu_bo_unref(&adev->wb.wb_obj);
  399. adev->wb.wb = NULL;
  400. adev->wb.wb_obj = NULL;
  401. }
  402. }
  403. /**
  404. * amdgpu_wb_init- Init Writeback driver info and allocate memory
  405. *
  406. * @adev: amdgpu_device pointer
  407. *
  408. * Disables Writeback and frees the Writeback memory (all asics).
  409. * Used at driver startup.
  410. * Returns 0 on success or an -error on failure.
  411. */
  412. static int amdgpu_wb_init(struct amdgpu_device *adev)
  413. {
  414. int r;
  415. if (adev->wb.wb_obj == NULL) {
  416. r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true,
  417. AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
  418. &adev->wb.wb_obj);
  419. if (r) {
  420. dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
  421. return r;
  422. }
  423. r = amdgpu_bo_reserve(adev->wb.wb_obj, false);
  424. if (unlikely(r != 0)) {
  425. amdgpu_wb_fini(adev);
  426. return r;
  427. }
  428. r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT,
  429. &adev->wb.gpu_addr);
  430. if (r) {
  431. amdgpu_bo_unreserve(adev->wb.wb_obj);
  432. dev_warn(adev->dev, "(%d) pin WB bo failed\n", r);
  433. amdgpu_wb_fini(adev);
  434. return r;
  435. }
  436. r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)&adev->wb.wb);
  437. amdgpu_bo_unreserve(adev->wb.wb_obj);
  438. if (r) {
  439. dev_warn(adev->dev, "(%d) map WB bo failed\n", r);
  440. amdgpu_wb_fini(adev);
  441. return r;
  442. }
  443. adev->wb.num_wb = AMDGPU_MAX_WB;
  444. memset(&adev->wb.used, 0, sizeof(adev->wb.used));
  445. /* clear wb memory */
  446. memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE);
  447. }
  448. return 0;
  449. }
  450. /**
  451. * amdgpu_wb_get - Allocate a wb entry
  452. *
  453. * @adev: amdgpu_device pointer
  454. * @wb: wb index
  455. *
  456. * Allocate a wb slot for use by the driver (all asics).
  457. * Returns 0 on success or -EINVAL on failure.
  458. */
  459. int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
  460. {
  461. unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
  462. if (offset < adev->wb.num_wb) {
  463. __set_bit(offset, adev->wb.used);
  464. *wb = offset;
  465. return 0;
  466. } else {
  467. return -EINVAL;
  468. }
  469. }
  470. /**
  471. * amdgpu_wb_free - Free a wb entry
  472. *
  473. * @adev: amdgpu_device pointer
  474. * @wb: wb index
  475. *
  476. * Free a wb slot allocated for use by the driver (all asics)
  477. */
  478. void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
  479. {
  480. if (wb < adev->wb.num_wb)
  481. __clear_bit(wb, adev->wb.used);
  482. }
  483. /**
  484. * amdgpu_vram_location - try to find VRAM location
  485. * @adev: amdgpu device structure holding all necessary informations
  486. * @mc: memory controller structure holding memory informations
  487. * @base: base address at which to put VRAM
  488. *
  489. * Function will place try to place VRAM at base address provided
  490. * as parameter (which is so far either PCI aperture address or
  491. * for IGP TOM base address).
  492. *
  493. * If there is not enough space to fit the unvisible VRAM in the 32bits
  494. * address space then we limit the VRAM size to the aperture.
  495. *
  496. * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
  497. * this shouldn't be a problem as we are using the PCI aperture as a reference.
  498. * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
  499. * not IGP.
  500. *
  501. * Note: we use mc_vram_size as on some board we need to program the mc to
  502. * cover the whole aperture even if VRAM size is inferior to aperture size
  503. * Novell bug 204882 + along with lots of ubuntu ones
  504. *
  505. * Note: when limiting vram it's safe to overwritte real_vram_size because
  506. * we are not in case where real_vram_size is inferior to mc_vram_size (ie
  507. * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
  508. * ones)
  509. *
  510. * Note: IGP TOM addr should be the same as the aperture addr, we don't
  511. * explicitly check for that thought.
  512. *
  513. * FIXME: when reducing VRAM size align new size on power of 2.
  514. */
  515. void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
  516. {
  517. uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
  518. mc->vram_start = base;
  519. if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
  520. dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
  521. mc->real_vram_size = mc->aper_size;
  522. mc->mc_vram_size = mc->aper_size;
  523. }
  524. mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
  525. if (limit && limit < mc->real_vram_size)
  526. mc->real_vram_size = limit;
  527. dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
  528. mc->mc_vram_size >> 20, mc->vram_start,
  529. mc->vram_end, mc->real_vram_size >> 20);
  530. }
  531. /**
  532. * amdgpu_gtt_location - try to find GTT location
  533. * @adev: amdgpu device structure holding all necessary informations
  534. * @mc: memory controller structure holding memory informations
  535. *
  536. * Function will place try to place GTT before or after VRAM.
  537. *
  538. * If GTT size is bigger than space left then we ajust GTT size.
  539. * Thus function will never fails.
  540. *
  541. * FIXME: when reducing GTT size align new size on power of 2.
  542. */
  543. void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
  544. {
  545. u64 size_af, size_bf;
  546. size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
  547. size_bf = mc->vram_start & ~mc->gtt_base_align;
  548. if (size_bf > size_af) {
  549. if (mc->gtt_size > size_bf) {
  550. dev_warn(adev->dev, "limiting GTT\n");
  551. mc->gtt_size = size_bf;
  552. }
  553. mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
  554. } else {
  555. if (mc->gtt_size > size_af) {
  556. dev_warn(adev->dev, "limiting GTT\n");
  557. mc->gtt_size = size_af;
  558. }
  559. mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
  560. }
  561. mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
  562. dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
  563. mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
  564. }
  565. /*
  566. * GPU helpers function.
  567. */
  568. /**
  569. * amdgpu_card_posted - check if the hw has already been initialized
  570. *
  571. * @adev: amdgpu_device pointer
  572. *
  573. * Check if the asic has been initialized (all asics).
  574. * Used at driver startup.
  575. * Returns true if initialized or false if not.
  576. */
  577. bool amdgpu_card_posted(struct amdgpu_device *adev)
  578. {
  579. uint32_t reg;
  580. /* then check MEM_SIZE, in case the crtcs are off */
  581. reg = RREG32(mmCONFIG_MEMSIZE);
  582. if (reg)
  583. return true;
  584. return false;
  585. }
  586. /**
  587. * amdgpu_dummy_page_init - init dummy page used by the driver
  588. *
  589. * @adev: amdgpu_device pointer
  590. *
  591. * Allocate the dummy page used by the driver (all asics).
  592. * This dummy page is used by the driver as a filler for gart entries
  593. * when pages are taken out of the GART
  594. * Returns 0 on sucess, -ENOMEM on failure.
  595. */
  596. int amdgpu_dummy_page_init(struct amdgpu_device *adev)
  597. {
  598. if (adev->dummy_page.page)
  599. return 0;
  600. adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
  601. if (adev->dummy_page.page == NULL)
  602. return -ENOMEM;
  603. adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
  604. 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
  605. if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
  606. dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
  607. __free_page(adev->dummy_page.page);
  608. adev->dummy_page.page = NULL;
  609. return -ENOMEM;
  610. }
  611. return 0;
  612. }
  613. /**
  614. * amdgpu_dummy_page_fini - free dummy page used by the driver
  615. *
  616. * @adev: amdgpu_device pointer
  617. *
  618. * Frees the dummy page used by the driver (all asics).
  619. */
  620. void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
  621. {
  622. if (adev->dummy_page.page == NULL)
  623. return;
  624. pci_unmap_page(adev->pdev, adev->dummy_page.addr,
  625. PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
  626. __free_page(adev->dummy_page.page);
  627. adev->dummy_page.page = NULL;
  628. }
  629. /* ATOM accessor methods */
  630. /*
  631. * ATOM is an interpreted byte code stored in tables in the vbios. The
  632. * driver registers callbacks to access registers and the interpreter
  633. * in the driver parses the tables and executes then to program specific
  634. * actions (set display modes, asic init, etc.). See amdgpu_atombios.c,
  635. * atombios.h, and atom.c
  636. */
  637. /**
  638. * cail_pll_read - read PLL register
  639. *
  640. * @info: atom card_info pointer
  641. * @reg: PLL register offset
  642. *
  643. * Provides a PLL register accessor for the atom interpreter (r4xx+).
  644. * Returns the value of the PLL register.
  645. */
  646. static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
  647. {
  648. return 0;
  649. }
  650. /**
  651. * cail_pll_write - write PLL register
  652. *
  653. * @info: atom card_info pointer
  654. * @reg: PLL register offset
  655. * @val: value to write to the pll register
  656. *
  657. * Provides a PLL register accessor for the atom interpreter (r4xx+).
  658. */
  659. static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
  660. {
  661. }
  662. /**
  663. * cail_mc_read - read MC (Memory Controller) register
  664. *
  665. * @info: atom card_info pointer
  666. * @reg: MC register offset
  667. *
  668. * Provides an MC register accessor for the atom interpreter (r4xx+).
  669. * Returns the value of the MC register.
  670. */
  671. static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
  672. {
  673. return 0;
  674. }
  675. /**
  676. * cail_mc_write - write MC (Memory Controller) register
  677. *
  678. * @info: atom card_info pointer
  679. * @reg: MC register offset
  680. * @val: value to write to the pll register
  681. *
  682. * Provides a MC register accessor for the atom interpreter (r4xx+).
  683. */
  684. static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
  685. {
  686. }
  687. /**
  688. * cail_reg_write - write MMIO register
  689. *
  690. * @info: atom card_info pointer
  691. * @reg: MMIO register offset
  692. * @val: value to write to the pll register
  693. *
  694. * Provides a MMIO register accessor for the atom interpreter (r4xx+).
  695. */
  696. static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
  697. {
  698. struct amdgpu_device *adev = info->dev->dev_private;
  699. WREG32(reg, val);
  700. }
  701. /**
  702. * cail_reg_read - read MMIO register
  703. *
  704. * @info: atom card_info pointer
  705. * @reg: MMIO register offset
  706. *
  707. * Provides an MMIO register accessor for the atom interpreter (r4xx+).
  708. * Returns the value of the MMIO register.
  709. */
  710. static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
  711. {
  712. struct amdgpu_device *adev = info->dev->dev_private;
  713. uint32_t r;
  714. r = RREG32(reg);
  715. return r;
  716. }
  717. /**
  718. * cail_ioreg_write - write IO register
  719. *
  720. * @info: atom card_info pointer
  721. * @reg: IO register offset
  722. * @val: value to write to the pll register
  723. *
  724. * Provides a IO register accessor for the atom interpreter (r4xx+).
  725. */
  726. static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
  727. {
  728. struct amdgpu_device *adev = info->dev->dev_private;
  729. WREG32_IO(reg, val);
  730. }
  731. /**
  732. * cail_ioreg_read - read IO register
  733. *
  734. * @info: atom card_info pointer
  735. * @reg: IO register offset
  736. *
  737. * Provides an IO register accessor for the atom interpreter (r4xx+).
  738. * Returns the value of the IO register.
  739. */
  740. static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
  741. {
  742. struct amdgpu_device *adev = info->dev->dev_private;
  743. uint32_t r;
  744. r = RREG32_IO(reg);
  745. return r;
  746. }
  747. /**
  748. * amdgpu_atombios_fini - free the driver info and callbacks for atombios
  749. *
  750. * @adev: amdgpu_device pointer
  751. *
  752. * Frees the driver info and register access callbacks for the ATOM
  753. * interpreter (r4xx+).
  754. * Called at driver shutdown.
  755. */
  756. static void amdgpu_atombios_fini(struct amdgpu_device *adev)
  757. {
  758. if (adev->mode_info.atom_context)
  759. kfree(adev->mode_info.atom_context->scratch);
  760. kfree(adev->mode_info.atom_context);
  761. adev->mode_info.atom_context = NULL;
  762. kfree(adev->mode_info.atom_card_info);
  763. adev->mode_info.atom_card_info = NULL;
  764. }
  765. /**
  766. * amdgpu_atombios_init - init the driver info and callbacks for atombios
  767. *
  768. * @adev: amdgpu_device pointer
  769. *
  770. * Initializes the driver info and register access callbacks for the
  771. * ATOM interpreter (r4xx+).
  772. * Returns 0 on sucess, -ENOMEM on failure.
  773. * Called at driver startup.
  774. */
  775. static int amdgpu_atombios_init(struct amdgpu_device *adev)
  776. {
  777. struct card_info *atom_card_info =
  778. kzalloc(sizeof(struct card_info), GFP_KERNEL);
  779. if (!atom_card_info)
  780. return -ENOMEM;
  781. adev->mode_info.atom_card_info = atom_card_info;
  782. atom_card_info->dev = adev->ddev;
  783. atom_card_info->reg_read = cail_reg_read;
  784. atom_card_info->reg_write = cail_reg_write;
  785. /* needed for iio ops */
  786. if (adev->rio_mem) {
  787. atom_card_info->ioreg_read = cail_ioreg_read;
  788. atom_card_info->ioreg_write = cail_ioreg_write;
  789. } else {
  790. DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
  791. atom_card_info->ioreg_read = cail_reg_read;
  792. atom_card_info->ioreg_write = cail_reg_write;
  793. }
  794. atom_card_info->mc_read = cail_mc_read;
  795. atom_card_info->mc_write = cail_mc_write;
  796. atom_card_info->pll_read = cail_pll_read;
  797. atom_card_info->pll_write = cail_pll_write;
  798. adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
  799. if (!adev->mode_info.atom_context) {
  800. amdgpu_atombios_fini(adev);
  801. return -ENOMEM;
  802. }
  803. mutex_init(&adev->mode_info.atom_context->mutex);
  804. amdgpu_atombios_scratch_regs_init(adev);
  805. amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context);
  806. return 0;
  807. }
  808. /* if we get transitioned to only one device, take VGA back */
  809. /**
  810. * amdgpu_vga_set_decode - enable/disable vga decode
  811. *
  812. * @cookie: amdgpu_device pointer
  813. * @state: enable/disable vga decode
  814. *
  815. * Enable/disable vga decode (all asics).
  816. * Returns VGA resource flags.
  817. */
  818. static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
  819. {
  820. struct amdgpu_device *adev = cookie;
  821. amdgpu_asic_set_vga_state(adev, state);
  822. if (state)
  823. return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
  824. VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  825. else
  826. return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  827. }
  828. /**
  829. * amdgpu_check_pot_argument - check that argument is a power of two
  830. *
  831. * @arg: value to check
  832. *
  833. * Validates that a certain argument is a power of two (all asics).
  834. * Returns true if argument is valid.
  835. */
  836. static bool amdgpu_check_pot_argument(int arg)
  837. {
  838. return (arg & (arg - 1)) == 0;
  839. }
  840. /**
  841. * amdgpu_check_arguments - validate module params
  842. *
  843. * @adev: amdgpu_device pointer
  844. *
  845. * Validates certain module parameters and updates
  846. * the associated values used by the driver (all asics).
  847. */
  848. static void amdgpu_check_arguments(struct amdgpu_device *adev)
  849. {
  850. if (amdgpu_sched_jobs < 4) {
  851. dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
  852. amdgpu_sched_jobs);
  853. amdgpu_sched_jobs = 4;
  854. } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){
  855. dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
  856. amdgpu_sched_jobs);
  857. amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
  858. }
  859. if (amdgpu_gart_size != -1) {
  860. /* gtt size must be greater or equal to 32M */
  861. if (amdgpu_gart_size < 32) {
  862. dev_warn(adev->dev, "gart size (%d) too small\n",
  863. amdgpu_gart_size);
  864. amdgpu_gart_size = -1;
  865. }
  866. }
  867. if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
  868. dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
  869. amdgpu_vm_size);
  870. amdgpu_vm_size = 8;
  871. }
  872. if (amdgpu_vm_size < 1) {
  873. dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
  874. amdgpu_vm_size);
  875. amdgpu_vm_size = 8;
  876. }
  877. /*
  878. * Max GPUVM size for Cayman, SI and CI are 40 bits.
  879. */
  880. if (amdgpu_vm_size > 1024) {
  881. dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
  882. amdgpu_vm_size);
  883. amdgpu_vm_size = 8;
  884. }
  885. /* defines number of bits in page table versus page directory,
  886. * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
  887. * page table and the remaining bits are in the page directory */
  888. if (amdgpu_vm_block_size == -1) {
  889. /* Total bits covered by PD + PTs */
  890. unsigned bits = ilog2(amdgpu_vm_size) + 18;
  891. /* Make sure the PD is 4K in size up to 8GB address space.
  892. Above that split equal between PD and PTs */
  893. if (amdgpu_vm_size <= 8)
  894. amdgpu_vm_block_size = bits - 9;
  895. else
  896. amdgpu_vm_block_size = (bits + 3) / 2;
  897. } else if (amdgpu_vm_block_size < 9) {
  898. dev_warn(adev->dev, "VM page table size (%d) too small\n",
  899. amdgpu_vm_block_size);
  900. amdgpu_vm_block_size = 9;
  901. }
  902. if (amdgpu_vm_block_size > 24 ||
  903. (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
  904. dev_warn(adev->dev, "VM page table size (%d) too large\n",
  905. amdgpu_vm_block_size);
  906. amdgpu_vm_block_size = 9;
  907. }
  908. }
  909. /**
  910. * amdgpu_switcheroo_set_state - set switcheroo state
  911. *
  912. * @pdev: pci dev pointer
  913. * @state: vga_switcheroo state
  914. *
  915. * Callback for the switcheroo driver. Suspends or resumes the
  916. * the asics before or after it is powered up using ACPI methods.
  917. */
  918. static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
  919. {
  920. struct drm_device *dev = pci_get_drvdata(pdev);
  921. if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
  922. return;
  923. if (state == VGA_SWITCHEROO_ON) {
  924. unsigned d3_delay = dev->pdev->d3_delay;
  925. printk(KERN_INFO "amdgpu: switched on\n");
  926. /* don't suspend or resume card normally */
  927. dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
  928. amdgpu_resume_kms(dev, true, true);
  929. dev->pdev->d3_delay = d3_delay;
  930. dev->switch_power_state = DRM_SWITCH_POWER_ON;
  931. drm_kms_helper_poll_enable(dev);
  932. } else {
  933. printk(KERN_INFO "amdgpu: switched off\n");
  934. drm_kms_helper_poll_disable(dev);
  935. dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
  936. amdgpu_suspend_kms(dev, true, true);
  937. dev->switch_power_state = DRM_SWITCH_POWER_OFF;
  938. }
  939. }
  940. /**
  941. * amdgpu_switcheroo_can_switch - see if switcheroo state can change
  942. *
  943. * @pdev: pci dev pointer
  944. *
  945. * Callback for the switcheroo driver. Check of the switcheroo
  946. * state can be changed.
  947. * Returns true if the state can be changed, false if not.
  948. */
  949. static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
  950. {
  951. struct drm_device *dev = pci_get_drvdata(pdev);
  952. /*
  953. * FIXME: open_count is protected by drm_global_mutex but that would lead to
  954. * locking inversion with the driver load path. And the access here is
  955. * completely racy anyway. So don't bother with locking for now.
  956. */
  957. return dev->open_count == 0;
  958. }
  959. static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
  960. .set_gpu_state = amdgpu_switcheroo_set_state,
  961. .reprobe = NULL,
  962. .can_switch = amdgpu_switcheroo_can_switch,
  963. };
  964. int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
  965. enum amd_ip_block_type block_type,
  966. enum amd_clockgating_state state)
  967. {
  968. int i, r = 0;
  969. for (i = 0; i < adev->num_ip_blocks; i++) {
  970. if (adev->ip_blocks[i].type == block_type) {
  971. r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
  972. state);
  973. if (r)
  974. return r;
  975. }
  976. }
  977. return r;
  978. }
  979. int amdgpu_set_powergating_state(struct amdgpu_device *adev,
  980. enum amd_ip_block_type block_type,
  981. enum amd_powergating_state state)
  982. {
  983. int i, r = 0;
  984. for (i = 0; i < adev->num_ip_blocks; i++) {
  985. if (adev->ip_blocks[i].type == block_type) {
  986. r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev,
  987. state);
  988. if (r)
  989. return r;
  990. }
  991. }
  992. return r;
  993. }
  994. const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
  995. struct amdgpu_device *adev,
  996. enum amd_ip_block_type type)
  997. {
  998. int i;
  999. for (i = 0; i < adev->num_ip_blocks; i++)
  1000. if (adev->ip_blocks[i].type == type)
  1001. return &adev->ip_blocks[i];
  1002. return NULL;
  1003. }
  1004. /**
  1005. * amdgpu_ip_block_version_cmp
  1006. *
  1007. * @adev: amdgpu_device pointer
  1008. * @type: enum amd_ip_block_type
  1009. * @major: major version
  1010. * @minor: minor version
  1011. *
  1012. * return 0 if equal or greater
  1013. * return 1 if smaller or the ip_block doesn't exist
  1014. */
  1015. int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
  1016. enum amd_ip_block_type type,
  1017. u32 major, u32 minor)
  1018. {
  1019. const struct amdgpu_ip_block_version *ip_block;
  1020. ip_block = amdgpu_get_ip_block(adev, type);
  1021. if (ip_block && ((ip_block->major > major) ||
  1022. ((ip_block->major == major) &&
  1023. (ip_block->minor >= minor))))
  1024. return 0;
  1025. return 1;
  1026. }
  1027. static int amdgpu_early_init(struct amdgpu_device *adev)
  1028. {
  1029. int i, r;
  1030. switch (adev->asic_type) {
  1031. case CHIP_TOPAZ:
  1032. case CHIP_TONGA:
  1033. case CHIP_FIJI:
  1034. case CHIP_POLARIS11:
  1035. case CHIP_POLARIS10:
  1036. case CHIP_CARRIZO:
  1037. case CHIP_STONEY:
  1038. if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
  1039. adev->family = AMDGPU_FAMILY_CZ;
  1040. else
  1041. adev->family = AMDGPU_FAMILY_VI;
  1042. r = vi_set_ip_blocks(adev);
  1043. if (r)
  1044. return r;
  1045. break;
  1046. #ifdef CONFIG_DRM_AMDGPU_CIK
  1047. case CHIP_BONAIRE:
  1048. case CHIP_HAWAII:
  1049. case CHIP_KAVERI:
  1050. case CHIP_KABINI:
  1051. case CHIP_MULLINS:
  1052. if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
  1053. adev->family = AMDGPU_FAMILY_CI;
  1054. else
  1055. adev->family = AMDGPU_FAMILY_KV;
  1056. r = cik_set_ip_blocks(adev);
  1057. if (r)
  1058. return r;
  1059. break;
  1060. #endif
  1061. default:
  1062. /* FIXME: not supported yet */
  1063. return -EINVAL;
  1064. }
  1065. adev->ip_block_status = kcalloc(adev->num_ip_blocks,
  1066. sizeof(struct amdgpu_ip_block_status), GFP_KERNEL);
  1067. if (adev->ip_block_status == NULL)
  1068. return -ENOMEM;
  1069. if (adev->ip_blocks == NULL) {
  1070. DRM_ERROR("No IP blocks found!\n");
  1071. return r;
  1072. }
  1073. for (i = 0; i < adev->num_ip_blocks; i++) {
  1074. if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
  1075. DRM_ERROR("disabled ip block: %d\n", i);
  1076. adev->ip_block_status[i].valid = false;
  1077. } else {
  1078. if (adev->ip_blocks[i].funcs->early_init) {
  1079. r = adev->ip_blocks[i].funcs->early_init((void *)adev);
  1080. if (r == -ENOENT) {
  1081. adev->ip_block_status[i].valid = false;
  1082. } else if (r) {
  1083. DRM_ERROR("early_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
  1084. return r;
  1085. } else {
  1086. adev->ip_block_status[i].valid = true;
  1087. }
  1088. } else {
  1089. adev->ip_block_status[i].valid = true;
  1090. }
  1091. }
  1092. }
  1093. return 0;
  1094. }
  1095. static int amdgpu_init(struct amdgpu_device *adev)
  1096. {
  1097. int i, r;
  1098. for (i = 0; i < adev->num_ip_blocks; i++) {
  1099. if (!adev->ip_block_status[i].valid)
  1100. continue;
  1101. r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
  1102. if (r) {
  1103. DRM_ERROR("sw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
  1104. return r;
  1105. }
  1106. adev->ip_block_status[i].sw = true;
  1107. /* need to do gmc hw init early so we can allocate gpu mem */
  1108. if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
  1109. r = amdgpu_vram_scratch_init(adev);
  1110. if (r) {
  1111. DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
  1112. return r;
  1113. }
  1114. r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
  1115. if (r) {
  1116. DRM_ERROR("hw_init %d failed %d\n", i, r);
  1117. return r;
  1118. }
  1119. r = amdgpu_wb_init(adev);
  1120. if (r) {
  1121. DRM_ERROR("amdgpu_wb_init failed %d\n", r);
  1122. return r;
  1123. }
  1124. adev->ip_block_status[i].hw = true;
  1125. }
  1126. }
  1127. for (i = 0; i < adev->num_ip_blocks; i++) {
  1128. if (!adev->ip_block_status[i].sw)
  1129. continue;
  1130. /* gmc hw init is done early */
  1131. if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)
  1132. continue;
  1133. r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
  1134. if (r) {
  1135. DRM_ERROR("hw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
  1136. return r;
  1137. }
  1138. adev->ip_block_status[i].hw = true;
  1139. }
  1140. return 0;
  1141. }
  1142. static int amdgpu_late_init(struct amdgpu_device *adev)
  1143. {
  1144. int i = 0, r;
  1145. for (i = 0; i < adev->num_ip_blocks; i++) {
  1146. if (!adev->ip_block_status[i].valid)
  1147. continue;
  1148. /* enable clockgating to save power */
  1149. r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
  1150. AMD_CG_STATE_GATE);
  1151. if (r) {
  1152. DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
  1153. return r;
  1154. }
  1155. if (adev->ip_blocks[i].funcs->late_init) {
  1156. r = adev->ip_blocks[i].funcs->late_init((void *)adev);
  1157. if (r) {
  1158. DRM_ERROR("late_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
  1159. return r;
  1160. }
  1161. }
  1162. }
  1163. return 0;
  1164. }
  1165. static int amdgpu_fini(struct amdgpu_device *adev)
  1166. {
  1167. int i, r;
  1168. for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
  1169. if (!adev->ip_block_status[i].hw)
  1170. continue;
  1171. if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
  1172. amdgpu_wb_fini(adev);
  1173. amdgpu_vram_scratch_fini(adev);
  1174. }
  1175. /* ungate blocks before hw fini so that we can shutdown the blocks safely */
  1176. r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
  1177. AMD_CG_STATE_UNGATE);
  1178. if (r) {
  1179. DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
  1180. return r;
  1181. }
  1182. r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
  1183. /* XXX handle errors */
  1184. if (r) {
  1185. DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
  1186. }
  1187. adev->ip_block_status[i].hw = false;
  1188. }
  1189. for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
  1190. if (!adev->ip_block_status[i].sw)
  1191. continue;
  1192. r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
  1193. /* XXX handle errors */
  1194. if (r) {
  1195. DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
  1196. }
  1197. adev->ip_block_status[i].sw = false;
  1198. adev->ip_block_status[i].valid = false;
  1199. }
  1200. for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
  1201. if (adev->ip_blocks[i].funcs->late_fini)
  1202. adev->ip_blocks[i].funcs->late_fini((void *)adev);
  1203. }
  1204. return 0;
  1205. }
  1206. static int amdgpu_suspend(struct amdgpu_device *adev)
  1207. {
  1208. int i, r;
  1209. /* ungate SMC block first */
  1210. r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
  1211. AMD_CG_STATE_UNGATE);
  1212. if (r) {
  1213. DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
  1214. }
  1215. for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
  1216. if (!adev->ip_block_status[i].valid)
  1217. continue;
  1218. /* ungate blocks so that suspend can properly shut them down */
  1219. if (i != AMD_IP_BLOCK_TYPE_SMC) {
  1220. r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
  1221. AMD_CG_STATE_UNGATE);
  1222. if (r) {
  1223. DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
  1224. }
  1225. }
  1226. /* XXX handle errors */
  1227. r = adev->ip_blocks[i].funcs->suspend(adev);
  1228. /* XXX handle errors */
  1229. if (r) {
  1230. DRM_ERROR("suspend of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
  1231. }
  1232. }
  1233. return 0;
  1234. }
  1235. static int amdgpu_resume(struct amdgpu_device *adev)
  1236. {
  1237. int i, r;
  1238. for (i = 0; i < adev->num_ip_blocks; i++) {
  1239. if (!adev->ip_block_status[i].valid)
  1240. continue;
  1241. r = adev->ip_blocks[i].funcs->resume(adev);
  1242. if (r) {
  1243. DRM_ERROR("resume of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
  1244. return r;
  1245. }
  1246. }
  1247. return 0;
  1248. }
  1249. /**
  1250. * amdgpu_device_init - initialize the driver
  1251. *
  1252. * @adev: amdgpu_device pointer
  1253. * @pdev: drm dev pointer
  1254. * @pdev: pci dev pointer
  1255. * @flags: driver flags
  1256. *
  1257. * Initializes the driver info and hw (all asics).
  1258. * Returns 0 for success or an error on failure.
  1259. * Called at driver startup.
  1260. */
  1261. int amdgpu_device_init(struct amdgpu_device *adev,
  1262. struct drm_device *ddev,
  1263. struct pci_dev *pdev,
  1264. uint32_t flags)
  1265. {
  1266. int r, i;
  1267. bool runtime = false;
  1268. adev->shutdown = false;
  1269. adev->dev = &pdev->dev;
  1270. adev->ddev = ddev;
  1271. adev->pdev = pdev;
  1272. adev->flags = flags;
  1273. adev->asic_type = flags & AMD_ASIC_MASK;
  1274. adev->is_atom_bios = false;
  1275. adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
  1276. adev->mc.gtt_size = 512 * 1024 * 1024;
  1277. adev->accel_working = false;
  1278. adev->num_rings = 0;
  1279. adev->mman.buffer_funcs = NULL;
  1280. adev->mman.buffer_funcs_ring = NULL;
  1281. adev->vm_manager.vm_pte_funcs = NULL;
  1282. adev->vm_manager.vm_pte_num_rings = 0;
  1283. adev->gart.gart_funcs = NULL;
  1284. adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
  1285. adev->smc_rreg = &amdgpu_invalid_rreg;
  1286. adev->smc_wreg = &amdgpu_invalid_wreg;
  1287. adev->pcie_rreg = &amdgpu_invalid_rreg;
  1288. adev->pcie_wreg = &amdgpu_invalid_wreg;
  1289. adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
  1290. adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
  1291. adev->didt_rreg = &amdgpu_invalid_rreg;
  1292. adev->didt_wreg = &amdgpu_invalid_wreg;
  1293. adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
  1294. adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
  1295. DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
  1296. amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
  1297. pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
  1298. /* mutex initialization are all done here so we
  1299. * can recall function without having locking issues */
  1300. mutex_init(&adev->vm_manager.lock);
  1301. atomic_set(&adev->irq.ih.lock, 0);
  1302. mutex_init(&adev->pm.mutex);
  1303. mutex_init(&adev->gfx.gpu_clock_mutex);
  1304. mutex_init(&adev->srbm_mutex);
  1305. mutex_init(&adev->grbm_idx_mutex);
  1306. mutex_init(&adev->mn_lock);
  1307. hash_init(adev->mn_hash);
  1308. amdgpu_check_arguments(adev);
  1309. /* Registers mapping */
  1310. /* TODO: block userspace mapping of io register */
  1311. spin_lock_init(&adev->mmio_idx_lock);
  1312. spin_lock_init(&adev->smc_idx_lock);
  1313. spin_lock_init(&adev->pcie_idx_lock);
  1314. spin_lock_init(&adev->uvd_ctx_idx_lock);
  1315. spin_lock_init(&adev->didt_idx_lock);
  1316. spin_lock_init(&adev->audio_endpt_idx_lock);
  1317. adev->rmmio_base = pci_resource_start(adev->pdev, 5);
  1318. adev->rmmio_size = pci_resource_len(adev->pdev, 5);
  1319. adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
  1320. if (adev->rmmio == NULL) {
  1321. return -ENOMEM;
  1322. }
  1323. DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
  1324. DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
  1325. /* doorbell bar mapping */
  1326. amdgpu_doorbell_init(adev);
  1327. /* io port mapping */
  1328. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  1329. if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
  1330. adev->rio_mem_size = pci_resource_len(adev->pdev, i);
  1331. adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
  1332. break;
  1333. }
  1334. }
  1335. if (adev->rio_mem == NULL)
  1336. DRM_ERROR("Unable to find PCI I/O BAR\n");
  1337. /* early init functions */
  1338. r = amdgpu_early_init(adev);
  1339. if (r)
  1340. return r;
  1341. /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
  1342. /* this will fail for cards that aren't VGA class devices, just
  1343. * ignore it */
  1344. vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
  1345. if (amdgpu_runtime_pm == 1)
  1346. runtime = true;
  1347. if (amdgpu_device_is_px(ddev))
  1348. runtime = true;
  1349. vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime);
  1350. if (runtime)
  1351. vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
  1352. /* Read BIOS */
  1353. if (!amdgpu_get_bios(adev))
  1354. return -EINVAL;
  1355. /* Must be an ATOMBIOS */
  1356. if (!adev->is_atom_bios) {
  1357. dev_err(adev->dev, "Expecting atombios for GPU\n");
  1358. return -EINVAL;
  1359. }
  1360. r = amdgpu_atombios_init(adev);
  1361. if (r) {
  1362. dev_err(adev->dev, "amdgpu_atombios_init failed\n");
  1363. return r;
  1364. }
  1365. /* See if the asic supports SR-IOV */
  1366. adev->virtualization.supports_sr_iov =
  1367. amdgpu_atombios_has_gpu_virtualization_table(adev);
  1368. /* Post card if necessary */
  1369. if (!amdgpu_card_posted(adev)) {
  1370. if (!adev->bios) {
  1371. dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
  1372. return -EINVAL;
  1373. }
  1374. DRM_INFO("GPU not posted. posting now...\n");
  1375. amdgpu_atom_asic_init(adev->mode_info.atom_context);
  1376. }
  1377. /* Initialize clocks */
  1378. r = amdgpu_atombios_get_clock_info(adev);
  1379. if (r) {
  1380. dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
  1381. return r;
  1382. }
  1383. /* init i2c buses */
  1384. amdgpu_atombios_i2c_init(adev);
  1385. /* Fence driver */
  1386. r = amdgpu_fence_driver_init(adev);
  1387. if (r) {
  1388. dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
  1389. return r;
  1390. }
  1391. /* init the mode config */
  1392. drm_mode_config_init(adev->ddev);
  1393. r = amdgpu_init(adev);
  1394. if (r) {
  1395. dev_err(adev->dev, "amdgpu_init failed\n");
  1396. amdgpu_fini(adev);
  1397. return r;
  1398. }
  1399. adev->accel_working = true;
  1400. amdgpu_fbdev_init(adev);
  1401. r = amdgpu_ib_pool_init(adev);
  1402. if (r) {
  1403. dev_err(adev->dev, "IB initialization failed (%d).\n", r);
  1404. return r;
  1405. }
  1406. r = amdgpu_ib_ring_tests(adev);
  1407. if (r)
  1408. DRM_ERROR("ib ring test failed (%d).\n", r);
  1409. r = amdgpu_gem_debugfs_init(adev);
  1410. if (r) {
  1411. DRM_ERROR("registering gem debugfs failed (%d).\n", r);
  1412. }
  1413. r = amdgpu_debugfs_regs_init(adev);
  1414. if (r) {
  1415. DRM_ERROR("registering register debugfs failed (%d).\n", r);
  1416. }
  1417. if ((amdgpu_testing & 1)) {
  1418. if (adev->accel_working)
  1419. amdgpu_test_moves(adev);
  1420. else
  1421. DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
  1422. }
  1423. if ((amdgpu_testing & 2)) {
  1424. if (adev->accel_working)
  1425. amdgpu_test_syncing(adev);
  1426. else
  1427. DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n");
  1428. }
  1429. if (amdgpu_benchmarking) {
  1430. if (adev->accel_working)
  1431. amdgpu_benchmark(adev, amdgpu_benchmarking);
  1432. else
  1433. DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
  1434. }
  1435. /* enable clockgating, etc. after ib tests, etc. since some blocks require
  1436. * explicit gating rather than handling it automatically.
  1437. */
  1438. r = amdgpu_late_init(adev);
  1439. if (r) {
  1440. dev_err(adev->dev, "amdgpu_late_init failed\n");
  1441. return r;
  1442. }
  1443. return 0;
  1444. }
  1445. static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev);
  1446. /**
  1447. * amdgpu_device_fini - tear down the driver
  1448. *
  1449. * @adev: amdgpu_device pointer
  1450. *
  1451. * Tear down the driver info (all asics).
  1452. * Called at driver shutdown.
  1453. */
  1454. void amdgpu_device_fini(struct amdgpu_device *adev)
  1455. {
  1456. int r;
  1457. DRM_INFO("amdgpu: finishing device.\n");
  1458. adev->shutdown = true;
  1459. /* evict vram memory */
  1460. amdgpu_bo_evict_vram(adev);
  1461. amdgpu_ib_pool_fini(adev);
  1462. amdgpu_fence_driver_fini(adev);
  1463. amdgpu_fbdev_fini(adev);
  1464. r = amdgpu_fini(adev);
  1465. kfree(adev->ip_block_status);
  1466. adev->ip_block_status = NULL;
  1467. adev->accel_working = false;
  1468. /* free i2c buses */
  1469. amdgpu_i2c_fini(adev);
  1470. amdgpu_atombios_fini(adev);
  1471. kfree(adev->bios);
  1472. adev->bios = NULL;
  1473. vga_switcheroo_unregister_client(adev->pdev);
  1474. vga_client_register(adev->pdev, NULL, NULL, NULL);
  1475. if (adev->rio_mem)
  1476. pci_iounmap(adev->pdev, adev->rio_mem);
  1477. adev->rio_mem = NULL;
  1478. iounmap(adev->rmmio);
  1479. adev->rmmio = NULL;
  1480. amdgpu_doorbell_fini(adev);
  1481. amdgpu_debugfs_regs_cleanup(adev);
  1482. amdgpu_debugfs_remove_files(adev);
  1483. }
  1484. /*
  1485. * Suspend & resume.
  1486. */
  1487. /**
  1488. * amdgpu_suspend_kms - initiate device suspend
  1489. *
  1490. * @pdev: drm dev pointer
  1491. * @state: suspend state
  1492. *
  1493. * Puts the hw in the suspend state (all asics).
  1494. * Returns 0 for success or an error on failure.
  1495. * Called at driver suspend.
  1496. */
  1497. int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
  1498. {
  1499. struct amdgpu_device *adev;
  1500. struct drm_crtc *crtc;
  1501. struct drm_connector *connector;
  1502. int r;
  1503. if (dev == NULL || dev->dev_private == NULL) {
  1504. return -ENODEV;
  1505. }
  1506. adev = dev->dev_private;
  1507. if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
  1508. return 0;
  1509. drm_kms_helper_poll_disable(dev);
  1510. /* turn off display hw */
  1511. drm_modeset_lock_all(dev);
  1512. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  1513. drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
  1514. }
  1515. drm_modeset_unlock_all(dev);
  1516. /* unpin the front buffers and cursors */
  1517. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1518. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  1519. struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
  1520. struct amdgpu_bo *robj;
  1521. if (amdgpu_crtc->cursor_bo) {
  1522. struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
  1523. r = amdgpu_bo_reserve(aobj, false);
  1524. if (r == 0) {
  1525. amdgpu_bo_unpin(aobj);
  1526. amdgpu_bo_unreserve(aobj);
  1527. }
  1528. }
  1529. if (rfb == NULL || rfb->obj == NULL) {
  1530. continue;
  1531. }
  1532. robj = gem_to_amdgpu_bo(rfb->obj);
  1533. /* don't unpin kernel fb objects */
  1534. if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
  1535. r = amdgpu_bo_reserve(robj, false);
  1536. if (r == 0) {
  1537. amdgpu_bo_unpin(robj);
  1538. amdgpu_bo_unreserve(robj);
  1539. }
  1540. }
  1541. }
  1542. /* evict vram memory */
  1543. amdgpu_bo_evict_vram(adev);
  1544. amdgpu_fence_driver_suspend(adev);
  1545. r = amdgpu_suspend(adev);
  1546. /* evict remaining vram memory */
  1547. amdgpu_bo_evict_vram(adev);
  1548. pci_save_state(dev->pdev);
  1549. if (suspend) {
  1550. /* Shut down the device */
  1551. pci_disable_device(dev->pdev);
  1552. pci_set_power_state(dev->pdev, PCI_D3hot);
  1553. }
  1554. if (fbcon) {
  1555. console_lock();
  1556. amdgpu_fbdev_set_suspend(adev, 1);
  1557. console_unlock();
  1558. }
  1559. return 0;
  1560. }
  1561. /**
  1562. * amdgpu_resume_kms - initiate device resume
  1563. *
  1564. * @pdev: drm dev pointer
  1565. *
  1566. * Bring the hw back to operating state (all asics).
  1567. * Returns 0 for success or an error on failure.
  1568. * Called at driver resume.
  1569. */
  1570. int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
  1571. {
  1572. struct drm_connector *connector;
  1573. struct amdgpu_device *adev = dev->dev_private;
  1574. struct drm_crtc *crtc;
  1575. int r;
  1576. if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
  1577. return 0;
  1578. if (fbcon) {
  1579. console_lock();
  1580. }
  1581. if (resume) {
  1582. pci_set_power_state(dev->pdev, PCI_D0);
  1583. pci_restore_state(dev->pdev);
  1584. if (pci_enable_device(dev->pdev)) {
  1585. if (fbcon)
  1586. console_unlock();
  1587. return -1;
  1588. }
  1589. }
  1590. /* post card */
  1591. if (!amdgpu_card_posted(adev))
  1592. amdgpu_atom_asic_init(adev->mode_info.atom_context);
  1593. r = amdgpu_resume(adev);
  1594. if (r)
  1595. DRM_ERROR("amdgpu_resume failed (%d).\n", r);
  1596. amdgpu_fence_driver_resume(adev);
  1597. if (resume) {
  1598. r = amdgpu_ib_ring_tests(adev);
  1599. if (r)
  1600. DRM_ERROR("ib ring test failed (%d).\n", r);
  1601. }
  1602. r = amdgpu_late_init(adev);
  1603. if (r)
  1604. return r;
  1605. /* pin cursors */
  1606. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1607. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  1608. if (amdgpu_crtc->cursor_bo) {
  1609. struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
  1610. r = amdgpu_bo_reserve(aobj, false);
  1611. if (r == 0) {
  1612. r = amdgpu_bo_pin(aobj,
  1613. AMDGPU_GEM_DOMAIN_VRAM,
  1614. &amdgpu_crtc->cursor_addr);
  1615. if (r != 0)
  1616. DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
  1617. amdgpu_bo_unreserve(aobj);
  1618. }
  1619. }
  1620. }
  1621. /* blat the mode back in */
  1622. if (fbcon) {
  1623. drm_helper_resume_force_mode(dev);
  1624. /* turn on display hw */
  1625. drm_modeset_lock_all(dev);
  1626. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  1627. drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
  1628. }
  1629. drm_modeset_unlock_all(dev);
  1630. }
  1631. drm_kms_helper_poll_enable(dev);
  1632. drm_helper_hpd_irq_event(dev);
  1633. if (fbcon) {
  1634. amdgpu_fbdev_set_suspend(adev, 0);
  1635. console_unlock();
  1636. }
  1637. return 0;
  1638. }
  1639. /**
  1640. * amdgpu_gpu_reset - reset the asic
  1641. *
  1642. * @adev: amdgpu device pointer
  1643. *
  1644. * Attempt the reset the GPU if it has hung (all asics).
  1645. * Returns 0 for success or an error on failure.
  1646. */
  1647. int amdgpu_gpu_reset(struct amdgpu_device *adev)
  1648. {
  1649. unsigned ring_sizes[AMDGPU_MAX_RINGS];
  1650. uint32_t *ring_data[AMDGPU_MAX_RINGS];
  1651. bool saved = false;
  1652. int i, r;
  1653. int resched;
  1654. atomic_inc(&adev->gpu_reset_counter);
  1655. /* block TTM */
  1656. resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
  1657. r = amdgpu_suspend(adev);
  1658. for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
  1659. struct amdgpu_ring *ring = adev->rings[i];
  1660. if (!ring)
  1661. continue;
  1662. ring_sizes[i] = amdgpu_ring_backup(ring, &ring_data[i]);
  1663. if (ring_sizes[i]) {
  1664. saved = true;
  1665. dev_info(adev->dev, "Saved %d dwords of commands "
  1666. "on ring %d.\n", ring_sizes[i], i);
  1667. }
  1668. }
  1669. retry:
  1670. r = amdgpu_asic_reset(adev);
  1671. /* post card */
  1672. amdgpu_atom_asic_init(adev->mode_info.atom_context);
  1673. if (!r) {
  1674. dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
  1675. r = amdgpu_resume(adev);
  1676. }
  1677. if (!r) {
  1678. for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
  1679. struct amdgpu_ring *ring = adev->rings[i];
  1680. if (!ring)
  1681. continue;
  1682. amdgpu_ring_restore(ring, ring_sizes[i], ring_data[i]);
  1683. ring_sizes[i] = 0;
  1684. ring_data[i] = NULL;
  1685. }
  1686. r = amdgpu_ib_ring_tests(adev);
  1687. if (r) {
  1688. dev_err(adev->dev, "ib ring test failed (%d).\n", r);
  1689. if (saved) {
  1690. saved = false;
  1691. r = amdgpu_suspend(adev);
  1692. goto retry;
  1693. }
  1694. }
  1695. } else {
  1696. amdgpu_fence_driver_force_completion(adev);
  1697. for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
  1698. if (adev->rings[i])
  1699. kfree(ring_data[i]);
  1700. }
  1701. }
  1702. drm_helper_resume_force_mode(adev->ddev);
  1703. ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
  1704. if (r) {
  1705. /* bad news, how to tell it to userspace ? */
  1706. dev_info(adev->dev, "GPU reset failed\n");
  1707. }
  1708. return r;
  1709. }
  1710. #define AMDGPU_DEFAULT_PCIE_GEN_MASK 0x30007 /* gen: chipset 1/2, asic 1/2/3 */
  1711. #define AMDGPU_DEFAULT_PCIE_MLW_MASK 0x2f0000 /* 1/2/4/8/16 lanes */
  1712. void amdgpu_get_pcie_info(struct amdgpu_device *adev)
  1713. {
  1714. u32 mask;
  1715. int ret;
  1716. if (amdgpu_pcie_gen_cap)
  1717. adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
  1718. if (amdgpu_pcie_lane_cap)
  1719. adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
  1720. /* covers APUs as well */
  1721. if (pci_is_root_bus(adev->pdev->bus)) {
  1722. if (adev->pm.pcie_gen_mask == 0)
  1723. adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
  1724. if (adev->pm.pcie_mlw_mask == 0)
  1725. adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
  1726. return;
  1727. }
  1728. if (adev->pm.pcie_gen_mask == 0) {
  1729. ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
  1730. if (!ret) {
  1731. adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
  1732. CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
  1733. CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
  1734. if (mask & DRM_PCIE_SPEED_25)
  1735. adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
  1736. if (mask & DRM_PCIE_SPEED_50)
  1737. adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
  1738. if (mask & DRM_PCIE_SPEED_80)
  1739. adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
  1740. } else {
  1741. adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
  1742. }
  1743. }
  1744. if (adev->pm.pcie_mlw_mask == 0) {
  1745. ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
  1746. if (!ret) {
  1747. switch (mask) {
  1748. case 32:
  1749. adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
  1750. CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
  1751. CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
  1752. CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
  1753. CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
  1754. CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
  1755. CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
  1756. break;
  1757. case 16:
  1758. adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
  1759. CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
  1760. CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
  1761. CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
  1762. CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
  1763. CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
  1764. break;
  1765. case 12:
  1766. adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
  1767. CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
  1768. CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
  1769. CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
  1770. CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
  1771. break;
  1772. case 8:
  1773. adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
  1774. CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
  1775. CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
  1776. CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
  1777. break;
  1778. case 4:
  1779. adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
  1780. CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
  1781. CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
  1782. break;
  1783. case 2:
  1784. adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
  1785. CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
  1786. break;
  1787. case 1:
  1788. adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
  1789. break;
  1790. default:
  1791. break;
  1792. }
  1793. } else {
  1794. adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
  1795. }
  1796. }
  1797. }
  1798. /*
  1799. * Debugfs
  1800. */
  1801. int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
  1802. const struct drm_info_list *files,
  1803. unsigned nfiles)
  1804. {
  1805. unsigned i;
  1806. for (i = 0; i < adev->debugfs_count; i++) {
  1807. if (adev->debugfs[i].files == files) {
  1808. /* Already registered */
  1809. return 0;
  1810. }
  1811. }
  1812. i = adev->debugfs_count + 1;
  1813. if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
  1814. DRM_ERROR("Reached maximum number of debugfs components.\n");
  1815. DRM_ERROR("Report so we increase "
  1816. "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
  1817. return -EINVAL;
  1818. }
  1819. adev->debugfs[adev->debugfs_count].files = files;
  1820. adev->debugfs[adev->debugfs_count].num_files = nfiles;
  1821. adev->debugfs_count = i;
  1822. #if defined(CONFIG_DEBUG_FS)
  1823. drm_debugfs_create_files(files, nfiles,
  1824. adev->ddev->control->debugfs_root,
  1825. adev->ddev->control);
  1826. drm_debugfs_create_files(files, nfiles,
  1827. adev->ddev->primary->debugfs_root,
  1828. adev->ddev->primary);
  1829. #endif
  1830. return 0;
  1831. }
  1832. static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev)
  1833. {
  1834. #if defined(CONFIG_DEBUG_FS)
  1835. unsigned i;
  1836. for (i = 0; i < adev->debugfs_count; i++) {
  1837. drm_debugfs_remove_files(adev->debugfs[i].files,
  1838. adev->debugfs[i].num_files,
  1839. adev->ddev->control);
  1840. drm_debugfs_remove_files(adev->debugfs[i].files,
  1841. adev->debugfs[i].num_files,
  1842. adev->ddev->primary);
  1843. }
  1844. #endif
  1845. }
  1846. #if defined(CONFIG_DEBUG_FS)
  1847. static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
  1848. size_t size, loff_t *pos)
  1849. {
  1850. struct amdgpu_device *adev = f->f_inode->i_private;
  1851. ssize_t result = 0;
  1852. int r;
  1853. if (size & 0x3 || *pos & 0x3)
  1854. return -EINVAL;
  1855. while (size) {
  1856. uint32_t value;
  1857. if (*pos > adev->rmmio_size)
  1858. return result;
  1859. value = RREG32(*pos >> 2);
  1860. r = put_user(value, (uint32_t *)buf);
  1861. if (r)
  1862. return r;
  1863. result += 4;
  1864. buf += 4;
  1865. *pos += 4;
  1866. size -= 4;
  1867. }
  1868. return result;
  1869. }
  1870. static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
  1871. size_t size, loff_t *pos)
  1872. {
  1873. struct amdgpu_device *adev = f->f_inode->i_private;
  1874. ssize_t result = 0;
  1875. int r;
  1876. if (size & 0x3 || *pos & 0x3)
  1877. return -EINVAL;
  1878. while (size) {
  1879. uint32_t value;
  1880. if (*pos > adev->rmmio_size)
  1881. return result;
  1882. r = get_user(value, (uint32_t *)buf);
  1883. if (r)
  1884. return r;
  1885. WREG32(*pos >> 2, value);
  1886. result += 4;
  1887. buf += 4;
  1888. *pos += 4;
  1889. size -= 4;
  1890. }
  1891. return result;
  1892. }
  1893. static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
  1894. size_t size, loff_t *pos)
  1895. {
  1896. struct amdgpu_device *adev = f->f_inode->i_private;
  1897. ssize_t result = 0;
  1898. int r;
  1899. if (size & 0x3 || *pos & 0x3)
  1900. return -EINVAL;
  1901. while (size) {
  1902. uint32_t value;
  1903. value = RREG32_PCIE(*pos >> 2);
  1904. r = put_user(value, (uint32_t *)buf);
  1905. if (r)
  1906. return r;
  1907. result += 4;
  1908. buf += 4;
  1909. *pos += 4;
  1910. size -= 4;
  1911. }
  1912. return result;
  1913. }
  1914. static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
  1915. size_t size, loff_t *pos)
  1916. {
  1917. struct amdgpu_device *adev = f->f_inode->i_private;
  1918. ssize_t result = 0;
  1919. int r;
  1920. if (size & 0x3 || *pos & 0x3)
  1921. return -EINVAL;
  1922. while (size) {
  1923. uint32_t value;
  1924. r = get_user(value, (uint32_t *)buf);
  1925. if (r)
  1926. return r;
  1927. WREG32_PCIE(*pos >> 2, value);
  1928. result += 4;
  1929. buf += 4;
  1930. *pos += 4;
  1931. size -= 4;
  1932. }
  1933. return result;
  1934. }
  1935. static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
  1936. size_t size, loff_t *pos)
  1937. {
  1938. struct amdgpu_device *adev = f->f_inode->i_private;
  1939. ssize_t result = 0;
  1940. int r;
  1941. if (size & 0x3 || *pos & 0x3)
  1942. return -EINVAL;
  1943. while (size) {
  1944. uint32_t value;
  1945. value = RREG32_DIDT(*pos >> 2);
  1946. r = put_user(value, (uint32_t *)buf);
  1947. if (r)
  1948. return r;
  1949. result += 4;
  1950. buf += 4;
  1951. *pos += 4;
  1952. size -= 4;
  1953. }
  1954. return result;
  1955. }
  1956. static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
  1957. size_t size, loff_t *pos)
  1958. {
  1959. struct amdgpu_device *adev = f->f_inode->i_private;
  1960. ssize_t result = 0;
  1961. int r;
  1962. if (size & 0x3 || *pos & 0x3)
  1963. return -EINVAL;
  1964. while (size) {
  1965. uint32_t value;
  1966. r = get_user(value, (uint32_t *)buf);
  1967. if (r)
  1968. return r;
  1969. WREG32_DIDT(*pos >> 2, value);
  1970. result += 4;
  1971. buf += 4;
  1972. *pos += 4;
  1973. size -= 4;
  1974. }
  1975. return result;
  1976. }
  1977. static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
  1978. size_t size, loff_t *pos)
  1979. {
  1980. struct amdgpu_device *adev = f->f_inode->i_private;
  1981. ssize_t result = 0;
  1982. int r;
  1983. if (size & 0x3 || *pos & 0x3)
  1984. return -EINVAL;
  1985. while (size) {
  1986. uint32_t value;
  1987. value = RREG32_SMC(*pos >> 2);
  1988. r = put_user(value, (uint32_t *)buf);
  1989. if (r)
  1990. return r;
  1991. result += 4;
  1992. buf += 4;
  1993. *pos += 4;
  1994. size -= 4;
  1995. }
  1996. return result;
  1997. }
  1998. static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
  1999. size_t size, loff_t *pos)
  2000. {
  2001. struct amdgpu_device *adev = f->f_inode->i_private;
  2002. ssize_t result = 0;
  2003. int r;
  2004. if (size & 0x3 || *pos & 0x3)
  2005. return -EINVAL;
  2006. while (size) {
  2007. uint32_t value;
  2008. r = get_user(value, (uint32_t *)buf);
  2009. if (r)
  2010. return r;
  2011. WREG32_SMC(*pos >> 2, value);
  2012. result += 4;
  2013. buf += 4;
  2014. *pos += 4;
  2015. size -= 4;
  2016. }
  2017. return result;
  2018. }
  2019. static const struct file_operations amdgpu_debugfs_regs_fops = {
  2020. .owner = THIS_MODULE,
  2021. .read = amdgpu_debugfs_regs_read,
  2022. .write = amdgpu_debugfs_regs_write,
  2023. .llseek = default_llseek
  2024. };
  2025. static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
  2026. .owner = THIS_MODULE,
  2027. .read = amdgpu_debugfs_regs_didt_read,
  2028. .write = amdgpu_debugfs_regs_didt_write,
  2029. .llseek = default_llseek
  2030. };
  2031. static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
  2032. .owner = THIS_MODULE,
  2033. .read = amdgpu_debugfs_regs_pcie_read,
  2034. .write = amdgpu_debugfs_regs_pcie_write,
  2035. .llseek = default_llseek
  2036. };
  2037. static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
  2038. .owner = THIS_MODULE,
  2039. .read = amdgpu_debugfs_regs_smc_read,
  2040. .write = amdgpu_debugfs_regs_smc_write,
  2041. .llseek = default_llseek
  2042. };
  2043. static const struct file_operations *debugfs_regs[] = {
  2044. &amdgpu_debugfs_regs_fops,
  2045. &amdgpu_debugfs_regs_didt_fops,
  2046. &amdgpu_debugfs_regs_pcie_fops,
  2047. &amdgpu_debugfs_regs_smc_fops,
  2048. };
  2049. static const char *debugfs_regs_names[] = {
  2050. "amdgpu_regs",
  2051. "amdgpu_regs_didt",
  2052. "amdgpu_regs_pcie",
  2053. "amdgpu_regs_smc",
  2054. };
  2055. static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
  2056. {
  2057. struct drm_minor *minor = adev->ddev->primary;
  2058. struct dentry *ent, *root = minor->debugfs_root;
  2059. unsigned i, j;
  2060. for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
  2061. ent = debugfs_create_file(debugfs_regs_names[i],
  2062. S_IFREG | S_IRUGO, root,
  2063. adev, debugfs_regs[i]);
  2064. if (IS_ERR(ent)) {
  2065. for (j = 0; j < i; j++) {
  2066. debugfs_remove(adev->debugfs_regs[i]);
  2067. adev->debugfs_regs[i] = NULL;
  2068. }
  2069. return PTR_ERR(ent);
  2070. }
  2071. if (!i)
  2072. i_size_write(ent->d_inode, adev->rmmio_size);
  2073. adev->debugfs_regs[i] = ent;
  2074. }
  2075. return 0;
  2076. }
  2077. static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
  2078. {
  2079. unsigned i;
  2080. for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
  2081. if (adev->debugfs_regs[i]) {
  2082. debugfs_remove(adev->debugfs_regs[i]);
  2083. adev->debugfs_regs[i] = NULL;
  2084. }
  2085. }
  2086. }
  2087. int amdgpu_debugfs_init(struct drm_minor *minor)
  2088. {
  2089. return 0;
  2090. }
  2091. void amdgpu_debugfs_cleanup(struct drm_minor *minor)
  2092. {
  2093. }
  2094. #else
  2095. static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
  2096. {
  2097. return 0;
  2098. }
  2099. static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }
  2100. #endif