qed_l2.c 62 KB

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  1. /* QLogic qed NIC Driver
  2. * Copyright (c) 2015 QLogic Corporation
  3. *
  4. * This software is available under the terms of the GNU General Public License
  5. * (GPL) Version 2, available from the file COPYING in the main directory of
  6. * this source tree.
  7. */
  8. #include <linux/types.h>
  9. #include <asm/byteorder.h>
  10. #include <asm/param.h>
  11. #include <linux/delay.h>
  12. #include <linux/dma-mapping.h>
  13. #include <linux/etherdevice.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/kernel.h>
  16. #include <linux/module.h>
  17. #include <linux/pci.h>
  18. #include <linux/slab.h>
  19. #include <linux/stddef.h>
  20. #include <linux/string.h>
  21. #include <linux/version.h>
  22. #include <linux/workqueue.h>
  23. #include <linux/bitops.h>
  24. #include <linux/bug.h>
  25. #include "qed.h"
  26. #include <linux/qed/qed_chain.h>
  27. #include "qed_cxt.h"
  28. #include "qed_dev_api.h"
  29. #include <linux/qed/qed_eth_if.h>
  30. #include "qed_hsi.h"
  31. #include "qed_hw.h"
  32. #include "qed_int.h"
  33. #include "qed_l2.h"
  34. #include "qed_mcp.h"
  35. #include "qed_reg_addr.h"
  36. #include "qed_sp.h"
  37. #include "qed_sriov.h"
  38. #define QED_MAX_SGES_NUM 16
  39. #define CRC32_POLY 0x1edc6f41
  40. int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn,
  41. struct qed_sp_vport_start_params *p_params)
  42. {
  43. struct vport_start_ramrod_data *p_ramrod = NULL;
  44. struct qed_spq_entry *p_ent = NULL;
  45. struct qed_sp_init_data init_data;
  46. u8 abs_vport_id = 0;
  47. int rc = -EINVAL;
  48. u16 rx_mode = 0;
  49. rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
  50. if (rc)
  51. return rc;
  52. memset(&init_data, 0, sizeof(init_data));
  53. init_data.cid = qed_spq_get_cid(p_hwfn);
  54. init_data.opaque_fid = p_params->opaque_fid;
  55. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  56. rc = qed_sp_init_request(p_hwfn, &p_ent,
  57. ETH_RAMROD_VPORT_START,
  58. PROTOCOLID_ETH, &init_data);
  59. if (rc)
  60. return rc;
  61. p_ramrod = &p_ent->ramrod.vport_start;
  62. p_ramrod->vport_id = abs_vport_id;
  63. p_ramrod->mtu = cpu_to_le16(p_params->mtu);
  64. p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan;
  65. p_ramrod->drop_ttl0_en = p_params->drop_ttl0;
  66. p_ramrod->untagged = p_params->only_untagged;
  67. SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
  68. SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
  69. p_ramrod->rx_mode.state = cpu_to_le16(rx_mode);
  70. /* TPA related fields */
  71. memset(&p_ramrod->tpa_param, 0, sizeof(struct eth_vport_tpa_param));
  72. p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
  73. switch (p_params->tpa_mode) {
  74. case QED_TPA_MODE_GRO:
  75. p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
  76. p_ramrod->tpa_param.tpa_max_size = (u16)-1;
  77. p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
  78. p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
  79. p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
  80. p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
  81. p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
  82. p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
  83. break;
  84. default:
  85. break;
  86. }
  87. p_ramrod->tx_switching_en = p_params->tx_switching;
  88. p_ramrod->ctl_frame_mac_check_en = !!p_params->check_mac;
  89. p_ramrod->ctl_frame_ethtype_check_en = !!p_params->check_ethtype;
  90. /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
  91. p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev,
  92. p_params->concrete_fid);
  93. return qed_spq_post(p_hwfn, p_ent, NULL);
  94. }
  95. static int qed_sp_vport_start(struct qed_hwfn *p_hwfn,
  96. struct qed_sp_vport_start_params *p_params)
  97. {
  98. if (IS_VF(p_hwfn->cdev)) {
  99. return qed_vf_pf_vport_start(p_hwfn, p_params->vport_id,
  100. p_params->mtu,
  101. p_params->remove_inner_vlan,
  102. p_params->tpa_mode,
  103. p_params->max_buffers_per_cqe,
  104. p_params->only_untagged);
  105. }
  106. return qed_sp_eth_vport_start(p_hwfn, p_params);
  107. }
  108. static int
  109. qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn,
  110. struct vport_update_ramrod_data *p_ramrod,
  111. struct qed_rss_params *p_params)
  112. {
  113. struct eth_vport_rss_config *rss = &p_ramrod->rss_config;
  114. u16 abs_l2_queue = 0, capabilities = 0;
  115. int rc = 0, i;
  116. if (!p_params) {
  117. p_ramrod->common.update_rss_flg = 0;
  118. return rc;
  119. }
  120. BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE !=
  121. ETH_RSS_IND_TABLE_ENTRIES_NUM);
  122. rc = qed_fw_rss_eng(p_hwfn, p_params->rss_eng_id, &rss->rss_id);
  123. if (rc)
  124. return rc;
  125. p_ramrod->common.update_rss_flg = p_params->update_rss_config;
  126. rss->update_rss_capabilities = p_params->update_rss_capabilities;
  127. rss->update_rss_ind_table = p_params->update_rss_ind_table;
  128. rss->update_rss_key = p_params->update_rss_key;
  129. rss->rss_mode = p_params->rss_enable ?
  130. ETH_VPORT_RSS_MODE_REGULAR :
  131. ETH_VPORT_RSS_MODE_DISABLED;
  132. SET_FIELD(capabilities,
  133. ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
  134. !!(p_params->rss_caps & QED_RSS_IPV4));
  135. SET_FIELD(capabilities,
  136. ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
  137. !!(p_params->rss_caps & QED_RSS_IPV6));
  138. SET_FIELD(capabilities,
  139. ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
  140. !!(p_params->rss_caps & QED_RSS_IPV4_TCP));
  141. SET_FIELD(capabilities,
  142. ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
  143. !!(p_params->rss_caps & QED_RSS_IPV6_TCP));
  144. SET_FIELD(capabilities,
  145. ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
  146. !!(p_params->rss_caps & QED_RSS_IPV4_UDP));
  147. SET_FIELD(capabilities,
  148. ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
  149. !!(p_params->rss_caps & QED_RSS_IPV6_UDP));
  150. rss->tbl_size = p_params->rss_table_size_log;
  151. rss->capabilities = cpu_to_le16(capabilities);
  152. DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
  153. "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
  154. p_ramrod->common.update_rss_flg,
  155. rss->rss_mode, rss->update_rss_capabilities,
  156. capabilities, rss->update_rss_ind_table,
  157. rss->update_rss_key);
  158. for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
  159. rc = qed_fw_l2_queue(p_hwfn,
  160. (u8)p_params->rss_ind_table[i],
  161. &abs_l2_queue);
  162. if (rc)
  163. return rc;
  164. rss->indirection_table[i] = cpu_to_le16(abs_l2_queue);
  165. DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, "i= %d, queue = %d\n",
  166. i, rss->indirection_table[i]);
  167. }
  168. for (i = 0; i < 10; i++)
  169. rss->rss_key[i] = cpu_to_le32(p_params->rss_key[i]);
  170. return rc;
  171. }
  172. static void
  173. qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn,
  174. struct vport_update_ramrod_data *p_ramrod,
  175. struct qed_filter_accept_flags accept_flags)
  176. {
  177. p_ramrod->common.update_rx_mode_flg =
  178. accept_flags.update_rx_mode_config;
  179. p_ramrod->common.update_tx_mode_flg =
  180. accept_flags.update_tx_mode_config;
  181. /* Set Rx mode accept flags */
  182. if (p_ramrod->common.update_rx_mode_flg) {
  183. u8 accept_filter = accept_flags.rx_accept_filter;
  184. u16 state = 0;
  185. SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
  186. !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) ||
  187. !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)));
  188. SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
  189. !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED));
  190. SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
  191. !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) ||
  192. !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
  193. SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
  194. (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
  195. !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
  196. SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
  197. !!(accept_filter & QED_ACCEPT_BCAST));
  198. p_ramrod->rx_mode.state = cpu_to_le16(state);
  199. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  200. "p_ramrod->rx_mode.state = 0x%x\n", state);
  201. }
  202. /* Set Tx mode accept flags */
  203. if (p_ramrod->common.update_tx_mode_flg) {
  204. u8 accept_filter = accept_flags.tx_accept_filter;
  205. u16 state = 0;
  206. SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
  207. !!(accept_filter & QED_ACCEPT_NONE));
  208. SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
  209. !!(accept_filter & QED_ACCEPT_NONE));
  210. SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
  211. (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
  212. !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
  213. SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
  214. !!(accept_filter & QED_ACCEPT_BCAST));
  215. p_ramrod->tx_mode.state = cpu_to_le16(state);
  216. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  217. "p_ramrod->tx_mode.state = 0x%x\n", state);
  218. }
  219. }
  220. static void
  221. qed_sp_vport_update_sge_tpa(struct qed_hwfn *p_hwfn,
  222. struct vport_update_ramrod_data *p_ramrod,
  223. struct qed_sge_tpa_params *p_params)
  224. {
  225. struct eth_vport_tpa_param *p_tpa;
  226. if (!p_params) {
  227. p_ramrod->common.update_tpa_param_flg = 0;
  228. p_ramrod->common.update_tpa_en_flg = 0;
  229. p_ramrod->common.update_tpa_param_flg = 0;
  230. return;
  231. }
  232. p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg;
  233. p_tpa = &p_ramrod->tpa_param;
  234. p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg;
  235. p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg;
  236. p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg;
  237. p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg;
  238. p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg;
  239. p_tpa->max_buff_num = p_params->max_buffers_per_cqe;
  240. p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg;
  241. p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg;
  242. p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg;
  243. p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num;
  244. p_tpa->tpa_max_size = p_params->tpa_max_size;
  245. p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start;
  246. p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont;
  247. }
  248. static void
  249. qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn,
  250. struct vport_update_ramrod_data *p_ramrod,
  251. struct qed_sp_vport_update_params *p_params)
  252. {
  253. int i;
  254. memset(&p_ramrod->approx_mcast.bins, 0,
  255. sizeof(p_ramrod->approx_mcast.bins));
  256. if (!p_params->update_approx_mcast_flg)
  257. return;
  258. p_ramrod->common.update_approx_mcast_flg = 1;
  259. for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
  260. u32 *p_bins = (u32 *)p_params->bins;
  261. p_ramrod->approx_mcast.bins[i] = cpu_to_le32(p_bins[i]);
  262. }
  263. }
  264. int qed_sp_vport_update(struct qed_hwfn *p_hwfn,
  265. struct qed_sp_vport_update_params *p_params,
  266. enum spq_mode comp_mode,
  267. struct qed_spq_comp_cb *p_comp_data)
  268. {
  269. struct qed_rss_params *p_rss_params = p_params->rss_params;
  270. struct vport_update_ramrod_data_cmn *p_cmn;
  271. struct qed_sp_init_data init_data;
  272. struct vport_update_ramrod_data *p_ramrod = NULL;
  273. struct qed_spq_entry *p_ent = NULL;
  274. u8 abs_vport_id = 0, val;
  275. int rc = -EINVAL;
  276. if (IS_VF(p_hwfn->cdev)) {
  277. rc = qed_vf_pf_vport_update(p_hwfn, p_params);
  278. return rc;
  279. }
  280. rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
  281. if (rc)
  282. return rc;
  283. memset(&init_data, 0, sizeof(init_data));
  284. init_data.cid = qed_spq_get_cid(p_hwfn);
  285. init_data.opaque_fid = p_params->opaque_fid;
  286. init_data.comp_mode = comp_mode;
  287. init_data.p_comp_data = p_comp_data;
  288. rc = qed_sp_init_request(p_hwfn, &p_ent,
  289. ETH_RAMROD_VPORT_UPDATE,
  290. PROTOCOLID_ETH, &init_data);
  291. if (rc)
  292. return rc;
  293. /* Copy input params to ramrod according to FW struct */
  294. p_ramrod = &p_ent->ramrod.vport_update;
  295. p_cmn = &p_ramrod->common;
  296. p_cmn->vport_id = abs_vport_id;
  297. p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
  298. p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
  299. p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
  300. p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
  301. p_cmn->accept_any_vlan = p_params->accept_any_vlan;
  302. val = p_params->update_accept_any_vlan_flg;
  303. p_cmn->update_accept_any_vlan_flg = val;
  304. p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg;
  305. val = p_params->update_inner_vlan_removal_flg;
  306. p_cmn->update_inner_vlan_removal_en_flg = val;
  307. p_cmn->default_vlan_en = p_params->default_vlan_enable_flg;
  308. val = p_params->update_default_vlan_enable_flg;
  309. p_cmn->update_default_vlan_en_flg = val;
  310. p_cmn->default_vlan = cpu_to_le16(p_params->default_vlan);
  311. p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg;
  312. p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg;
  313. p_ramrod->common.tx_switching_en = p_params->tx_switching_flg;
  314. p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg;
  315. p_cmn->anti_spoofing_en = p_params->anti_spoofing_en;
  316. val = p_params->update_anti_spoofing_en_flg;
  317. p_ramrod->common.update_anti_spoofing_en_flg = val;
  318. rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
  319. if (rc) {
  320. /* Return spq entry which is taken in qed_sp_init_request()*/
  321. qed_spq_return_entry(p_hwfn, p_ent);
  322. return rc;
  323. }
  324. /* Update mcast bins for VFs, PF doesn't use this functionality */
  325. qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
  326. qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
  327. qed_sp_vport_update_sge_tpa(p_hwfn, p_ramrod, p_params->sge_tpa_params);
  328. return qed_spq_post(p_hwfn, p_ent, NULL);
  329. }
  330. int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, u16 opaque_fid, u8 vport_id)
  331. {
  332. struct vport_stop_ramrod_data *p_ramrod;
  333. struct qed_sp_init_data init_data;
  334. struct qed_spq_entry *p_ent;
  335. u8 abs_vport_id = 0;
  336. int rc;
  337. if (IS_VF(p_hwfn->cdev))
  338. return qed_vf_pf_vport_stop(p_hwfn);
  339. rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id);
  340. if (rc)
  341. return rc;
  342. memset(&init_data, 0, sizeof(init_data));
  343. init_data.cid = qed_spq_get_cid(p_hwfn);
  344. init_data.opaque_fid = opaque_fid;
  345. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  346. rc = qed_sp_init_request(p_hwfn, &p_ent,
  347. ETH_RAMROD_VPORT_STOP,
  348. PROTOCOLID_ETH, &init_data);
  349. if (rc)
  350. return rc;
  351. p_ramrod = &p_ent->ramrod.vport_stop;
  352. p_ramrod->vport_id = abs_vport_id;
  353. return qed_spq_post(p_hwfn, p_ent, NULL);
  354. }
  355. static int
  356. qed_vf_pf_accept_flags(struct qed_hwfn *p_hwfn,
  357. struct qed_filter_accept_flags *p_accept_flags)
  358. {
  359. struct qed_sp_vport_update_params s_params;
  360. memset(&s_params, 0, sizeof(s_params));
  361. memcpy(&s_params.accept_flags, p_accept_flags,
  362. sizeof(struct qed_filter_accept_flags));
  363. return qed_vf_pf_vport_update(p_hwfn, &s_params);
  364. }
  365. static int qed_filter_accept_cmd(struct qed_dev *cdev,
  366. u8 vport,
  367. struct qed_filter_accept_flags accept_flags,
  368. u8 update_accept_any_vlan,
  369. u8 accept_any_vlan,
  370. enum spq_mode comp_mode,
  371. struct qed_spq_comp_cb *p_comp_data)
  372. {
  373. struct qed_sp_vport_update_params vport_update_params;
  374. int i, rc;
  375. /* Prepare and send the vport rx_mode change */
  376. memset(&vport_update_params, 0, sizeof(vport_update_params));
  377. vport_update_params.vport_id = vport;
  378. vport_update_params.accept_flags = accept_flags;
  379. vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
  380. vport_update_params.accept_any_vlan = accept_any_vlan;
  381. for_each_hwfn(cdev, i) {
  382. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  383. vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
  384. if (IS_VF(cdev)) {
  385. rc = qed_vf_pf_accept_flags(p_hwfn, &accept_flags);
  386. if (rc)
  387. return rc;
  388. continue;
  389. }
  390. rc = qed_sp_vport_update(p_hwfn, &vport_update_params,
  391. comp_mode, p_comp_data);
  392. if (rc) {
  393. DP_ERR(cdev, "Update rx_mode failed %d\n", rc);
  394. return rc;
  395. }
  396. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  397. "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
  398. accept_flags.rx_accept_filter,
  399. accept_flags.tx_accept_filter);
  400. if (update_accept_any_vlan)
  401. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  402. "accept_any_vlan=%d configured\n",
  403. accept_any_vlan);
  404. }
  405. return 0;
  406. }
  407. static int qed_sp_release_queue_cid(
  408. struct qed_hwfn *p_hwfn,
  409. struct qed_hw_cid_data *p_cid_data)
  410. {
  411. if (!p_cid_data->b_cid_allocated)
  412. return 0;
  413. qed_cxt_release_cid(p_hwfn, p_cid_data->cid);
  414. p_cid_data->b_cid_allocated = false;
  415. return 0;
  416. }
  417. int qed_sp_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn,
  418. u16 opaque_fid,
  419. u32 cid,
  420. struct qed_queue_start_common_params *p_params,
  421. u8 stats_id,
  422. u16 bd_max_bytes,
  423. dma_addr_t bd_chain_phys_addr,
  424. dma_addr_t cqe_pbl_addr,
  425. u16 cqe_pbl_size, bool b_use_zone_a_prod)
  426. {
  427. struct rx_queue_start_ramrod_data *p_ramrod = NULL;
  428. struct qed_spq_entry *p_ent = NULL;
  429. struct qed_sp_init_data init_data;
  430. struct qed_hw_cid_data *p_rx_cid;
  431. u16 abs_rx_q_id = 0;
  432. u8 abs_vport_id = 0;
  433. int rc = -EINVAL;
  434. /* Store information for the stop */
  435. p_rx_cid = &p_hwfn->p_rx_cids[p_params->queue_id];
  436. p_rx_cid->cid = cid;
  437. p_rx_cid->opaque_fid = opaque_fid;
  438. p_rx_cid->vport_id = p_params->vport_id;
  439. rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
  440. if (rc)
  441. return rc;
  442. rc = qed_fw_l2_queue(p_hwfn, p_params->queue_id, &abs_rx_q_id);
  443. if (rc)
  444. return rc;
  445. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  446. "opaque_fid=0x%x, cid=0x%x, rx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
  447. opaque_fid,
  448. cid, p_params->queue_id, p_params->vport_id, p_params->sb);
  449. /* Get SPQ entry */
  450. memset(&init_data, 0, sizeof(init_data));
  451. init_data.cid = cid;
  452. init_data.opaque_fid = opaque_fid;
  453. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  454. rc = qed_sp_init_request(p_hwfn, &p_ent,
  455. ETH_RAMROD_RX_QUEUE_START,
  456. PROTOCOLID_ETH, &init_data);
  457. if (rc)
  458. return rc;
  459. p_ramrod = &p_ent->ramrod.rx_queue_start;
  460. p_ramrod->sb_id = cpu_to_le16(p_params->sb);
  461. p_ramrod->sb_index = p_params->sb_idx;
  462. p_ramrod->vport_id = abs_vport_id;
  463. p_ramrod->stats_counter_id = stats_id;
  464. p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id);
  465. p_ramrod->complete_cqe_flg = 0;
  466. p_ramrod->complete_event_flg = 1;
  467. p_ramrod->bd_max_bytes = cpu_to_le16(bd_max_bytes);
  468. DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
  469. p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size);
  470. DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
  471. if (p_params->vf_qid || b_use_zone_a_prod) {
  472. p_ramrod->vf_rx_prod_index = p_params->vf_qid;
  473. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  474. "Queue%s is meant for VF rxq[%02x]\n",
  475. b_use_zone_a_prod ? " [legacy]" : "",
  476. p_params->vf_qid);
  477. p_ramrod->vf_rx_prod_use_zone_a = b_use_zone_a_prod;
  478. }
  479. return qed_spq_post(p_hwfn, p_ent, NULL);
  480. }
  481. static int
  482. qed_sp_eth_rx_queue_start(struct qed_hwfn *p_hwfn,
  483. u16 opaque_fid,
  484. struct qed_queue_start_common_params *p_params,
  485. u16 bd_max_bytes,
  486. dma_addr_t bd_chain_phys_addr,
  487. dma_addr_t cqe_pbl_addr,
  488. u16 cqe_pbl_size, void __iomem **pp_prod)
  489. {
  490. struct qed_hw_cid_data *p_rx_cid;
  491. u32 init_prod_val = 0;
  492. u16 abs_l2_queue = 0;
  493. u8 abs_stats_id = 0;
  494. int rc;
  495. if (IS_VF(p_hwfn->cdev)) {
  496. return qed_vf_pf_rxq_start(p_hwfn,
  497. p_params->queue_id,
  498. p_params->sb,
  499. (u8)p_params->sb_idx,
  500. bd_max_bytes,
  501. bd_chain_phys_addr,
  502. cqe_pbl_addr, cqe_pbl_size, pp_prod);
  503. }
  504. rc = qed_fw_l2_queue(p_hwfn, p_params->queue_id, &abs_l2_queue);
  505. if (rc)
  506. return rc;
  507. rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_stats_id);
  508. if (rc)
  509. return rc;
  510. *pp_prod = (u8 __iomem *)p_hwfn->regview +
  511. GTT_BAR0_MAP_REG_MSDM_RAM +
  512. MSTORM_ETH_PF_PRODS_OFFSET(abs_l2_queue);
  513. /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
  514. __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
  515. (u32 *)(&init_prod_val));
  516. /* Allocate a CID for the queue */
  517. p_rx_cid = &p_hwfn->p_rx_cids[p_params->queue_id];
  518. rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, &p_rx_cid->cid);
  519. if (rc) {
  520. DP_NOTICE(p_hwfn, "Failed to acquire cid\n");
  521. return rc;
  522. }
  523. p_rx_cid->b_cid_allocated = true;
  524. rc = qed_sp_eth_rxq_start_ramrod(p_hwfn,
  525. opaque_fid,
  526. p_rx_cid->cid,
  527. p_params,
  528. abs_stats_id,
  529. bd_max_bytes,
  530. bd_chain_phys_addr,
  531. cqe_pbl_addr, cqe_pbl_size, false);
  532. if (rc)
  533. qed_sp_release_queue_cid(p_hwfn, p_rx_cid);
  534. return rc;
  535. }
  536. int qed_sp_eth_rx_queues_update(struct qed_hwfn *p_hwfn,
  537. u16 rx_queue_id,
  538. u8 num_rxqs,
  539. u8 complete_cqe_flg,
  540. u8 complete_event_flg,
  541. enum spq_mode comp_mode,
  542. struct qed_spq_comp_cb *p_comp_data)
  543. {
  544. struct rx_queue_update_ramrod_data *p_ramrod = NULL;
  545. struct qed_spq_entry *p_ent = NULL;
  546. struct qed_sp_init_data init_data;
  547. struct qed_hw_cid_data *p_rx_cid;
  548. u16 qid, abs_rx_q_id = 0;
  549. int rc = -EINVAL;
  550. u8 i;
  551. memset(&init_data, 0, sizeof(init_data));
  552. init_data.comp_mode = comp_mode;
  553. init_data.p_comp_data = p_comp_data;
  554. for (i = 0; i < num_rxqs; i++) {
  555. qid = rx_queue_id + i;
  556. p_rx_cid = &p_hwfn->p_rx_cids[qid];
  557. /* Get SPQ entry */
  558. init_data.cid = p_rx_cid->cid;
  559. init_data.opaque_fid = p_rx_cid->opaque_fid;
  560. rc = qed_sp_init_request(p_hwfn, &p_ent,
  561. ETH_RAMROD_RX_QUEUE_UPDATE,
  562. PROTOCOLID_ETH, &init_data);
  563. if (rc)
  564. return rc;
  565. p_ramrod = &p_ent->ramrod.rx_queue_update;
  566. qed_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
  567. qed_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id);
  568. p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id);
  569. p_ramrod->complete_cqe_flg = complete_cqe_flg;
  570. p_ramrod->complete_event_flg = complete_event_flg;
  571. rc = qed_spq_post(p_hwfn, p_ent, NULL);
  572. if (rc)
  573. return rc;
  574. }
  575. return rc;
  576. }
  577. int qed_sp_eth_rx_queue_stop(struct qed_hwfn *p_hwfn,
  578. u16 rx_queue_id,
  579. bool eq_completion_only, bool cqe_completion)
  580. {
  581. struct qed_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
  582. struct rx_queue_stop_ramrod_data *p_ramrod = NULL;
  583. struct qed_spq_entry *p_ent = NULL;
  584. struct qed_sp_init_data init_data;
  585. u16 abs_rx_q_id = 0;
  586. int rc = -EINVAL;
  587. if (IS_VF(p_hwfn->cdev))
  588. return qed_vf_pf_rxq_stop(p_hwfn, rx_queue_id, cqe_completion);
  589. /* Get SPQ entry */
  590. memset(&init_data, 0, sizeof(init_data));
  591. init_data.cid = p_rx_cid->cid;
  592. init_data.opaque_fid = p_rx_cid->opaque_fid;
  593. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  594. rc = qed_sp_init_request(p_hwfn, &p_ent,
  595. ETH_RAMROD_RX_QUEUE_STOP,
  596. PROTOCOLID_ETH, &init_data);
  597. if (rc)
  598. return rc;
  599. p_ramrod = &p_ent->ramrod.rx_queue_stop;
  600. qed_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
  601. qed_fw_l2_queue(p_hwfn, rx_queue_id, &abs_rx_q_id);
  602. p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id);
  603. /* Cleaning the queue requires the completion to arrive there.
  604. * In addition, VFs require the answer to come as eqe to PF.
  605. */
  606. p_ramrod->complete_cqe_flg =
  607. (!!(p_rx_cid->opaque_fid == p_hwfn->hw_info.opaque_fid) &&
  608. !eq_completion_only) || cqe_completion;
  609. p_ramrod->complete_event_flg =
  610. !(p_rx_cid->opaque_fid == p_hwfn->hw_info.opaque_fid) ||
  611. eq_completion_only;
  612. rc = qed_spq_post(p_hwfn, p_ent, NULL);
  613. if (rc)
  614. return rc;
  615. return qed_sp_release_queue_cid(p_hwfn, p_rx_cid);
  616. }
  617. int qed_sp_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn,
  618. u16 opaque_fid,
  619. u32 cid,
  620. struct qed_queue_start_common_params *p_params,
  621. u8 stats_id,
  622. dma_addr_t pbl_addr,
  623. u16 pbl_size,
  624. union qed_qm_pq_params *p_pq_params)
  625. {
  626. struct tx_queue_start_ramrod_data *p_ramrod = NULL;
  627. struct qed_spq_entry *p_ent = NULL;
  628. struct qed_sp_init_data init_data;
  629. struct qed_hw_cid_data *p_tx_cid;
  630. u16 pq_id, abs_tx_q_id = 0;
  631. int rc = -EINVAL;
  632. u8 abs_vport_id;
  633. /* Store information for the stop */
  634. p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id];
  635. p_tx_cid->cid = cid;
  636. p_tx_cid->opaque_fid = opaque_fid;
  637. rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
  638. if (rc)
  639. return rc;
  640. rc = qed_fw_l2_queue(p_hwfn, p_params->queue_id, &abs_tx_q_id);
  641. if (rc)
  642. return rc;
  643. /* Get SPQ entry */
  644. memset(&init_data, 0, sizeof(init_data));
  645. init_data.cid = cid;
  646. init_data.opaque_fid = opaque_fid;
  647. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  648. rc = qed_sp_init_request(p_hwfn, &p_ent,
  649. ETH_RAMROD_TX_QUEUE_START,
  650. PROTOCOLID_ETH, &init_data);
  651. if (rc)
  652. return rc;
  653. p_ramrod = &p_ent->ramrod.tx_queue_start;
  654. p_ramrod->vport_id = abs_vport_id;
  655. p_ramrod->sb_id = cpu_to_le16(p_params->sb);
  656. p_ramrod->sb_index = p_params->sb_idx;
  657. p_ramrod->stats_counter_id = stats_id;
  658. p_ramrod->queue_zone_id = cpu_to_le16(abs_tx_q_id);
  659. p_ramrod->pbl_size = cpu_to_le16(pbl_size);
  660. DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr);
  661. pq_id = qed_get_qm_pq(p_hwfn, PROTOCOLID_ETH, p_pq_params);
  662. p_ramrod->qm_pq_id = cpu_to_le16(pq_id);
  663. return qed_spq_post(p_hwfn, p_ent, NULL);
  664. }
  665. static int
  666. qed_sp_eth_tx_queue_start(struct qed_hwfn *p_hwfn,
  667. u16 opaque_fid,
  668. struct qed_queue_start_common_params *p_params,
  669. dma_addr_t pbl_addr,
  670. u16 pbl_size, void __iomem **pp_doorbell)
  671. {
  672. struct qed_hw_cid_data *p_tx_cid;
  673. union qed_qm_pq_params pq_params;
  674. u8 abs_stats_id = 0;
  675. int rc;
  676. if (IS_VF(p_hwfn->cdev)) {
  677. return qed_vf_pf_txq_start(p_hwfn,
  678. p_params->queue_id,
  679. p_params->sb,
  680. p_params->sb_idx,
  681. pbl_addr, pbl_size, pp_doorbell);
  682. }
  683. rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_stats_id);
  684. if (rc)
  685. return rc;
  686. p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id];
  687. memset(p_tx_cid, 0, sizeof(*p_tx_cid));
  688. memset(&pq_params, 0, sizeof(pq_params));
  689. /* Allocate a CID for the queue */
  690. rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, &p_tx_cid->cid);
  691. if (rc) {
  692. DP_NOTICE(p_hwfn, "Failed to acquire cid\n");
  693. return rc;
  694. }
  695. p_tx_cid->b_cid_allocated = true;
  696. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  697. "opaque_fid=0x%x, cid=0x%x, tx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
  698. opaque_fid, p_tx_cid->cid,
  699. p_params->queue_id, p_params->vport_id, p_params->sb);
  700. rc = qed_sp_eth_txq_start_ramrod(p_hwfn,
  701. opaque_fid,
  702. p_tx_cid->cid,
  703. p_params,
  704. abs_stats_id,
  705. pbl_addr,
  706. pbl_size,
  707. &pq_params);
  708. *pp_doorbell = (u8 __iomem *)p_hwfn->doorbells +
  709. qed_db_addr(p_tx_cid->cid, DQ_DEMS_LEGACY);
  710. if (rc)
  711. qed_sp_release_queue_cid(p_hwfn, p_tx_cid);
  712. return rc;
  713. }
  714. int qed_sp_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, u16 tx_queue_id)
  715. {
  716. struct qed_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
  717. struct qed_spq_entry *p_ent = NULL;
  718. struct qed_sp_init_data init_data;
  719. int rc = -EINVAL;
  720. if (IS_VF(p_hwfn->cdev))
  721. return qed_vf_pf_txq_stop(p_hwfn, tx_queue_id);
  722. /* Get SPQ entry */
  723. memset(&init_data, 0, sizeof(init_data));
  724. init_data.cid = p_tx_cid->cid;
  725. init_data.opaque_fid = p_tx_cid->opaque_fid;
  726. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  727. rc = qed_sp_init_request(p_hwfn, &p_ent,
  728. ETH_RAMROD_TX_QUEUE_STOP,
  729. PROTOCOLID_ETH, &init_data);
  730. if (rc)
  731. return rc;
  732. rc = qed_spq_post(p_hwfn, p_ent, NULL);
  733. if (rc)
  734. return rc;
  735. return qed_sp_release_queue_cid(p_hwfn, p_tx_cid);
  736. }
  737. static enum eth_filter_action qed_filter_action(enum qed_filter_opcode opcode)
  738. {
  739. enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
  740. switch (opcode) {
  741. case QED_FILTER_ADD:
  742. action = ETH_FILTER_ACTION_ADD;
  743. break;
  744. case QED_FILTER_REMOVE:
  745. action = ETH_FILTER_ACTION_REMOVE;
  746. break;
  747. case QED_FILTER_FLUSH:
  748. action = ETH_FILTER_ACTION_REMOVE_ALL;
  749. break;
  750. default:
  751. action = MAX_ETH_FILTER_ACTION;
  752. }
  753. return action;
  754. }
  755. static void qed_set_fw_mac_addr(__le16 *fw_msb,
  756. __le16 *fw_mid,
  757. __le16 *fw_lsb,
  758. u8 *mac)
  759. {
  760. ((u8 *)fw_msb)[0] = mac[1];
  761. ((u8 *)fw_msb)[1] = mac[0];
  762. ((u8 *)fw_mid)[0] = mac[3];
  763. ((u8 *)fw_mid)[1] = mac[2];
  764. ((u8 *)fw_lsb)[0] = mac[5];
  765. ((u8 *)fw_lsb)[1] = mac[4];
  766. }
  767. static int
  768. qed_filter_ucast_common(struct qed_hwfn *p_hwfn,
  769. u16 opaque_fid,
  770. struct qed_filter_ucast *p_filter_cmd,
  771. struct vport_filter_update_ramrod_data **pp_ramrod,
  772. struct qed_spq_entry **pp_ent,
  773. enum spq_mode comp_mode,
  774. struct qed_spq_comp_cb *p_comp_data)
  775. {
  776. u8 vport_to_add_to = 0, vport_to_remove_from = 0;
  777. struct vport_filter_update_ramrod_data *p_ramrod;
  778. struct eth_filter_cmd *p_first_filter;
  779. struct eth_filter_cmd *p_second_filter;
  780. struct qed_sp_init_data init_data;
  781. enum eth_filter_action action;
  782. int rc;
  783. rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
  784. &vport_to_remove_from);
  785. if (rc)
  786. return rc;
  787. rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
  788. &vport_to_add_to);
  789. if (rc)
  790. return rc;
  791. /* Get SPQ entry */
  792. memset(&init_data, 0, sizeof(init_data));
  793. init_data.cid = qed_spq_get_cid(p_hwfn);
  794. init_data.opaque_fid = opaque_fid;
  795. init_data.comp_mode = comp_mode;
  796. init_data.p_comp_data = p_comp_data;
  797. rc = qed_sp_init_request(p_hwfn, pp_ent,
  798. ETH_RAMROD_FILTERS_UPDATE,
  799. PROTOCOLID_ETH, &init_data);
  800. if (rc)
  801. return rc;
  802. *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
  803. p_ramrod = *pp_ramrod;
  804. p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
  805. p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
  806. switch (p_filter_cmd->opcode) {
  807. case QED_FILTER_REPLACE:
  808. case QED_FILTER_MOVE:
  809. p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break;
  810. default:
  811. p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break;
  812. }
  813. p_first_filter = &p_ramrod->filter_cmds[0];
  814. p_second_filter = &p_ramrod->filter_cmds[1];
  815. switch (p_filter_cmd->type) {
  816. case QED_FILTER_MAC:
  817. p_first_filter->type = ETH_FILTER_TYPE_MAC; break;
  818. case QED_FILTER_VLAN:
  819. p_first_filter->type = ETH_FILTER_TYPE_VLAN; break;
  820. case QED_FILTER_MAC_VLAN:
  821. p_first_filter->type = ETH_FILTER_TYPE_PAIR; break;
  822. case QED_FILTER_INNER_MAC:
  823. p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break;
  824. case QED_FILTER_INNER_VLAN:
  825. p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break;
  826. case QED_FILTER_INNER_PAIR:
  827. p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break;
  828. case QED_FILTER_INNER_MAC_VNI_PAIR:
  829. p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
  830. break;
  831. case QED_FILTER_MAC_VNI_PAIR:
  832. p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break;
  833. case QED_FILTER_VNI:
  834. p_first_filter->type = ETH_FILTER_TYPE_VNI; break;
  835. }
  836. if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
  837. (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
  838. (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
  839. (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
  840. (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
  841. (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) {
  842. qed_set_fw_mac_addr(&p_first_filter->mac_msb,
  843. &p_first_filter->mac_mid,
  844. &p_first_filter->mac_lsb,
  845. (u8 *)p_filter_cmd->mac);
  846. }
  847. if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
  848. (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
  849. (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
  850. (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
  851. p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan);
  852. if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
  853. (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
  854. (p_first_filter->type == ETH_FILTER_TYPE_VNI))
  855. p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni);
  856. if (p_filter_cmd->opcode == QED_FILTER_MOVE) {
  857. p_second_filter->type = p_first_filter->type;
  858. p_second_filter->mac_msb = p_first_filter->mac_msb;
  859. p_second_filter->mac_mid = p_first_filter->mac_mid;
  860. p_second_filter->mac_lsb = p_first_filter->mac_lsb;
  861. p_second_filter->vlan_id = p_first_filter->vlan_id;
  862. p_second_filter->vni = p_first_filter->vni;
  863. p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
  864. p_first_filter->vport_id = vport_to_remove_from;
  865. p_second_filter->action = ETH_FILTER_ACTION_ADD;
  866. p_second_filter->vport_id = vport_to_add_to;
  867. } else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) {
  868. p_first_filter->vport_id = vport_to_add_to;
  869. memcpy(p_second_filter, p_first_filter,
  870. sizeof(*p_second_filter));
  871. p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL;
  872. p_second_filter->action = ETH_FILTER_ACTION_ADD;
  873. } else {
  874. action = qed_filter_action(p_filter_cmd->opcode);
  875. if (action == MAX_ETH_FILTER_ACTION) {
  876. DP_NOTICE(p_hwfn,
  877. "%d is not supported yet\n",
  878. p_filter_cmd->opcode);
  879. return -EINVAL;
  880. }
  881. p_first_filter->action = action;
  882. p_first_filter->vport_id = (p_filter_cmd->opcode ==
  883. QED_FILTER_REMOVE) ?
  884. vport_to_remove_from :
  885. vport_to_add_to;
  886. }
  887. return 0;
  888. }
  889. int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn,
  890. u16 opaque_fid,
  891. struct qed_filter_ucast *p_filter_cmd,
  892. enum spq_mode comp_mode,
  893. struct qed_spq_comp_cb *p_comp_data)
  894. {
  895. struct vport_filter_update_ramrod_data *p_ramrod = NULL;
  896. struct qed_spq_entry *p_ent = NULL;
  897. struct eth_filter_cmd_header *p_header;
  898. int rc;
  899. rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
  900. &p_ramrod, &p_ent,
  901. comp_mode, p_comp_data);
  902. if (rc) {
  903. DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
  904. return rc;
  905. }
  906. p_header = &p_ramrod->filter_cmd_hdr;
  907. p_header->assert_on_error = p_filter_cmd->assert_on_error;
  908. rc = qed_spq_post(p_hwfn, p_ent, NULL);
  909. if (rc) {
  910. DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc);
  911. return rc;
  912. }
  913. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  914. "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
  915. (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" :
  916. ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ?
  917. "REMOVE" :
  918. ((p_filter_cmd->opcode == QED_FILTER_MOVE) ?
  919. "MOVE" : "REPLACE")),
  920. (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" :
  921. ((p_filter_cmd->type == QED_FILTER_VLAN) ?
  922. "VLAN" : "MAC & VLAN"),
  923. p_ramrod->filter_cmd_hdr.cmd_cnt,
  924. p_filter_cmd->is_rx_filter,
  925. p_filter_cmd->is_tx_filter);
  926. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  927. "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
  928. p_filter_cmd->vport_to_add_to,
  929. p_filter_cmd->vport_to_remove_from,
  930. p_filter_cmd->mac[0],
  931. p_filter_cmd->mac[1],
  932. p_filter_cmd->mac[2],
  933. p_filter_cmd->mac[3],
  934. p_filter_cmd->mac[4],
  935. p_filter_cmd->mac[5],
  936. p_filter_cmd->vlan);
  937. return 0;
  938. }
  939. /*******************************************************************************
  940. * Description:
  941. * Calculates crc 32 on a buffer
  942. * Note: crc32_length MUST be aligned to 8
  943. * Return:
  944. ******************************************************************************/
  945. static u32 qed_calc_crc32c(u8 *crc32_packet,
  946. u32 crc32_length, u32 crc32_seed, u8 complement)
  947. {
  948. u32 byte = 0, bit = 0, crc32_result = crc32_seed;
  949. u8 msb = 0, current_byte = 0;
  950. if ((!crc32_packet) ||
  951. (crc32_length == 0) ||
  952. ((crc32_length % 8) != 0))
  953. return crc32_result;
  954. for (byte = 0; byte < crc32_length; byte++) {
  955. current_byte = crc32_packet[byte];
  956. for (bit = 0; bit < 8; bit++) {
  957. msb = (u8)(crc32_result >> 31);
  958. crc32_result = crc32_result << 1;
  959. if (msb != (0x1 & (current_byte >> bit))) {
  960. crc32_result = crc32_result ^ CRC32_POLY;
  961. crc32_result |= 1; /*crc32_result[0] = 1;*/
  962. }
  963. }
  964. }
  965. return crc32_result;
  966. }
  967. static u32 qed_crc32c_le(u32 seed, u8 *mac, u32 len)
  968. {
  969. u32 packet_buf[2] = { 0 };
  970. memcpy((u8 *)(&packet_buf[0]), &mac[0], 6);
  971. return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
  972. }
  973. u8 qed_mcast_bin_from_mac(u8 *mac)
  974. {
  975. u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
  976. mac, ETH_ALEN);
  977. return crc & 0xff;
  978. }
  979. static int
  980. qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn,
  981. u16 opaque_fid,
  982. struct qed_filter_mcast *p_filter_cmd,
  983. enum spq_mode comp_mode,
  984. struct qed_spq_comp_cb *p_comp_data)
  985. {
  986. unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
  987. struct vport_update_ramrod_data *p_ramrod = NULL;
  988. struct qed_spq_entry *p_ent = NULL;
  989. struct qed_sp_init_data init_data;
  990. u8 abs_vport_id = 0;
  991. int rc, i;
  992. if (p_filter_cmd->opcode == QED_FILTER_ADD)
  993. rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
  994. &abs_vport_id);
  995. else
  996. rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
  997. &abs_vport_id);
  998. if (rc)
  999. return rc;
  1000. /* Get SPQ entry */
  1001. memset(&init_data, 0, sizeof(init_data));
  1002. init_data.cid = qed_spq_get_cid(p_hwfn);
  1003. init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
  1004. init_data.comp_mode = comp_mode;
  1005. init_data.p_comp_data = p_comp_data;
  1006. rc = qed_sp_init_request(p_hwfn, &p_ent,
  1007. ETH_RAMROD_VPORT_UPDATE,
  1008. PROTOCOLID_ETH, &init_data);
  1009. if (rc) {
  1010. DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
  1011. return rc;
  1012. }
  1013. p_ramrod = &p_ent->ramrod.vport_update;
  1014. p_ramrod->common.update_approx_mcast_flg = 1;
  1015. /* explicitly clear out the entire vector */
  1016. memset(&p_ramrod->approx_mcast.bins, 0,
  1017. sizeof(p_ramrod->approx_mcast.bins));
  1018. memset(bins, 0, sizeof(unsigned long) *
  1019. ETH_MULTICAST_MAC_BINS_IN_REGS);
  1020. /* filter ADD op is explicit set op and it removes
  1021. * any existing filters for the vport
  1022. */
  1023. if (p_filter_cmd->opcode == QED_FILTER_ADD) {
  1024. for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
  1025. u32 bit;
  1026. bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]);
  1027. __set_bit(bit, bins);
  1028. }
  1029. /* Convert to correct endianity */
  1030. for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
  1031. struct vport_update_ramrod_mcast *p_ramrod_bins;
  1032. u32 *p_bins = (u32 *)bins;
  1033. p_ramrod_bins = &p_ramrod->approx_mcast;
  1034. p_ramrod_bins->bins[i] = cpu_to_le32(p_bins[i]);
  1035. }
  1036. }
  1037. p_ramrod->common.vport_id = abs_vport_id;
  1038. return qed_spq_post(p_hwfn, p_ent, NULL);
  1039. }
  1040. static int qed_filter_mcast_cmd(struct qed_dev *cdev,
  1041. struct qed_filter_mcast *p_filter_cmd,
  1042. enum spq_mode comp_mode,
  1043. struct qed_spq_comp_cb *p_comp_data)
  1044. {
  1045. int rc = 0;
  1046. int i;
  1047. /* only ADD and REMOVE operations are supported for multi-cast */
  1048. if ((p_filter_cmd->opcode != QED_FILTER_ADD &&
  1049. (p_filter_cmd->opcode != QED_FILTER_REMOVE)) ||
  1050. (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS))
  1051. return -EINVAL;
  1052. for_each_hwfn(cdev, i) {
  1053. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1054. u16 opaque_fid;
  1055. if (IS_VF(cdev)) {
  1056. qed_vf_pf_filter_mcast(p_hwfn, p_filter_cmd);
  1057. continue;
  1058. }
  1059. opaque_fid = p_hwfn->hw_info.opaque_fid;
  1060. rc = qed_sp_eth_filter_mcast(p_hwfn,
  1061. opaque_fid,
  1062. p_filter_cmd,
  1063. comp_mode, p_comp_data);
  1064. }
  1065. return rc;
  1066. }
  1067. static int qed_filter_ucast_cmd(struct qed_dev *cdev,
  1068. struct qed_filter_ucast *p_filter_cmd,
  1069. enum spq_mode comp_mode,
  1070. struct qed_spq_comp_cb *p_comp_data)
  1071. {
  1072. int rc = 0;
  1073. int i;
  1074. for_each_hwfn(cdev, i) {
  1075. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1076. u16 opaque_fid;
  1077. if (IS_VF(cdev)) {
  1078. rc = qed_vf_pf_filter_ucast(p_hwfn, p_filter_cmd);
  1079. continue;
  1080. }
  1081. opaque_fid = p_hwfn->hw_info.opaque_fid;
  1082. rc = qed_sp_eth_filter_ucast(p_hwfn,
  1083. opaque_fid,
  1084. p_filter_cmd,
  1085. comp_mode, p_comp_data);
  1086. if (rc)
  1087. break;
  1088. }
  1089. return rc;
  1090. }
  1091. /* Statistics related code */
  1092. static void __qed_get_vport_pstats_addrlen(struct qed_hwfn *p_hwfn,
  1093. u32 *p_addr,
  1094. u32 *p_len, u16 statistics_bin)
  1095. {
  1096. if (IS_PF(p_hwfn->cdev)) {
  1097. *p_addr = BAR0_MAP_REG_PSDM_RAM +
  1098. PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
  1099. *p_len = sizeof(struct eth_pstorm_per_queue_stat);
  1100. } else {
  1101. struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
  1102. struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
  1103. *p_addr = p_resp->pfdev_info.stats_info.pstats.address;
  1104. *p_len = p_resp->pfdev_info.stats_info.pstats.len;
  1105. }
  1106. }
  1107. static void __qed_get_vport_pstats(struct qed_hwfn *p_hwfn,
  1108. struct qed_ptt *p_ptt,
  1109. struct qed_eth_stats *p_stats,
  1110. u16 statistics_bin)
  1111. {
  1112. struct eth_pstorm_per_queue_stat pstats;
  1113. u32 pstats_addr = 0, pstats_len = 0;
  1114. __qed_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
  1115. statistics_bin);
  1116. memset(&pstats, 0, sizeof(pstats));
  1117. qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);
  1118. p_stats->tx_ucast_bytes += HILO_64_REGPAIR(pstats.sent_ucast_bytes);
  1119. p_stats->tx_mcast_bytes += HILO_64_REGPAIR(pstats.sent_mcast_bytes);
  1120. p_stats->tx_bcast_bytes += HILO_64_REGPAIR(pstats.sent_bcast_bytes);
  1121. p_stats->tx_ucast_pkts += HILO_64_REGPAIR(pstats.sent_ucast_pkts);
  1122. p_stats->tx_mcast_pkts += HILO_64_REGPAIR(pstats.sent_mcast_pkts);
  1123. p_stats->tx_bcast_pkts += HILO_64_REGPAIR(pstats.sent_bcast_pkts);
  1124. p_stats->tx_err_drop_pkts += HILO_64_REGPAIR(pstats.error_drop_pkts);
  1125. }
  1126. static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn,
  1127. struct qed_ptt *p_ptt,
  1128. struct qed_eth_stats *p_stats,
  1129. u16 statistics_bin)
  1130. {
  1131. struct tstorm_per_port_stat tstats;
  1132. u32 tstats_addr, tstats_len;
  1133. if (IS_PF(p_hwfn->cdev)) {
  1134. tstats_addr = BAR0_MAP_REG_TSDM_RAM +
  1135. TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
  1136. tstats_len = sizeof(struct tstorm_per_port_stat);
  1137. } else {
  1138. struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
  1139. struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
  1140. tstats_addr = p_resp->pfdev_info.stats_info.tstats.address;
  1141. tstats_len = p_resp->pfdev_info.stats_info.tstats.len;
  1142. }
  1143. memset(&tstats, 0, sizeof(tstats));
  1144. qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);
  1145. p_stats->mftag_filter_discards +=
  1146. HILO_64_REGPAIR(tstats.mftag_filter_discard);
  1147. p_stats->mac_filter_discards +=
  1148. HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
  1149. }
  1150. static void __qed_get_vport_ustats_addrlen(struct qed_hwfn *p_hwfn,
  1151. u32 *p_addr,
  1152. u32 *p_len, u16 statistics_bin)
  1153. {
  1154. if (IS_PF(p_hwfn->cdev)) {
  1155. *p_addr = BAR0_MAP_REG_USDM_RAM +
  1156. USTORM_QUEUE_STAT_OFFSET(statistics_bin);
  1157. *p_len = sizeof(struct eth_ustorm_per_queue_stat);
  1158. } else {
  1159. struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
  1160. struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
  1161. *p_addr = p_resp->pfdev_info.stats_info.ustats.address;
  1162. *p_len = p_resp->pfdev_info.stats_info.ustats.len;
  1163. }
  1164. }
  1165. static void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn,
  1166. struct qed_ptt *p_ptt,
  1167. struct qed_eth_stats *p_stats,
  1168. u16 statistics_bin)
  1169. {
  1170. struct eth_ustorm_per_queue_stat ustats;
  1171. u32 ustats_addr = 0, ustats_len = 0;
  1172. __qed_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
  1173. statistics_bin);
  1174. memset(&ustats, 0, sizeof(ustats));
  1175. qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);
  1176. p_stats->rx_ucast_bytes += HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
  1177. p_stats->rx_mcast_bytes += HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
  1178. p_stats->rx_bcast_bytes += HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
  1179. p_stats->rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
  1180. p_stats->rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
  1181. p_stats->rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
  1182. }
  1183. static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn,
  1184. u32 *p_addr,
  1185. u32 *p_len, u16 statistics_bin)
  1186. {
  1187. if (IS_PF(p_hwfn->cdev)) {
  1188. *p_addr = BAR0_MAP_REG_MSDM_RAM +
  1189. MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
  1190. *p_len = sizeof(struct eth_mstorm_per_queue_stat);
  1191. } else {
  1192. struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
  1193. struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
  1194. *p_addr = p_resp->pfdev_info.stats_info.mstats.address;
  1195. *p_len = p_resp->pfdev_info.stats_info.mstats.len;
  1196. }
  1197. }
  1198. static void __qed_get_vport_mstats(struct qed_hwfn *p_hwfn,
  1199. struct qed_ptt *p_ptt,
  1200. struct qed_eth_stats *p_stats,
  1201. u16 statistics_bin)
  1202. {
  1203. struct eth_mstorm_per_queue_stat mstats;
  1204. u32 mstats_addr = 0, mstats_len = 0;
  1205. __qed_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
  1206. statistics_bin);
  1207. memset(&mstats, 0, sizeof(mstats));
  1208. qed_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);
  1209. p_stats->no_buff_discards += HILO_64_REGPAIR(mstats.no_buff_discard);
  1210. p_stats->packet_too_big_discard +=
  1211. HILO_64_REGPAIR(mstats.packet_too_big_discard);
  1212. p_stats->ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard);
  1213. p_stats->tpa_coalesced_pkts +=
  1214. HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
  1215. p_stats->tpa_coalesced_events +=
  1216. HILO_64_REGPAIR(mstats.tpa_coalesced_events);
  1217. p_stats->tpa_aborts_num += HILO_64_REGPAIR(mstats.tpa_aborts_num);
  1218. p_stats->tpa_coalesced_bytes +=
  1219. HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
  1220. }
  1221. static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn,
  1222. struct qed_ptt *p_ptt,
  1223. struct qed_eth_stats *p_stats)
  1224. {
  1225. struct port_stats port_stats;
  1226. int j;
  1227. memset(&port_stats, 0, sizeof(port_stats));
  1228. qed_memcpy_from(p_hwfn, p_ptt, &port_stats,
  1229. p_hwfn->mcp_info->port_addr +
  1230. offsetof(struct public_port, stats),
  1231. sizeof(port_stats));
  1232. p_stats->rx_64_byte_packets += port_stats.eth.r64;
  1233. p_stats->rx_65_to_127_byte_packets += port_stats.eth.r127;
  1234. p_stats->rx_128_to_255_byte_packets += port_stats.eth.r255;
  1235. p_stats->rx_256_to_511_byte_packets += port_stats.eth.r511;
  1236. p_stats->rx_512_to_1023_byte_packets += port_stats.eth.r1023;
  1237. p_stats->rx_1024_to_1518_byte_packets += port_stats.eth.r1518;
  1238. p_stats->rx_1519_to_1522_byte_packets += port_stats.eth.r1522;
  1239. p_stats->rx_1519_to_2047_byte_packets += port_stats.eth.r2047;
  1240. p_stats->rx_2048_to_4095_byte_packets += port_stats.eth.r4095;
  1241. p_stats->rx_4096_to_9216_byte_packets += port_stats.eth.r9216;
  1242. p_stats->rx_9217_to_16383_byte_packets += port_stats.eth.r16383;
  1243. p_stats->rx_crc_errors += port_stats.eth.rfcs;
  1244. p_stats->rx_mac_crtl_frames += port_stats.eth.rxcf;
  1245. p_stats->rx_pause_frames += port_stats.eth.rxpf;
  1246. p_stats->rx_pfc_frames += port_stats.eth.rxpp;
  1247. p_stats->rx_align_errors += port_stats.eth.raln;
  1248. p_stats->rx_carrier_errors += port_stats.eth.rfcr;
  1249. p_stats->rx_oversize_packets += port_stats.eth.rovr;
  1250. p_stats->rx_jabbers += port_stats.eth.rjbr;
  1251. p_stats->rx_undersize_packets += port_stats.eth.rund;
  1252. p_stats->rx_fragments += port_stats.eth.rfrg;
  1253. p_stats->tx_64_byte_packets += port_stats.eth.t64;
  1254. p_stats->tx_65_to_127_byte_packets += port_stats.eth.t127;
  1255. p_stats->tx_128_to_255_byte_packets += port_stats.eth.t255;
  1256. p_stats->tx_256_to_511_byte_packets += port_stats.eth.t511;
  1257. p_stats->tx_512_to_1023_byte_packets += port_stats.eth.t1023;
  1258. p_stats->tx_1024_to_1518_byte_packets += port_stats.eth.t1518;
  1259. p_stats->tx_1519_to_2047_byte_packets += port_stats.eth.t2047;
  1260. p_stats->tx_2048_to_4095_byte_packets += port_stats.eth.t4095;
  1261. p_stats->tx_4096_to_9216_byte_packets += port_stats.eth.t9216;
  1262. p_stats->tx_9217_to_16383_byte_packets += port_stats.eth.t16383;
  1263. p_stats->tx_pause_frames += port_stats.eth.txpf;
  1264. p_stats->tx_pfc_frames += port_stats.eth.txpp;
  1265. p_stats->tx_lpi_entry_count += port_stats.eth.tlpiec;
  1266. p_stats->tx_total_collisions += port_stats.eth.tncl;
  1267. p_stats->rx_mac_bytes += port_stats.eth.rbyte;
  1268. p_stats->rx_mac_uc_packets += port_stats.eth.rxuca;
  1269. p_stats->rx_mac_mc_packets += port_stats.eth.rxmca;
  1270. p_stats->rx_mac_bc_packets += port_stats.eth.rxbca;
  1271. p_stats->rx_mac_frames_ok += port_stats.eth.rxpok;
  1272. p_stats->tx_mac_bytes += port_stats.eth.tbyte;
  1273. p_stats->tx_mac_uc_packets += port_stats.eth.txuca;
  1274. p_stats->tx_mac_mc_packets += port_stats.eth.txmca;
  1275. p_stats->tx_mac_bc_packets += port_stats.eth.txbca;
  1276. p_stats->tx_mac_ctrl_frames += port_stats.eth.txcf;
  1277. for (j = 0; j < 8; j++) {
  1278. p_stats->brb_truncates += port_stats.brb.brb_truncate[j];
  1279. p_stats->brb_discards += port_stats.brb.brb_discard[j];
  1280. }
  1281. }
  1282. static void __qed_get_vport_stats(struct qed_hwfn *p_hwfn,
  1283. struct qed_ptt *p_ptt,
  1284. struct qed_eth_stats *stats,
  1285. u16 statistics_bin, bool b_get_port_stats)
  1286. {
  1287. __qed_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
  1288. __qed_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
  1289. __qed_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin);
  1290. __qed_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
  1291. if (b_get_port_stats && p_hwfn->mcp_info)
  1292. __qed_get_vport_port_stats(p_hwfn, p_ptt, stats);
  1293. }
  1294. static void _qed_get_vport_stats(struct qed_dev *cdev,
  1295. struct qed_eth_stats *stats)
  1296. {
  1297. u8 fw_vport = 0;
  1298. int i;
  1299. memset(stats, 0, sizeof(*stats));
  1300. for_each_hwfn(cdev, i) {
  1301. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1302. struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
  1303. : NULL;
  1304. if (IS_PF(cdev)) {
  1305. /* The main vport index is relative first */
  1306. if (qed_fw_vport(p_hwfn, 0, &fw_vport)) {
  1307. DP_ERR(p_hwfn, "No vport available!\n");
  1308. goto out;
  1309. }
  1310. }
  1311. if (IS_PF(cdev) && !p_ptt) {
  1312. DP_ERR(p_hwfn, "Failed to acquire ptt\n");
  1313. continue;
  1314. }
  1315. __qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
  1316. IS_PF(cdev) ? true : false);
  1317. out:
  1318. if (IS_PF(cdev) && p_ptt)
  1319. qed_ptt_release(p_hwfn, p_ptt);
  1320. }
  1321. }
  1322. void qed_get_vport_stats(struct qed_dev *cdev, struct qed_eth_stats *stats)
  1323. {
  1324. u32 i;
  1325. if (!cdev) {
  1326. memset(stats, 0, sizeof(*stats));
  1327. return;
  1328. }
  1329. _qed_get_vport_stats(cdev, stats);
  1330. if (!cdev->reset_stats)
  1331. return;
  1332. /* Reduce the statistics baseline */
  1333. for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++)
  1334. ((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i];
  1335. }
  1336. /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
  1337. void qed_reset_vport_stats(struct qed_dev *cdev)
  1338. {
  1339. int i;
  1340. for_each_hwfn(cdev, i) {
  1341. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1342. struct eth_mstorm_per_queue_stat mstats;
  1343. struct eth_ustorm_per_queue_stat ustats;
  1344. struct eth_pstorm_per_queue_stat pstats;
  1345. struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
  1346. : NULL;
  1347. u32 addr = 0, len = 0;
  1348. if (IS_PF(cdev) && !p_ptt) {
  1349. DP_ERR(p_hwfn, "Failed to acquire ptt\n");
  1350. continue;
  1351. }
  1352. memset(&mstats, 0, sizeof(mstats));
  1353. __qed_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
  1354. qed_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
  1355. memset(&ustats, 0, sizeof(ustats));
  1356. __qed_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
  1357. qed_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
  1358. memset(&pstats, 0, sizeof(pstats));
  1359. __qed_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
  1360. qed_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
  1361. if (IS_PF(cdev))
  1362. qed_ptt_release(p_hwfn, p_ptt);
  1363. }
  1364. /* PORT statistics are not necessarily reset, so we need to
  1365. * read and create a baseline for future statistics.
  1366. */
  1367. if (!cdev->reset_stats)
  1368. DP_INFO(cdev, "Reset stats not allocated\n");
  1369. else
  1370. _qed_get_vport_stats(cdev, cdev->reset_stats);
  1371. }
  1372. static int qed_fill_eth_dev_info(struct qed_dev *cdev,
  1373. struct qed_dev_eth_info *info)
  1374. {
  1375. int i;
  1376. memset(info, 0, sizeof(*info));
  1377. info->num_tc = 1;
  1378. if (IS_PF(cdev)) {
  1379. int max_vf_vlan_filters = 0;
  1380. if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
  1381. for_each_hwfn(cdev, i)
  1382. info->num_queues +=
  1383. FEAT_NUM(&cdev->hwfns[i], QED_PF_L2_QUE);
  1384. if (cdev->int_params.fp_msix_cnt)
  1385. info->num_queues =
  1386. min_t(u8, info->num_queues,
  1387. cdev->int_params.fp_msix_cnt);
  1388. } else {
  1389. info->num_queues = cdev->num_hwfns;
  1390. }
  1391. if (IS_QED_SRIOV(cdev))
  1392. max_vf_vlan_filters = cdev->p_iov_info->total_vfs *
  1393. QED_ETH_VF_NUM_VLAN_FILTERS;
  1394. info->num_vlan_filters = RESC_NUM(&cdev->hwfns[0], QED_VLAN) -
  1395. max_vf_vlan_filters;
  1396. ether_addr_copy(info->port_mac,
  1397. cdev->hwfns[0].hw_info.hw_mac_addr);
  1398. } else {
  1399. qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev), &info->num_queues);
  1400. if (cdev->num_hwfns > 1) {
  1401. u8 queues = 0;
  1402. qed_vf_get_num_rxqs(&cdev->hwfns[1], &queues);
  1403. info->num_queues += queues;
  1404. }
  1405. qed_vf_get_num_vlan_filters(&cdev->hwfns[0],
  1406. &info->num_vlan_filters);
  1407. qed_vf_get_port_mac(&cdev->hwfns[0], info->port_mac);
  1408. info->is_legacy = !!cdev->hwfns[0].vf_iov_info->b_pre_fp_hsi;
  1409. }
  1410. qed_fill_dev_info(cdev, &info->common);
  1411. if (IS_VF(cdev))
  1412. memset(info->common.hw_mac, 0, ETH_ALEN);
  1413. return 0;
  1414. }
  1415. static void qed_register_eth_ops(struct qed_dev *cdev,
  1416. struct qed_eth_cb_ops *ops, void *cookie)
  1417. {
  1418. cdev->protocol_ops.eth = ops;
  1419. cdev->ops_cookie = cookie;
  1420. /* For VF, we start bulletin reading */
  1421. if (IS_VF(cdev))
  1422. qed_vf_start_iov_wq(cdev);
  1423. }
  1424. static bool qed_check_mac(struct qed_dev *cdev, u8 *mac)
  1425. {
  1426. if (IS_PF(cdev))
  1427. return true;
  1428. return qed_vf_check_mac(&cdev->hwfns[0], mac);
  1429. }
  1430. static int qed_start_vport(struct qed_dev *cdev,
  1431. struct qed_start_vport_params *params)
  1432. {
  1433. int rc, i;
  1434. for_each_hwfn(cdev, i) {
  1435. struct qed_sp_vport_start_params start = { 0 };
  1436. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1437. start.tpa_mode = params->gro_enable ? QED_TPA_MODE_GRO :
  1438. QED_TPA_MODE_NONE;
  1439. start.remove_inner_vlan = params->remove_inner_vlan;
  1440. start.only_untagged = true; /* untagged only */
  1441. start.drop_ttl0 = params->drop_ttl0;
  1442. start.opaque_fid = p_hwfn->hw_info.opaque_fid;
  1443. start.concrete_fid = p_hwfn->hw_info.concrete_fid;
  1444. start.vport_id = params->vport_id;
  1445. start.max_buffers_per_cqe = 16;
  1446. start.mtu = params->mtu;
  1447. rc = qed_sp_vport_start(p_hwfn, &start);
  1448. if (rc) {
  1449. DP_ERR(cdev, "Failed to start VPORT\n");
  1450. return rc;
  1451. }
  1452. qed_hw_start_fastpath(p_hwfn);
  1453. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  1454. "Started V-PORT %d with MTU %d\n",
  1455. start.vport_id, start.mtu);
  1456. }
  1457. if (params->clear_stats)
  1458. qed_reset_vport_stats(cdev);
  1459. return 0;
  1460. }
  1461. static int qed_stop_vport(struct qed_dev *cdev, u8 vport_id)
  1462. {
  1463. int rc, i;
  1464. for_each_hwfn(cdev, i) {
  1465. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1466. rc = qed_sp_vport_stop(p_hwfn,
  1467. p_hwfn->hw_info.opaque_fid, vport_id);
  1468. if (rc) {
  1469. DP_ERR(cdev, "Failed to stop VPORT\n");
  1470. return rc;
  1471. }
  1472. }
  1473. return 0;
  1474. }
  1475. static int qed_update_vport(struct qed_dev *cdev,
  1476. struct qed_update_vport_params *params)
  1477. {
  1478. struct qed_sp_vport_update_params sp_params;
  1479. struct qed_rss_params sp_rss_params;
  1480. int rc, i;
  1481. if (!cdev)
  1482. return -ENODEV;
  1483. memset(&sp_params, 0, sizeof(sp_params));
  1484. memset(&sp_rss_params, 0, sizeof(sp_rss_params));
  1485. /* Translate protocol params into sp params */
  1486. sp_params.vport_id = params->vport_id;
  1487. sp_params.update_vport_active_rx_flg = params->update_vport_active_flg;
  1488. sp_params.update_vport_active_tx_flg = params->update_vport_active_flg;
  1489. sp_params.vport_active_rx_flg = params->vport_active_flg;
  1490. sp_params.vport_active_tx_flg = params->vport_active_flg;
  1491. sp_params.update_tx_switching_flg = params->update_tx_switching_flg;
  1492. sp_params.tx_switching_flg = params->tx_switching_flg;
  1493. sp_params.accept_any_vlan = params->accept_any_vlan;
  1494. sp_params.update_accept_any_vlan_flg =
  1495. params->update_accept_any_vlan_flg;
  1496. /* RSS - is a bit tricky, since upper-layer isn't familiar with hwfns.
  1497. * We need to re-fix the rss values per engine for CMT.
  1498. */
  1499. if (cdev->num_hwfns > 1 && params->update_rss_flg) {
  1500. struct qed_update_vport_rss_params *rss = &params->rss_params;
  1501. int k, max = 0;
  1502. /* Find largest entry, since it's possible RSS needs to
  1503. * be disabled [in case only 1 queue per-hwfn]
  1504. */
  1505. for (k = 0; k < QED_RSS_IND_TABLE_SIZE; k++)
  1506. max = (max > rss->rss_ind_table[k]) ?
  1507. max : rss->rss_ind_table[k];
  1508. /* Either fix RSS values or disable RSS */
  1509. if (cdev->num_hwfns < max + 1) {
  1510. int divisor = (max + cdev->num_hwfns - 1) /
  1511. cdev->num_hwfns;
  1512. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  1513. "CMT - fixing RSS values (modulo %02x)\n",
  1514. divisor);
  1515. for (k = 0; k < QED_RSS_IND_TABLE_SIZE; k++)
  1516. rss->rss_ind_table[k] =
  1517. rss->rss_ind_table[k] % divisor;
  1518. } else {
  1519. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  1520. "CMT - 1 queue per-hwfn; Disabling RSS\n");
  1521. params->update_rss_flg = 0;
  1522. }
  1523. }
  1524. /* Now, update the RSS configuration for actual configuration */
  1525. if (params->update_rss_flg) {
  1526. sp_rss_params.update_rss_config = 1;
  1527. sp_rss_params.rss_enable = 1;
  1528. sp_rss_params.update_rss_capabilities = 1;
  1529. sp_rss_params.update_rss_ind_table = 1;
  1530. sp_rss_params.update_rss_key = 1;
  1531. sp_rss_params.rss_caps = params->rss_params.rss_caps;
  1532. sp_rss_params.rss_table_size_log = 7; /* 2^7 = 128 */
  1533. memcpy(sp_rss_params.rss_ind_table,
  1534. params->rss_params.rss_ind_table,
  1535. QED_RSS_IND_TABLE_SIZE * sizeof(u16));
  1536. memcpy(sp_rss_params.rss_key, params->rss_params.rss_key,
  1537. QED_RSS_KEY_SIZE * sizeof(u32));
  1538. sp_params.rss_params = &sp_rss_params;
  1539. }
  1540. for_each_hwfn(cdev, i) {
  1541. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1542. sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
  1543. rc = qed_sp_vport_update(p_hwfn, &sp_params,
  1544. QED_SPQ_MODE_EBLOCK,
  1545. NULL);
  1546. if (rc) {
  1547. DP_ERR(cdev, "Failed to update VPORT\n");
  1548. return rc;
  1549. }
  1550. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  1551. "Updated V-PORT %d: active_flag %d [update %d]\n",
  1552. params->vport_id, params->vport_active_flg,
  1553. params->update_vport_active_flg);
  1554. }
  1555. return 0;
  1556. }
  1557. static int qed_start_rxq(struct qed_dev *cdev,
  1558. struct qed_queue_start_common_params *params,
  1559. u16 bd_max_bytes,
  1560. dma_addr_t bd_chain_phys_addr,
  1561. dma_addr_t cqe_pbl_addr,
  1562. u16 cqe_pbl_size,
  1563. void __iomem **pp_prod)
  1564. {
  1565. struct qed_hwfn *p_hwfn;
  1566. int rc, hwfn_index;
  1567. hwfn_index = params->rss_id % cdev->num_hwfns;
  1568. p_hwfn = &cdev->hwfns[hwfn_index];
  1569. /* Fix queue ID in 100g mode */
  1570. params->queue_id /= cdev->num_hwfns;
  1571. rc = qed_sp_eth_rx_queue_start(p_hwfn,
  1572. p_hwfn->hw_info.opaque_fid,
  1573. params,
  1574. bd_max_bytes,
  1575. bd_chain_phys_addr,
  1576. cqe_pbl_addr,
  1577. cqe_pbl_size,
  1578. pp_prod);
  1579. if (rc) {
  1580. DP_ERR(cdev, "Failed to start RXQ#%d\n", params->queue_id);
  1581. return rc;
  1582. }
  1583. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  1584. "Started RX-Q %d [rss %d] on V-PORT %d and SB %d\n",
  1585. params->queue_id, params->rss_id, params->vport_id,
  1586. params->sb);
  1587. return 0;
  1588. }
  1589. static int qed_stop_rxq(struct qed_dev *cdev,
  1590. struct qed_stop_rxq_params *params)
  1591. {
  1592. int rc, hwfn_index;
  1593. struct qed_hwfn *p_hwfn;
  1594. hwfn_index = params->rss_id % cdev->num_hwfns;
  1595. p_hwfn = &cdev->hwfns[hwfn_index];
  1596. rc = qed_sp_eth_rx_queue_stop(p_hwfn,
  1597. params->rx_queue_id / cdev->num_hwfns,
  1598. params->eq_completion_only, false);
  1599. if (rc) {
  1600. DP_ERR(cdev, "Failed to stop RXQ#%d\n", params->rx_queue_id);
  1601. return rc;
  1602. }
  1603. return 0;
  1604. }
  1605. static int qed_start_txq(struct qed_dev *cdev,
  1606. struct qed_queue_start_common_params *p_params,
  1607. dma_addr_t pbl_addr,
  1608. u16 pbl_size,
  1609. void __iomem **pp_doorbell)
  1610. {
  1611. struct qed_hwfn *p_hwfn;
  1612. int rc, hwfn_index;
  1613. hwfn_index = p_params->rss_id % cdev->num_hwfns;
  1614. p_hwfn = &cdev->hwfns[hwfn_index];
  1615. /* Fix queue ID in 100g mode */
  1616. p_params->queue_id /= cdev->num_hwfns;
  1617. rc = qed_sp_eth_tx_queue_start(p_hwfn,
  1618. p_hwfn->hw_info.opaque_fid,
  1619. p_params,
  1620. pbl_addr,
  1621. pbl_size,
  1622. pp_doorbell);
  1623. if (rc) {
  1624. DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id);
  1625. return rc;
  1626. }
  1627. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  1628. "Started TX-Q %d [rss %d] on V-PORT %d and SB %d\n",
  1629. p_params->queue_id, p_params->rss_id, p_params->vport_id,
  1630. p_params->sb);
  1631. return 0;
  1632. }
  1633. #define QED_HW_STOP_RETRY_LIMIT (10)
  1634. static int qed_fastpath_stop(struct qed_dev *cdev)
  1635. {
  1636. qed_hw_stop_fastpath(cdev);
  1637. return 0;
  1638. }
  1639. static int qed_stop_txq(struct qed_dev *cdev,
  1640. struct qed_stop_txq_params *params)
  1641. {
  1642. struct qed_hwfn *p_hwfn;
  1643. int rc, hwfn_index;
  1644. hwfn_index = params->rss_id % cdev->num_hwfns;
  1645. p_hwfn = &cdev->hwfns[hwfn_index];
  1646. rc = qed_sp_eth_tx_queue_stop(p_hwfn,
  1647. params->tx_queue_id / cdev->num_hwfns);
  1648. if (rc) {
  1649. DP_ERR(cdev, "Failed to stop TXQ#%d\n", params->tx_queue_id);
  1650. return rc;
  1651. }
  1652. return 0;
  1653. }
  1654. static int qed_tunn_configure(struct qed_dev *cdev,
  1655. struct qed_tunn_params *tunn_params)
  1656. {
  1657. struct qed_tunn_update_params tunn_info;
  1658. int i, rc;
  1659. if (IS_VF(cdev))
  1660. return 0;
  1661. memset(&tunn_info, 0, sizeof(tunn_info));
  1662. if (tunn_params->update_vxlan_port == 1) {
  1663. tunn_info.update_vxlan_udp_port = 1;
  1664. tunn_info.vxlan_udp_port = tunn_params->vxlan_port;
  1665. }
  1666. if (tunn_params->update_geneve_port == 1) {
  1667. tunn_info.update_geneve_udp_port = 1;
  1668. tunn_info.geneve_udp_port = tunn_params->geneve_port;
  1669. }
  1670. for_each_hwfn(cdev, i) {
  1671. struct qed_hwfn *hwfn = &cdev->hwfns[i];
  1672. rc = qed_sp_pf_update_tunn_cfg(hwfn, &tunn_info,
  1673. QED_SPQ_MODE_EBLOCK, NULL);
  1674. if (rc)
  1675. return rc;
  1676. }
  1677. return 0;
  1678. }
  1679. static int qed_configure_filter_rx_mode(struct qed_dev *cdev,
  1680. enum qed_filter_rx_mode_type type)
  1681. {
  1682. struct qed_filter_accept_flags accept_flags;
  1683. memset(&accept_flags, 0, sizeof(accept_flags));
  1684. accept_flags.update_rx_mode_config = 1;
  1685. accept_flags.update_tx_mode_config = 1;
  1686. accept_flags.rx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
  1687. QED_ACCEPT_MCAST_MATCHED |
  1688. QED_ACCEPT_BCAST;
  1689. accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
  1690. QED_ACCEPT_MCAST_MATCHED |
  1691. QED_ACCEPT_BCAST;
  1692. if (type == QED_FILTER_RX_MODE_TYPE_PROMISC)
  1693. accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED |
  1694. QED_ACCEPT_MCAST_UNMATCHED;
  1695. else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC)
  1696. accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
  1697. return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false,
  1698. QED_SPQ_MODE_CB, NULL);
  1699. }
  1700. static int qed_configure_filter_ucast(struct qed_dev *cdev,
  1701. struct qed_filter_ucast_params *params)
  1702. {
  1703. struct qed_filter_ucast ucast;
  1704. if (!params->vlan_valid && !params->mac_valid) {
  1705. DP_NOTICE(cdev,
  1706. "Tried configuring a unicast filter, but both MAC and VLAN are not set\n");
  1707. return -EINVAL;
  1708. }
  1709. memset(&ucast, 0, sizeof(ucast));
  1710. switch (params->type) {
  1711. case QED_FILTER_XCAST_TYPE_ADD:
  1712. ucast.opcode = QED_FILTER_ADD;
  1713. break;
  1714. case QED_FILTER_XCAST_TYPE_DEL:
  1715. ucast.opcode = QED_FILTER_REMOVE;
  1716. break;
  1717. case QED_FILTER_XCAST_TYPE_REPLACE:
  1718. ucast.opcode = QED_FILTER_REPLACE;
  1719. break;
  1720. default:
  1721. DP_NOTICE(cdev, "Unknown unicast filter type %d\n",
  1722. params->type);
  1723. }
  1724. if (params->vlan_valid && params->mac_valid) {
  1725. ucast.type = QED_FILTER_MAC_VLAN;
  1726. ether_addr_copy(ucast.mac, params->mac);
  1727. ucast.vlan = params->vlan;
  1728. } else if (params->mac_valid) {
  1729. ucast.type = QED_FILTER_MAC;
  1730. ether_addr_copy(ucast.mac, params->mac);
  1731. } else {
  1732. ucast.type = QED_FILTER_VLAN;
  1733. ucast.vlan = params->vlan;
  1734. }
  1735. ucast.is_rx_filter = true;
  1736. ucast.is_tx_filter = true;
  1737. return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL);
  1738. }
  1739. static int qed_configure_filter_mcast(struct qed_dev *cdev,
  1740. struct qed_filter_mcast_params *params)
  1741. {
  1742. struct qed_filter_mcast mcast;
  1743. int i;
  1744. memset(&mcast, 0, sizeof(mcast));
  1745. switch (params->type) {
  1746. case QED_FILTER_XCAST_TYPE_ADD:
  1747. mcast.opcode = QED_FILTER_ADD;
  1748. break;
  1749. case QED_FILTER_XCAST_TYPE_DEL:
  1750. mcast.opcode = QED_FILTER_REMOVE;
  1751. break;
  1752. default:
  1753. DP_NOTICE(cdev, "Unknown multicast filter type %d\n",
  1754. params->type);
  1755. }
  1756. mcast.num_mc_addrs = params->num;
  1757. for (i = 0; i < mcast.num_mc_addrs; i++)
  1758. ether_addr_copy(mcast.mac[i], params->mac[i]);
  1759. return qed_filter_mcast_cmd(cdev, &mcast, QED_SPQ_MODE_CB, NULL);
  1760. }
  1761. static int qed_configure_filter(struct qed_dev *cdev,
  1762. struct qed_filter_params *params)
  1763. {
  1764. enum qed_filter_rx_mode_type accept_flags;
  1765. switch (params->type) {
  1766. case QED_FILTER_TYPE_UCAST:
  1767. return qed_configure_filter_ucast(cdev, &params->filter.ucast);
  1768. case QED_FILTER_TYPE_MCAST:
  1769. return qed_configure_filter_mcast(cdev, &params->filter.mcast);
  1770. case QED_FILTER_TYPE_RX_MODE:
  1771. accept_flags = params->filter.accept_flags;
  1772. return qed_configure_filter_rx_mode(cdev, accept_flags);
  1773. default:
  1774. DP_NOTICE(cdev, "Unknown filter type %d\n", (int)params->type);
  1775. return -EINVAL;
  1776. }
  1777. }
  1778. static int qed_fp_cqe_completion(struct qed_dev *dev,
  1779. u8 rss_id, struct eth_slow_path_rx_cqe *cqe)
  1780. {
  1781. return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns],
  1782. cqe);
  1783. }
  1784. #ifdef CONFIG_QED_SRIOV
  1785. extern const struct qed_iov_hv_ops qed_iov_ops_pass;
  1786. #endif
  1787. #ifdef CONFIG_DCB
  1788. extern const struct qed_eth_dcbnl_ops qed_dcbnl_ops_pass;
  1789. #endif
  1790. static const struct qed_eth_ops qed_eth_ops_pass = {
  1791. .common = &qed_common_ops_pass,
  1792. #ifdef CONFIG_QED_SRIOV
  1793. .iov = &qed_iov_ops_pass,
  1794. #endif
  1795. #ifdef CONFIG_DCB
  1796. .dcb = &qed_dcbnl_ops_pass,
  1797. #endif
  1798. .fill_dev_info = &qed_fill_eth_dev_info,
  1799. .register_ops = &qed_register_eth_ops,
  1800. .check_mac = &qed_check_mac,
  1801. .vport_start = &qed_start_vport,
  1802. .vport_stop = &qed_stop_vport,
  1803. .vport_update = &qed_update_vport,
  1804. .q_rx_start = &qed_start_rxq,
  1805. .q_rx_stop = &qed_stop_rxq,
  1806. .q_tx_start = &qed_start_txq,
  1807. .q_tx_stop = &qed_stop_txq,
  1808. .filter_config = &qed_configure_filter,
  1809. .fastpath_stop = &qed_fastpath_stop,
  1810. .eth_cqe_completion = &qed_fp_cqe_completion,
  1811. .get_vport_stats = &qed_get_vport_stats,
  1812. .tunn_config = &qed_tunn_configure,
  1813. };
  1814. const struct qed_eth_ops *qed_get_eth_ops(void)
  1815. {
  1816. return &qed_eth_ops_pass;
  1817. }
  1818. EXPORT_SYMBOL(qed_get_eth_ops);
  1819. void qed_put_eth_ops(void)
  1820. {
  1821. /* TODO - reference count for module? */
  1822. }
  1823. EXPORT_SYMBOL(qed_put_eth_ops);