async_tx.c 7.7 KB

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  1. /*
  2. * core routines for the asynchronous memory transfer/transform api
  3. *
  4. * Copyright © 2006, Intel Corporation.
  5. *
  6. * Dan Williams <dan.j.williams@intel.com>
  7. *
  8. * with architecture considerations by:
  9. * Neil Brown <neilb@suse.de>
  10. * Jeff Garzik <jeff@garzik.org>
  11. *
  12. * This program is free software; you can redistribute it and/or modify it
  13. * under the terms and conditions of the GNU General Public License,
  14. * version 2, as published by the Free Software Foundation.
  15. *
  16. * This program is distributed in the hope it will be useful, but WITHOUT
  17. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  19. * more details.
  20. *
  21. * You should have received a copy of the GNU General Public License along with
  22. * this program; if not, write to the Free Software Foundation, Inc.,
  23. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  24. *
  25. */
  26. #include <linux/rculist.h>
  27. #include <linux/kernel.h>
  28. #include <linux/async_tx.h>
  29. #ifdef CONFIG_DMA_ENGINE
  30. static int __init async_tx_init(void)
  31. {
  32. async_dmaengine_get();
  33. printk(KERN_INFO "async_tx: api initialized (async)\n");
  34. return 0;
  35. }
  36. static void __exit async_tx_exit(void)
  37. {
  38. async_dmaengine_put();
  39. }
  40. module_init(async_tx_init);
  41. module_exit(async_tx_exit);
  42. /**
  43. * __async_tx_find_channel - find a channel to carry out the operation or let
  44. * the transaction execute synchronously
  45. * @submit: transaction dependency and submission modifiers
  46. * @tx_type: transaction type
  47. */
  48. struct dma_chan *
  49. __async_tx_find_channel(struct async_submit_ctl *submit,
  50. enum dma_transaction_type tx_type)
  51. {
  52. struct dma_async_tx_descriptor *depend_tx = submit->depend_tx;
  53. /* see if we can keep the chain on one channel */
  54. if (depend_tx &&
  55. dma_has_cap(tx_type, depend_tx->chan->device->cap_mask))
  56. return depend_tx->chan;
  57. return async_dma_find_channel(tx_type);
  58. }
  59. EXPORT_SYMBOL_GPL(__async_tx_find_channel);
  60. #endif
  61. /**
  62. * async_tx_channel_switch - queue an interrupt descriptor with a dependency
  63. * pre-attached.
  64. * @depend_tx: the operation that must finish before the new operation runs
  65. * @tx: the new operation
  66. */
  67. static void
  68. async_tx_channel_switch(struct dma_async_tx_descriptor *depend_tx,
  69. struct dma_async_tx_descriptor *tx)
  70. {
  71. struct dma_chan *chan = depend_tx->chan;
  72. struct dma_device *device = chan->device;
  73. struct dma_async_tx_descriptor *intr_tx = (void *) ~0;
  74. /* first check to see if we can still append to depend_tx */
  75. spin_lock_bh(&depend_tx->lock);
  76. if (depend_tx->parent && depend_tx->chan == tx->chan) {
  77. tx->parent = depend_tx;
  78. depend_tx->next = tx;
  79. intr_tx = NULL;
  80. }
  81. spin_unlock_bh(&depend_tx->lock);
  82. /* attached dependency, flush the parent channel */
  83. if (!intr_tx) {
  84. device->device_issue_pending(chan);
  85. return;
  86. }
  87. /* see if we can schedule an interrupt
  88. * otherwise poll for completion
  89. */
  90. if (dma_has_cap(DMA_INTERRUPT, device->cap_mask))
  91. intr_tx = device->device_prep_dma_interrupt(chan, 0);
  92. else
  93. intr_tx = NULL;
  94. if (intr_tx) {
  95. intr_tx->callback = NULL;
  96. intr_tx->callback_param = NULL;
  97. tx->parent = intr_tx;
  98. /* safe to set ->next outside the lock since we know we are
  99. * not submitted yet
  100. */
  101. intr_tx->next = tx;
  102. /* check if we need to append */
  103. spin_lock_bh(&depend_tx->lock);
  104. if (depend_tx->parent) {
  105. intr_tx->parent = depend_tx;
  106. depend_tx->next = intr_tx;
  107. async_tx_ack(intr_tx);
  108. intr_tx = NULL;
  109. }
  110. spin_unlock_bh(&depend_tx->lock);
  111. if (intr_tx) {
  112. intr_tx->parent = NULL;
  113. intr_tx->tx_submit(intr_tx);
  114. async_tx_ack(intr_tx);
  115. }
  116. device->device_issue_pending(chan);
  117. } else {
  118. if (dma_wait_for_async_tx(depend_tx) == DMA_ERROR)
  119. panic("%s: DMA_ERROR waiting for depend_tx\n",
  120. __func__);
  121. tx->tx_submit(tx);
  122. }
  123. }
  124. /**
  125. * submit_disposition - flags for routing an incoming operation
  126. * @ASYNC_TX_SUBMITTED: we were able to append the new operation under the lock
  127. * @ASYNC_TX_CHANNEL_SWITCH: when the lock is dropped schedule a channel switch
  128. * @ASYNC_TX_DIRECT_SUBMIT: when the lock is dropped submit directly
  129. *
  130. * while holding depend_tx->lock we must avoid submitting new operations
  131. * to prevent a circular locking dependency with drivers that already
  132. * hold a channel lock when calling async_tx_run_dependencies.
  133. */
  134. enum submit_disposition {
  135. ASYNC_TX_SUBMITTED,
  136. ASYNC_TX_CHANNEL_SWITCH,
  137. ASYNC_TX_DIRECT_SUBMIT,
  138. };
  139. void
  140. async_tx_submit(struct dma_chan *chan, struct dma_async_tx_descriptor *tx,
  141. struct async_submit_ctl *submit)
  142. {
  143. struct dma_async_tx_descriptor *depend_tx = submit->depend_tx;
  144. tx->callback = submit->cb_fn;
  145. tx->callback_param = submit->cb_param;
  146. if (depend_tx) {
  147. enum submit_disposition s;
  148. /* sanity check the dependency chain:
  149. * 1/ if ack is already set then we cannot be sure
  150. * we are referring to the correct operation
  151. * 2/ dependencies are 1:1 i.e. two transactions can
  152. * not depend on the same parent
  153. */
  154. BUG_ON(async_tx_test_ack(depend_tx) || depend_tx->next ||
  155. tx->parent);
  156. /* the lock prevents async_tx_run_dependencies from missing
  157. * the setting of ->next when ->parent != NULL
  158. */
  159. spin_lock_bh(&depend_tx->lock);
  160. if (depend_tx->parent) {
  161. /* we have a parent so we can not submit directly
  162. * if we are staying on the same channel: append
  163. * else: channel switch
  164. */
  165. if (depend_tx->chan == chan) {
  166. tx->parent = depend_tx;
  167. depend_tx->next = tx;
  168. s = ASYNC_TX_SUBMITTED;
  169. } else
  170. s = ASYNC_TX_CHANNEL_SWITCH;
  171. } else {
  172. /* we do not have a parent so we may be able to submit
  173. * directly if we are staying on the same channel
  174. */
  175. if (depend_tx->chan == chan)
  176. s = ASYNC_TX_DIRECT_SUBMIT;
  177. else
  178. s = ASYNC_TX_CHANNEL_SWITCH;
  179. }
  180. spin_unlock_bh(&depend_tx->lock);
  181. switch (s) {
  182. case ASYNC_TX_SUBMITTED:
  183. break;
  184. case ASYNC_TX_CHANNEL_SWITCH:
  185. async_tx_channel_switch(depend_tx, tx);
  186. break;
  187. case ASYNC_TX_DIRECT_SUBMIT:
  188. tx->parent = NULL;
  189. tx->tx_submit(tx);
  190. break;
  191. }
  192. } else {
  193. tx->parent = NULL;
  194. tx->tx_submit(tx);
  195. }
  196. if (submit->flags & ASYNC_TX_ACK)
  197. async_tx_ack(tx);
  198. if (depend_tx)
  199. async_tx_ack(depend_tx);
  200. }
  201. EXPORT_SYMBOL_GPL(async_tx_submit);
  202. /**
  203. * async_trigger_callback - schedules the callback function to be run
  204. * @submit: submission and completion parameters
  205. *
  206. * honored flags: ASYNC_TX_ACK
  207. *
  208. * The callback is run after any dependent operations have completed.
  209. */
  210. struct dma_async_tx_descriptor *
  211. async_trigger_callback(struct async_submit_ctl *submit)
  212. {
  213. struct dma_chan *chan;
  214. struct dma_device *device;
  215. struct dma_async_tx_descriptor *tx;
  216. struct dma_async_tx_descriptor *depend_tx = submit->depend_tx;
  217. if (depend_tx) {
  218. chan = depend_tx->chan;
  219. device = chan->device;
  220. /* see if we can schedule an interrupt
  221. * otherwise poll for completion
  222. */
  223. if (device && !dma_has_cap(DMA_INTERRUPT, device->cap_mask))
  224. device = NULL;
  225. tx = device ? device->device_prep_dma_interrupt(chan, 0) : NULL;
  226. } else
  227. tx = NULL;
  228. if (tx) {
  229. pr_debug("%s: (async)\n", __func__);
  230. async_tx_submit(chan, tx, submit);
  231. } else {
  232. pr_debug("%s: (sync)\n", __func__);
  233. /* wait for any prerequisite operations */
  234. async_tx_quiesce(&submit->depend_tx);
  235. async_tx_sync_epilog(submit);
  236. }
  237. return tx;
  238. }
  239. EXPORT_SYMBOL_GPL(async_trigger_callback);
  240. /**
  241. * async_tx_quiesce - ensure tx is complete and freeable upon return
  242. * @tx - transaction to quiesce
  243. */
  244. void async_tx_quiesce(struct dma_async_tx_descriptor **tx)
  245. {
  246. if (*tx) {
  247. /* if ack is already set then we cannot be sure
  248. * we are referring to the correct operation
  249. */
  250. BUG_ON(async_tx_test_ack(*tx));
  251. if (dma_wait_for_async_tx(*tx) == DMA_ERROR)
  252. panic("DMA_ERROR waiting for transaction\n");
  253. async_tx_ack(*tx);
  254. *tx = NULL;
  255. }
  256. }
  257. EXPORT_SYMBOL_GPL(async_tx_quiesce);
  258. MODULE_AUTHOR("Intel Corporation");
  259. MODULE_DESCRIPTION("Asynchronous Bulk Memory Transactions API");
  260. MODULE_LICENSE("GPL");