otg.c 4.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214
  1. /*
  2. * otg.c - ChipIdea USB IP core OTG driver
  3. *
  4. * Copyright (C) 2013 Freescale Semiconductor, Inc.
  5. *
  6. * Author: Peter Chen
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. /*
  13. * This file mainly handles otgsc register, OTG fsm operations for HNP and SRP
  14. * are also included.
  15. */
  16. #include <linux/usb/otg.h>
  17. #include <linux/usb/gadget.h>
  18. #include <linux/usb/chipidea.h>
  19. #include "ci.h"
  20. #include "bits.h"
  21. #include "otg.h"
  22. #include "otg_fsm.h"
  23. /**
  24. * hw_read_otgsc returns otgsc register bits value.
  25. * @mask: bitfield mask
  26. */
  27. u32 hw_read_otgsc(struct ci_hdrc *ci, u32 mask)
  28. {
  29. struct ci_hdrc_cable *cable;
  30. u32 val = hw_read(ci, OP_OTGSC, mask);
  31. /*
  32. * If using extcon framework for VBUS and/or ID signal
  33. * detection overwrite OTGSC register value
  34. */
  35. cable = &ci->platdata->vbus_extcon;
  36. if (!IS_ERR(cable->edev)) {
  37. if (cable->changed)
  38. val |= OTGSC_BSVIS;
  39. else
  40. val &= ~OTGSC_BSVIS;
  41. cable->changed = false;
  42. if (cable->state)
  43. val |= OTGSC_BSV;
  44. else
  45. val &= ~OTGSC_BSV;
  46. }
  47. cable = &ci->platdata->id_extcon;
  48. if (!IS_ERR(cable->edev)) {
  49. if (cable->changed)
  50. val |= OTGSC_IDIS;
  51. else
  52. val &= ~OTGSC_IDIS;
  53. cable->changed = false;
  54. if (cable->state)
  55. val |= OTGSC_ID;
  56. else
  57. val &= ~OTGSC_ID;
  58. }
  59. return val;
  60. }
  61. /**
  62. * hw_write_otgsc updates target bits of OTGSC register.
  63. * @mask: bitfield mask
  64. * @data: to be written
  65. */
  66. void hw_write_otgsc(struct ci_hdrc *ci, u32 mask, u32 data)
  67. {
  68. hw_write(ci, OP_OTGSC, mask | OTGSC_INT_STATUS_BITS, data);
  69. }
  70. /**
  71. * ci_otg_role - pick role based on ID pin state
  72. * @ci: the controller
  73. */
  74. enum ci_role ci_otg_role(struct ci_hdrc *ci)
  75. {
  76. enum ci_role role = hw_read_otgsc(ci, OTGSC_ID)
  77. ? CI_ROLE_GADGET
  78. : CI_ROLE_HOST;
  79. return role;
  80. }
  81. void ci_handle_vbus_change(struct ci_hdrc *ci)
  82. {
  83. if (!ci->is_otg)
  84. return;
  85. if (hw_read_otgsc(ci, OTGSC_BSV))
  86. usb_gadget_vbus_connect(&ci->gadget);
  87. else
  88. usb_gadget_vbus_disconnect(&ci->gadget);
  89. }
  90. /**
  91. * When we switch to device mode, the vbus value should be lower
  92. * than OTGSC_BSV before connecting to host.
  93. *
  94. * @ci: the controller
  95. *
  96. * This function returns an error code if timeout
  97. */
  98. static int hw_wait_vbus_lower_bsv(struct ci_hdrc *ci)
  99. {
  100. unsigned long elapse = jiffies + msecs_to_jiffies(5000);
  101. u32 mask = OTGSC_BSV;
  102. while (hw_read_otgsc(ci, mask)) {
  103. if (time_after(jiffies, elapse)) {
  104. dev_err(ci->dev, "timeout waiting for %08x in OTGSC\n",
  105. mask);
  106. return -ETIMEDOUT;
  107. }
  108. msleep(20);
  109. }
  110. return 0;
  111. }
  112. static void ci_handle_id_switch(struct ci_hdrc *ci)
  113. {
  114. enum ci_role role = ci_otg_role(ci);
  115. if (role != ci->role) {
  116. dev_dbg(ci->dev, "switching from %s to %s\n",
  117. ci_role(ci)->name, ci->roles[role]->name);
  118. ci_role_stop(ci);
  119. if (role == CI_ROLE_GADGET)
  120. /*
  121. * wait vbus lower than OTGSC_BSV before connecting
  122. * to host
  123. */
  124. hw_wait_vbus_lower_bsv(ci);
  125. ci_role_start(ci, role);
  126. }
  127. }
  128. /**
  129. * ci_otg_work - perform otg (vbus/id) event handle
  130. * @work: work struct
  131. */
  132. static void ci_otg_work(struct work_struct *work)
  133. {
  134. struct ci_hdrc *ci = container_of(work, struct ci_hdrc, work);
  135. if (ci_otg_is_fsm_mode(ci) && !ci_otg_fsm_work(ci)) {
  136. enable_irq(ci->irq);
  137. return;
  138. }
  139. pm_runtime_get_sync(ci->dev);
  140. if (ci->id_event) {
  141. ci->id_event = false;
  142. ci_handle_id_switch(ci);
  143. } else if (ci->b_sess_valid_event) {
  144. ci->b_sess_valid_event = false;
  145. ci_handle_vbus_change(ci);
  146. } else
  147. dev_err(ci->dev, "unexpected event occurs at %s\n", __func__);
  148. pm_runtime_put_sync(ci->dev);
  149. enable_irq(ci->irq);
  150. }
  151. /**
  152. * ci_hdrc_otg_init - initialize otg struct
  153. * ci: the controller
  154. */
  155. int ci_hdrc_otg_init(struct ci_hdrc *ci)
  156. {
  157. INIT_WORK(&ci->work, ci_otg_work);
  158. ci->wq = create_freezable_workqueue("ci_otg");
  159. if (!ci->wq) {
  160. dev_err(ci->dev, "can't create workqueue\n");
  161. return -ENODEV;
  162. }
  163. if (ci_otg_is_fsm_mode(ci))
  164. return ci_hdrc_otg_fsm_init(ci);
  165. return 0;
  166. }
  167. /**
  168. * ci_hdrc_otg_destroy - destroy otg struct
  169. * ci: the controller
  170. */
  171. void ci_hdrc_otg_destroy(struct ci_hdrc *ci)
  172. {
  173. if (ci->wq) {
  174. flush_workqueue(ci->wq);
  175. destroy_workqueue(ci->wq);
  176. }
  177. /* Disable all OTG irq and clear status */
  178. hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
  179. OTGSC_INT_STATUS_BITS);
  180. if (ci_otg_is_fsm_mode(ci))
  181. ci_hdrc_otg_fsm_remove(ci);
  182. }