devices.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <linux/module.h>
  3. #include <linux/kernel.h>
  4. #include <linux/init.h>
  5. #include <linux/platform_device.h>
  6. #include <linux/dma-mapping.h>
  7. #include <linux/dmaengine.h>
  8. #include <linux/spi/pxa2xx_spi.h>
  9. #include <linux/platform_data/i2c-pxa.h>
  10. #include "udc.h"
  11. #include <linux/platform_data/usb-pxa3xx-ulpi.h>
  12. #include <linux/platform_data/video-pxafb.h>
  13. #include <linux/platform_data/mmc-pxamci.h>
  14. #include <linux/platform_data/irda-pxaficp.h>
  15. #include <mach/irqs.h>
  16. #include <linux/platform_data/usb-ohci-pxa27x.h>
  17. #include <linux/platform_data/keypad-pxa27x.h>
  18. #include <linux/platform_data/media/camera-pxa.h>
  19. #include <mach/audio.h>
  20. #include <mach/hardware.h>
  21. #include <linux/platform_data/mmp_dma.h>
  22. #include <linux/platform_data/mtd-nand-pxa3xx.h>
  23. #include "devices.h"
  24. #include "generic.h"
  25. void __init pxa_register_device(struct platform_device *dev, void *data)
  26. {
  27. int ret;
  28. dev->dev.platform_data = data;
  29. ret = platform_device_register(dev);
  30. if (ret)
  31. dev_err(&dev->dev, "unable to register device: %d\n", ret);
  32. }
  33. static struct resource pxa_resource_pmu = {
  34. .start = IRQ_PMU,
  35. .end = IRQ_PMU,
  36. .flags = IORESOURCE_IRQ,
  37. };
  38. struct platform_device pxa_device_pmu = {
  39. .name = "xscale-pmu",
  40. .id = -1,
  41. .resource = &pxa_resource_pmu,
  42. .num_resources = 1,
  43. };
  44. static struct resource pxamci_resources[] = {
  45. [0] = {
  46. .start = 0x41100000,
  47. .end = 0x41100fff,
  48. .flags = IORESOURCE_MEM,
  49. },
  50. [1] = {
  51. .start = IRQ_MMC,
  52. .end = IRQ_MMC,
  53. .flags = IORESOURCE_IRQ,
  54. },
  55. };
  56. static u64 pxamci_dmamask = 0xffffffffUL;
  57. struct platform_device pxa_device_mci = {
  58. .name = "pxa2xx-mci",
  59. .id = 0,
  60. .dev = {
  61. .dma_mask = &pxamci_dmamask,
  62. .coherent_dma_mask = 0xffffffff,
  63. },
  64. .num_resources = ARRAY_SIZE(pxamci_resources),
  65. .resource = pxamci_resources,
  66. };
  67. void __init pxa_set_mci_info(struct pxamci_platform_data *info)
  68. {
  69. pxa_register_device(&pxa_device_mci, info);
  70. }
  71. static struct pxa2xx_udc_mach_info pxa_udc_info = {
  72. .gpio_pullup = -1,
  73. };
  74. void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
  75. {
  76. memcpy(&pxa_udc_info, info, sizeof *info);
  77. }
  78. static struct resource pxa2xx_udc_resources[] = {
  79. [0] = {
  80. .start = 0x40600000,
  81. .end = 0x4060ffff,
  82. .flags = IORESOURCE_MEM,
  83. },
  84. [1] = {
  85. .start = IRQ_USB,
  86. .end = IRQ_USB,
  87. .flags = IORESOURCE_IRQ,
  88. },
  89. };
  90. static u64 udc_dma_mask = ~(u32)0;
  91. struct platform_device pxa25x_device_udc = {
  92. .name = "pxa25x-udc",
  93. .id = -1,
  94. .resource = pxa2xx_udc_resources,
  95. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  96. .dev = {
  97. .platform_data = &pxa_udc_info,
  98. .dma_mask = &udc_dma_mask,
  99. }
  100. };
  101. struct platform_device pxa27x_device_udc = {
  102. .name = "pxa27x-udc",
  103. .id = -1,
  104. .resource = pxa2xx_udc_resources,
  105. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  106. .dev = {
  107. .platform_data = &pxa_udc_info,
  108. .dma_mask = &udc_dma_mask,
  109. }
  110. };
  111. #ifdef CONFIG_PXA3xx
  112. static struct resource pxa3xx_u2d_resources[] = {
  113. [0] = {
  114. .start = 0x54100000,
  115. .end = 0x54100fff,
  116. .flags = IORESOURCE_MEM,
  117. },
  118. [1] = {
  119. .start = IRQ_USB2,
  120. .end = IRQ_USB2,
  121. .flags = IORESOURCE_IRQ,
  122. },
  123. };
  124. struct platform_device pxa3xx_device_u2d = {
  125. .name = "pxa3xx-u2d",
  126. .id = -1,
  127. .resource = pxa3xx_u2d_resources,
  128. .num_resources = ARRAY_SIZE(pxa3xx_u2d_resources),
  129. };
  130. void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info)
  131. {
  132. pxa_register_device(&pxa3xx_device_u2d, info);
  133. }
  134. #endif /* CONFIG_PXA3xx */
  135. static struct resource pxafb_resources[] = {
  136. [0] = {
  137. .start = 0x44000000,
  138. .end = 0x4400ffff,
  139. .flags = IORESOURCE_MEM,
  140. },
  141. [1] = {
  142. .start = IRQ_LCD,
  143. .end = IRQ_LCD,
  144. .flags = IORESOURCE_IRQ,
  145. },
  146. };
  147. static u64 fb_dma_mask = ~(u64)0;
  148. struct platform_device pxa_device_fb = {
  149. .name = "pxa2xx-fb",
  150. .id = -1,
  151. .dev = {
  152. .dma_mask = &fb_dma_mask,
  153. .coherent_dma_mask = 0xffffffff,
  154. },
  155. .num_resources = ARRAY_SIZE(pxafb_resources),
  156. .resource = pxafb_resources,
  157. };
  158. void __init pxa_set_fb_info(struct device *parent, struct pxafb_mach_info *info)
  159. {
  160. pxa_device_fb.dev.parent = parent;
  161. pxa_register_device(&pxa_device_fb, info);
  162. }
  163. static struct resource pxa_resource_ffuart[] = {
  164. {
  165. .start = 0x40100000,
  166. .end = 0x40100023,
  167. .flags = IORESOURCE_MEM,
  168. }, {
  169. .start = IRQ_FFUART,
  170. .end = IRQ_FFUART,
  171. .flags = IORESOURCE_IRQ,
  172. }
  173. };
  174. struct platform_device pxa_device_ffuart = {
  175. .name = "pxa2xx-uart",
  176. .id = 0,
  177. .resource = pxa_resource_ffuart,
  178. .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
  179. };
  180. void __init pxa_set_ffuart_info(void *info)
  181. {
  182. pxa_register_device(&pxa_device_ffuart, info);
  183. }
  184. static struct resource pxa_resource_btuart[] = {
  185. {
  186. .start = 0x40200000,
  187. .end = 0x40200023,
  188. .flags = IORESOURCE_MEM,
  189. }, {
  190. .start = IRQ_BTUART,
  191. .end = IRQ_BTUART,
  192. .flags = IORESOURCE_IRQ,
  193. }
  194. };
  195. struct platform_device pxa_device_btuart = {
  196. .name = "pxa2xx-uart",
  197. .id = 1,
  198. .resource = pxa_resource_btuart,
  199. .num_resources = ARRAY_SIZE(pxa_resource_btuart),
  200. };
  201. void __init pxa_set_btuart_info(void *info)
  202. {
  203. pxa_register_device(&pxa_device_btuart, info);
  204. }
  205. static struct resource pxa_resource_stuart[] = {
  206. {
  207. .start = 0x40700000,
  208. .end = 0x40700023,
  209. .flags = IORESOURCE_MEM,
  210. }, {
  211. .start = IRQ_STUART,
  212. .end = IRQ_STUART,
  213. .flags = IORESOURCE_IRQ,
  214. }
  215. };
  216. struct platform_device pxa_device_stuart = {
  217. .name = "pxa2xx-uart",
  218. .id = 2,
  219. .resource = pxa_resource_stuart,
  220. .num_resources = ARRAY_SIZE(pxa_resource_stuart),
  221. };
  222. void __init pxa_set_stuart_info(void *info)
  223. {
  224. pxa_register_device(&pxa_device_stuart, info);
  225. }
  226. static struct resource pxa_resource_hwuart[] = {
  227. {
  228. .start = 0x41600000,
  229. .end = 0x4160002F,
  230. .flags = IORESOURCE_MEM,
  231. }, {
  232. .start = IRQ_HWUART,
  233. .end = IRQ_HWUART,
  234. .flags = IORESOURCE_IRQ,
  235. }
  236. };
  237. struct platform_device pxa_device_hwuart = {
  238. .name = "pxa2xx-uart",
  239. .id = 3,
  240. .resource = pxa_resource_hwuart,
  241. .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
  242. };
  243. void __init pxa_set_hwuart_info(void *info)
  244. {
  245. if (cpu_is_pxa255())
  246. pxa_register_device(&pxa_device_hwuart, info);
  247. else
  248. pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware");
  249. }
  250. static struct resource pxai2c_resources[] = {
  251. {
  252. .start = 0x40301680,
  253. .end = 0x403016a3,
  254. .flags = IORESOURCE_MEM,
  255. }, {
  256. .start = IRQ_I2C,
  257. .end = IRQ_I2C,
  258. .flags = IORESOURCE_IRQ,
  259. },
  260. };
  261. struct platform_device pxa_device_i2c = {
  262. .name = "pxa2xx-i2c",
  263. .id = 0,
  264. .resource = pxai2c_resources,
  265. .num_resources = ARRAY_SIZE(pxai2c_resources),
  266. };
  267. void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
  268. {
  269. pxa_register_device(&pxa_device_i2c, info);
  270. }
  271. #ifdef CONFIG_PXA27x
  272. static struct resource pxa27x_resources_i2c_power[] = {
  273. {
  274. .start = 0x40f00180,
  275. .end = 0x40f001a3,
  276. .flags = IORESOURCE_MEM,
  277. }, {
  278. .start = IRQ_PWRI2C,
  279. .end = IRQ_PWRI2C,
  280. .flags = IORESOURCE_IRQ,
  281. },
  282. };
  283. struct platform_device pxa27x_device_i2c_power = {
  284. .name = "pxa2xx-i2c",
  285. .id = 1,
  286. .resource = pxa27x_resources_i2c_power,
  287. .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power),
  288. };
  289. #endif
  290. static struct resource pxai2s_resources[] = {
  291. {
  292. .start = 0x40400000,
  293. .end = 0x40400083,
  294. .flags = IORESOURCE_MEM,
  295. }, {
  296. .start = IRQ_I2S,
  297. .end = IRQ_I2S,
  298. .flags = IORESOURCE_IRQ,
  299. },
  300. };
  301. struct platform_device pxa_device_i2s = {
  302. .name = "pxa2xx-i2s",
  303. .id = -1,
  304. .resource = pxai2s_resources,
  305. .num_resources = ARRAY_SIZE(pxai2s_resources),
  306. };
  307. struct platform_device pxa_device_asoc_ssp1 = {
  308. .name = "pxa-ssp-dai",
  309. .id = 0,
  310. };
  311. struct platform_device pxa_device_asoc_ssp2= {
  312. .name = "pxa-ssp-dai",
  313. .id = 1,
  314. };
  315. struct platform_device pxa_device_asoc_ssp3 = {
  316. .name = "pxa-ssp-dai",
  317. .id = 2,
  318. };
  319. struct platform_device pxa_device_asoc_ssp4 = {
  320. .name = "pxa-ssp-dai",
  321. .id = 3,
  322. };
  323. struct platform_device pxa_device_asoc_platform = {
  324. .name = "pxa-pcm-audio",
  325. .id = -1,
  326. };
  327. static u64 pxaficp_dmamask = ~(u32)0;
  328. static struct resource pxa_ir_resources[] = {
  329. [0] = {
  330. .start = IRQ_STUART,
  331. .end = IRQ_STUART,
  332. .flags = IORESOURCE_IRQ,
  333. },
  334. [1] = {
  335. .start = IRQ_ICP,
  336. .end = IRQ_ICP,
  337. .flags = IORESOURCE_IRQ,
  338. },
  339. [3] = {
  340. .start = 0x40800000,
  341. .end = 0x4080001b,
  342. .flags = IORESOURCE_MEM,
  343. },
  344. [4] = {
  345. .start = 0x40700000,
  346. .end = 0x40700023,
  347. .flags = IORESOURCE_MEM,
  348. },
  349. };
  350. struct platform_device pxa_device_ficp = {
  351. .name = "pxa2xx-ir",
  352. .id = -1,
  353. .num_resources = ARRAY_SIZE(pxa_ir_resources),
  354. .resource = pxa_ir_resources,
  355. .dev = {
  356. .dma_mask = &pxaficp_dmamask,
  357. .coherent_dma_mask = 0xffffffff,
  358. },
  359. };
  360. void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
  361. {
  362. pxa_register_device(&pxa_device_ficp, info);
  363. }
  364. static struct resource pxa_rtc_resources[] = {
  365. [0] = {
  366. .start = 0x40900000,
  367. .end = 0x40900000 + 0x3b,
  368. .flags = IORESOURCE_MEM,
  369. },
  370. [1] = {
  371. .start = IRQ_RTC1Hz,
  372. .end = IRQ_RTC1Hz,
  373. .name = "rtc 1Hz",
  374. .flags = IORESOURCE_IRQ,
  375. },
  376. [2] = {
  377. .start = IRQ_RTCAlrm,
  378. .end = IRQ_RTCAlrm,
  379. .name = "rtc alarm",
  380. .flags = IORESOURCE_IRQ,
  381. },
  382. };
  383. struct platform_device pxa_device_rtc = {
  384. .name = "pxa-rtc",
  385. .id = -1,
  386. .num_resources = ARRAY_SIZE(pxa_rtc_resources),
  387. .resource = pxa_rtc_resources,
  388. };
  389. struct platform_device sa1100_device_rtc = {
  390. .name = "sa1100-rtc",
  391. .id = -1,
  392. .num_resources = ARRAY_SIZE(pxa_rtc_resources),
  393. .resource = pxa_rtc_resources,
  394. };
  395. static struct resource pxa_ac97_resources[] = {
  396. [0] = {
  397. .start = 0x40500000,
  398. .end = 0x40500000 + 0xfff,
  399. .flags = IORESOURCE_MEM,
  400. },
  401. [1] = {
  402. .start = IRQ_AC97,
  403. .end = IRQ_AC97,
  404. .flags = IORESOURCE_IRQ,
  405. },
  406. };
  407. static u64 pxa_ac97_dmamask = 0xffffffffUL;
  408. struct platform_device pxa_device_ac97 = {
  409. .name = "pxa2xx-ac97",
  410. .id = -1,
  411. .dev = {
  412. .dma_mask = &pxa_ac97_dmamask,
  413. .coherent_dma_mask = 0xffffffff,
  414. },
  415. .num_resources = ARRAY_SIZE(pxa_ac97_resources),
  416. .resource = pxa_ac97_resources,
  417. };
  418. void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
  419. {
  420. pxa_register_device(&pxa_device_ac97, ops);
  421. }
  422. #ifdef CONFIG_PXA25x
  423. static struct resource pxa25x_resource_pwm0[] = {
  424. [0] = {
  425. .start = 0x40b00000,
  426. .end = 0x40b0000f,
  427. .flags = IORESOURCE_MEM,
  428. },
  429. };
  430. struct platform_device pxa25x_device_pwm0 = {
  431. .name = "pxa25x-pwm",
  432. .id = 0,
  433. .resource = pxa25x_resource_pwm0,
  434. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0),
  435. };
  436. static struct resource pxa25x_resource_pwm1[] = {
  437. [0] = {
  438. .start = 0x40c00000,
  439. .end = 0x40c0000f,
  440. .flags = IORESOURCE_MEM,
  441. },
  442. };
  443. struct platform_device pxa25x_device_pwm1 = {
  444. .name = "pxa25x-pwm",
  445. .id = 1,
  446. .resource = pxa25x_resource_pwm1,
  447. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1),
  448. };
  449. static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
  450. static struct resource pxa25x_resource_ssp[] = {
  451. [0] = {
  452. .start = 0x41000000,
  453. .end = 0x4100001f,
  454. .flags = IORESOURCE_MEM,
  455. },
  456. [1] = {
  457. .start = IRQ_SSP,
  458. .end = IRQ_SSP,
  459. .flags = IORESOURCE_IRQ,
  460. },
  461. };
  462. struct platform_device pxa25x_device_ssp = {
  463. .name = "pxa25x-ssp",
  464. .id = 0,
  465. .dev = {
  466. .dma_mask = &pxa25x_ssp_dma_mask,
  467. .coherent_dma_mask = DMA_BIT_MASK(32),
  468. },
  469. .resource = pxa25x_resource_ssp,
  470. .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
  471. };
  472. static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
  473. static struct resource pxa25x_resource_nssp[] = {
  474. [0] = {
  475. .start = 0x41400000,
  476. .end = 0x4140002f,
  477. .flags = IORESOURCE_MEM,
  478. },
  479. [1] = {
  480. .start = IRQ_NSSP,
  481. .end = IRQ_NSSP,
  482. .flags = IORESOURCE_IRQ,
  483. },
  484. };
  485. struct platform_device pxa25x_device_nssp = {
  486. .name = "pxa25x-nssp",
  487. .id = 1,
  488. .dev = {
  489. .dma_mask = &pxa25x_nssp_dma_mask,
  490. .coherent_dma_mask = DMA_BIT_MASK(32),
  491. },
  492. .resource = pxa25x_resource_nssp,
  493. .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
  494. };
  495. static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
  496. static struct resource pxa25x_resource_assp[] = {
  497. [0] = {
  498. .start = 0x41500000,
  499. .end = 0x4150002f,
  500. .flags = IORESOURCE_MEM,
  501. },
  502. [1] = {
  503. .start = IRQ_ASSP,
  504. .end = IRQ_ASSP,
  505. .flags = IORESOURCE_IRQ,
  506. },
  507. };
  508. struct platform_device pxa25x_device_assp = {
  509. /* ASSP is basically equivalent to NSSP */
  510. .name = "pxa25x-nssp",
  511. .id = 2,
  512. .dev = {
  513. .dma_mask = &pxa25x_assp_dma_mask,
  514. .coherent_dma_mask = DMA_BIT_MASK(32),
  515. },
  516. .resource = pxa25x_resource_assp,
  517. .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
  518. };
  519. #endif /* CONFIG_PXA25x */
  520. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  521. static struct resource pxa27x_resource_camera[] = {
  522. [0] = {
  523. .start = 0x50000000,
  524. .end = 0x50000fff,
  525. .flags = IORESOURCE_MEM,
  526. },
  527. [1] = {
  528. .start = IRQ_CAMERA,
  529. .end = IRQ_CAMERA,
  530. .flags = IORESOURCE_IRQ,
  531. },
  532. };
  533. static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
  534. static struct platform_device pxa27x_device_camera = {
  535. .name = "pxa27x-camera",
  536. .id = 0, /* This is used to put cameras on this interface */
  537. .dev = {
  538. .dma_mask = &pxa27x_dma_mask_camera,
  539. .coherent_dma_mask = 0xffffffff,
  540. },
  541. .num_resources = ARRAY_SIZE(pxa27x_resource_camera),
  542. .resource = pxa27x_resource_camera,
  543. };
  544. void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
  545. {
  546. pxa_register_device(&pxa27x_device_camera, info);
  547. }
  548. static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
  549. static struct resource pxa27x_resource_ohci[] = {
  550. [0] = {
  551. .start = 0x4C000000,
  552. .end = 0x4C00ff6f,
  553. .flags = IORESOURCE_MEM,
  554. },
  555. [1] = {
  556. .start = IRQ_USBH1,
  557. .end = IRQ_USBH1,
  558. .flags = IORESOURCE_IRQ,
  559. },
  560. };
  561. struct platform_device pxa27x_device_ohci = {
  562. .name = "pxa27x-ohci",
  563. .id = -1,
  564. .dev = {
  565. .dma_mask = &pxa27x_ohci_dma_mask,
  566. .coherent_dma_mask = DMA_BIT_MASK(32),
  567. },
  568. .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
  569. .resource = pxa27x_resource_ohci,
  570. };
  571. void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
  572. {
  573. pxa_register_device(&pxa27x_device_ohci, info);
  574. }
  575. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
  576. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  577. static struct resource pxa27x_resource_keypad[] = {
  578. [0] = {
  579. .start = 0x41500000,
  580. .end = 0x4150004c,
  581. .flags = IORESOURCE_MEM,
  582. },
  583. [1] = {
  584. .start = IRQ_KEYPAD,
  585. .end = IRQ_KEYPAD,
  586. .flags = IORESOURCE_IRQ,
  587. },
  588. };
  589. struct platform_device pxa27x_device_keypad = {
  590. .name = "pxa27x-keypad",
  591. .id = -1,
  592. .resource = pxa27x_resource_keypad,
  593. .num_resources = ARRAY_SIZE(pxa27x_resource_keypad),
  594. };
  595. void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
  596. {
  597. pxa_register_device(&pxa27x_device_keypad, info);
  598. }
  599. static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
  600. static struct resource pxa27x_resource_ssp1[] = {
  601. [0] = {
  602. .start = 0x41000000,
  603. .end = 0x4100003f,
  604. .flags = IORESOURCE_MEM,
  605. },
  606. [1] = {
  607. .start = IRQ_SSP,
  608. .end = IRQ_SSP,
  609. .flags = IORESOURCE_IRQ,
  610. },
  611. };
  612. struct platform_device pxa27x_device_ssp1 = {
  613. .name = "pxa27x-ssp",
  614. .id = 0,
  615. .dev = {
  616. .dma_mask = &pxa27x_ssp1_dma_mask,
  617. .coherent_dma_mask = DMA_BIT_MASK(32),
  618. },
  619. .resource = pxa27x_resource_ssp1,
  620. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
  621. };
  622. static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
  623. static struct resource pxa27x_resource_ssp2[] = {
  624. [0] = {
  625. .start = 0x41700000,
  626. .end = 0x4170003f,
  627. .flags = IORESOURCE_MEM,
  628. },
  629. [1] = {
  630. .start = IRQ_SSP2,
  631. .end = IRQ_SSP2,
  632. .flags = IORESOURCE_IRQ,
  633. },
  634. };
  635. struct platform_device pxa27x_device_ssp2 = {
  636. .name = "pxa27x-ssp",
  637. .id = 1,
  638. .dev = {
  639. .dma_mask = &pxa27x_ssp2_dma_mask,
  640. .coherent_dma_mask = DMA_BIT_MASK(32),
  641. },
  642. .resource = pxa27x_resource_ssp2,
  643. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
  644. };
  645. static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
  646. static struct resource pxa27x_resource_ssp3[] = {
  647. [0] = {
  648. .start = 0x41900000,
  649. .end = 0x4190003f,
  650. .flags = IORESOURCE_MEM,
  651. },
  652. [1] = {
  653. .start = IRQ_SSP3,
  654. .end = IRQ_SSP3,
  655. .flags = IORESOURCE_IRQ,
  656. },
  657. };
  658. struct platform_device pxa27x_device_ssp3 = {
  659. .name = "pxa27x-ssp",
  660. .id = 2,
  661. .dev = {
  662. .dma_mask = &pxa27x_ssp3_dma_mask,
  663. .coherent_dma_mask = DMA_BIT_MASK(32),
  664. },
  665. .resource = pxa27x_resource_ssp3,
  666. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
  667. };
  668. static struct resource pxa27x_resource_pwm0[] = {
  669. [0] = {
  670. .start = 0x40b00000,
  671. .end = 0x40b0001f,
  672. .flags = IORESOURCE_MEM,
  673. },
  674. };
  675. struct platform_device pxa27x_device_pwm0 = {
  676. .name = "pxa27x-pwm",
  677. .id = 0,
  678. .resource = pxa27x_resource_pwm0,
  679. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0),
  680. };
  681. static struct resource pxa27x_resource_pwm1[] = {
  682. [0] = {
  683. .start = 0x40c00000,
  684. .end = 0x40c0001f,
  685. .flags = IORESOURCE_MEM,
  686. },
  687. };
  688. struct platform_device pxa27x_device_pwm1 = {
  689. .name = "pxa27x-pwm",
  690. .id = 1,
  691. .resource = pxa27x_resource_pwm1,
  692. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
  693. };
  694. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
  695. #ifdef CONFIG_PXA3xx
  696. static struct resource pxa3xx_resources_mci2[] = {
  697. [0] = {
  698. .start = 0x42000000,
  699. .end = 0x42000fff,
  700. .flags = IORESOURCE_MEM,
  701. },
  702. [1] = {
  703. .start = IRQ_MMC2,
  704. .end = IRQ_MMC2,
  705. .flags = IORESOURCE_IRQ,
  706. },
  707. };
  708. struct platform_device pxa3xx_device_mci2 = {
  709. .name = "pxa2xx-mci",
  710. .id = 1,
  711. .dev = {
  712. .dma_mask = &pxamci_dmamask,
  713. .coherent_dma_mask = 0xffffffff,
  714. },
  715. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
  716. .resource = pxa3xx_resources_mci2,
  717. };
  718. void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
  719. {
  720. pxa_register_device(&pxa3xx_device_mci2, info);
  721. }
  722. static struct resource pxa3xx_resources_mci3[] = {
  723. [0] = {
  724. .start = 0x42500000,
  725. .end = 0x42500fff,
  726. .flags = IORESOURCE_MEM,
  727. },
  728. [1] = {
  729. .start = IRQ_MMC3,
  730. .end = IRQ_MMC3,
  731. .flags = IORESOURCE_IRQ,
  732. },
  733. };
  734. struct platform_device pxa3xx_device_mci3 = {
  735. .name = "pxa2xx-mci",
  736. .id = 2,
  737. .dev = {
  738. .dma_mask = &pxamci_dmamask,
  739. .coherent_dma_mask = 0xffffffff,
  740. },
  741. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
  742. .resource = pxa3xx_resources_mci3,
  743. };
  744. void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
  745. {
  746. pxa_register_device(&pxa3xx_device_mci3, info);
  747. }
  748. static struct resource pxa3xx_resources_gcu[] = {
  749. {
  750. .start = 0x54000000,
  751. .end = 0x54000fff,
  752. .flags = IORESOURCE_MEM,
  753. },
  754. {
  755. .start = IRQ_GCU,
  756. .end = IRQ_GCU,
  757. .flags = IORESOURCE_IRQ,
  758. },
  759. };
  760. static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
  761. struct platform_device pxa3xx_device_gcu = {
  762. .name = "pxa3xx-gcu",
  763. .id = -1,
  764. .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu),
  765. .resource = pxa3xx_resources_gcu,
  766. .dev = {
  767. .dma_mask = &pxa3xx_gcu_dmamask,
  768. .coherent_dma_mask = 0xffffffff,
  769. },
  770. };
  771. #endif /* CONFIG_PXA3xx */
  772. #if defined(CONFIG_PXA3xx)
  773. static struct resource pxa3xx_resources_i2c_power[] = {
  774. {
  775. .start = 0x40f500c0,
  776. .end = 0x40f500d3,
  777. .flags = IORESOURCE_MEM,
  778. }, {
  779. .start = IRQ_PWRI2C,
  780. .end = IRQ_PWRI2C,
  781. .flags = IORESOURCE_IRQ,
  782. },
  783. };
  784. struct platform_device pxa3xx_device_i2c_power = {
  785. .name = "pxa3xx-pwri2c",
  786. .id = 1,
  787. .resource = pxa3xx_resources_i2c_power,
  788. .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power),
  789. };
  790. static struct resource pxa3xx_resources_nand[] = {
  791. [0] = {
  792. .start = 0x43100000,
  793. .end = 0x43100053,
  794. .flags = IORESOURCE_MEM,
  795. },
  796. [1] = {
  797. .start = IRQ_NAND,
  798. .end = IRQ_NAND,
  799. .flags = IORESOURCE_IRQ,
  800. },
  801. };
  802. static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
  803. struct platform_device pxa3xx_device_nand = {
  804. .name = "pxa3xx-nand",
  805. .id = -1,
  806. .dev = {
  807. .dma_mask = &pxa3xx_nand_dma_mask,
  808. .coherent_dma_mask = DMA_BIT_MASK(32),
  809. },
  810. .num_resources = ARRAY_SIZE(pxa3xx_resources_nand),
  811. .resource = pxa3xx_resources_nand,
  812. };
  813. void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
  814. {
  815. pxa_register_device(&pxa3xx_device_nand, info);
  816. }
  817. static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
  818. static struct resource pxa3xx_resource_ssp4[] = {
  819. [0] = {
  820. .start = 0x41a00000,
  821. .end = 0x41a0003f,
  822. .flags = IORESOURCE_MEM,
  823. },
  824. [1] = {
  825. .start = IRQ_SSP4,
  826. .end = IRQ_SSP4,
  827. .flags = IORESOURCE_IRQ,
  828. },
  829. };
  830. /*
  831. * PXA3xx SSP is basically equivalent to PXA27x.
  832. * However, we need to register the device by the correct name in order to
  833. * make the driver set the correct internal type, hence we provide specific
  834. * platform_devices for each of them.
  835. */
  836. struct platform_device pxa3xx_device_ssp1 = {
  837. .name = "pxa3xx-ssp",
  838. .id = 0,
  839. .dev = {
  840. .dma_mask = &pxa27x_ssp1_dma_mask,
  841. .coherent_dma_mask = DMA_BIT_MASK(32),
  842. },
  843. .resource = pxa27x_resource_ssp1,
  844. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
  845. };
  846. struct platform_device pxa3xx_device_ssp2 = {
  847. .name = "pxa3xx-ssp",
  848. .id = 1,
  849. .dev = {
  850. .dma_mask = &pxa27x_ssp2_dma_mask,
  851. .coherent_dma_mask = DMA_BIT_MASK(32),
  852. },
  853. .resource = pxa27x_resource_ssp2,
  854. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
  855. };
  856. struct platform_device pxa3xx_device_ssp3 = {
  857. .name = "pxa3xx-ssp",
  858. .id = 2,
  859. .dev = {
  860. .dma_mask = &pxa27x_ssp3_dma_mask,
  861. .coherent_dma_mask = DMA_BIT_MASK(32),
  862. },
  863. .resource = pxa27x_resource_ssp3,
  864. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
  865. };
  866. struct platform_device pxa3xx_device_ssp4 = {
  867. .name = "pxa3xx-ssp",
  868. .id = 3,
  869. .dev = {
  870. .dma_mask = &pxa3xx_ssp4_dma_mask,
  871. .coherent_dma_mask = DMA_BIT_MASK(32),
  872. },
  873. .resource = pxa3xx_resource_ssp4,
  874. .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
  875. };
  876. #endif /* CONFIG_PXA3xx */
  877. struct resource pxa_resource_gpio[] = {
  878. {
  879. .start = 0x40e00000,
  880. .end = 0x40e0ffff,
  881. .flags = IORESOURCE_MEM,
  882. }, {
  883. .start = IRQ_GPIO0,
  884. .end = IRQ_GPIO0,
  885. .name = "gpio0",
  886. .flags = IORESOURCE_IRQ,
  887. }, {
  888. .start = IRQ_GPIO1,
  889. .end = IRQ_GPIO1,
  890. .name = "gpio1",
  891. .flags = IORESOURCE_IRQ,
  892. }, {
  893. .start = IRQ_GPIO_2_x,
  894. .end = IRQ_GPIO_2_x,
  895. .name = "gpio_mux",
  896. .flags = IORESOURCE_IRQ,
  897. },
  898. };
  899. struct platform_device pxa25x_device_gpio = {
  900. #ifdef CONFIG_CPU_PXA26x
  901. .name = "pxa26x-gpio",
  902. #else
  903. .name = "pxa25x-gpio",
  904. #endif
  905. .id = -1,
  906. .num_resources = ARRAY_SIZE(pxa_resource_gpio),
  907. .resource = pxa_resource_gpio,
  908. };
  909. struct platform_device pxa27x_device_gpio = {
  910. .name = "pxa27x-gpio",
  911. .id = -1,
  912. .num_resources = ARRAY_SIZE(pxa_resource_gpio),
  913. .resource = pxa_resource_gpio,
  914. };
  915. struct platform_device pxa3xx_device_gpio = {
  916. .name = "pxa3xx-gpio",
  917. .id = -1,
  918. .num_resources = ARRAY_SIZE(pxa_resource_gpio),
  919. .resource = pxa_resource_gpio,
  920. };
  921. struct platform_device pxa93x_device_gpio = {
  922. .name = "pxa93x-gpio",
  923. .id = -1,
  924. .num_resources = ARRAY_SIZE(pxa_resource_gpio),
  925. .resource = pxa_resource_gpio,
  926. };
  927. /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
  928. * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
  929. void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
  930. {
  931. struct platform_device *pd;
  932. pd = platform_device_alloc("pxa2xx-spi", id);
  933. if (pd == NULL) {
  934. printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
  935. id);
  936. return;
  937. }
  938. pd->dev.platform_data = info;
  939. platform_device_add(pd);
  940. }
  941. static struct resource pxa_dma_resource[] = {
  942. [0] = {
  943. .start = 0x40000000,
  944. .end = 0x4000ffff,
  945. .flags = IORESOURCE_MEM,
  946. },
  947. [1] = {
  948. .start = IRQ_DMA,
  949. .end = IRQ_DMA,
  950. .flags = IORESOURCE_IRQ,
  951. },
  952. };
  953. static u64 pxadma_dmamask = 0xffffffffUL;
  954. static struct platform_device pxa2xx_pxa_dma = {
  955. .name = "pxa-dma",
  956. .id = 0,
  957. .dev = {
  958. .dma_mask = &pxadma_dmamask,
  959. .coherent_dma_mask = 0xffffffff,
  960. },
  961. .num_resources = ARRAY_SIZE(pxa_dma_resource),
  962. .resource = pxa_dma_resource,
  963. };
  964. void __init pxa2xx_set_dmac_info(struct mmp_dma_platdata *dma_pdata)
  965. {
  966. pxa_register_device(&pxa2xx_pxa_dma, dma_pdata);
  967. }