omap_crtc.c 18 KB

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  1. /*
  2. * drivers/gpu/drm/omapdrm/omap_crtc.c
  3. *
  4. * Copyright (C) 2011 Texas Instruments
  5. * Author: Rob Clark <rob@ti.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include "omap_drv.h"
  20. #include <drm/drm_mode.h>
  21. #include "drm_crtc.h"
  22. #include "drm_crtc_helper.h"
  23. #define to_omap_crtc(x) container_of(x, struct omap_crtc, base)
  24. struct omap_crtc {
  25. struct drm_crtc base;
  26. struct drm_plane *plane;
  27. const char *name;
  28. int pipe;
  29. enum omap_channel channel;
  30. struct omap_overlay_manager_info info;
  31. /*
  32. * Temporary: eventually this will go away, but it is needed
  33. * for now to keep the output's happy. (They only need
  34. * mgr->id.) Eventually this will be replaced w/ something
  35. * more common-panel-framework-y
  36. */
  37. struct omap_overlay_manager *mgr;
  38. struct omap_video_timings timings;
  39. bool enabled;
  40. bool full_update;
  41. struct omap_drm_apply apply;
  42. struct omap_drm_irq apply_irq;
  43. struct omap_drm_irq error_irq;
  44. /* list of in-progress apply's: */
  45. struct list_head pending_applies;
  46. /* list of queued apply's: */
  47. struct list_head queued_applies;
  48. /* for handling queued and in-progress applies: */
  49. struct work_struct apply_work;
  50. /* if there is a pending flip, these will be non-null: */
  51. struct drm_pending_vblank_event *event;
  52. struct drm_framebuffer *old_fb;
  53. /* for handling page flips without caring about what
  54. * the callback is called from. Possibly we should just
  55. * make omap_gem always call the cb from the worker so
  56. * we don't have to care about this..
  57. *
  58. * XXX maybe fold into apply_work??
  59. */
  60. struct work_struct page_flip_work;
  61. };
  62. uint32_t pipe2vbl(struct drm_crtc *crtc)
  63. {
  64. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  65. return dispc_mgr_get_vsync_irq(omap_crtc->channel);
  66. }
  67. /*
  68. * Manager-ops, callbacks from output when they need to configure
  69. * the upstream part of the video pipe.
  70. *
  71. * Most of these we can ignore until we add support for command-mode
  72. * panels.. for video-mode the crtc-helpers already do an adequate
  73. * job of sequencing the setup of the video pipe in the proper order
  74. */
  75. /* ovl-mgr-id -> crtc */
  76. static struct omap_crtc *omap_crtcs[8];
  77. /* we can probably ignore these until we support command-mode panels: */
  78. static int omap_crtc_connect(struct omap_overlay_manager *mgr,
  79. struct omap_dss_device *dst)
  80. {
  81. if (mgr->output)
  82. return -EINVAL;
  83. if ((mgr->supported_outputs & dst->id) == 0)
  84. return -EINVAL;
  85. dst->manager = mgr;
  86. mgr->output = dst;
  87. return 0;
  88. }
  89. static void omap_crtc_disconnect(struct omap_overlay_manager *mgr,
  90. struct omap_dss_device *dst)
  91. {
  92. mgr->output->manager = NULL;
  93. mgr->output = NULL;
  94. }
  95. static void omap_crtc_start_update(struct omap_overlay_manager *mgr)
  96. {
  97. }
  98. static int omap_crtc_enable(struct omap_overlay_manager *mgr)
  99. {
  100. return 0;
  101. }
  102. static void omap_crtc_disable(struct omap_overlay_manager *mgr)
  103. {
  104. }
  105. static void omap_crtc_set_timings(struct omap_overlay_manager *mgr,
  106. const struct omap_video_timings *timings)
  107. {
  108. struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
  109. DBG("%s", omap_crtc->name);
  110. omap_crtc->timings = *timings;
  111. omap_crtc->full_update = true;
  112. }
  113. static void omap_crtc_set_lcd_config(struct omap_overlay_manager *mgr,
  114. const struct dss_lcd_mgr_config *config)
  115. {
  116. struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
  117. DBG("%s", omap_crtc->name);
  118. dispc_mgr_set_lcd_config(omap_crtc->channel, config);
  119. }
  120. static int omap_crtc_register_framedone_handler(
  121. struct omap_overlay_manager *mgr,
  122. void (*handler)(void *), void *data)
  123. {
  124. return 0;
  125. }
  126. static void omap_crtc_unregister_framedone_handler(
  127. struct omap_overlay_manager *mgr,
  128. void (*handler)(void *), void *data)
  129. {
  130. }
  131. static const struct dss_mgr_ops mgr_ops = {
  132. .connect = omap_crtc_connect,
  133. .disconnect = omap_crtc_disconnect,
  134. .start_update = omap_crtc_start_update,
  135. .enable = omap_crtc_enable,
  136. .disable = omap_crtc_disable,
  137. .set_timings = omap_crtc_set_timings,
  138. .set_lcd_config = omap_crtc_set_lcd_config,
  139. .register_framedone_handler = omap_crtc_register_framedone_handler,
  140. .unregister_framedone_handler = omap_crtc_unregister_framedone_handler,
  141. };
  142. /*
  143. * CRTC funcs:
  144. */
  145. static void omap_crtc_destroy(struct drm_crtc *crtc)
  146. {
  147. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  148. DBG("%s", omap_crtc->name);
  149. WARN_ON(omap_crtc->apply_irq.registered);
  150. omap_irq_unregister(crtc->dev, &omap_crtc->error_irq);
  151. omap_crtc->plane->funcs->destroy(omap_crtc->plane);
  152. drm_crtc_cleanup(crtc);
  153. kfree(omap_crtc);
  154. }
  155. static void omap_crtc_dpms(struct drm_crtc *crtc, int mode)
  156. {
  157. struct omap_drm_private *priv = crtc->dev->dev_private;
  158. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  159. bool enabled = (mode == DRM_MODE_DPMS_ON);
  160. int i;
  161. DBG("%s: %d", omap_crtc->name, mode);
  162. if (enabled != omap_crtc->enabled) {
  163. omap_crtc->enabled = enabled;
  164. omap_crtc->full_update = true;
  165. omap_crtc_apply(crtc, &omap_crtc->apply);
  166. /* also enable our private plane: */
  167. WARN_ON(omap_plane_dpms(omap_crtc->plane, mode));
  168. /* and any attached overlay planes: */
  169. for (i = 0; i < priv->num_planes; i++) {
  170. struct drm_plane *plane = priv->planes[i];
  171. if (plane->crtc == crtc)
  172. WARN_ON(omap_plane_dpms(plane, mode));
  173. }
  174. }
  175. }
  176. static bool omap_crtc_mode_fixup(struct drm_crtc *crtc,
  177. const struct drm_display_mode *mode,
  178. struct drm_display_mode *adjusted_mode)
  179. {
  180. return true;
  181. }
  182. static int omap_crtc_mode_set(struct drm_crtc *crtc,
  183. struct drm_display_mode *mode,
  184. struct drm_display_mode *adjusted_mode,
  185. int x, int y,
  186. struct drm_framebuffer *old_fb)
  187. {
  188. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  189. mode = adjusted_mode;
  190. DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
  191. omap_crtc->name, mode->base.id, mode->name,
  192. mode->vrefresh, mode->clock,
  193. mode->hdisplay, mode->hsync_start,
  194. mode->hsync_end, mode->htotal,
  195. mode->vdisplay, mode->vsync_start,
  196. mode->vsync_end, mode->vtotal,
  197. mode->type, mode->flags);
  198. copy_timings_drm_to_omap(&omap_crtc->timings, mode);
  199. omap_crtc->full_update = true;
  200. return omap_plane_mode_set(omap_crtc->plane, crtc, crtc->primary->fb,
  201. 0, 0, mode->hdisplay, mode->vdisplay,
  202. x << 16, y << 16,
  203. mode->hdisplay << 16, mode->vdisplay << 16,
  204. NULL, NULL);
  205. }
  206. static void omap_crtc_prepare(struct drm_crtc *crtc)
  207. {
  208. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  209. DBG("%s", omap_crtc->name);
  210. omap_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
  211. }
  212. static void omap_crtc_commit(struct drm_crtc *crtc)
  213. {
  214. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  215. DBG("%s", omap_crtc->name);
  216. omap_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
  217. }
  218. static int omap_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
  219. struct drm_framebuffer *old_fb)
  220. {
  221. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  222. struct drm_plane *plane = omap_crtc->plane;
  223. struct drm_display_mode *mode = &crtc->mode;
  224. return omap_plane_mode_set(plane, crtc, crtc->primary->fb,
  225. 0, 0, mode->hdisplay, mode->vdisplay,
  226. x << 16, y << 16,
  227. mode->hdisplay << 16, mode->vdisplay << 16,
  228. NULL, NULL);
  229. }
  230. static void vblank_cb(void *arg)
  231. {
  232. struct drm_crtc *crtc = arg;
  233. struct drm_device *dev = crtc->dev;
  234. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  235. unsigned long flags;
  236. spin_lock_irqsave(&dev->event_lock, flags);
  237. /* wakeup userspace */
  238. if (omap_crtc->event)
  239. drm_send_vblank_event(dev, omap_crtc->pipe, omap_crtc->event);
  240. omap_crtc->event = NULL;
  241. omap_crtc->old_fb = NULL;
  242. spin_unlock_irqrestore(&dev->event_lock, flags);
  243. }
  244. static void page_flip_worker(struct work_struct *work)
  245. {
  246. struct omap_crtc *omap_crtc =
  247. container_of(work, struct omap_crtc, page_flip_work);
  248. struct drm_crtc *crtc = &omap_crtc->base;
  249. struct drm_display_mode *mode = &crtc->mode;
  250. struct drm_gem_object *bo;
  251. mutex_lock(&crtc->mutex);
  252. omap_plane_mode_set(omap_crtc->plane, crtc, crtc->primary->fb,
  253. 0, 0, mode->hdisplay, mode->vdisplay,
  254. crtc->x << 16, crtc->y << 16,
  255. mode->hdisplay << 16, mode->vdisplay << 16,
  256. vblank_cb, crtc);
  257. mutex_unlock(&crtc->mutex);
  258. bo = omap_framebuffer_bo(crtc->primary->fb, 0);
  259. drm_gem_object_unreference_unlocked(bo);
  260. }
  261. static void page_flip_cb(void *arg)
  262. {
  263. struct drm_crtc *crtc = arg;
  264. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  265. struct omap_drm_private *priv = crtc->dev->dev_private;
  266. /* avoid assumptions about what ctxt we are called from: */
  267. queue_work(priv->wq, &omap_crtc->page_flip_work);
  268. }
  269. static int omap_crtc_page_flip_locked(struct drm_crtc *crtc,
  270. struct drm_framebuffer *fb,
  271. struct drm_pending_vblank_event *event,
  272. uint32_t page_flip_flags)
  273. {
  274. struct drm_device *dev = crtc->dev;
  275. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  276. struct drm_plane *primary = crtc->primary;
  277. struct drm_gem_object *bo;
  278. DBG("%d -> %d (event=%p)", primary->fb ? primary->fb->base.id : -1,
  279. fb->base.id, event);
  280. if (omap_crtc->old_fb) {
  281. dev_err(dev->dev, "already a pending flip\n");
  282. return -EINVAL;
  283. }
  284. omap_crtc->event = event;
  285. primary->fb = fb;
  286. /*
  287. * Hold a reference temporarily until the crtc is updated
  288. * and takes the reference to the bo. This avoids it
  289. * getting freed from under us:
  290. */
  291. bo = omap_framebuffer_bo(fb, 0);
  292. drm_gem_object_reference(bo);
  293. omap_gem_op_async(bo, OMAP_GEM_READ, page_flip_cb, crtc);
  294. return 0;
  295. }
  296. static int omap_crtc_set_property(struct drm_crtc *crtc,
  297. struct drm_property *property, uint64_t val)
  298. {
  299. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  300. struct omap_drm_private *priv = crtc->dev->dev_private;
  301. if (property == priv->rotation_prop) {
  302. crtc->invert_dimensions =
  303. !!(val & ((1LL << DRM_ROTATE_90) | (1LL << DRM_ROTATE_270)));
  304. }
  305. return omap_plane_set_property(omap_crtc->plane, property, val);
  306. }
  307. static const struct drm_crtc_funcs omap_crtc_funcs = {
  308. .set_config = drm_crtc_helper_set_config,
  309. .destroy = omap_crtc_destroy,
  310. .page_flip = omap_crtc_page_flip_locked,
  311. .set_property = omap_crtc_set_property,
  312. };
  313. static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = {
  314. .dpms = omap_crtc_dpms,
  315. .mode_fixup = omap_crtc_mode_fixup,
  316. .mode_set = omap_crtc_mode_set,
  317. .prepare = omap_crtc_prepare,
  318. .commit = omap_crtc_commit,
  319. .mode_set_base = omap_crtc_mode_set_base,
  320. };
  321. const struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc)
  322. {
  323. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  324. return &omap_crtc->timings;
  325. }
  326. enum omap_channel omap_crtc_channel(struct drm_crtc *crtc)
  327. {
  328. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  329. return omap_crtc->channel;
  330. }
  331. static void omap_crtc_error_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
  332. {
  333. struct omap_crtc *omap_crtc =
  334. container_of(irq, struct omap_crtc, error_irq);
  335. struct drm_crtc *crtc = &omap_crtc->base;
  336. DRM_ERROR("%s: errors: %08x\n", omap_crtc->name, irqstatus);
  337. /* avoid getting in a flood, unregister the irq until next vblank */
  338. __omap_irq_unregister(crtc->dev, &omap_crtc->error_irq);
  339. }
  340. static void omap_crtc_apply_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
  341. {
  342. struct omap_crtc *omap_crtc =
  343. container_of(irq, struct omap_crtc, apply_irq);
  344. struct drm_crtc *crtc = &omap_crtc->base;
  345. if (!omap_crtc->error_irq.registered)
  346. __omap_irq_register(crtc->dev, &omap_crtc->error_irq);
  347. if (!dispc_mgr_go_busy(omap_crtc->channel)) {
  348. struct omap_drm_private *priv =
  349. crtc->dev->dev_private;
  350. DBG("%s: apply done", omap_crtc->name);
  351. __omap_irq_unregister(crtc->dev, &omap_crtc->apply_irq);
  352. queue_work(priv->wq, &omap_crtc->apply_work);
  353. }
  354. }
  355. static void apply_worker(struct work_struct *work)
  356. {
  357. struct omap_crtc *omap_crtc =
  358. container_of(work, struct omap_crtc, apply_work);
  359. struct drm_crtc *crtc = &omap_crtc->base;
  360. struct drm_device *dev = crtc->dev;
  361. struct omap_drm_apply *apply, *n;
  362. bool need_apply;
  363. /*
  364. * Synchronize everything on mode_config.mutex, to keep
  365. * the callbacks and list modification all serialized
  366. * with respect to modesetting ioctls from userspace.
  367. */
  368. mutex_lock(&crtc->mutex);
  369. dispc_runtime_get();
  370. /*
  371. * If we are still pending a previous update, wait.. when the
  372. * pending update completes, we get kicked again.
  373. */
  374. if (omap_crtc->apply_irq.registered)
  375. goto out;
  376. /* finish up previous apply's: */
  377. list_for_each_entry_safe(apply, n,
  378. &omap_crtc->pending_applies, pending_node) {
  379. apply->post_apply(apply);
  380. list_del(&apply->pending_node);
  381. }
  382. need_apply = !list_empty(&omap_crtc->queued_applies);
  383. /* then handle the next round of of queued apply's: */
  384. list_for_each_entry_safe(apply, n,
  385. &omap_crtc->queued_applies, queued_node) {
  386. apply->pre_apply(apply);
  387. list_del(&apply->queued_node);
  388. apply->queued = false;
  389. list_add_tail(&apply->pending_node,
  390. &omap_crtc->pending_applies);
  391. }
  392. if (need_apply) {
  393. enum omap_channel channel = omap_crtc->channel;
  394. DBG("%s: GO", omap_crtc->name);
  395. if (dispc_mgr_is_enabled(channel)) {
  396. omap_irq_register(dev, &omap_crtc->apply_irq);
  397. dispc_mgr_go(channel);
  398. } else {
  399. struct omap_drm_private *priv = dev->dev_private;
  400. queue_work(priv->wq, &omap_crtc->apply_work);
  401. }
  402. }
  403. out:
  404. dispc_runtime_put();
  405. mutex_unlock(&crtc->mutex);
  406. }
  407. int omap_crtc_apply(struct drm_crtc *crtc,
  408. struct omap_drm_apply *apply)
  409. {
  410. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  411. WARN_ON(!mutex_is_locked(&crtc->mutex));
  412. /* no need to queue it again if it is already queued: */
  413. if (apply->queued)
  414. return 0;
  415. apply->queued = true;
  416. list_add_tail(&apply->queued_node, &omap_crtc->queued_applies);
  417. /*
  418. * If there are no currently pending updates, then go ahead and
  419. * kick the worker immediately, otherwise it will run again when
  420. * the current update finishes.
  421. */
  422. if (list_empty(&omap_crtc->pending_applies)) {
  423. struct omap_drm_private *priv = crtc->dev->dev_private;
  424. queue_work(priv->wq, &omap_crtc->apply_work);
  425. }
  426. return 0;
  427. }
  428. /* called only from apply */
  429. static void set_enabled(struct drm_crtc *crtc, bool enable)
  430. {
  431. struct drm_device *dev = crtc->dev;
  432. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  433. enum omap_channel channel = omap_crtc->channel;
  434. struct omap_irq_wait *wait = NULL;
  435. if (dispc_mgr_is_enabled(channel) == enable)
  436. return;
  437. /* ignore sync-lost irqs during enable/disable */
  438. omap_irq_unregister(crtc->dev, &omap_crtc->error_irq);
  439. if (dispc_mgr_get_framedone_irq(channel)) {
  440. if (!enable) {
  441. wait = omap_irq_wait_init(dev,
  442. dispc_mgr_get_framedone_irq(channel), 1);
  443. }
  444. } else {
  445. /*
  446. * When we disable digit output, we need to wait until fields
  447. * are done. Otherwise the DSS is still working, and turning
  448. * off the clocks prevents DSS from going to OFF mode. And when
  449. * enabling, we need to wait for the extra sync losts
  450. */
  451. wait = omap_irq_wait_init(dev,
  452. dispc_mgr_get_vsync_irq(channel), 2);
  453. }
  454. dispc_mgr_enable(channel, enable);
  455. if (wait) {
  456. int ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100));
  457. if (ret) {
  458. dev_err(dev->dev, "%s: timeout waiting for %s\n",
  459. omap_crtc->name, enable ? "enable" : "disable");
  460. }
  461. }
  462. omap_irq_register(crtc->dev, &omap_crtc->error_irq);
  463. }
  464. static void omap_crtc_pre_apply(struct omap_drm_apply *apply)
  465. {
  466. struct omap_crtc *omap_crtc =
  467. container_of(apply, struct omap_crtc, apply);
  468. struct drm_crtc *crtc = &omap_crtc->base;
  469. struct drm_encoder *encoder = NULL;
  470. DBG("%s: enabled=%d, full=%d", omap_crtc->name,
  471. omap_crtc->enabled, omap_crtc->full_update);
  472. if (omap_crtc->full_update) {
  473. struct omap_drm_private *priv = crtc->dev->dev_private;
  474. int i;
  475. for (i = 0; i < priv->num_encoders; i++) {
  476. if (priv->encoders[i]->crtc == crtc) {
  477. encoder = priv->encoders[i];
  478. break;
  479. }
  480. }
  481. }
  482. if (!omap_crtc->enabled) {
  483. set_enabled(&omap_crtc->base, false);
  484. if (encoder)
  485. omap_encoder_set_enabled(encoder, false);
  486. } else {
  487. if (encoder) {
  488. omap_encoder_set_enabled(encoder, false);
  489. omap_encoder_update(encoder, omap_crtc->mgr,
  490. &omap_crtc->timings);
  491. omap_encoder_set_enabled(encoder, true);
  492. omap_crtc->full_update = false;
  493. }
  494. dispc_mgr_setup(omap_crtc->channel, &omap_crtc->info);
  495. dispc_mgr_set_timings(omap_crtc->channel,
  496. &omap_crtc->timings);
  497. set_enabled(&omap_crtc->base, true);
  498. }
  499. omap_crtc->full_update = false;
  500. }
  501. static void omap_crtc_post_apply(struct omap_drm_apply *apply)
  502. {
  503. /* nothing needed for post-apply */
  504. }
  505. static const char *channel_names[] = {
  506. [OMAP_DSS_CHANNEL_LCD] = "lcd",
  507. [OMAP_DSS_CHANNEL_DIGIT] = "tv",
  508. [OMAP_DSS_CHANNEL_LCD2] = "lcd2",
  509. };
  510. void omap_crtc_pre_init(void)
  511. {
  512. dss_install_mgr_ops(&mgr_ops);
  513. }
  514. void omap_crtc_pre_uninit(void)
  515. {
  516. dss_uninstall_mgr_ops();
  517. }
  518. /* initialize crtc */
  519. struct drm_crtc *omap_crtc_init(struct drm_device *dev,
  520. struct drm_plane *plane, enum omap_channel channel, int id)
  521. {
  522. struct drm_crtc *crtc = NULL;
  523. struct omap_crtc *omap_crtc;
  524. struct omap_overlay_manager_info *info;
  525. DBG("%s", channel_names[channel]);
  526. omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL);
  527. if (!omap_crtc)
  528. goto fail;
  529. crtc = &omap_crtc->base;
  530. INIT_WORK(&omap_crtc->page_flip_work, page_flip_worker);
  531. INIT_WORK(&omap_crtc->apply_work, apply_worker);
  532. INIT_LIST_HEAD(&omap_crtc->pending_applies);
  533. INIT_LIST_HEAD(&omap_crtc->queued_applies);
  534. omap_crtc->apply.pre_apply = omap_crtc_pre_apply;
  535. omap_crtc->apply.post_apply = omap_crtc_post_apply;
  536. omap_crtc->channel = channel;
  537. omap_crtc->plane = plane;
  538. omap_crtc->plane->crtc = crtc;
  539. omap_crtc->name = channel_names[channel];
  540. omap_crtc->pipe = id;
  541. omap_crtc->apply_irq.irqmask = pipe2vbl(crtc);
  542. omap_crtc->apply_irq.irq = omap_crtc_apply_irq;
  543. omap_crtc->error_irq.irqmask =
  544. dispc_mgr_get_sync_lost_irq(channel);
  545. omap_crtc->error_irq.irq = omap_crtc_error_irq;
  546. omap_irq_register(dev, &omap_crtc->error_irq);
  547. /* temporary: */
  548. omap_crtc->mgr = omap_dss_get_overlay_manager(channel);
  549. /* TODO: fix hard-coded setup.. add properties! */
  550. info = &omap_crtc->info;
  551. info->default_color = 0x00000000;
  552. info->trans_key = 0x00000000;
  553. info->trans_key_type = OMAP_DSS_COLOR_KEY_GFX_DST;
  554. info->trans_enabled = false;
  555. drm_crtc_init(dev, crtc, &omap_crtc_funcs);
  556. drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs);
  557. omap_plane_install_properties(omap_crtc->plane, &crtc->base);
  558. omap_crtcs[channel] = omap_crtc;
  559. return crtc;
  560. fail:
  561. if (crtc)
  562. omap_crtc_destroy(crtc);
  563. return NULL;
  564. }