tilcdc_drv.c 19 KB

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  1. /*
  2. * Copyright (C) 2012 Texas Instruments
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. /* LCDC DRM driver, based on da8xx-fb */
  18. #include <linux/component.h>
  19. #include <linux/pinctrl/consumer.h>
  20. #include <linux/suspend.h>
  21. #include <drm/drm_atomic.h>
  22. #include <drm/drm_atomic_helper.h>
  23. #include "tilcdc_drv.h"
  24. #include "tilcdc_regs.h"
  25. #include "tilcdc_tfp410.h"
  26. #include "tilcdc_panel.h"
  27. #include "tilcdc_external.h"
  28. #include "drm_fb_helper.h"
  29. static LIST_HEAD(module_list);
  30. static const u32 tilcdc_rev1_formats[] = { DRM_FORMAT_RGB565 };
  31. static const u32 tilcdc_straight_formats[] = { DRM_FORMAT_RGB565,
  32. DRM_FORMAT_BGR888,
  33. DRM_FORMAT_XBGR8888 };
  34. static const u32 tilcdc_crossed_formats[] = { DRM_FORMAT_BGR565,
  35. DRM_FORMAT_RGB888,
  36. DRM_FORMAT_XRGB8888 };
  37. static const u32 tilcdc_legacy_formats[] = { DRM_FORMAT_RGB565,
  38. DRM_FORMAT_RGB888,
  39. DRM_FORMAT_XRGB8888 };
  40. void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
  41. const struct tilcdc_module_ops *funcs)
  42. {
  43. mod->name = name;
  44. mod->funcs = funcs;
  45. INIT_LIST_HEAD(&mod->list);
  46. list_add(&mod->list, &module_list);
  47. }
  48. void tilcdc_module_cleanup(struct tilcdc_module *mod)
  49. {
  50. list_del(&mod->list);
  51. }
  52. static struct of_device_id tilcdc_of_match[];
  53. static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev,
  54. struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
  55. {
  56. return drm_fb_cma_create(dev, file_priv, mode_cmd);
  57. }
  58. static void tilcdc_fb_output_poll_changed(struct drm_device *dev)
  59. {
  60. struct tilcdc_drm_private *priv = dev->dev_private;
  61. drm_fbdev_cma_hotplug_event(priv->fbdev);
  62. }
  63. static int tilcdc_atomic_check(struct drm_device *dev,
  64. struct drm_atomic_state *state)
  65. {
  66. int ret;
  67. ret = drm_atomic_helper_check_modeset(dev, state);
  68. if (ret)
  69. return ret;
  70. ret = drm_atomic_helper_check_planes(dev, state);
  71. if (ret)
  72. return ret;
  73. /*
  74. * tilcdc ->atomic_check can update ->mode_changed if pixel format
  75. * changes, hence will we check modeset changes again.
  76. */
  77. ret = drm_atomic_helper_check_modeset(dev, state);
  78. if (ret)
  79. return ret;
  80. return ret;
  81. }
  82. static int tilcdc_commit(struct drm_device *dev,
  83. struct drm_atomic_state *state,
  84. bool async)
  85. {
  86. int ret;
  87. ret = drm_atomic_helper_prepare_planes(dev, state);
  88. if (ret)
  89. return ret;
  90. drm_atomic_helper_swap_state(state, true);
  91. /*
  92. * Everything below can be run asynchronously without the need to grab
  93. * any modeset locks at all under one condition: It must be guaranteed
  94. * that the asynchronous work has either been cancelled (if the driver
  95. * supports it, which at least requires that the framebuffers get
  96. * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
  97. * before the new state gets committed on the software side with
  98. * drm_atomic_helper_swap_state().
  99. *
  100. * This scheme allows new atomic state updates to be prepared and
  101. * checked in parallel to the asynchronous completion of the previous
  102. * update. Which is important since compositors need to figure out the
  103. * composition of the next frame right after having submitted the
  104. * current layout.
  105. */
  106. /* Keep HW on while we commit the state. */
  107. pm_runtime_get_sync(dev->dev);
  108. drm_atomic_helper_commit_modeset_disables(dev, state);
  109. drm_atomic_helper_commit_planes(dev, state, 0);
  110. drm_atomic_helper_commit_modeset_enables(dev, state);
  111. /* Now HW should remain on if need becase the crtc is enabled */
  112. pm_runtime_put_sync(dev->dev);
  113. drm_atomic_helper_wait_for_vblanks(dev, state);
  114. drm_atomic_helper_cleanup_planes(dev, state);
  115. return 0;
  116. }
  117. static const struct drm_mode_config_funcs mode_config_funcs = {
  118. .fb_create = tilcdc_fb_create,
  119. .output_poll_changed = tilcdc_fb_output_poll_changed,
  120. .atomic_check = tilcdc_atomic_check,
  121. .atomic_commit = tilcdc_commit,
  122. };
  123. static void modeset_init(struct drm_device *dev)
  124. {
  125. struct tilcdc_drm_private *priv = dev->dev_private;
  126. struct tilcdc_module *mod;
  127. list_for_each_entry(mod, &module_list, list) {
  128. DBG("loading module: %s", mod->name);
  129. mod->funcs->modeset_init(mod, dev);
  130. }
  131. dev->mode_config.min_width = 0;
  132. dev->mode_config.min_height = 0;
  133. dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc);
  134. dev->mode_config.max_height = 2048;
  135. dev->mode_config.funcs = &mode_config_funcs;
  136. }
  137. #ifdef CONFIG_CPU_FREQ
  138. static int cpufreq_transition(struct notifier_block *nb,
  139. unsigned long val, void *data)
  140. {
  141. struct tilcdc_drm_private *priv = container_of(nb,
  142. struct tilcdc_drm_private, freq_transition);
  143. if (val == CPUFREQ_POSTCHANGE)
  144. tilcdc_crtc_update_clk(priv->crtc);
  145. return 0;
  146. }
  147. #endif
  148. /*
  149. * DRM operations:
  150. */
  151. static void tilcdc_fini(struct drm_device *dev)
  152. {
  153. struct tilcdc_drm_private *priv = dev->dev_private;
  154. if (priv->crtc)
  155. tilcdc_crtc_shutdown(priv->crtc);
  156. if (priv->is_registered)
  157. drm_dev_unregister(dev);
  158. drm_kms_helper_poll_fini(dev);
  159. if (priv->fbdev)
  160. drm_fbdev_cma_fini(priv->fbdev);
  161. drm_irq_uninstall(dev);
  162. drm_mode_config_cleanup(dev);
  163. tilcdc_remove_external_device(dev);
  164. #ifdef CONFIG_CPU_FREQ
  165. if (priv->freq_transition.notifier_call)
  166. cpufreq_unregister_notifier(&priv->freq_transition,
  167. CPUFREQ_TRANSITION_NOTIFIER);
  168. #endif
  169. if (priv->clk)
  170. clk_put(priv->clk);
  171. if (priv->mmio)
  172. iounmap(priv->mmio);
  173. if (priv->wq) {
  174. flush_workqueue(priv->wq);
  175. destroy_workqueue(priv->wq);
  176. }
  177. dev->dev_private = NULL;
  178. pm_runtime_disable(dev->dev);
  179. drm_dev_unref(dev);
  180. }
  181. static int tilcdc_init(struct drm_driver *ddrv, struct device *dev)
  182. {
  183. struct drm_device *ddev;
  184. struct platform_device *pdev = to_platform_device(dev);
  185. struct device_node *node = dev->of_node;
  186. struct tilcdc_drm_private *priv;
  187. struct resource *res;
  188. u32 bpp = 0;
  189. int ret;
  190. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  191. if (!priv) {
  192. dev_err(dev, "failed to allocate private data\n");
  193. return -ENOMEM;
  194. }
  195. ddev = drm_dev_alloc(ddrv, dev);
  196. if (IS_ERR(ddev))
  197. return PTR_ERR(ddev);
  198. ddev->platformdev = pdev;
  199. ddev->dev_private = priv;
  200. platform_set_drvdata(pdev, ddev);
  201. drm_mode_config_init(ddev);
  202. priv->is_componentized =
  203. tilcdc_get_external_components(dev, NULL) > 0;
  204. priv->wq = alloc_ordered_workqueue("tilcdc", 0);
  205. if (!priv->wq) {
  206. ret = -ENOMEM;
  207. goto init_failed;
  208. }
  209. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  210. if (!res) {
  211. dev_err(dev, "failed to get memory resource\n");
  212. ret = -EINVAL;
  213. goto init_failed;
  214. }
  215. priv->mmio = ioremap_nocache(res->start, resource_size(res));
  216. if (!priv->mmio) {
  217. dev_err(dev, "failed to ioremap\n");
  218. ret = -ENOMEM;
  219. goto init_failed;
  220. }
  221. priv->clk = clk_get(dev, "fck");
  222. if (IS_ERR(priv->clk)) {
  223. dev_err(dev, "failed to get functional clock\n");
  224. ret = -ENODEV;
  225. goto init_failed;
  226. }
  227. #ifdef CONFIG_CPU_FREQ
  228. priv->freq_transition.notifier_call = cpufreq_transition;
  229. ret = cpufreq_register_notifier(&priv->freq_transition,
  230. CPUFREQ_TRANSITION_NOTIFIER);
  231. if (ret) {
  232. dev_err(dev, "failed to register cpufreq notifier\n");
  233. priv->freq_transition.notifier_call = NULL;
  234. goto init_failed;
  235. }
  236. #endif
  237. if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
  238. priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH;
  239. DBG("Maximum Bandwidth Value %d", priv->max_bandwidth);
  240. if (of_property_read_u32(node, "ti,max-width", &priv->max_width))
  241. priv->max_width = TILCDC_DEFAULT_MAX_WIDTH;
  242. DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width);
  243. if (of_property_read_u32(node, "ti,max-pixelclock",
  244. &priv->max_pixelclock))
  245. priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK;
  246. DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock);
  247. pm_runtime_enable(dev);
  248. /* Determine LCD IP Version */
  249. pm_runtime_get_sync(dev);
  250. switch (tilcdc_read(ddev, LCDC_PID_REG)) {
  251. case 0x4c100102:
  252. priv->rev = 1;
  253. break;
  254. case 0x4f200800:
  255. case 0x4f201000:
  256. priv->rev = 2;
  257. break;
  258. default:
  259. dev_warn(dev, "Unknown PID Reg value 0x%08x, "
  260. "defaulting to LCD revision 1\n",
  261. tilcdc_read(ddev, LCDC_PID_REG));
  262. priv->rev = 1;
  263. break;
  264. }
  265. pm_runtime_put_sync(dev);
  266. if (priv->rev == 1) {
  267. DBG("Revision 1 LCDC supports only RGB565 format");
  268. priv->pixelformats = tilcdc_rev1_formats;
  269. priv->num_pixelformats = ARRAY_SIZE(tilcdc_rev1_formats);
  270. bpp = 16;
  271. } else {
  272. const char *str = "\0";
  273. of_property_read_string(node, "blue-and-red-wiring", &str);
  274. if (0 == strcmp(str, "crossed")) {
  275. DBG("Configured for crossed blue and red wires");
  276. priv->pixelformats = tilcdc_crossed_formats;
  277. priv->num_pixelformats =
  278. ARRAY_SIZE(tilcdc_crossed_formats);
  279. bpp = 32; /* Choose bpp with RGB support for fbdef */
  280. } else if (0 == strcmp(str, "straight")) {
  281. DBG("Configured for straight blue and red wires");
  282. priv->pixelformats = tilcdc_straight_formats;
  283. priv->num_pixelformats =
  284. ARRAY_SIZE(tilcdc_straight_formats);
  285. bpp = 16; /* Choose bpp with RGB support for fbdef */
  286. } else {
  287. DBG("Blue and red wiring '%s' unknown, use legacy mode",
  288. str);
  289. priv->pixelformats = tilcdc_legacy_formats;
  290. priv->num_pixelformats =
  291. ARRAY_SIZE(tilcdc_legacy_formats);
  292. bpp = 16; /* This is just a guess */
  293. }
  294. }
  295. ret = tilcdc_crtc_create(ddev);
  296. if (ret < 0) {
  297. dev_err(dev, "failed to create crtc\n");
  298. goto init_failed;
  299. }
  300. modeset_init(ddev);
  301. if (priv->is_componentized) {
  302. ret = component_bind_all(dev, ddev);
  303. if (ret < 0)
  304. goto init_failed;
  305. ret = tilcdc_add_component_encoder(ddev);
  306. if (ret < 0)
  307. goto init_failed;
  308. } else {
  309. ret = tilcdc_attach_external_device(ddev);
  310. if (ret)
  311. goto init_failed;
  312. }
  313. if (!priv->external_connector &&
  314. ((priv->num_encoders == 0) || (priv->num_connectors == 0))) {
  315. dev_err(dev, "no encoders/connectors found\n");
  316. ret = -ENXIO;
  317. goto init_failed;
  318. }
  319. ret = drm_vblank_init(ddev, 1);
  320. if (ret < 0) {
  321. dev_err(dev, "failed to initialize vblank\n");
  322. goto init_failed;
  323. }
  324. ret = drm_irq_install(ddev, platform_get_irq(pdev, 0));
  325. if (ret < 0) {
  326. dev_err(dev, "failed to install IRQ handler\n");
  327. goto init_failed;
  328. }
  329. drm_mode_config_reset(ddev);
  330. priv->fbdev = drm_fbdev_cma_init(ddev, bpp,
  331. ddev->mode_config.num_crtc,
  332. ddev->mode_config.num_connector);
  333. if (IS_ERR(priv->fbdev)) {
  334. ret = PTR_ERR(priv->fbdev);
  335. goto init_failed;
  336. }
  337. drm_kms_helper_poll_init(ddev);
  338. ret = drm_dev_register(ddev, 0);
  339. if (ret)
  340. goto init_failed;
  341. priv->is_registered = true;
  342. return 0;
  343. init_failed:
  344. tilcdc_fini(ddev);
  345. return ret;
  346. }
  347. static void tilcdc_lastclose(struct drm_device *dev)
  348. {
  349. struct tilcdc_drm_private *priv = dev->dev_private;
  350. drm_fbdev_cma_restore_mode(priv->fbdev);
  351. }
  352. static irqreturn_t tilcdc_irq(int irq, void *arg)
  353. {
  354. struct drm_device *dev = arg;
  355. struct tilcdc_drm_private *priv = dev->dev_private;
  356. return tilcdc_crtc_irq(priv->crtc);
  357. }
  358. static int tilcdc_enable_vblank(struct drm_device *dev, unsigned int pipe)
  359. {
  360. return 0;
  361. }
  362. static void tilcdc_disable_vblank(struct drm_device *dev, unsigned int pipe)
  363. {
  364. return;
  365. }
  366. #if defined(CONFIG_DEBUG_FS)
  367. static const struct {
  368. const char *name;
  369. uint8_t rev;
  370. uint8_t save;
  371. uint32_t reg;
  372. } registers[] = {
  373. #define REG(rev, save, reg) { #reg, rev, save, reg }
  374. /* exists in revision 1: */
  375. REG(1, false, LCDC_PID_REG),
  376. REG(1, true, LCDC_CTRL_REG),
  377. REG(1, false, LCDC_STAT_REG),
  378. REG(1, true, LCDC_RASTER_CTRL_REG),
  379. REG(1, true, LCDC_RASTER_TIMING_0_REG),
  380. REG(1, true, LCDC_RASTER_TIMING_1_REG),
  381. REG(1, true, LCDC_RASTER_TIMING_2_REG),
  382. REG(1, true, LCDC_DMA_CTRL_REG),
  383. REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG),
  384. REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG),
  385. REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG),
  386. REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG),
  387. /* new in revision 2: */
  388. REG(2, false, LCDC_RAW_STAT_REG),
  389. REG(2, false, LCDC_MASKED_STAT_REG),
  390. REG(2, true, LCDC_INT_ENABLE_SET_REG),
  391. REG(2, false, LCDC_INT_ENABLE_CLR_REG),
  392. REG(2, false, LCDC_END_OF_INT_IND_REG),
  393. REG(2, true, LCDC_CLK_ENABLE_REG),
  394. #undef REG
  395. };
  396. #endif
  397. #ifdef CONFIG_DEBUG_FS
  398. static int tilcdc_regs_show(struct seq_file *m, void *arg)
  399. {
  400. struct drm_info_node *node = (struct drm_info_node *) m->private;
  401. struct drm_device *dev = node->minor->dev;
  402. struct tilcdc_drm_private *priv = dev->dev_private;
  403. unsigned i;
  404. pm_runtime_get_sync(dev->dev);
  405. seq_printf(m, "revision: %d\n", priv->rev);
  406. for (i = 0; i < ARRAY_SIZE(registers); i++)
  407. if (priv->rev >= registers[i].rev)
  408. seq_printf(m, "%s:\t %08x\n", registers[i].name,
  409. tilcdc_read(dev, registers[i].reg));
  410. pm_runtime_put_sync(dev->dev);
  411. return 0;
  412. }
  413. static int tilcdc_mm_show(struct seq_file *m, void *arg)
  414. {
  415. struct drm_info_node *node = (struct drm_info_node *) m->private;
  416. struct drm_device *dev = node->minor->dev;
  417. return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm);
  418. }
  419. static struct drm_info_list tilcdc_debugfs_list[] = {
  420. { "regs", tilcdc_regs_show, 0 },
  421. { "mm", tilcdc_mm_show, 0 },
  422. { "fb", drm_fb_cma_debugfs_show, 0 },
  423. };
  424. static int tilcdc_debugfs_init(struct drm_minor *minor)
  425. {
  426. struct drm_device *dev = minor->dev;
  427. struct tilcdc_module *mod;
  428. int ret;
  429. ret = drm_debugfs_create_files(tilcdc_debugfs_list,
  430. ARRAY_SIZE(tilcdc_debugfs_list),
  431. minor->debugfs_root, minor);
  432. list_for_each_entry(mod, &module_list, list)
  433. if (mod->funcs->debugfs_init)
  434. mod->funcs->debugfs_init(mod, minor);
  435. if (ret) {
  436. dev_err(dev->dev, "could not install tilcdc_debugfs_list\n");
  437. return ret;
  438. }
  439. return ret;
  440. }
  441. static void tilcdc_debugfs_cleanup(struct drm_minor *minor)
  442. {
  443. struct tilcdc_module *mod;
  444. drm_debugfs_remove_files(tilcdc_debugfs_list,
  445. ARRAY_SIZE(tilcdc_debugfs_list), minor);
  446. list_for_each_entry(mod, &module_list, list)
  447. if (mod->funcs->debugfs_cleanup)
  448. mod->funcs->debugfs_cleanup(mod, minor);
  449. }
  450. #endif
  451. static const struct file_operations fops = {
  452. .owner = THIS_MODULE,
  453. .open = drm_open,
  454. .release = drm_release,
  455. .unlocked_ioctl = drm_ioctl,
  456. .compat_ioctl = drm_compat_ioctl,
  457. .poll = drm_poll,
  458. .read = drm_read,
  459. .llseek = no_llseek,
  460. .mmap = drm_gem_cma_mmap,
  461. };
  462. static struct drm_driver tilcdc_driver = {
  463. .driver_features = (DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET |
  464. DRIVER_PRIME | DRIVER_ATOMIC),
  465. .lastclose = tilcdc_lastclose,
  466. .irq_handler = tilcdc_irq,
  467. .get_vblank_counter = drm_vblank_no_hw_counter,
  468. .enable_vblank = tilcdc_enable_vblank,
  469. .disable_vblank = tilcdc_disable_vblank,
  470. .gem_free_object_unlocked = drm_gem_cma_free_object,
  471. .gem_vm_ops = &drm_gem_cma_vm_ops,
  472. .dumb_create = drm_gem_cma_dumb_create,
  473. .dumb_map_offset = drm_gem_cma_dumb_map_offset,
  474. .dumb_destroy = drm_gem_dumb_destroy,
  475. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  476. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  477. .gem_prime_import = drm_gem_prime_import,
  478. .gem_prime_export = drm_gem_prime_export,
  479. .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
  480. .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
  481. .gem_prime_vmap = drm_gem_cma_prime_vmap,
  482. .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
  483. .gem_prime_mmap = drm_gem_cma_prime_mmap,
  484. #ifdef CONFIG_DEBUG_FS
  485. .debugfs_init = tilcdc_debugfs_init,
  486. .debugfs_cleanup = tilcdc_debugfs_cleanup,
  487. #endif
  488. .fops = &fops,
  489. .name = "tilcdc",
  490. .desc = "TI LCD Controller DRM",
  491. .date = "20121205",
  492. .major = 1,
  493. .minor = 0,
  494. };
  495. /*
  496. * Power management:
  497. */
  498. #ifdef CONFIG_PM_SLEEP
  499. static int tilcdc_pm_suspend(struct device *dev)
  500. {
  501. struct drm_device *ddev = dev_get_drvdata(dev);
  502. struct tilcdc_drm_private *priv = ddev->dev_private;
  503. priv->saved_state = drm_atomic_helper_suspend(ddev);
  504. /* Select sleep pin state */
  505. pinctrl_pm_select_sleep_state(dev);
  506. return 0;
  507. }
  508. static int tilcdc_pm_resume(struct device *dev)
  509. {
  510. struct drm_device *ddev = dev_get_drvdata(dev);
  511. struct tilcdc_drm_private *priv = ddev->dev_private;
  512. int ret = 0;
  513. /* Select default pin state */
  514. pinctrl_pm_select_default_state(dev);
  515. if (priv->saved_state)
  516. ret = drm_atomic_helper_resume(ddev, priv->saved_state);
  517. return ret;
  518. }
  519. #endif
  520. static const struct dev_pm_ops tilcdc_pm_ops = {
  521. SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume)
  522. };
  523. /*
  524. * Platform driver:
  525. */
  526. static int tilcdc_bind(struct device *dev)
  527. {
  528. return tilcdc_init(&tilcdc_driver, dev);
  529. }
  530. static void tilcdc_unbind(struct device *dev)
  531. {
  532. struct drm_device *ddev = dev_get_drvdata(dev);
  533. /* Check if a subcomponent has already triggered the unloading. */
  534. if (!ddev->dev_private)
  535. return;
  536. tilcdc_fini(dev_get_drvdata(dev));
  537. }
  538. static const struct component_master_ops tilcdc_comp_ops = {
  539. .bind = tilcdc_bind,
  540. .unbind = tilcdc_unbind,
  541. };
  542. static int tilcdc_pdev_probe(struct platform_device *pdev)
  543. {
  544. struct component_match *match = NULL;
  545. int ret;
  546. /* bail out early if no DT data: */
  547. if (!pdev->dev.of_node) {
  548. dev_err(&pdev->dev, "device-tree data is missing\n");
  549. return -ENXIO;
  550. }
  551. ret = tilcdc_get_external_components(&pdev->dev, &match);
  552. if (ret < 0)
  553. return ret;
  554. else if (ret == 0)
  555. return tilcdc_init(&tilcdc_driver, &pdev->dev);
  556. else
  557. return component_master_add_with_match(&pdev->dev,
  558. &tilcdc_comp_ops,
  559. match);
  560. }
  561. static int tilcdc_pdev_remove(struct platform_device *pdev)
  562. {
  563. int ret;
  564. ret = tilcdc_get_external_components(&pdev->dev, NULL);
  565. if (ret < 0)
  566. return ret;
  567. else if (ret == 0)
  568. tilcdc_fini(platform_get_drvdata(pdev));
  569. else
  570. component_master_del(&pdev->dev, &tilcdc_comp_ops);
  571. return 0;
  572. }
  573. static struct of_device_id tilcdc_of_match[] = {
  574. { .compatible = "ti,am33xx-tilcdc", },
  575. { .compatible = "ti,da850-tilcdc", },
  576. { },
  577. };
  578. MODULE_DEVICE_TABLE(of, tilcdc_of_match);
  579. static struct platform_driver tilcdc_platform_driver = {
  580. .probe = tilcdc_pdev_probe,
  581. .remove = tilcdc_pdev_remove,
  582. .driver = {
  583. .name = "tilcdc",
  584. .pm = &tilcdc_pm_ops,
  585. .of_match_table = tilcdc_of_match,
  586. },
  587. };
  588. static int __init tilcdc_drm_init(void)
  589. {
  590. DBG("init");
  591. tilcdc_tfp410_init();
  592. tilcdc_panel_init();
  593. return platform_driver_register(&tilcdc_platform_driver);
  594. }
  595. static void __exit tilcdc_drm_fini(void)
  596. {
  597. DBG("fini");
  598. platform_driver_unregister(&tilcdc_platform_driver);
  599. tilcdc_panel_fini();
  600. tilcdc_tfp410_fini();
  601. }
  602. module_init(tilcdc_drm_init);
  603. module_exit(tilcdc_drm_fini);
  604. MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
  605. MODULE_DESCRIPTION("TI LCD Controller DRM Driver");
  606. MODULE_LICENSE("GPL");