amdgpu_queue_mgr.c 6.1 KB

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  1. /*
  2. * Copyright 2017 Valve Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Andres Rodriguez
  23. */
  24. #include "amdgpu.h"
  25. #include "amdgpu_ring.h"
  26. static int amdgpu_queue_mapper_init(struct amdgpu_queue_mapper *mapper,
  27. int hw_ip)
  28. {
  29. if (!mapper)
  30. return -EINVAL;
  31. if (hw_ip > AMDGPU_MAX_IP_NUM)
  32. return -EINVAL;
  33. mapper->hw_ip = hw_ip;
  34. mutex_init(&mapper->lock);
  35. memset(mapper->queue_map, 0, sizeof(mapper->queue_map));
  36. return 0;
  37. }
  38. static struct amdgpu_ring *amdgpu_get_cached_map(struct amdgpu_queue_mapper *mapper,
  39. int ring)
  40. {
  41. return mapper->queue_map[ring];
  42. }
  43. static int amdgpu_update_cached_map(struct amdgpu_queue_mapper *mapper,
  44. int ring, struct amdgpu_ring *pring)
  45. {
  46. if (WARN_ON(mapper->queue_map[ring])) {
  47. DRM_ERROR("Un-expected ring re-map\n");
  48. return -EINVAL;
  49. }
  50. mapper->queue_map[ring] = pring;
  51. return 0;
  52. }
  53. static int amdgpu_identity_map(struct amdgpu_device *adev,
  54. struct amdgpu_queue_mapper *mapper,
  55. int ring,
  56. struct amdgpu_ring **out_ring)
  57. {
  58. switch (mapper->hw_ip) {
  59. case AMDGPU_HW_IP_GFX:
  60. *out_ring = &adev->gfx.gfx_ring[ring];
  61. break;
  62. case AMDGPU_HW_IP_COMPUTE:
  63. *out_ring = &adev->gfx.compute_ring[ring];
  64. break;
  65. case AMDGPU_HW_IP_DMA:
  66. *out_ring = &adev->sdma.instance[ring].ring;
  67. break;
  68. case AMDGPU_HW_IP_UVD:
  69. *out_ring = &adev->uvd.ring;
  70. break;
  71. case AMDGPU_HW_IP_VCE:
  72. *out_ring = &adev->vce.ring[ring];
  73. break;
  74. case AMDGPU_HW_IP_UVD_ENC:
  75. *out_ring = &adev->uvd.ring_enc[ring];
  76. break;
  77. case AMDGPU_HW_IP_VCN_DEC:
  78. *out_ring = &adev->vcn.ring_dec;
  79. break;
  80. case AMDGPU_HW_IP_VCN_ENC:
  81. *out_ring = &adev->vcn.ring_enc[ring];
  82. break;
  83. default:
  84. *out_ring = NULL;
  85. DRM_ERROR("unknown HW IP type: %d\n", mapper->hw_ip);
  86. return -EINVAL;
  87. }
  88. return amdgpu_update_cached_map(mapper, ring, *out_ring);
  89. }
  90. /**
  91. * amdgpu_queue_mgr_init - init an amdgpu_queue_mgr struct
  92. *
  93. * @adev: amdgpu_device pointer
  94. * @mgr: amdgpu_queue_mgr structure holding queue information
  95. *
  96. * Initialize the the selected @mgr (all asics).
  97. *
  98. * Returns 0 on success, error on failure.
  99. */
  100. int amdgpu_queue_mgr_init(struct amdgpu_device *adev,
  101. struct amdgpu_queue_mgr *mgr)
  102. {
  103. int i, r;
  104. if (!adev || !mgr)
  105. return -EINVAL;
  106. memset(mgr, 0, sizeof(*mgr));
  107. for (i = 0; i < AMDGPU_MAX_IP_NUM; ++i) {
  108. r = amdgpu_queue_mapper_init(&mgr->mapper[i], i);
  109. if (r)
  110. return r;
  111. }
  112. return 0;
  113. }
  114. /**
  115. * amdgpu_queue_mgr_fini - de-initialize an amdgpu_queue_mgr struct
  116. *
  117. * @adev: amdgpu_device pointer
  118. * @mgr: amdgpu_queue_mgr structure holding queue information
  119. *
  120. * De-initialize the the selected @mgr (all asics).
  121. *
  122. * Returns 0 on success, error on failure.
  123. */
  124. int amdgpu_queue_mgr_fini(struct amdgpu_device *adev,
  125. struct amdgpu_queue_mgr *mgr)
  126. {
  127. return 0;
  128. }
  129. /**
  130. * amdgpu_queue_mgr_map - Map a userspace ring id to an amdgpu_ring
  131. *
  132. * @adev: amdgpu_device pointer
  133. * @mgr: amdgpu_queue_mgr structure holding queue information
  134. * @hw_ip: HW IP enum
  135. * @instance: HW instance
  136. * @ring: user ring id
  137. * @our_ring: pointer to mapped amdgpu_ring
  138. *
  139. * Map a userspace ring id to an appropriate kernel ring. Different
  140. * policies are configurable at a HW IP level.
  141. *
  142. * Returns 0 on success, error on failure.
  143. */
  144. int amdgpu_queue_mgr_map(struct amdgpu_device *adev,
  145. struct amdgpu_queue_mgr *mgr,
  146. int hw_ip, int instance, int ring,
  147. struct amdgpu_ring **out_ring)
  148. {
  149. int r, ip_num_rings;
  150. struct amdgpu_queue_mapper *mapper = &mgr->mapper[hw_ip];
  151. if (!adev || !mgr || !out_ring)
  152. return -EINVAL;
  153. if (hw_ip >= AMDGPU_MAX_IP_NUM)
  154. return -EINVAL;
  155. if (ring >= AMDGPU_MAX_RINGS)
  156. return -EINVAL;
  157. /* Right now all IPs have only one instance - multiple rings. */
  158. if (instance != 0) {
  159. DRM_ERROR("invalid ip instance: %d\n", instance);
  160. return -EINVAL;
  161. }
  162. switch (hw_ip) {
  163. case AMDGPU_HW_IP_GFX:
  164. ip_num_rings = adev->gfx.num_gfx_rings;
  165. break;
  166. case AMDGPU_HW_IP_COMPUTE:
  167. ip_num_rings = adev->gfx.num_compute_rings;
  168. break;
  169. case AMDGPU_HW_IP_DMA:
  170. ip_num_rings = adev->sdma.num_instances;
  171. break;
  172. case AMDGPU_HW_IP_UVD:
  173. ip_num_rings = 1;
  174. break;
  175. case AMDGPU_HW_IP_VCE:
  176. ip_num_rings = adev->vce.num_rings;
  177. break;
  178. case AMDGPU_HW_IP_UVD_ENC:
  179. ip_num_rings = adev->uvd.num_enc_rings;
  180. break;
  181. case AMDGPU_HW_IP_VCN_DEC:
  182. ip_num_rings = 1;
  183. break;
  184. case AMDGPU_HW_IP_VCN_ENC:
  185. ip_num_rings = adev->vcn.num_enc_rings;
  186. break;
  187. default:
  188. DRM_ERROR("unknown ip type: %d\n", hw_ip);
  189. return -EINVAL;
  190. }
  191. if (ring >= ip_num_rings) {
  192. DRM_ERROR("Ring index:%d exceeds maximum:%d for ip:%d\n",
  193. ring, ip_num_rings, hw_ip);
  194. return -EINVAL;
  195. }
  196. mutex_lock(&mapper->lock);
  197. *out_ring = amdgpu_get_cached_map(mapper, ring);
  198. if (*out_ring) {
  199. /* cache hit */
  200. r = 0;
  201. goto out_unlock;
  202. }
  203. switch (mapper->hw_ip) {
  204. case AMDGPU_HW_IP_GFX:
  205. case AMDGPU_HW_IP_COMPUTE:
  206. case AMDGPU_HW_IP_DMA:
  207. case AMDGPU_HW_IP_UVD:
  208. case AMDGPU_HW_IP_VCE:
  209. case AMDGPU_HW_IP_UVD_ENC:
  210. case AMDGPU_HW_IP_VCN_DEC:
  211. case AMDGPU_HW_IP_VCN_ENC:
  212. r = amdgpu_identity_map(adev, mapper, ring, out_ring);
  213. break;
  214. default:
  215. *out_ring = NULL;
  216. r = -EINVAL;
  217. DRM_ERROR("unknown HW IP type: %d\n", mapper->hw_ip);
  218. }
  219. out_unlock:
  220. mutex_unlock(&mapper->lock);
  221. return r;
  222. }