logicpd-som-lv.dtsi 8.0 KB

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  1. /*
  2. * This program is free software; you can redistribute it and/or modify
  3. * it under the terms of the GNU General Public License version 2 as
  4. * published by the Free Software Foundation.
  5. */
  6. #include <dt-bindings/input/input.h>
  7. / {
  8. cpus {
  9. cpu@0 {
  10. cpu0-supply = <&vcc>;
  11. };
  12. };
  13. wl12xx_vmmc: wl12xx_vmmc {
  14. compatible = "regulator-fixed";
  15. regulator-name = "vwl1271";
  16. regulator-min-microvolt = <1800000>;
  17. regulator-max-microvolt = <1800000>;
  18. gpio = <&gpio1 3 0>; /* gpio_3 */
  19. startup-delay-us = <70000>;
  20. enable-active-high;
  21. vin-supply = <&vmmc2>;
  22. };
  23. /* HS USB Host PHY on PORT 1 */
  24. hsusb2_phy: hsusb2_phy {
  25. compatible = "usb-nop-xceiv";
  26. reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */
  27. };
  28. };
  29. &gpmc {
  30. ranges = <0 0 0x00000000 0x1000000>; /* CS0: 16MB for NAND */
  31. nand@0,0 {
  32. compatible = "ti,omap2-nand";
  33. reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
  34. interrupt-parent = <&gpmc>;
  35. interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
  36. <1 IRQ_TYPE_NONE>; /* termcount */
  37. linux,mtd-name = "micron,mt29f4g16abbda3w";
  38. nand-bus-width = <16>;
  39. ti,nand-ecc-opt = "bch8";
  40. rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
  41. gpmc,sync-clk-ps = <0>;
  42. gpmc,cs-on-ns = <0>;
  43. gpmc,cs-rd-off-ns = <44>;
  44. gpmc,cs-wr-off-ns = <44>;
  45. gpmc,adv-on-ns = <6>;
  46. gpmc,adv-rd-off-ns = <34>;
  47. gpmc,adv-wr-off-ns = <44>;
  48. gpmc,we-off-ns = <40>;
  49. gpmc,oe-off-ns = <54>;
  50. gpmc,access-ns = <64>;
  51. gpmc,rd-cycle-ns = <82>;
  52. gpmc,wr-cycle-ns = <82>;
  53. gpmc,wr-access-ns = <40>;
  54. gpmc,wr-data-mux-bus-ns = <0>;
  55. gpmc,device-width = <2>;
  56. #address-cells = <1>;
  57. #size-cells = <1>;
  58. /* u-boot uses mtdparts=omap2-nand.0:512k(x-loader),1920k(u-boot),128k(u-boot-env),4m(kernel),-(fs) */
  59. x-loader@0 {
  60. label = "x-loader";
  61. reg = <0 0x80000>;
  62. };
  63. bootloaders@80000 {
  64. label = "u-boot";
  65. reg = <0x80000 0x1e0000>;
  66. };
  67. bootloaders_env@260000 {
  68. label = "u-boot-env";
  69. reg = <0x260000 0x20000>;
  70. };
  71. kernel@280000 {
  72. label = "kernel";
  73. reg = <0x280000 0x400000>;
  74. };
  75. filesystem@680000 {
  76. label = "fs";
  77. reg = <0x680000 0>; /* 0 = MTDPART_SIZ_FULL */
  78. };
  79. };
  80. };
  81. &i2c1 {
  82. clock-frequency = <2600000>;
  83. twl: twl@48 {
  84. reg = <0x48>;
  85. interrupts = <7>; /* SYS_NIRQ cascaded to intc */
  86. interrupt-parent = <&intc>;
  87. twl_audio: audio {
  88. compatible = "ti,twl4030-audio";
  89. codec {
  90. };
  91. };
  92. };
  93. };
  94. &i2c2 {
  95. clock-frequency = <400000>;
  96. };
  97. &i2c3 {
  98. clock-frequency = <400000>;
  99. };
  100. &mmc3 {
  101. interrupts-extended = <&intc 94 &omap3_pmx_core2 0x46>;
  102. pinctrl-0 = <&mmc3_pins>;
  103. pinctrl-names = "default";
  104. vmmc-supply = <&wl12xx_vmmc>;
  105. non-removable;
  106. bus-width = <4>;
  107. cap-power-off-card;
  108. #address-cells = <1>;
  109. #size-cells = <0>;
  110. wlcore: wlcore@2 {
  111. compatible = "ti,wl1273";
  112. reg = <2>;
  113. interrupt-parent = <&gpio5>;
  114. interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; /* gpio 152 */
  115. ref-clock-frequency = <26000000>;
  116. };
  117. };
  118. &usbhshost {
  119. port2-mode = "ehci-phy";
  120. };
  121. &usbhsehci {
  122. phys = <0 &hsusb2_phy>;
  123. };
  124. &omap3_pmx_core {
  125. pinctrl-names = "default";
  126. pinctrl-0 = <&hsusb2_pins>;
  127. mmc3_pins: pinmux_mm3_pins {
  128. pinctrl-single,pins = <
  129. OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */
  130. OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */
  131. OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */
  132. OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */
  133. OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4) /* mcbsp4_clkx.gpio_152 */
  134. OMAP3_CORE1_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */
  135. OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */
  136. OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs2.sdmmc_clk */
  137. >;
  138. };
  139. mcbsp2_pins: pinmux_mcbsp2_pins {
  140. pinctrl-single,pins = <
  141. OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */
  142. OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */
  143. OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */
  144. OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */
  145. >;
  146. };
  147. uart2_pins: pinmux_uart2_pins {
  148. pinctrl-single,pins = <
  149. OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */
  150. OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/
  151. OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
  152. OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
  153. OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* GPIO_162,BT_EN */
  154. >;
  155. };
  156. mcspi1_pins: pinmux_mcspi1_pins {
  157. pinctrl-single,pins = <
  158. OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */
  159. OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */
  160. OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
  161. OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */
  162. >;
  163. };
  164. hsusb2_pins: pinmux_hsusb2_pins {
  165. pinctrl-single,pins = <
  166. OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
  167. OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
  168. OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
  169. OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
  170. OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
  171. OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
  172. >;
  173. };
  174. hsusb_otg_pins: pinmux_hsusb_otg_pins {
  175. pinctrl-single,pins = <
  176. OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */
  177. OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */
  178. OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */
  179. OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */
  180. OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */
  181. OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */
  182. OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */
  183. OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */
  184. OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */
  185. OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */
  186. OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */
  187. OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */
  188. >;
  189. };
  190. };
  191. &omap3_pmx_wkup {
  192. pinctrl-names = "default";
  193. pinctrl-0 = <&hsusb2_reset_pin>;
  194. hsusb2_reset_pin: pinmux_hsusb1_reset_pin {
  195. pinctrl-single,pins = <
  196. OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */
  197. >;
  198. };
  199. };
  200. &omap3_pmx_core2 {
  201. pinctrl-names = "default";
  202. pinctrl-0 = <&hsusb2_2_pins>;
  203. hsusb2_2_pins: pinmux_hsusb2_2_pins {
  204. pinctrl-single,pins = <
  205. OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
  206. OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
  207. OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
  208. OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
  209. OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
  210. OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
  211. >;
  212. };
  213. };
  214. &uart2 {
  215. interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
  216. pinctrl-names = "default";
  217. pinctrl-0 = <&uart2_pins>;
  218. };
  219. &mcspi1 {
  220. pinctrl-names = "default";
  221. pinctrl-0 = <&mcspi1_pins>;
  222. };
  223. #include "twl4030.dtsi"
  224. #include "twl4030_omap3.dtsi"
  225. &twl {
  226. twl_power: power {
  227. compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle";
  228. ti,use_poweroff;
  229. };
  230. };
  231. &twl_gpio {
  232. ti,use-leds;
  233. };