amdgpu_job.c 6.2 KB

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  1. /*
  2. * Copyright 2015 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. *
  23. */
  24. #include <linux/kthread.h>
  25. #include <linux/wait.h>
  26. #include <linux/sched.h>
  27. #include <drm/drmP.h>
  28. #include "amdgpu.h"
  29. #include "amdgpu_trace.h"
  30. static void amdgpu_job_timedout(struct drm_sched_job *s_job)
  31. {
  32. struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched);
  33. struct amdgpu_job *job = to_amdgpu_job(s_job);
  34. DRM_ERROR("ring %s timeout, last signaled seq=%u, last emitted seq=%u\n",
  35. job->base.sched->name, atomic_read(&ring->fence_drv.last_seq),
  36. ring->fence_drv.sync_seq);
  37. amdgpu_device_gpu_recover(job->adev, job, false);
  38. }
  39. int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
  40. struct amdgpu_job **job, struct amdgpu_vm *vm)
  41. {
  42. size_t size = sizeof(struct amdgpu_job);
  43. if (num_ibs == 0)
  44. return -EINVAL;
  45. size += sizeof(struct amdgpu_ib) * num_ibs;
  46. *job = kzalloc(size, GFP_KERNEL);
  47. if (!*job)
  48. return -ENOMEM;
  49. (*job)->adev = adev;
  50. (*job)->vm = vm;
  51. (*job)->ibs = (void *)&(*job)[1];
  52. (*job)->num_ibs = num_ibs;
  53. amdgpu_sync_create(&(*job)->sync);
  54. amdgpu_sync_create(&(*job)->sched_sync);
  55. (*job)->vram_lost_counter = atomic_read(&adev->vram_lost_counter);
  56. return 0;
  57. }
  58. int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
  59. struct amdgpu_job **job)
  60. {
  61. int r;
  62. r = amdgpu_job_alloc(adev, 1, job, NULL);
  63. if (r)
  64. return r;
  65. r = amdgpu_ib_get(adev, NULL, size, &(*job)->ibs[0]);
  66. if (r)
  67. kfree(*job);
  68. else
  69. (*job)->vm_pd_addr = adev->gart.table_addr;
  70. return r;
  71. }
  72. void amdgpu_job_free_resources(struct amdgpu_job *job)
  73. {
  74. struct dma_fence *f;
  75. unsigned i;
  76. /* use sched fence if available */
  77. f = job->base.s_fence ? &job->base.s_fence->finished : job->fence;
  78. for (i = 0; i < job->num_ibs; ++i)
  79. amdgpu_ib_free(job->adev, &job->ibs[i], f);
  80. }
  81. static void amdgpu_job_free_cb(struct drm_sched_job *s_job)
  82. {
  83. struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched);
  84. struct amdgpu_job *job = to_amdgpu_job(s_job);
  85. amdgpu_ring_priority_put(ring, s_job->s_priority);
  86. dma_fence_put(job->fence);
  87. amdgpu_sync_free(&job->sync);
  88. amdgpu_sync_free(&job->sched_sync);
  89. kfree(job);
  90. }
  91. void amdgpu_job_free(struct amdgpu_job *job)
  92. {
  93. amdgpu_job_free_resources(job);
  94. dma_fence_put(job->fence);
  95. amdgpu_sync_free(&job->sync);
  96. amdgpu_sync_free(&job->sched_sync);
  97. kfree(job);
  98. }
  99. int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity,
  100. void *owner, struct dma_fence **f)
  101. {
  102. struct amdgpu_ring *ring = to_amdgpu_ring(entity->sched);
  103. int r;
  104. if (!f)
  105. return -EINVAL;
  106. r = drm_sched_job_init(&job->base, entity->sched, entity, owner);
  107. if (r)
  108. return r;
  109. job->owner = owner;
  110. *f = dma_fence_get(&job->base.s_fence->finished);
  111. amdgpu_job_free_resources(job);
  112. amdgpu_ring_priority_get(ring, job->base.s_priority);
  113. drm_sched_entity_push_job(&job->base, entity);
  114. return 0;
  115. }
  116. int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring,
  117. struct dma_fence **fence)
  118. {
  119. int r;
  120. job->base.sched = &ring->sched;
  121. r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, NULL, fence);
  122. job->fence = dma_fence_get(*fence);
  123. if (r)
  124. return r;
  125. amdgpu_job_free(job);
  126. return 0;
  127. }
  128. static struct dma_fence *amdgpu_job_dependency(struct drm_sched_job *sched_job,
  129. struct drm_sched_entity *s_entity)
  130. {
  131. struct amdgpu_ring *ring = to_amdgpu_ring(s_entity->sched);
  132. struct amdgpu_job *job = to_amdgpu_job(sched_job);
  133. struct amdgpu_vm *vm = job->vm;
  134. bool explicit = false;
  135. int r;
  136. struct dma_fence *fence = amdgpu_sync_get_fence(&job->sync, &explicit);
  137. if (fence && explicit) {
  138. if (drm_sched_dependency_optimized(fence, s_entity)) {
  139. r = amdgpu_sync_fence(job->adev, &job->sched_sync, fence, false);
  140. if (r)
  141. DRM_ERROR("Error adding fence to sync (%d)\n", r);
  142. }
  143. }
  144. while (fence == NULL && vm && !job->vmid) {
  145. r = amdgpu_vmid_grab(vm, ring, &job->sync,
  146. &job->base.s_fence->finished,
  147. job);
  148. if (r)
  149. DRM_ERROR("Error getting VM ID (%d)\n", r);
  150. fence = amdgpu_sync_get_fence(&job->sync, NULL);
  151. }
  152. return fence;
  153. }
  154. static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)
  155. {
  156. struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched);
  157. struct dma_fence *fence = NULL, *finished;
  158. struct amdgpu_device *adev;
  159. struct amdgpu_job *job;
  160. int r;
  161. if (!sched_job) {
  162. DRM_ERROR("job is null\n");
  163. return NULL;
  164. }
  165. job = to_amdgpu_job(sched_job);
  166. finished = &job->base.s_fence->finished;
  167. adev = job->adev;
  168. BUG_ON(amdgpu_sync_peek_fence(&job->sync, NULL));
  169. trace_amdgpu_sched_run_job(job);
  170. if (job->vram_lost_counter != atomic_read(&adev->vram_lost_counter))
  171. dma_fence_set_error(finished, -ECANCELED);/* skip IB as well if VRAM lost */
  172. if (finished->error < 0) {
  173. DRM_INFO("Skip scheduling IBs!\n");
  174. } else {
  175. r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job,
  176. &fence);
  177. if (r)
  178. DRM_ERROR("Error scheduling IBs (%d)\n", r);
  179. }
  180. /* if gpu reset, hw fence will be replaced here */
  181. dma_fence_put(job->fence);
  182. job->fence = dma_fence_get(fence);
  183. amdgpu_job_free_resources(job);
  184. return fence;
  185. }
  186. const struct drm_sched_backend_ops amdgpu_sched_ops = {
  187. .dependency = amdgpu_job_dependency,
  188. .run_job = amdgpu_job_run,
  189. .timedout_job = amdgpu_job_timedout,
  190. .free_job = amdgpu_job_free_cb
  191. };