qeth_core_main.c 162 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968396939703971397239733974397539763977397839793980398139823983398439853986398739883989399039913992399339943995399639973998399940004001400240034004400540064007400840094010401140124013401440154016401740184019402040214022402340244025402640274028402940304031403240334034403540364037403840394040404140424043404440454046404740484049405040514052405340544055405640574058405940604061406240634064406540664067406840694070407140724073407440754076407740784079408040814082408340844085408640874088408940904091409240934094409540964097409840994100410141024103410441054106410741084109411041114112411341144115411641174118411941204121412241234124412541264127412841294130413141324133413441354136413741384139414041414142414341444145414641474148414941504151415241534154415541564157415841594160416141624163416441654166416741684169417041714172417341744175417641774178417941804181418241834184418541864187418841894190419141924193419441954196419741984199420042014202420342044205420642074208420942104211421242134214421542164217421842194220422142224223422442254226422742284229423042314232423342344235423642374238423942404241424242434244424542464247424842494250425142524253425442554256425742584259426042614262426342644265426642674268426942704271427242734274427542764277427842794280428142824283428442854286428742884289429042914292429342944295429642974298429943004301430243034304430543064307430843094310431143124313431443154316431743184319432043214322432343244325432643274328432943304331433243334334433543364337433843394340434143424343434443454346434743484349435043514352435343544355435643574358435943604361436243634364436543664367436843694370437143724373437443754376437743784379438043814382438343844385438643874388438943904391439243934394439543964397439843994400440144024403440444054406440744084409441044114412441344144415441644174418441944204421442244234424442544264427442844294430443144324433443444354436443744384439444044414442444344444445444644474448444944504451445244534454445544564457445844594460446144624463446444654466446744684469447044714472447344744475447644774478447944804481448244834484448544864487448844894490449144924493449444954496449744984499450045014502450345044505450645074508450945104511451245134514451545164517451845194520452145224523452445254526452745284529453045314532453345344535453645374538453945404541454245434544454545464547454845494550455145524553455445554556455745584559456045614562456345644565456645674568456945704571457245734574457545764577457845794580458145824583458445854586458745884589459045914592459345944595459645974598459946004601460246034604460546064607460846094610461146124613461446154616461746184619462046214622462346244625462646274628462946304631463246334634463546364637463846394640464146424643464446454646464746484649465046514652465346544655465646574658465946604661466246634664466546664667466846694670467146724673467446754676467746784679468046814682468346844685468646874688468946904691469246934694469546964697469846994700470147024703470447054706470747084709471047114712471347144715471647174718471947204721472247234724472547264727472847294730473147324733473447354736473747384739474047414742474347444745474647474748474947504751475247534754475547564757475847594760476147624763476447654766476747684769477047714772477347744775477647774778477947804781478247834784478547864787478847894790479147924793479447954796479747984799480048014802480348044805480648074808480948104811481248134814481548164817481848194820482148224823482448254826482748284829483048314832483348344835483648374838483948404841484248434844484548464847484848494850485148524853485448554856485748584859486048614862486348644865486648674868486948704871487248734874487548764877487848794880488148824883488448854886488748884889489048914892489348944895489648974898489949004901490249034904490549064907490849094910491149124913491449154916491749184919492049214922492349244925492649274928492949304931493249334934493549364937493849394940494149424943494449454946494749484949495049514952495349544955495649574958495949604961496249634964496549664967496849694970497149724973497449754976497749784979498049814982498349844985498649874988498949904991499249934994499549964997499849995000500150025003500450055006500750085009501050115012501350145015501650175018501950205021502250235024502550265027502850295030503150325033503450355036503750385039504050415042504350445045504650475048504950505051505250535054505550565057505850595060506150625063506450655066506750685069507050715072507350745075507650775078507950805081508250835084508550865087508850895090509150925093509450955096509750985099510051015102510351045105510651075108510951105111511251135114511551165117511851195120512151225123512451255126512751285129513051315132513351345135513651375138513951405141514251435144514551465147514851495150515151525153515451555156515751585159516051615162516351645165516651675168516951705171517251735174517551765177517851795180518151825183518451855186518751885189519051915192519351945195519651975198519952005201520252035204520552065207520852095210521152125213521452155216521752185219522052215222522352245225522652275228522952305231523252335234523552365237523852395240524152425243524452455246524752485249525052515252525352545255525652575258525952605261526252635264526552665267526852695270527152725273527452755276527752785279528052815282528352845285528652875288528952905291529252935294529552965297529852995300530153025303530453055306530753085309531053115312531353145315531653175318531953205321532253235324532553265327532853295330533153325333533453355336533753385339534053415342534353445345534653475348534953505351535253535354535553565357535853595360536153625363536453655366536753685369537053715372537353745375537653775378537953805381538253835384538553865387538853895390539153925393539453955396539753985399540054015402540354045405540654075408540954105411541254135414541554165417541854195420542154225423542454255426542754285429543054315432543354345435543654375438543954405441544254435444544554465447544854495450545154525453545454555456545754585459546054615462546354645465546654675468546954705471547254735474547554765477547854795480548154825483548454855486548754885489549054915492549354945495549654975498549955005501550255035504550555065507550855095510551155125513551455155516551755185519552055215522552355245525552655275528552955305531553255335534553555365537553855395540554155425543554455455546554755485549555055515552555355545555555655575558555955605561556255635564556555665567556855695570557155725573557455755576557755785579558055815582558355845585558655875588558955905591559255935594559555965597559855995600560156025603560456055606560756085609561056115612561356145615561656175618561956205621562256235624562556265627562856295630563156325633563456355636563756385639564056415642564356445645564656475648564956505651565256535654565556565657565856595660566156625663566456655666566756685669567056715672567356745675567656775678567956805681568256835684568556865687568856895690569156925693569456955696569756985699570057015702570357045705570657075708570957105711571257135714571557165717571857195720572157225723572457255726572757285729573057315732573357345735573657375738573957405741574257435744574557465747574857495750575157525753575457555756575757585759576057615762576357645765576657675768576957705771577257735774577557765777577857795780578157825783578457855786578757885789579057915792579357945795579657975798579958005801580258035804580558065807580858095810581158125813581458155816581758185819582058215822582358245825582658275828582958305831583258335834583558365837583858395840584158425843584458455846584758485849585058515852585358545855585658575858585958605861586258635864586558665867586858695870587158725873587458755876587758785879588058815882588358845885588658875888588958905891589258935894589558965897589858995900590159025903590459055906590759085909591059115912591359145915591659175918591959205921592259235924592559265927592859295930593159325933593459355936593759385939594059415942594359445945594659475948594959505951595259535954595559565957595859595960596159625963596459655966
  1. /*
  2. * Copyright IBM Corp. 2007, 2009
  3. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  4. * Frank Pavlic <fpavlic@de.ibm.com>,
  5. * Thomas Spatzier <tspat@de.ibm.com>,
  6. * Frank Blaschka <frank.blaschka@de.ibm.com>
  7. */
  8. #define KMSG_COMPONENT "qeth"
  9. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  10. #include <linux/module.h>
  11. #include <linux/moduleparam.h>
  12. #include <linux/string.h>
  13. #include <linux/errno.h>
  14. #include <linux/kernel.h>
  15. #include <linux/ip.h>
  16. #include <linux/tcp.h>
  17. #include <linux/mii.h>
  18. #include <linux/kthread.h>
  19. #include <linux/slab.h>
  20. #include <net/iucv/af_iucv.h>
  21. #include <net/dsfield.h>
  22. #include <asm/ebcdic.h>
  23. #include <asm/chpid.h>
  24. #include <asm/io.h>
  25. #include <asm/sysinfo.h>
  26. #include <asm/compat.h>
  27. #include "qeth_core.h"
  28. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  29. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  30. /* N P A M L V H */
  31. [QETH_DBF_SETUP] = {"qeth_setup",
  32. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  33. [QETH_DBF_MSG] = {"qeth_msg", 8, 1, 11 * sizeof(long), 3,
  34. &debug_sprintf_view, NULL},
  35. [QETH_DBF_CTRL] = {"qeth_control",
  36. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  37. };
  38. EXPORT_SYMBOL_GPL(qeth_dbf);
  39. struct qeth_card_list_struct qeth_core_card_list;
  40. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  41. struct kmem_cache *qeth_core_header_cache;
  42. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  43. static struct kmem_cache *qeth_qdio_outbuf_cache;
  44. static struct device *qeth_core_root_dev;
  45. static unsigned int known_devices[][6] = QETH_MODELLIST_ARRAY;
  46. static struct lock_class_key qdio_out_skb_queue_key;
  47. static struct mutex qeth_mod_mutex;
  48. static void qeth_send_control_data_cb(struct qeth_channel *,
  49. struct qeth_cmd_buffer *);
  50. static int qeth_issue_next_read(struct qeth_card *);
  51. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  52. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  53. static void qeth_free_buffer_pool(struct qeth_card *);
  54. static int qeth_qdio_establish(struct qeth_card *);
  55. static void qeth_free_qdio_buffers(struct qeth_card *);
  56. static void qeth_notify_skbs(struct qeth_qdio_out_q *queue,
  57. struct qeth_qdio_out_buffer *buf,
  58. enum iucv_tx_notify notification);
  59. static void qeth_release_skbs(struct qeth_qdio_out_buffer *buf);
  60. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  61. struct qeth_qdio_out_buffer *buf,
  62. enum qeth_qdio_buffer_states newbufstate);
  63. static int qeth_init_qdio_out_buf(struct qeth_qdio_out_q *, int);
  64. struct workqueue_struct *qeth_wq;
  65. EXPORT_SYMBOL_GPL(qeth_wq);
  66. static void qeth_close_dev_handler(struct work_struct *work)
  67. {
  68. struct qeth_card *card;
  69. card = container_of(work, struct qeth_card, close_dev_work);
  70. QETH_CARD_TEXT(card, 2, "cldevhdl");
  71. rtnl_lock();
  72. dev_close(card->dev);
  73. rtnl_unlock();
  74. ccwgroup_set_offline(card->gdev);
  75. }
  76. void qeth_close_dev(struct qeth_card *card)
  77. {
  78. QETH_CARD_TEXT(card, 2, "cldevsubm");
  79. queue_work(qeth_wq, &card->close_dev_work);
  80. }
  81. EXPORT_SYMBOL_GPL(qeth_close_dev);
  82. static inline const char *qeth_get_cardname(struct qeth_card *card)
  83. {
  84. if (card->info.guestlan) {
  85. switch (card->info.type) {
  86. case QETH_CARD_TYPE_OSD:
  87. return " Virtual NIC QDIO";
  88. case QETH_CARD_TYPE_IQD:
  89. return " Virtual NIC Hiper";
  90. case QETH_CARD_TYPE_OSM:
  91. return " Virtual NIC QDIO - OSM";
  92. case QETH_CARD_TYPE_OSX:
  93. return " Virtual NIC QDIO - OSX";
  94. default:
  95. return " unknown";
  96. }
  97. } else {
  98. switch (card->info.type) {
  99. case QETH_CARD_TYPE_OSD:
  100. return " OSD Express";
  101. case QETH_CARD_TYPE_IQD:
  102. return " HiperSockets";
  103. case QETH_CARD_TYPE_OSN:
  104. return " OSN QDIO";
  105. case QETH_CARD_TYPE_OSM:
  106. return " OSM QDIO";
  107. case QETH_CARD_TYPE_OSX:
  108. return " OSX QDIO";
  109. default:
  110. return " unknown";
  111. }
  112. }
  113. return " n/a";
  114. }
  115. /* max length to be returned: 14 */
  116. const char *qeth_get_cardname_short(struct qeth_card *card)
  117. {
  118. if (card->info.guestlan) {
  119. switch (card->info.type) {
  120. case QETH_CARD_TYPE_OSD:
  121. return "Virt.NIC QDIO";
  122. case QETH_CARD_TYPE_IQD:
  123. return "Virt.NIC Hiper";
  124. case QETH_CARD_TYPE_OSM:
  125. return "Virt.NIC OSM";
  126. case QETH_CARD_TYPE_OSX:
  127. return "Virt.NIC OSX";
  128. default:
  129. return "unknown";
  130. }
  131. } else {
  132. switch (card->info.type) {
  133. case QETH_CARD_TYPE_OSD:
  134. switch (card->info.link_type) {
  135. case QETH_LINK_TYPE_FAST_ETH:
  136. return "OSD_100";
  137. case QETH_LINK_TYPE_HSTR:
  138. return "HSTR";
  139. case QETH_LINK_TYPE_GBIT_ETH:
  140. return "OSD_1000";
  141. case QETH_LINK_TYPE_10GBIT_ETH:
  142. return "OSD_10GIG";
  143. case QETH_LINK_TYPE_LANE_ETH100:
  144. return "OSD_FE_LANE";
  145. case QETH_LINK_TYPE_LANE_TR:
  146. return "OSD_TR_LANE";
  147. case QETH_LINK_TYPE_LANE_ETH1000:
  148. return "OSD_GbE_LANE";
  149. case QETH_LINK_TYPE_LANE:
  150. return "OSD_ATM_LANE";
  151. default:
  152. return "OSD_Express";
  153. }
  154. case QETH_CARD_TYPE_IQD:
  155. return "HiperSockets";
  156. case QETH_CARD_TYPE_OSN:
  157. return "OSN";
  158. case QETH_CARD_TYPE_OSM:
  159. return "OSM_1000";
  160. case QETH_CARD_TYPE_OSX:
  161. return "OSX_10GIG";
  162. default:
  163. return "unknown";
  164. }
  165. }
  166. return "n/a";
  167. }
  168. void qeth_set_recovery_task(struct qeth_card *card)
  169. {
  170. card->recovery_task = current;
  171. }
  172. EXPORT_SYMBOL_GPL(qeth_set_recovery_task);
  173. void qeth_clear_recovery_task(struct qeth_card *card)
  174. {
  175. card->recovery_task = NULL;
  176. }
  177. EXPORT_SYMBOL_GPL(qeth_clear_recovery_task);
  178. static bool qeth_is_recovery_task(const struct qeth_card *card)
  179. {
  180. return card->recovery_task == current;
  181. }
  182. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  183. int clear_start_mask)
  184. {
  185. unsigned long flags;
  186. spin_lock_irqsave(&card->thread_mask_lock, flags);
  187. card->thread_allowed_mask = threads;
  188. if (clear_start_mask)
  189. card->thread_start_mask &= threads;
  190. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  191. wake_up(&card->wait_q);
  192. }
  193. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  194. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  195. {
  196. unsigned long flags;
  197. int rc = 0;
  198. spin_lock_irqsave(&card->thread_mask_lock, flags);
  199. rc = (card->thread_running_mask & threads);
  200. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  201. return rc;
  202. }
  203. EXPORT_SYMBOL_GPL(qeth_threads_running);
  204. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  205. {
  206. if (qeth_is_recovery_task(card))
  207. return 0;
  208. return wait_event_interruptible(card->wait_q,
  209. qeth_threads_running(card, threads) == 0);
  210. }
  211. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  212. void qeth_clear_working_pool_list(struct qeth_card *card)
  213. {
  214. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  215. QETH_CARD_TEXT(card, 5, "clwrklst");
  216. list_for_each_entry_safe(pool_entry, tmp,
  217. &card->qdio.in_buf_pool.entry_list, list){
  218. list_del(&pool_entry->list);
  219. }
  220. }
  221. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  222. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  223. {
  224. struct qeth_buffer_pool_entry *pool_entry;
  225. void *ptr;
  226. int i, j;
  227. QETH_CARD_TEXT(card, 5, "alocpool");
  228. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  229. pool_entry = kzalloc(sizeof(*pool_entry), GFP_KERNEL);
  230. if (!pool_entry) {
  231. qeth_free_buffer_pool(card);
  232. return -ENOMEM;
  233. }
  234. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  235. ptr = (void *) __get_free_page(GFP_KERNEL);
  236. if (!ptr) {
  237. while (j > 0)
  238. free_page((unsigned long)
  239. pool_entry->elements[--j]);
  240. kfree(pool_entry);
  241. qeth_free_buffer_pool(card);
  242. return -ENOMEM;
  243. }
  244. pool_entry->elements[j] = ptr;
  245. }
  246. list_add(&pool_entry->init_list,
  247. &card->qdio.init_pool.entry_list);
  248. }
  249. return 0;
  250. }
  251. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  252. {
  253. QETH_CARD_TEXT(card, 2, "realcbp");
  254. if ((card->state != CARD_STATE_DOWN) &&
  255. (card->state != CARD_STATE_RECOVER))
  256. return -EPERM;
  257. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  258. qeth_clear_working_pool_list(card);
  259. qeth_free_buffer_pool(card);
  260. card->qdio.in_buf_pool.buf_count = bufcnt;
  261. card->qdio.init_pool.buf_count = bufcnt;
  262. return qeth_alloc_buffer_pool(card);
  263. }
  264. EXPORT_SYMBOL_GPL(qeth_realloc_buffer_pool);
  265. static void qeth_free_qdio_queue(struct qeth_qdio_q *q)
  266. {
  267. if (!q)
  268. return;
  269. qdio_free_buffers(q->qdio_bufs, QDIO_MAX_BUFFERS_PER_Q);
  270. kfree(q);
  271. }
  272. static struct qeth_qdio_q *qeth_alloc_qdio_queue(void)
  273. {
  274. struct qeth_qdio_q *q = kzalloc(sizeof(*q), GFP_KERNEL);
  275. int i;
  276. if (!q)
  277. return NULL;
  278. if (qdio_alloc_buffers(q->qdio_bufs, QDIO_MAX_BUFFERS_PER_Q)) {
  279. kfree(q);
  280. return NULL;
  281. }
  282. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  283. q->bufs[i].buffer = q->qdio_bufs[i];
  284. QETH_DBF_HEX(SETUP, 2, &q, sizeof(void *));
  285. return q;
  286. }
  287. static inline int qeth_cq_init(struct qeth_card *card)
  288. {
  289. int rc;
  290. if (card->options.cq == QETH_CQ_ENABLED) {
  291. QETH_DBF_TEXT(SETUP, 2, "cqinit");
  292. qdio_reset_buffers(card->qdio.c_q->qdio_bufs,
  293. QDIO_MAX_BUFFERS_PER_Q);
  294. card->qdio.c_q->next_buf_to_init = 127;
  295. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT,
  296. card->qdio.no_in_queues - 1, 0,
  297. 127);
  298. if (rc) {
  299. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  300. goto out;
  301. }
  302. }
  303. rc = 0;
  304. out:
  305. return rc;
  306. }
  307. static inline int qeth_alloc_cq(struct qeth_card *card)
  308. {
  309. int rc;
  310. if (card->options.cq == QETH_CQ_ENABLED) {
  311. int i;
  312. struct qdio_outbuf_state *outbuf_states;
  313. QETH_DBF_TEXT(SETUP, 2, "cqon");
  314. card->qdio.c_q = qeth_alloc_qdio_queue();
  315. if (!card->qdio.c_q) {
  316. rc = -1;
  317. goto kmsg_out;
  318. }
  319. card->qdio.no_in_queues = 2;
  320. card->qdio.out_bufstates =
  321. kzalloc(card->qdio.no_out_queues *
  322. QDIO_MAX_BUFFERS_PER_Q *
  323. sizeof(struct qdio_outbuf_state), GFP_KERNEL);
  324. outbuf_states = card->qdio.out_bufstates;
  325. if (outbuf_states == NULL) {
  326. rc = -1;
  327. goto free_cq_out;
  328. }
  329. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  330. card->qdio.out_qs[i]->bufstates = outbuf_states;
  331. outbuf_states += QDIO_MAX_BUFFERS_PER_Q;
  332. }
  333. } else {
  334. QETH_DBF_TEXT(SETUP, 2, "nocq");
  335. card->qdio.c_q = NULL;
  336. card->qdio.no_in_queues = 1;
  337. }
  338. QETH_DBF_TEXT_(SETUP, 2, "iqc%d", card->qdio.no_in_queues);
  339. rc = 0;
  340. out:
  341. return rc;
  342. free_cq_out:
  343. qeth_free_qdio_queue(card->qdio.c_q);
  344. card->qdio.c_q = NULL;
  345. kmsg_out:
  346. dev_err(&card->gdev->dev, "Failed to create completion queue\n");
  347. goto out;
  348. }
  349. static inline void qeth_free_cq(struct qeth_card *card)
  350. {
  351. if (card->qdio.c_q) {
  352. --card->qdio.no_in_queues;
  353. qeth_free_qdio_queue(card->qdio.c_q);
  354. card->qdio.c_q = NULL;
  355. }
  356. kfree(card->qdio.out_bufstates);
  357. card->qdio.out_bufstates = NULL;
  358. }
  359. static inline enum iucv_tx_notify qeth_compute_cq_notification(int sbalf15,
  360. int delayed) {
  361. enum iucv_tx_notify n;
  362. switch (sbalf15) {
  363. case 0:
  364. n = delayed ? TX_NOTIFY_DELAYED_OK : TX_NOTIFY_OK;
  365. break;
  366. case 4:
  367. case 16:
  368. case 17:
  369. case 18:
  370. n = delayed ? TX_NOTIFY_DELAYED_UNREACHABLE :
  371. TX_NOTIFY_UNREACHABLE;
  372. break;
  373. default:
  374. n = delayed ? TX_NOTIFY_DELAYED_GENERALERROR :
  375. TX_NOTIFY_GENERALERROR;
  376. break;
  377. }
  378. return n;
  379. }
  380. static inline void qeth_cleanup_handled_pending(struct qeth_qdio_out_q *q,
  381. int bidx, int forced_cleanup)
  382. {
  383. if (q->card->options.cq != QETH_CQ_ENABLED)
  384. return;
  385. if (q->bufs[bidx]->next_pending != NULL) {
  386. struct qeth_qdio_out_buffer *head = q->bufs[bidx];
  387. struct qeth_qdio_out_buffer *c = q->bufs[bidx]->next_pending;
  388. while (c) {
  389. if (forced_cleanup ||
  390. atomic_read(&c->state) ==
  391. QETH_QDIO_BUF_HANDLED_DELAYED) {
  392. struct qeth_qdio_out_buffer *f = c;
  393. QETH_CARD_TEXT(f->q->card, 5, "fp");
  394. QETH_CARD_TEXT_(f->q->card, 5, "%lx", (long) f);
  395. /* release here to avoid interleaving between
  396. outbound tasklet and inbound tasklet
  397. regarding notifications and lifecycle */
  398. qeth_release_skbs(c);
  399. c = f->next_pending;
  400. WARN_ON_ONCE(head->next_pending != f);
  401. head->next_pending = c;
  402. kmem_cache_free(qeth_qdio_outbuf_cache, f);
  403. } else {
  404. head = c;
  405. c = c->next_pending;
  406. }
  407. }
  408. }
  409. if (forced_cleanup && (atomic_read(&(q->bufs[bidx]->state)) ==
  410. QETH_QDIO_BUF_HANDLED_DELAYED)) {
  411. /* for recovery situations */
  412. q->bufs[bidx]->aob = q->bufstates[bidx].aob;
  413. qeth_init_qdio_out_buf(q, bidx);
  414. QETH_CARD_TEXT(q->card, 2, "clprecov");
  415. }
  416. }
  417. static inline void qeth_qdio_handle_aob(struct qeth_card *card,
  418. unsigned long phys_aob_addr) {
  419. struct qaob *aob;
  420. struct qeth_qdio_out_buffer *buffer;
  421. enum iucv_tx_notify notification;
  422. aob = (struct qaob *) phys_to_virt(phys_aob_addr);
  423. QETH_CARD_TEXT(card, 5, "haob");
  424. QETH_CARD_TEXT_(card, 5, "%lx", phys_aob_addr);
  425. buffer = (struct qeth_qdio_out_buffer *) aob->user1;
  426. QETH_CARD_TEXT_(card, 5, "%lx", aob->user1);
  427. if (atomic_cmpxchg(&buffer->state, QETH_QDIO_BUF_PRIMED,
  428. QETH_QDIO_BUF_IN_CQ) == QETH_QDIO_BUF_PRIMED) {
  429. notification = TX_NOTIFY_OK;
  430. } else {
  431. WARN_ON_ONCE(atomic_read(&buffer->state) !=
  432. QETH_QDIO_BUF_PENDING);
  433. atomic_set(&buffer->state, QETH_QDIO_BUF_IN_CQ);
  434. notification = TX_NOTIFY_DELAYED_OK;
  435. }
  436. if (aob->aorc != 0) {
  437. QETH_CARD_TEXT_(card, 2, "aorc%02X", aob->aorc);
  438. notification = qeth_compute_cq_notification(aob->aorc, 1);
  439. }
  440. qeth_notify_skbs(buffer->q, buffer, notification);
  441. buffer->aob = NULL;
  442. qeth_clear_output_buffer(buffer->q, buffer,
  443. QETH_QDIO_BUF_HANDLED_DELAYED);
  444. /* from here on: do not touch buffer anymore */
  445. qdio_release_aob(aob);
  446. }
  447. static inline int qeth_is_cq(struct qeth_card *card, unsigned int queue)
  448. {
  449. return card->options.cq == QETH_CQ_ENABLED &&
  450. card->qdio.c_q != NULL &&
  451. queue != 0 &&
  452. queue == card->qdio.no_in_queues - 1;
  453. }
  454. static int qeth_issue_next_read(struct qeth_card *card)
  455. {
  456. int rc;
  457. struct qeth_cmd_buffer *iob;
  458. QETH_CARD_TEXT(card, 5, "issnxrd");
  459. if (card->read.state != CH_STATE_UP)
  460. return -EIO;
  461. iob = qeth_get_buffer(&card->read);
  462. if (!iob) {
  463. dev_warn(&card->gdev->dev, "The qeth device driver "
  464. "failed to recover an error on the device\n");
  465. QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
  466. "available\n", dev_name(&card->gdev->dev));
  467. return -ENOMEM;
  468. }
  469. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  470. QETH_CARD_TEXT(card, 6, "noirqpnd");
  471. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  472. (addr_t) iob, 0, 0);
  473. if (rc) {
  474. QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
  475. "rc=%i\n", dev_name(&card->gdev->dev), rc);
  476. atomic_set(&card->read.irq_pending, 0);
  477. card->read_or_write_problem = 1;
  478. qeth_schedule_recovery(card);
  479. wake_up(&card->wait_q);
  480. }
  481. return rc;
  482. }
  483. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  484. {
  485. struct qeth_reply *reply;
  486. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  487. if (reply) {
  488. atomic_set(&reply->refcnt, 1);
  489. atomic_set(&reply->received, 0);
  490. reply->card = card;
  491. }
  492. return reply;
  493. }
  494. static void qeth_get_reply(struct qeth_reply *reply)
  495. {
  496. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  497. atomic_inc(&reply->refcnt);
  498. }
  499. static void qeth_put_reply(struct qeth_reply *reply)
  500. {
  501. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  502. if (atomic_dec_and_test(&reply->refcnt))
  503. kfree(reply);
  504. }
  505. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  506. struct qeth_card *card)
  507. {
  508. char *ipa_name;
  509. int com = cmd->hdr.command;
  510. ipa_name = qeth_get_ipa_cmd_name(com);
  511. if (rc)
  512. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s/%s returned "
  513. "x%X \"%s\"\n",
  514. ipa_name, com, dev_name(&card->gdev->dev),
  515. QETH_CARD_IFNAME(card), rc,
  516. qeth_get_ipa_msg(rc));
  517. else
  518. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s/%s succeeded\n",
  519. ipa_name, com, dev_name(&card->gdev->dev),
  520. QETH_CARD_IFNAME(card));
  521. }
  522. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  523. struct qeth_cmd_buffer *iob)
  524. {
  525. struct qeth_ipa_cmd *cmd = NULL;
  526. QETH_CARD_TEXT(card, 5, "chkipad");
  527. if (IS_IPA(iob->data)) {
  528. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  529. if (IS_IPA_REPLY(cmd)) {
  530. if (cmd->hdr.command != IPA_CMD_SETCCID &&
  531. cmd->hdr.command != IPA_CMD_DELCCID &&
  532. cmd->hdr.command != IPA_CMD_MODCCID &&
  533. cmd->hdr.command != IPA_CMD_SET_DIAG_ASS)
  534. qeth_issue_ipa_msg(cmd,
  535. cmd->hdr.return_code, card);
  536. return cmd;
  537. } else {
  538. switch (cmd->hdr.command) {
  539. case IPA_CMD_STOPLAN:
  540. if (cmd->hdr.return_code ==
  541. IPA_RC_VEPA_TO_VEB_TRANSITION) {
  542. dev_err(&card->gdev->dev,
  543. "Interface %s is down because the "
  544. "adjacent port is no longer in "
  545. "reflective relay mode\n",
  546. QETH_CARD_IFNAME(card));
  547. qeth_close_dev(card);
  548. } else {
  549. dev_warn(&card->gdev->dev,
  550. "The link for interface %s on CHPID"
  551. " 0x%X failed\n",
  552. QETH_CARD_IFNAME(card),
  553. card->info.chpid);
  554. qeth_issue_ipa_msg(cmd,
  555. cmd->hdr.return_code, card);
  556. }
  557. card->lan_online = 0;
  558. if (card->dev && netif_carrier_ok(card->dev))
  559. netif_carrier_off(card->dev);
  560. return NULL;
  561. case IPA_CMD_STARTLAN:
  562. dev_info(&card->gdev->dev,
  563. "The link for %s on CHPID 0x%X has"
  564. " been restored\n",
  565. QETH_CARD_IFNAME(card),
  566. card->info.chpid);
  567. netif_carrier_on(card->dev);
  568. card->lan_online = 1;
  569. if (card->info.hwtrap)
  570. card->info.hwtrap = 2;
  571. qeth_schedule_recovery(card);
  572. return NULL;
  573. case IPA_CMD_SETBRIDGEPORT:
  574. case IPA_CMD_ADDRESS_CHANGE_NOTIF:
  575. if (card->discipline->control_event_handler
  576. (card, cmd))
  577. return cmd;
  578. else
  579. return NULL;
  580. case IPA_CMD_MODCCID:
  581. return cmd;
  582. case IPA_CMD_REGISTER_LOCAL_ADDR:
  583. QETH_CARD_TEXT(card, 3, "irla");
  584. break;
  585. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  586. QETH_CARD_TEXT(card, 3, "urla");
  587. break;
  588. default:
  589. QETH_DBF_MESSAGE(2, "Received data is IPA "
  590. "but not a reply!\n");
  591. break;
  592. }
  593. }
  594. }
  595. return cmd;
  596. }
  597. void qeth_clear_ipacmd_list(struct qeth_card *card)
  598. {
  599. struct qeth_reply *reply, *r;
  600. unsigned long flags;
  601. QETH_CARD_TEXT(card, 4, "clipalst");
  602. spin_lock_irqsave(&card->lock, flags);
  603. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  604. qeth_get_reply(reply);
  605. reply->rc = -EIO;
  606. atomic_inc(&reply->received);
  607. list_del_init(&reply->list);
  608. wake_up(&reply->wait_q);
  609. qeth_put_reply(reply);
  610. }
  611. spin_unlock_irqrestore(&card->lock, flags);
  612. atomic_set(&card->write.irq_pending, 0);
  613. }
  614. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  615. static int qeth_check_idx_response(struct qeth_card *card,
  616. unsigned char *buffer)
  617. {
  618. if (!buffer)
  619. return 0;
  620. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  621. if ((buffer[2] & 0xc0) == 0xc0) {
  622. QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
  623. "with cause code 0x%02x%s\n",
  624. buffer[4],
  625. ((buffer[4] == 0x22) ?
  626. " -- try another portname" : ""));
  627. QETH_CARD_TEXT(card, 2, "ckidxres");
  628. QETH_CARD_TEXT(card, 2, " idxterm");
  629. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  630. if (buffer[4] == 0xf6) {
  631. dev_err(&card->gdev->dev,
  632. "The qeth device is not configured "
  633. "for the OSI layer required by z/VM\n");
  634. return -EPERM;
  635. }
  636. return -EIO;
  637. }
  638. return 0;
  639. }
  640. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  641. __u32 len)
  642. {
  643. struct qeth_card *card;
  644. card = CARD_FROM_CDEV(channel->ccwdev);
  645. QETH_CARD_TEXT(card, 4, "setupccw");
  646. if (channel == &card->read)
  647. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  648. else
  649. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  650. channel->ccw.count = len;
  651. channel->ccw.cda = (__u32) __pa(iob);
  652. }
  653. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  654. {
  655. __u8 index;
  656. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "getbuff");
  657. index = channel->io_buf_no;
  658. do {
  659. if (channel->iob[index].state == BUF_STATE_FREE) {
  660. channel->iob[index].state = BUF_STATE_LOCKED;
  661. channel->io_buf_no = (channel->io_buf_no + 1) %
  662. QETH_CMD_BUFFER_NO;
  663. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  664. return channel->iob + index;
  665. }
  666. index = (index + 1) % QETH_CMD_BUFFER_NO;
  667. } while (index != channel->io_buf_no);
  668. return NULL;
  669. }
  670. void qeth_release_buffer(struct qeth_channel *channel,
  671. struct qeth_cmd_buffer *iob)
  672. {
  673. unsigned long flags;
  674. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "relbuff");
  675. spin_lock_irqsave(&channel->iob_lock, flags);
  676. memset(iob->data, 0, QETH_BUFSIZE);
  677. iob->state = BUF_STATE_FREE;
  678. iob->callback = qeth_send_control_data_cb;
  679. iob->rc = 0;
  680. spin_unlock_irqrestore(&channel->iob_lock, flags);
  681. wake_up(&channel->wait_q);
  682. }
  683. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  684. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  685. {
  686. struct qeth_cmd_buffer *buffer = NULL;
  687. unsigned long flags;
  688. spin_lock_irqsave(&channel->iob_lock, flags);
  689. buffer = __qeth_get_buffer(channel);
  690. spin_unlock_irqrestore(&channel->iob_lock, flags);
  691. return buffer;
  692. }
  693. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  694. {
  695. struct qeth_cmd_buffer *buffer;
  696. wait_event(channel->wait_q,
  697. ((buffer = qeth_get_buffer(channel)) != NULL));
  698. return buffer;
  699. }
  700. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  701. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  702. {
  703. int cnt;
  704. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  705. qeth_release_buffer(channel, &channel->iob[cnt]);
  706. channel->buf_no = 0;
  707. channel->io_buf_no = 0;
  708. }
  709. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  710. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  711. struct qeth_cmd_buffer *iob)
  712. {
  713. struct qeth_card *card;
  714. struct qeth_reply *reply, *r;
  715. struct qeth_ipa_cmd *cmd;
  716. unsigned long flags;
  717. int keep_reply;
  718. int rc = 0;
  719. card = CARD_FROM_CDEV(channel->ccwdev);
  720. QETH_CARD_TEXT(card, 4, "sndctlcb");
  721. rc = qeth_check_idx_response(card, iob->data);
  722. switch (rc) {
  723. case 0:
  724. break;
  725. case -EIO:
  726. qeth_clear_ipacmd_list(card);
  727. qeth_schedule_recovery(card);
  728. /* fall through */
  729. default:
  730. goto out;
  731. }
  732. cmd = qeth_check_ipa_data(card, iob);
  733. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  734. goto out;
  735. /*in case of OSN : check if cmd is set */
  736. if (card->info.type == QETH_CARD_TYPE_OSN &&
  737. cmd &&
  738. cmd->hdr.command != IPA_CMD_STARTLAN &&
  739. card->osn_info.assist_cb != NULL) {
  740. card->osn_info.assist_cb(card->dev, cmd);
  741. goto out;
  742. }
  743. spin_lock_irqsave(&card->lock, flags);
  744. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  745. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  746. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  747. qeth_get_reply(reply);
  748. list_del_init(&reply->list);
  749. spin_unlock_irqrestore(&card->lock, flags);
  750. keep_reply = 0;
  751. if (reply->callback != NULL) {
  752. if (cmd) {
  753. reply->offset = (__u16)((char *)cmd -
  754. (char *)iob->data);
  755. keep_reply = reply->callback(card,
  756. reply,
  757. (unsigned long)cmd);
  758. } else
  759. keep_reply = reply->callback(card,
  760. reply,
  761. (unsigned long)iob);
  762. }
  763. if (cmd)
  764. reply->rc = (u16) cmd->hdr.return_code;
  765. else if (iob->rc)
  766. reply->rc = iob->rc;
  767. if (keep_reply) {
  768. spin_lock_irqsave(&card->lock, flags);
  769. list_add_tail(&reply->list,
  770. &card->cmd_waiter_list);
  771. spin_unlock_irqrestore(&card->lock, flags);
  772. } else {
  773. atomic_inc(&reply->received);
  774. wake_up(&reply->wait_q);
  775. }
  776. qeth_put_reply(reply);
  777. goto out;
  778. }
  779. }
  780. spin_unlock_irqrestore(&card->lock, flags);
  781. out:
  782. memcpy(&card->seqno.pdu_hdr_ack,
  783. QETH_PDU_HEADER_SEQ_NO(iob->data),
  784. QETH_SEQ_NO_LENGTH);
  785. qeth_release_buffer(channel, iob);
  786. }
  787. static int qeth_setup_channel(struct qeth_channel *channel)
  788. {
  789. int cnt;
  790. QETH_DBF_TEXT(SETUP, 2, "setupch");
  791. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  792. channel->iob[cnt].data =
  793. kzalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  794. if (channel->iob[cnt].data == NULL)
  795. break;
  796. channel->iob[cnt].state = BUF_STATE_FREE;
  797. channel->iob[cnt].channel = channel;
  798. channel->iob[cnt].callback = qeth_send_control_data_cb;
  799. channel->iob[cnt].rc = 0;
  800. }
  801. if (cnt < QETH_CMD_BUFFER_NO) {
  802. while (cnt-- > 0)
  803. kfree(channel->iob[cnt].data);
  804. return -ENOMEM;
  805. }
  806. channel->buf_no = 0;
  807. channel->io_buf_no = 0;
  808. atomic_set(&channel->irq_pending, 0);
  809. spin_lock_init(&channel->iob_lock);
  810. init_waitqueue_head(&channel->wait_q);
  811. return 0;
  812. }
  813. static int qeth_set_thread_start_bit(struct qeth_card *card,
  814. unsigned long thread)
  815. {
  816. unsigned long flags;
  817. spin_lock_irqsave(&card->thread_mask_lock, flags);
  818. if (!(card->thread_allowed_mask & thread) ||
  819. (card->thread_start_mask & thread)) {
  820. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  821. return -EPERM;
  822. }
  823. card->thread_start_mask |= thread;
  824. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  825. return 0;
  826. }
  827. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  828. {
  829. unsigned long flags;
  830. spin_lock_irqsave(&card->thread_mask_lock, flags);
  831. card->thread_start_mask &= ~thread;
  832. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  833. wake_up(&card->wait_q);
  834. }
  835. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  836. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  837. {
  838. unsigned long flags;
  839. spin_lock_irqsave(&card->thread_mask_lock, flags);
  840. card->thread_running_mask &= ~thread;
  841. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  842. wake_up(&card->wait_q);
  843. }
  844. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  845. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  846. {
  847. unsigned long flags;
  848. int rc = 0;
  849. spin_lock_irqsave(&card->thread_mask_lock, flags);
  850. if (card->thread_start_mask & thread) {
  851. if ((card->thread_allowed_mask & thread) &&
  852. !(card->thread_running_mask & thread)) {
  853. rc = 1;
  854. card->thread_start_mask &= ~thread;
  855. card->thread_running_mask |= thread;
  856. } else
  857. rc = -EPERM;
  858. }
  859. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  860. return rc;
  861. }
  862. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  863. {
  864. int rc = 0;
  865. wait_event(card->wait_q,
  866. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  867. return rc;
  868. }
  869. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  870. void qeth_schedule_recovery(struct qeth_card *card)
  871. {
  872. QETH_CARD_TEXT(card, 2, "startrec");
  873. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  874. schedule_work(&card->kernel_thread_starter);
  875. }
  876. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  877. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  878. {
  879. int dstat, cstat;
  880. char *sense;
  881. struct qeth_card *card;
  882. sense = (char *) irb->ecw;
  883. cstat = irb->scsw.cmd.cstat;
  884. dstat = irb->scsw.cmd.dstat;
  885. card = CARD_FROM_CDEV(cdev);
  886. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  887. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  888. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  889. QETH_CARD_TEXT(card, 2, "CGENCHK");
  890. dev_warn(&cdev->dev, "The qeth device driver "
  891. "failed to recover an error on the device\n");
  892. QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x\n",
  893. dev_name(&cdev->dev), dstat, cstat);
  894. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  895. 16, 1, irb, 64, 1);
  896. return 1;
  897. }
  898. if (dstat & DEV_STAT_UNIT_CHECK) {
  899. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  900. SENSE_RESETTING_EVENT_FLAG) {
  901. QETH_CARD_TEXT(card, 2, "REVIND");
  902. return 1;
  903. }
  904. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  905. SENSE_COMMAND_REJECT_FLAG) {
  906. QETH_CARD_TEXT(card, 2, "CMDREJi");
  907. return 1;
  908. }
  909. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  910. QETH_CARD_TEXT(card, 2, "AFFE");
  911. return 1;
  912. }
  913. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  914. QETH_CARD_TEXT(card, 2, "ZEROSEN");
  915. return 0;
  916. }
  917. QETH_CARD_TEXT(card, 2, "DGENCHK");
  918. return 1;
  919. }
  920. return 0;
  921. }
  922. static long __qeth_check_irb_error(struct ccw_device *cdev,
  923. unsigned long intparm, struct irb *irb)
  924. {
  925. struct qeth_card *card;
  926. card = CARD_FROM_CDEV(cdev);
  927. if (!card || !IS_ERR(irb))
  928. return 0;
  929. switch (PTR_ERR(irb)) {
  930. case -EIO:
  931. QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
  932. dev_name(&cdev->dev));
  933. QETH_CARD_TEXT(card, 2, "ckirberr");
  934. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  935. break;
  936. case -ETIMEDOUT:
  937. dev_warn(&cdev->dev, "A hardware operation timed out"
  938. " on the device\n");
  939. QETH_CARD_TEXT(card, 2, "ckirberr");
  940. QETH_CARD_TEXT_(card, 2, " rc%d", -ETIMEDOUT);
  941. if (intparm == QETH_RCD_PARM) {
  942. if (card->data.ccwdev == cdev) {
  943. card->data.state = CH_STATE_DOWN;
  944. wake_up(&card->wait_q);
  945. }
  946. }
  947. break;
  948. default:
  949. QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
  950. dev_name(&cdev->dev), PTR_ERR(irb));
  951. QETH_CARD_TEXT(card, 2, "ckirberr");
  952. QETH_CARD_TEXT(card, 2, " rc???");
  953. }
  954. return PTR_ERR(irb);
  955. }
  956. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  957. struct irb *irb)
  958. {
  959. int rc;
  960. int cstat, dstat;
  961. struct qeth_cmd_buffer *buffer;
  962. struct qeth_channel *channel;
  963. struct qeth_card *card;
  964. struct qeth_cmd_buffer *iob;
  965. __u8 index;
  966. if (__qeth_check_irb_error(cdev, intparm, irb))
  967. return;
  968. cstat = irb->scsw.cmd.cstat;
  969. dstat = irb->scsw.cmd.dstat;
  970. card = CARD_FROM_CDEV(cdev);
  971. if (!card)
  972. return;
  973. QETH_CARD_TEXT(card, 5, "irq");
  974. if (card->read.ccwdev == cdev) {
  975. channel = &card->read;
  976. QETH_CARD_TEXT(card, 5, "read");
  977. } else if (card->write.ccwdev == cdev) {
  978. channel = &card->write;
  979. QETH_CARD_TEXT(card, 5, "write");
  980. } else {
  981. channel = &card->data;
  982. QETH_CARD_TEXT(card, 5, "data");
  983. }
  984. atomic_set(&channel->irq_pending, 0);
  985. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  986. channel->state = CH_STATE_STOPPED;
  987. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  988. channel->state = CH_STATE_HALTED;
  989. /*let's wake up immediately on data channel*/
  990. if ((channel == &card->data) && (intparm != 0) &&
  991. (intparm != QETH_RCD_PARM))
  992. goto out;
  993. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  994. QETH_CARD_TEXT(card, 6, "clrchpar");
  995. /* we don't have to handle this further */
  996. intparm = 0;
  997. }
  998. if (intparm == QETH_HALT_CHANNEL_PARM) {
  999. QETH_CARD_TEXT(card, 6, "hltchpar");
  1000. /* we don't have to handle this further */
  1001. intparm = 0;
  1002. }
  1003. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  1004. (dstat & DEV_STAT_UNIT_CHECK) ||
  1005. (cstat)) {
  1006. if (irb->esw.esw0.erw.cons) {
  1007. dev_warn(&channel->ccwdev->dev,
  1008. "The qeth device driver failed to recover "
  1009. "an error on the device\n");
  1010. QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
  1011. "0x%X dstat 0x%X\n",
  1012. dev_name(&channel->ccwdev->dev), cstat, dstat);
  1013. print_hex_dump(KERN_WARNING, "qeth: irb ",
  1014. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  1015. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  1016. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  1017. }
  1018. if (intparm == QETH_RCD_PARM) {
  1019. channel->state = CH_STATE_DOWN;
  1020. goto out;
  1021. }
  1022. rc = qeth_get_problem(cdev, irb);
  1023. if (rc) {
  1024. qeth_clear_ipacmd_list(card);
  1025. qeth_schedule_recovery(card);
  1026. goto out;
  1027. }
  1028. }
  1029. if (intparm == QETH_RCD_PARM) {
  1030. channel->state = CH_STATE_RCD_DONE;
  1031. goto out;
  1032. }
  1033. if (intparm) {
  1034. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  1035. buffer->state = BUF_STATE_PROCESSED;
  1036. }
  1037. if (channel == &card->data)
  1038. return;
  1039. if (channel == &card->read &&
  1040. channel->state == CH_STATE_UP)
  1041. qeth_issue_next_read(card);
  1042. iob = channel->iob;
  1043. index = channel->buf_no;
  1044. while (iob[index].state == BUF_STATE_PROCESSED) {
  1045. if (iob[index].callback != NULL)
  1046. iob[index].callback(channel, iob + index);
  1047. index = (index + 1) % QETH_CMD_BUFFER_NO;
  1048. }
  1049. channel->buf_no = index;
  1050. out:
  1051. wake_up(&card->wait_q);
  1052. return;
  1053. }
  1054. static void qeth_notify_skbs(struct qeth_qdio_out_q *q,
  1055. struct qeth_qdio_out_buffer *buf,
  1056. enum iucv_tx_notify notification)
  1057. {
  1058. struct sk_buff *skb;
  1059. if (skb_queue_empty(&buf->skb_list))
  1060. goto out;
  1061. skb = skb_peek(&buf->skb_list);
  1062. while (skb) {
  1063. QETH_CARD_TEXT_(q->card, 5, "skbn%d", notification);
  1064. QETH_CARD_TEXT_(q->card, 5, "%lx", (long) skb);
  1065. if (skb->protocol == ETH_P_AF_IUCV) {
  1066. if (skb->sk) {
  1067. struct iucv_sock *iucv = iucv_sk(skb->sk);
  1068. iucv->sk_txnotify(skb, notification);
  1069. }
  1070. }
  1071. if (skb_queue_is_last(&buf->skb_list, skb))
  1072. skb = NULL;
  1073. else
  1074. skb = skb_queue_next(&buf->skb_list, skb);
  1075. }
  1076. out:
  1077. return;
  1078. }
  1079. static void qeth_release_skbs(struct qeth_qdio_out_buffer *buf)
  1080. {
  1081. struct sk_buff *skb;
  1082. struct iucv_sock *iucv;
  1083. int notify_general_error = 0;
  1084. if (atomic_read(&buf->state) == QETH_QDIO_BUF_PENDING)
  1085. notify_general_error = 1;
  1086. /* release may never happen from within CQ tasklet scope */
  1087. WARN_ON_ONCE(atomic_read(&buf->state) == QETH_QDIO_BUF_IN_CQ);
  1088. skb = skb_dequeue(&buf->skb_list);
  1089. while (skb) {
  1090. QETH_CARD_TEXT(buf->q->card, 5, "skbr");
  1091. QETH_CARD_TEXT_(buf->q->card, 5, "%lx", (long) skb);
  1092. if (notify_general_error && skb->protocol == ETH_P_AF_IUCV) {
  1093. if (skb->sk) {
  1094. iucv = iucv_sk(skb->sk);
  1095. iucv->sk_txnotify(skb, TX_NOTIFY_GENERALERROR);
  1096. }
  1097. }
  1098. atomic_dec(&skb->users);
  1099. dev_kfree_skb_any(skb);
  1100. skb = skb_dequeue(&buf->skb_list);
  1101. }
  1102. }
  1103. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  1104. struct qeth_qdio_out_buffer *buf,
  1105. enum qeth_qdio_buffer_states newbufstate)
  1106. {
  1107. int i;
  1108. /* is PCI flag set on buffer? */
  1109. if (buf->buffer->element[0].sflags & SBAL_SFLAGS0_PCI_REQ)
  1110. atomic_dec(&queue->set_pci_flags_count);
  1111. if (newbufstate == QETH_QDIO_BUF_EMPTY) {
  1112. qeth_release_skbs(buf);
  1113. }
  1114. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  1115. if (buf->buffer->element[i].addr && buf->is_header[i])
  1116. kmem_cache_free(qeth_core_header_cache,
  1117. buf->buffer->element[i].addr);
  1118. buf->is_header[i] = 0;
  1119. buf->buffer->element[i].length = 0;
  1120. buf->buffer->element[i].addr = NULL;
  1121. buf->buffer->element[i].eflags = 0;
  1122. buf->buffer->element[i].sflags = 0;
  1123. }
  1124. buf->buffer->element[15].eflags = 0;
  1125. buf->buffer->element[15].sflags = 0;
  1126. buf->next_element_to_fill = 0;
  1127. atomic_set(&buf->state, newbufstate);
  1128. }
  1129. static void qeth_clear_outq_buffers(struct qeth_qdio_out_q *q, int free)
  1130. {
  1131. int j;
  1132. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1133. if (!q->bufs[j])
  1134. continue;
  1135. qeth_cleanup_handled_pending(q, j, 1);
  1136. qeth_clear_output_buffer(q, q->bufs[j], QETH_QDIO_BUF_EMPTY);
  1137. if (free) {
  1138. kmem_cache_free(qeth_qdio_outbuf_cache, q->bufs[j]);
  1139. q->bufs[j] = NULL;
  1140. }
  1141. }
  1142. }
  1143. void qeth_clear_qdio_buffers(struct qeth_card *card)
  1144. {
  1145. int i;
  1146. QETH_CARD_TEXT(card, 2, "clearqdbf");
  1147. /* clear outbound buffers to free skbs */
  1148. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1149. if (card->qdio.out_qs[i]) {
  1150. qeth_clear_outq_buffers(card->qdio.out_qs[i], 0);
  1151. }
  1152. }
  1153. }
  1154. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  1155. static void qeth_free_buffer_pool(struct qeth_card *card)
  1156. {
  1157. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  1158. int i = 0;
  1159. list_for_each_entry_safe(pool_entry, tmp,
  1160. &card->qdio.init_pool.entry_list, init_list){
  1161. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  1162. free_page((unsigned long)pool_entry->elements[i]);
  1163. list_del(&pool_entry->init_list);
  1164. kfree(pool_entry);
  1165. }
  1166. }
  1167. static void qeth_clean_channel(struct qeth_channel *channel)
  1168. {
  1169. int cnt;
  1170. QETH_DBF_TEXT(SETUP, 2, "freech");
  1171. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  1172. kfree(channel->iob[cnt].data);
  1173. }
  1174. static void qeth_set_single_write_queues(struct qeth_card *card)
  1175. {
  1176. if ((atomic_read(&card->qdio.state) != QETH_QDIO_UNINITIALIZED) &&
  1177. (card->qdio.no_out_queues == 4))
  1178. qeth_free_qdio_buffers(card);
  1179. card->qdio.no_out_queues = 1;
  1180. if (card->qdio.default_out_queue != 0)
  1181. dev_info(&card->gdev->dev, "Priority Queueing not supported\n");
  1182. card->qdio.default_out_queue = 0;
  1183. }
  1184. static void qeth_set_multiple_write_queues(struct qeth_card *card)
  1185. {
  1186. if ((atomic_read(&card->qdio.state) != QETH_QDIO_UNINITIALIZED) &&
  1187. (card->qdio.no_out_queues == 1)) {
  1188. qeth_free_qdio_buffers(card);
  1189. card->qdio.default_out_queue = 2;
  1190. }
  1191. card->qdio.no_out_queues = 4;
  1192. }
  1193. static void qeth_update_from_chp_desc(struct qeth_card *card)
  1194. {
  1195. struct ccw_device *ccwdev;
  1196. struct channel_path_desc *chp_dsc;
  1197. QETH_DBF_TEXT(SETUP, 2, "chp_desc");
  1198. ccwdev = card->data.ccwdev;
  1199. chp_dsc = ccw_device_get_chp_desc(ccwdev, 0);
  1200. if (!chp_dsc)
  1201. goto out;
  1202. card->info.func_level = 0x4100 + chp_dsc->desc;
  1203. if (card->info.type == QETH_CARD_TYPE_IQD)
  1204. goto out;
  1205. /* CHPP field bit 6 == 1 -> single queue */
  1206. if ((chp_dsc->chpp & 0x02) == 0x02)
  1207. qeth_set_single_write_queues(card);
  1208. else
  1209. qeth_set_multiple_write_queues(card);
  1210. out:
  1211. kfree(chp_dsc);
  1212. QETH_DBF_TEXT_(SETUP, 2, "nr:%x", card->qdio.no_out_queues);
  1213. QETH_DBF_TEXT_(SETUP, 2, "lvl:%02x", card->info.func_level);
  1214. }
  1215. static void qeth_init_qdio_info(struct qeth_card *card)
  1216. {
  1217. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  1218. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1219. /* inbound */
  1220. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1221. if (card->info.type == QETH_CARD_TYPE_IQD)
  1222. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_HSDEFAULT;
  1223. else
  1224. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  1225. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  1226. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  1227. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  1228. }
  1229. static void qeth_set_intial_options(struct qeth_card *card)
  1230. {
  1231. card->options.route4.type = NO_ROUTER;
  1232. card->options.route6.type = NO_ROUTER;
  1233. card->options.fake_broadcast = 0;
  1234. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  1235. card->options.performance_stats = 0;
  1236. card->options.rx_sg_cb = QETH_RX_SG_CB;
  1237. card->options.isolation = ISOLATION_MODE_NONE;
  1238. card->options.cq = QETH_CQ_DISABLED;
  1239. }
  1240. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  1241. {
  1242. unsigned long flags;
  1243. int rc = 0;
  1244. spin_lock_irqsave(&card->thread_mask_lock, flags);
  1245. QETH_CARD_TEXT_(card, 4, " %02x%02x%02x",
  1246. (u8) card->thread_start_mask,
  1247. (u8) card->thread_allowed_mask,
  1248. (u8) card->thread_running_mask);
  1249. rc = (card->thread_start_mask & thread);
  1250. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  1251. return rc;
  1252. }
  1253. static void qeth_start_kernel_thread(struct work_struct *work)
  1254. {
  1255. struct task_struct *ts;
  1256. struct qeth_card *card = container_of(work, struct qeth_card,
  1257. kernel_thread_starter);
  1258. QETH_CARD_TEXT(card , 2, "strthrd");
  1259. if (card->read.state != CH_STATE_UP &&
  1260. card->write.state != CH_STATE_UP)
  1261. return;
  1262. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD)) {
  1263. ts = kthread_run(card->discipline->recover, (void *)card,
  1264. "qeth_recover");
  1265. if (IS_ERR(ts)) {
  1266. qeth_clear_thread_start_bit(card, QETH_RECOVER_THREAD);
  1267. qeth_clear_thread_running_bit(card,
  1268. QETH_RECOVER_THREAD);
  1269. }
  1270. }
  1271. }
  1272. static int qeth_setup_card(struct qeth_card *card)
  1273. {
  1274. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  1275. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1276. card->read.state = CH_STATE_DOWN;
  1277. card->write.state = CH_STATE_DOWN;
  1278. card->data.state = CH_STATE_DOWN;
  1279. card->state = CARD_STATE_DOWN;
  1280. card->lan_online = 0;
  1281. card->read_or_write_problem = 0;
  1282. card->dev = NULL;
  1283. spin_lock_init(&card->vlanlock);
  1284. spin_lock_init(&card->mclock);
  1285. spin_lock_init(&card->lock);
  1286. spin_lock_init(&card->ip_lock);
  1287. spin_lock_init(&card->thread_mask_lock);
  1288. mutex_init(&card->conf_mutex);
  1289. mutex_init(&card->discipline_mutex);
  1290. card->thread_start_mask = 0;
  1291. card->thread_allowed_mask = 0;
  1292. card->thread_running_mask = 0;
  1293. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  1294. INIT_LIST_HEAD(&card->ip_list);
  1295. INIT_LIST_HEAD(card->ip_tbd_list);
  1296. INIT_LIST_HEAD(&card->cmd_waiter_list);
  1297. init_waitqueue_head(&card->wait_q);
  1298. /* initial options */
  1299. qeth_set_intial_options(card);
  1300. /* IP address takeover */
  1301. INIT_LIST_HEAD(&card->ipato.entries);
  1302. card->ipato.enabled = 0;
  1303. card->ipato.invert4 = 0;
  1304. card->ipato.invert6 = 0;
  1305. /* init QDIO stuff */
  1306. qeth_init_qdio_info(card);
  1307. INIT_DELAYED_WORK(&card->buffer_reclaim_work, qeth_buffer_reclaim_work);
  1308. INIT_WORK(&card->close_dev_work, qeth_close_dev_handler);
  1309. return 0;
  1310. }
  1311. static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
  1312. {
  1313. struct qeth_card *card = container_of(slr, struct qeth_card,
  1314. qeth_service_level);
  1315. if (card->info.mcl_level[0])
  1316. seq_printf(m, "qeth: %s firmware level %s\n",
  1317. CARD_BUS_ID(card), card->info.mcl_level);
  1318. }
  1319. static struct qeth_card *qeth_alloc_card(void)
  1320. {
  1321. struct qeth_card *card;
  1322. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1323. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1324. if (!card)
  1325. goto out;
  1326. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1327. card->ip_tbd_list = kzalloc(sizeof(struct list_head), GFP_KERNEL);
  1328. if (!card->ip_tbd_list) {
  1329. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1330. goto out_card;
  1331. }
  1332. if (qeth_setup_channel(&card->read))
  1333. goto out_ip;
  1334. if (qeth_setup_channel(&card->write))
  1335. goto out_channel;
  1336. card->options.layer2 = -1;
  1337. card->qeth_service_level.seq_print = qeth_core_sl_print;
  1338. register_service_level(&card->qeth_service_level);
  1339. return card;
  1340. out_channel:
  1341. qeth_clean_channel(&card->read);
  1342. out_ip:
  1343. kfree(card->ip_tbd_list);
  1344. out_card:
  1345. kfree(card);
  1346. out:
  1347. return NULL;
  1348. }
  1349. static int qeth_determine_card_type(struct qeth_card *card)
  1350. {
  1351. int i = 0;
  1352. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1353. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1354. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1355. while (known_devices[i][QETH_DEV_MODEL_IND]) {
  1356. if ((CARD_RDEV(card)->id.dev_type ==
  1357. known_devices[i][QETH_DEV_TYPE_IND]) &&
  1358. (CARD_RDEV(card)->id.dev_model ==
  1359. known_devices[i][QETH_DEV_MODEL_IND])) {
  1360. card->info.type = known_devices[i][QETH_DEV_MODEL_IND];
  1361. card->qdio.no_out_queues =
  1362. known_devices[i][QETH_QUEUE_NO_IND];
  1363. card->qdio.no_in_queues = 1;
  1364. card->info.is_multicast_different =
  1365. known_devices[i][QETH_MULTICAST_IND];
  1366. qeth_update_from_chp_desc(card);
  1367. return 0;
  1368. }
  1369. i++;
  1370. }
  1371. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1372. dev_err(&card->gdev->dev, "The adapter hardware is of an "
  1373. "unknown type\n");
  1374. return -ENOENT;
  1375. }
  1376. static int qeth_clear_channel(struct qeth_channel *channel)
  1377. {
  1378. unsigned long flags;
  1379. struct qeth_card *card;
  1380. int rc;
  1381. card = CARD_FROM_CDEV(channel->ccwdev);
  1382. QETH_CARD_TEXT(card, 3, "clearch");
  1383. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1384. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1385. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1386. if (rc)
  1387. return rc;
  1388. rc = wait_event_interruptible_timeout(card->wait_q,
  1389. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1390. if (rc == -ERESTARTSYS)
  1391. return rc;
  1392. if (channel->state != CH_STATE_STOPPED)
  1393. return -ETIME;
  1394. channel->state = CH_STATE_DOWN;
  1395. return 0;
  1396. }
  1397. static int qeth_halt_channel(struct qeth_channel *channel)
  1398. {
  1399. unsigned long flags;
  1400. struct qeth_card *card;
  1401. int rc;
  1402. card = CARD_FROM_CDEV(channel->ccwdev);
  1403. QETH_CARD_TEXT(card, 3, "haltch");
  1404. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1405. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1406. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1407. if (rc)
  1408. return rc;
  1409. rc = wait_event_interruptible_timeout(card->wait_q,
  1410. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1411. if (rc == -ERESTARTSYS)
  1412. return rc;
  1413. if (channel->state != CH_STATE_HALTED)
  1414. return -ETIME;
  1415. return 0;
  1416. }
  1417. static int qeth_halt_channels(struct qeth_card *card)
  1418. {
  1419. int rc1 = 0, rc2 = 0, rc3 = 0;
  1420. QETH_CARD_TEXT(card, 3, "haltchs");
  1421. rc1 = qeth_halt_channel(&card->read);
  1422. rc2 = qeth_halt_channel(&card->write);
  1423. rc3 = qeth_halt_channel(&card->data);
  1424. if (rc1)
  1425. return rc1;
  1426. if (rc2)
  1427. return rc2;
  1428. return rc3;
  1429. }
  1430. static int qeth_clear_channels(struct qeth_card *card)
  1431. {
  1432. int rc1 = 0, rc2 = 0, rc3 = 0;
  1433. QETH_CARD_TEXT(card, 3, "clearchs");
  1434. rc1 = qeth_clear_channel(&card->read);
  1435. rc2 = qeth_clear_channel(&card->write);
  1436. rc3 = qeth_clear_channel(&card->data);
  1437. if (rc1)
  1438. return rc1;
  1439. if (rc2)
  1440. return rc2;
  1441. return rc3;
  1442. }
  1443. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1444. {
  1445. int rc = 0;
  1446. QETH_CARD_TEXT(card, 3, "clhacrd");
  1447. if (halt)
  1448. rc = qeth_halt_channels(card);
  1449. if (rc)
  1450. return rc;
  1451. return qeth_clear_channels(card);
  1452. }
  1453. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1454. {
  1455. int rc = 0;
  1456. QETH_CARD_TEXT(card, 3, "qdioclr");
  1457. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1458. QETH_QDIO_CLEANING)) {
  1459. case QETH_QDIO_ESTABLISHED:
  1460. if (card->info.type == QETH_CARD_TYPE_IQD)
  1461. rc = qdio_shutdown(CARD_DDEV(card),
  1462. QDIO_FLAG_CLEANUP_USING_HALT);
  1463. else
  1464. rc = qdio_shutdown(CARD_DDEV(card),
  1465. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1466. if (rc)
  1467. QETH_CARD_TEXT_(card, 3, "1err%d", rc);
  1468. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1469. break;
  1470. case QETH_QDIO_CLEANING:
  1471. return rc;
  1472. default:
  1473. break;
  1474. }
  1475. rc = qeth_clear_halt_card(card, use_halt);
  1476. if (rc)
  1477. QETH_CARD_TEXT_(card, 3, "2err%d", rc);
  1478. card->state = CARD_STATE_DOWN;
  1479. return rc;
  1480. }
  1481. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1482. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1483. int *length)
  1484. {
  1485. struct ciw *ciw;
  1486. char *rcd_buf;
  1487. int ret;
  1488. struct qeth_channel *channel = &card->data;
  1489. unsigned long flags;
  1490. /*
  1491. * scan for RCD command in extended SenseID data
  1492. */
  1493. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1494. if (!ciw || ciw->cmd == 0)
  1495. return -EOPNOTSUPP;
  1496. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1497. if (!rcd_buf)
  1498. return -ENOMEM;
  1499. channel->ccw.cmd_code = ciw->cmd;
  1500. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1501. channel->ccw.count = ciw->count;
  1502. channel->ccw.flags = CCW_FLAG_SLI;
  1503. channel->state = CH_STATE_RCD;
  1504. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1505. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1506. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1507. QETH_RCD_TIMEOUT);
  1508. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1509. if (!ret)
  1510. wait_event(card->wait_q,
  1511. (channel->state == CH_STATE_RCD_DONE ||
  1512. channel->state == CH_STATE_DOWN));
  1513. if (channel->state == CH_STATE_DOWN)
  1514. ret = -EIO;
  1515. else
  1516. channel->state = CH_STATE_DOWN;
  1517. if (ret) {
  1518. kfree(rcd_buf);
  1519. *buffer = NULL;
  1520. *length = 0;
  1521. } else {
  1522. *length = ciw->count;
  1523. *buffer = rcd_buf;
  1524. }
  1525. return ret;
  1526. }
  1527. static void qeth_configure_unitaddr(struct qeth_card *card, char *prcd)
  1528. {
  1529. QETH_DBF_TEXT(SETUP, 2, "cfgunit");
  1530. card->info.chpid = prcd[30];
  1531. card->info.unit_addr2 = prcd[31];
  1532. card->info.cula = prcd[63];
  1533. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1534. (prcd[0x11] == _ascebc['M']));
  1535. }
  1536. static void qeth_configure_blkt_default(struct qeth_card *card, char *prcd)
  1537. {
  1538. QETH_DBF_TEXT(SETUP, 2, "cfgblkt");
  1539. if (prcd[74] == 0xF0 && prcd[75] == 0xF0 &&
  1540. prcd[76] >= 0xF1 && prcd[76] <= 0xF4) {
  1541. card->info.blkt.time_total = 0;
  1542. card->info.blkt.inter_packet = 0;
  1543. card->info.blkt.inter_packet_jumbo = 0;
  1544. } else {
  1545. card->info.blkt.time_total = 250;
  1546. card->info.blkt.inter_packet = 5;
  1547. card->info.blkt.inter_packet_jumbo = 15;
  1548. }
  1549. }
  1550. static void qeth_init_tokens(struct qeth_card *card)
  1551. {
  1552. card->token.issuer_rm_w = 0x00010103UL;
  1553. card->token.cm_filter_w = 0x00010108UL;
  1554. card->token.cm_connection_w = 0x0001010aUL;
  1555. card->token.ulp_filter_w = 0x0001010bUL;
  1556. card->token.ulp_connection_w = 0x0001010dUL;
  1557. }
  1558. static void qeth_init_func_level(struct qeth_card *card)
  1559. {
  1560. switch (card->info.type) {
  1561. case QETH_CARD_TYPE_IQD:
  1562. card->info.func_level = QETH_IDX_FUNC_LEVEL_IQD;
  1563. break;
  1564. case QETH_CARD_TYPE_OSD:
  1565. case QETH_CARD_TYPE_OSN:
  1566. card->info.func_level = QETH_IDX_FUNC_LEVEL_OSD;
  1567. break;
  1568. default:
  1569. break;
  1570. }
  1571. }
  1572. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1573. void (*idx_reply_cb)(struct qeth_channel *,
  1574. struct qeth_cmd_buffer *))
  1575. {
  1576. struct qeth_cmd_buffer *iob;
  1577. unsigned long flags;
  1578. int rc;
  1579. struct qeth_card *card;
  1580. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1581. card = CARD_FROM_CDEV(channel->ccwdev);
  1582. iob = qeth_get_buffer(channel);
  1583. iob->callback = idx_reply_cb;
  1584. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1585. channel->ccw.count = QETH_BUFSIZE;
  1586. channel->ccw.cda = (__u32) __pa(iob->data);
  1587. wait_event(card->wait_q,
  1588. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1589. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1590. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1591. rc = ccw_device_start(channel->ccwdev,
  1592. &channel->ccw, (addr_t) iob, 0, 0);
  1593. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1594. if (rc) {
  1595. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1596. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1597. atomic_set(&channel->irq_pending, 0);
  1598. wake_up(&card->wait_q);
  1599. return rc;
  1600. }
  1601. rc = wait_event_interruptible_timeout(card->wait_q,
  1602. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1603. if (rc == -ERESTARTSYS)
  1604. return rc;
  1605. if (channel->state != CH_STATE_UP) {
  1606. rc = -ETIME;
  1607. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1608. qeth_clear_cmd_buffers(channel);
  1609. } else
  1610. rc = 0;
  1611. return rc;
  1612. }
  1613. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1614. void (*idx_reply_cb)(struct qeth_channel *,
  1615. struct qeth_cmd_buffer *))
  1616. {
  1617. struct qeth_card *card;
  1618. struct qeth_cmd_buffer *iob;
  1619. unsigned long flags;
  1620. __u16 temp;
  1621. __u8 tmp;
  1622. int rc;
  1623. struct ccw_dev_id temp_devid;
  1624. card = CARD_FROM_CDEV(channel->ccwdev);
  1625. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1626. iob = qeth_get_buffer(channel);
  1627. iob->callback = idx_reply_cb;
  1628. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1629. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1630. channel->ccw.cda = (__u32) __pa(iob->data);
  1631. if (channel == &card->write) {
  1632. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1633. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1634. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1635. card->seqno.trans_hdr++;
  1636. } else {
  1637. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1638. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1639. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1640. }
  1641. tmp = ((__u8)card->info.portno) | 0x80;
  1642. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1643. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1644. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1645. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1646. &card->info.func_level, sizeof(__u16));
  1647. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1648. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1649. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1650. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1651. wait_event(card->wait_q,
  1652. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1653. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1654. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1655. rc = ccw_device_start(channel->ccwdev,
  1656. &channel->ccw, (addr_t) iob, 0, 0);
  1657. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1658. if (rc) {
  1659. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1660. rc);
  1661. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1662. atomic_set(&channel->irq_pending, 0);
  1663. wake_up(&card->wait_q);
  1664. return rc;
  1665. }
  1666. rc = wait_event_interruptible_timeout(card->wait_q,
  1667. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1668. if (rc == -ERESTARTSYS)
  1669. return rc;
  1670. if (channel->state != CH_STATE_ACTIVATING) {
  1671. dev_warn(&channel->ccwdev->dev, "The qeth device driver"
  1672. " failed to recover an error on the device\n");
  1673. QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
  1674. dev_name(&channel->ccwdev->dev));
  1675. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1676. qeth_clear_cmd_buffers(channel);
  1677. return -ETIME;
  1678. }
  1679. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1680. }
  1681. static int qeth_peer_func_level(int level)
  1682. {
  1683. if ((level & 0xff) == 8)
  1684. return (level & 0xff) + 0x400;
  1685. if (((level >> 8) & 3) == 1)
  1686. return (level & 0xff) + 0x200;
  1687. return level;
  1688. }
  1689. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1690. struct qeth_cmd_buffer *iob)
  1691. {
  1692. struct qeth_card *card;
  1693. __u16 temp;
  1694. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1695. if (channel->state == CH_STATE_DOWN) {
  1696. channel->state = CH_STATE_ACTIVATING;
  1697. goto out;
  1698. }
  1699. card = CARD_FROM_CDEV(channel->ccwdev);
  1700. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1701. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == QETH_IDX_ACT_ERR_EXCL)
  1702. dev_err(&card->write.ccwdev->dev,
  1703. "The adapter is used exclusively by another "
  1704. "host\n");
  1705. else
  1706. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
  1707. " negative reply\n",
  1708. dev_name(&card->write.ccwdev->dev));
  1709. goto out;
  1710. }
  1711. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1712. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1713. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
  1714. "function level mismatch (sent: 0x%x, received: "
  1715. "0x%x)\n", dev_name(&card->write.ccwdev->dev),
  1716. card->info.func_level, temp);
  1717. goto out;
  1718. }
  1719. channel->state = CH_STATE_UP;
  1720. out:
  1721. qeth_release_buffer(channel, iob);
  1722. }
  1723. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1724. struct qeth_cmd_buffer *iob)
  1725. {
  1726. struct qeth_card *card;
  1727. __u16 temp;
  1728. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1729. if (channel->state == CH_STATE_DOWN) {
  1730. channel->state = CH_STATE_ACTIVATING;
  1731. goto out;
  1732. }
  1733. card = CARD_FROM_CDEV(channel->ccwdev);
  1734. if (qeth_check_idx_response(card, iob->data))
  1735. goto out;
  1736. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1737. switch (QETH_IDX_ACT_CAUSE_CODE(iob->data)) {
  1738. case QETH_IDX_ACT_ERR_EXCL:
  1739. dev_err(&card->write.ccwdev->dev,
  1740. "The adapter is used exclusively by another "
  1741. "host\n");
  1742. break;
  1743. case QETH_IDX_ACT_ERR_AUTH:
  1744. case QETH_IDX_ACT_ERR_AUTH_USER:
  1745. dev_err(&card->read.ccwdev->dev,
  1746. "Setting the device online failed because of "
  1747. "insufficient authorization\n");
  1748. break;
  1749. default:
  1750. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
  1751. " negative reply\n",
  1752. dev_name(&card->read.ccwdev->dev));
  1753. }
  1754. QETH_CARD_TEXT_(card, 2, "idxread%c",
  1755. QETH_IDX_ACT_CAUSE_CODE(iob->data));
  1756. goto out;
  1757. }
  1758. /**
  1759. * * temporary fix for microcode bug
  1760. * * to revert it,replace OR by AND
  1761. * */
  1762. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1763. (card->info.type == QETH_CARD_TYPE_OSD))
  1764. card->info.portname_required = 1;
  1765. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1766. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1767. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
  1768. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1769. dev_name(&card->read.ccwdev->dev),
  1770. card->info.func_level, temp);
  1771. goto out;
  1772. }
  1773. memcpy(&card->token.issuer_rm_r,
  1774. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1775. QETH_MPC_TOKEN_LENGTH);
  1776. memcpy(&card->info.mcl_level[0],
  1777. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1778. channel->state = CH_STATE_UP;
  1779. out:
  1780. qeth_release_buffer(channel, iob);
  1781. }
  1782. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1783. struct qeth_cmd_buffer *iob)
  1784. {
  1785. qeth_setup_ccw(&card->write, iob->data, len);
  1786. iob->callback = qeth_release_buffer;
  1787. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1788. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1789. card->seqno.trans_hdr++;
  1790. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1791. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1792. card->seqno.pdu_hdr++;
  1793. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1794. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1795. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1796. }
  1797. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1798. int qeth_send_control_data(struct qeth_card *card, int len,
  1799. struct qeth_cmd_buffer *iob,
  1800. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1801. unsigned long),
  1802. void *reply_param)
  1803. {
  1804. int rc;
  1805. unsigned long flags;
  1806. struct qeth_reply *reply = NULL;
  1807. unsigned long timeout, event_timeout;
  1808. struct qeth_ipa_cmd *cmd;
  1809. QETH_CARD_TEXT(card, 2, "sendctl");
  1810. if (card->read_or_write_problem) {
  1811. qeth_release_buffer(iob->channel, iob);
  1812. return -EIO;
  1813. }
  1814. reply = qeth_alloc_reply(card);
  1815. if (!reply) {
  1816. return -ENOMEM;
  1817. }
  1818. reply->callback = reply_cb;
  1819. reply->param = reply_param;
  1820. if (card->state == CARD_STATE_DOWN)
  1821. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1822. else
  1823. reply->seqno = card->seqno.ipa++;
  1824. init_waitqueue_head(&reply->wait_q);
  1825. spin_lock_irqsave(&card->lock, flags);
  1826. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1827. spin_unlock_irqrestore(&card->lock, flags);
  1828. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1829. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1830. qeth_prepare_control_data(card, len, iob);
  1831. if (IS_IPA(iob->data))
  1832. event_timeout = QETH_IPA_TIMEOUT;
  1833. else
  1834. event_timeout = QETH_TIMEOUT;
  1835. timeout = jiffies + event_timeout;
  1836. QETH_CARD_TEXT(card, 6, "noirqpnd");
  1837. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1838. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1839. (addr_t) iob, 0, 0);
  1840. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1841. if (rc) {
  1842. QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
  1843. "ccw_device_start rc = %i\n",
  1844. dev_name(&card->write.ccwdev->dev), rc);
  1845. QETH_CARD_TEXT_(card, 2, " err%d", rc);
  1846. spin_lock_irqsave(&card->lock, flags);
  1847. list_del_init(&reply->list);
  1848. qeth_put_reply(reply);
  1849. spin_unlock_irqrestore(&card->lock, flags);
  1850. qeth_release_buffer(iob->channel, iob);
  1851. atomic_set(&card->write.irq_pending, 0);
  1852. wake_up(&card->wait_q);
  1853. return rc;
  1854. }
  1855. /* we have only one long running ipassist, since we can ensure
  1856. process context of this command we can sleep */
  1857. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  1858. if ((cmd->hdr.command == IPA_CMD_SETIP) &&
  1859. (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
  1860. if (!wait_event_timeout(reply->wait_q,
  1861. atomic_read(&reply->received), event_timeout))
  1862. goto time_err;
  1863. } else {
  1864. while (!atomic_read(&reply->received)) {
  1865. if (time_after(jiffies, timeout))
  1866. goto time_err;
  1867. cpu_relax();
  1868. }
  1869. }
  1870. if (reply->rc == -EIO)
  1871. goto error;
  1872. rc = reply->rc;
  1873. qeth_put_reply(reply);
  1874. return rc;
  1875. time_err:
  1876. reply->rc = -ETIME;
  1877. spin_lock_irqsave(&reply->card->lock, flags);
  1878. list_del_init(&reply->list);
  1879. spin_unlock_irqrestore(&reply->card->lock, flags);
  1880. atomic_inc(&reply->received);
  1881. error:
  1882. atomic_set(&card->write.irq_pending, 0);
  1883. qeth_release_buffer(iob->channel, iob);
  1884. card->write.buf_no = (card->write.buf_no + 1) % QETH_CMD_BUFFER_NO;
  1885. rc = reply->rc;
  1886. qeth_put_reply(reply);
  1887. return rc;
  1888. }
  1889. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1890. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1891. unsigned long data)
  1892. {
  1893. struct qeth_cmd_buffer *iob;
  1894. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1895. iob = (struct qeth_cmd_buffer *) data;
  1896. memcpy(&card->token.cm_filter_r,
  1897. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1898. QETH_MPC_TOKEN_LENGTH);
  1899. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1900. return 0;
  1901. }
  1902. static int qeth_cm_enable(struct qeth_card *card)
  1903. {
  1904. int rc;
  1905. struct qeth_cmd_buffer *iob;
  1906. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1907. iob = qeth_wait_for_buffer(&card->write);
  1908. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1909. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1910. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1911. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1912. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1913. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1914. qeth_cm_enable_cb, NULL);
  1915. return rc;
  1916. }
  1917. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1918. unsigned long data)
  1919. {
  1920. struct qeth_cmd_buffer *iob;
  1921. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1922. iob = (struct qeth_cmd_buffer *) data;
  1923. memcpy(&card->token.cm_connection_r,
  1924. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1925. QETH_MPC_TOKEN_LENGTH);
  1926. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1927. return 0;
  1928. }
  1929. static int qeth_cm_setup(struct qeth_card *card)
  1930. {
  1931. int rc;
  1932. struct qeth_cmd_buffer *iob;
  1933. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1934. iob = qeth_wait_for_buffer(&card->write);
  1935. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1936. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1937. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1938. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1939. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1940. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1941. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1942. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1943. qeth_cm_setup_cb, NULL);
  1944. return rc;
  1945. }
  1946. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1947. {
  1948. switch (card->info.type) {
  1949. case QETH_CARD_TYPE_UNKNOWN:
  1950. return 1500;
  1951. case QETH_CARD_TYPE_IQD:
  1952. return card->info.max_mtu;
  1953. case QETH_CARD_TYPE_OSD:
  1954. switch (card->info.link_type) {
  1955. case QETH_LINK_TYPE_HSTR:
  1956. case QETH_LINK_TYPE_LANE_TR:
  1957. return 2000;
  1958. default:
  1959. return card->options.layer2 ? 1500 : 1492;
  1960. }
  1961. case QETH_CARD_TYPE_OSM:
  1962. case QETH_CARD_TYPE_OSX:
  1963. return card->options.layer2 ? 1500 : 1492;
  1964. default:
  1965. return 1500;
  1966. }
  1967. }
  1968. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1969. {
  1970. switch (framesize) {
  1971. case 0x4000:
  1972. return 8192;
  1973. case 0x6000:
  1974. return 16384;
  1975. case 0xa000:
  1976. return 32768;
  1977. case 0xffff:
  1978. return 57344;
  1979. default:
  1980. return 0;
  1981. }
  1982. }
  1983. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1984. {
  1985. switch (card->info.type) {
  1986. case QETH_CARD_TYPE_OSD:
  1987. case QETH_CARD_TYPE_OSM:
  1988. case QETH_CARD_TYPE_OSX:
  1989. case QETH_CARD_TYPE_IQD:
  1990. return ((mtu >= 576) &&
  1991. (mtu <= card->info.max_mtu));
  1992. case QETH_CARD_TYPE_OSN:
  1993. case QETH_CARD_TYPE_UNKNOWN:
  1994. default:
  1995. return 1;
  1996. }
  1997. }
  1998. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1999. unsigned long data)
  2000. {
  2001. __u16 mtu, framesize;
  2002. __u16 len;
  2003. __u8 link_type;
  2004. struct qeth_cmd_buffer *iob;
  2005. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  2006. iob = (struct qeth_cmd_buffer *) data;
  2007. memcpy(&card->token.ulp_filter_r,
  2008. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  2009. QETH_MPC_TOKEN_LENGTH);
  2010. if (card->info.type == QETH_CARD_TYPE_IQD) {
  2011. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  2012. mtu = qeth_get_mtu_outof_framesize(framesize);
  2013. if (!mtu) {
  2014. iob->rc = -EINVAL;
  2015. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  2016. return 0;
  2017. }
  2018. if (card->info.initial_mtu && (card->info.initial_mtu != mtu)) {
  2019. /* frame size has changed */
  2020. if (card->dev &&
  2021. ((card->dev->mtu == card->info.initial_mtu) ||
  2022. (card->dev->mtu > mtu)))
  2023. card->dev->mtu = mtu;
  2024. qeth_free_qdio_buffers(card);
  2025. }
  2026. card->info.initial_mtu = mtu;
  2027. card->info.max_mtu = mtu;
  2028. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  2029. } else {
  2030. card->info.max_mtu = *(__u16 *)QETH_ULP_ENABLE_RESP_MAX_MTU(
  2031. iob->data);
  2032. card->info.initial_mtu = min(card->info.max_mtu,
  2033. qeth_get_initial_mtu_for_card(card));
  2034. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  2035. }
  2036. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  2037. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  2038. memcpy(&link_type,
  2039. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  2040. card->info.link_type = link_type;
  2041. } else
  2042. card->info.link_type = 0;
  2043. QETH_DBF_TEXT_(SETUP, 2, "link%d", card->info.link_type);
  2044. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  2045. return 0;
  2046. }
  2047. static int qeth_ulp_enable(struct qeth_card *card)
  2048. {
  2049. int rc;
  2050. char prot_type;
  2051. struct qeth_cmd_buffer *iob;
  2052. /*FIXME: trace view callbacks*/
  2053. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  2054. iob = qeth_wait_for_buffer(&card->write);
  2055. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  2056. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  2057. (__u8) card->info.portno;
  2058. if (card->options.layer2)
  2059. if (card->info.type == QETH_CARD_TYPE_OSN)
  2060. prot_type = QETH_PROT_OSN2;
  2061. else
  2062. prot_type = QETH_PROT_LAYER2;
  2063. else
  2064. prot_type = QETH_PROT_TCPIP;
  2065. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  2066. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  2067. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  2068. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  2069. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  2070. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  2071. card->info.portname, 9);
  2072. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  2073. qeth_ulp_enable_cb, NULL);
  2074. return rc;
  2075. }
  2076. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  2077. unsigned long data)
  2078. {
  2079. struct qeth_cmd_buffer *iob;
  2080. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  2081. iob = (struct qeth_cmd_buffer *) data;
  2082. memcpy(&card->token.ulp_connection_r,
  2083. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  2084. QETH_MPC_TOKEN_LENGTH);
  2085. if (!strncmp("00S", QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  2086. 3)) {
  2087. QETH_DBF_TEXT(SETUP, 2, "olmlimit");
  2088. dev_err(&card->gdev->dev, "A connection could not be "
  2089. "established because of an OLM limit\n");
  2090. iob->rc = -EMLINK;
  2091. }
  2092. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  2093. return 0;
  2094. }
  2095. static int qeth_ulp_setup(struct qeth_card *card)
  2096. {
  2097. int rc;
  2098. __u16 temp;
  2099. struct qeth_cmd_buffer *iob;
  2100. struct ccw_dev_id dev_id;
  2101. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  2102. iob = qeth_wait_for_buffer(&card->write);
  2103. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  2104. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  2105. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  2106. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  2107. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  2108. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  2109. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  2110. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  2111. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  2112. temp = (card->info.cula << 8) + card->info.unit_addr2;
  2113. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  2114. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  2115. qeth_ulp_setup_cb, NULL);
  2116. return rc;
  2117. }
  2118. static int qeth_init_qdio_out_buf(struct qeth_qdio_out_q *q, int bidx)
  2119. {
  2120. int rc;
  2121. struct qeth_qdio_out_buffer *newbuf;
  2122. rc = 0;
  2123. newbuf = kmem_cache_zalloc(qeth_qdio_outbuf_cache, GFP_ATOMIC);
  2124. if (!newbuf) {
  2125. rc = -ENOMEM;
  2126. goto out;
  2127. }
  2128. newbuf->buffer = q->qdio_bufs[bidx];
  2129. skb_queue_head_init(&newbuf->skb_list);
  2130. lockdep_set_class(&newbuf->skb_list.lock, &qdio_out_skb_queue_key);
  2131. newbuf->q = q;
  2132. newbuf->aob = NULL;
  2133. newbuf->next_pending = q->bufs[bidx];
  2134. atomic_set(&newbuf->state, QETH_QDIO_BUF_EMPTY);
  2135. q->bufs[bidx] = newbuf;
  2136. if (q->bufstates) {
  2137. q->bufstates[bidx].user = newbuf;
  2138. QETH_CARD_TEXT_(q->card, 2, "nbs%d", bidx);
  2139. QETH_CARD_TEXT_(q->card, 2, "%lx", (long) newbuf);
  2140. QETH_CARD_TEXT_(q->card, 2, "%lx",
  2141. (long) newbuf->next_pending);
  2142. }
  2143. out:
  2144. return rc;
  2145. }
  2146. static void qeth_free_qdio_out_buf(struct qeth_qdio_out_q *q)
  2147. {
  2148. if (!q)
  2149. return;
  2150. qdio_free_buffers(q->qdio_bufs, QDIO_MAX_BUFFERS_PER_Q);
  2151. kfree(q);
  2152. }
  2153. static struct qeth_qdio_out_q *qeth_alloc_qdio_out_buf(void)
  2154. {
  2155. struct qeth_qdio_out_q *q = kzalloc(sizeof(*q), GFP_KERNEL);
  2156. if (!q)
  2157. return NULL;
  2158. if (qdio_alloc_buffers(q->qdio_bufs, QDIO_MAX_BUFFERS_PER_Q)) {
  2159. kfree(q);
  2160. return NULL;
  2161. }
  2162. return q;
  2163. }
  2164. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  2165. {
  2166. int i, j;
  2167. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  2168. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  2169. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  2170. return 0;
  2171. QETH_DBF_TEXT(SETUP, 2, "inq");
  2172. card->qdio.in_q = qeth_alloc_qdio_queue();
  2173. if (!card->qdio.in_q)
  2174. goto out_nomem;
  2175. /* inbound buffer pool */
  2176. if (qeth_alloc_buffer_pool(card))
  2177. goto out_freeinq;
  2178. /* outbound */
  2179. card->qdio.out_qs =
  2180. kzalloc(card->qdio.no_out_queues *
  2181. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  2182. if (!card->qdio.out_qs)
  2183. goto out_freepool;
  2184. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2185. card->qdio.out_qs[i] = qeth_alloc_qdio_out_buf();
  2186. if (!card->qdio.out_qs[i])
  2187. goto out_freeoutq;
  2188. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  2189. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  2190. card->qdio.out_qs[i]->queue_no = i;
  2191. /* give outbound qeth_qdio_buffers their qdio_buffers */
  2192. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2193. WARN_ON(card->qdio.out_qs[i]->bufs[j] != NULL);
  2194. if (qeth_init_qdio_out_buf(card->qdio.out_qs[i], j))
  2195. goto out_freeoutqbufs;
  2196. }
  2197. }
  2198. /* completion */
  2199. if (qeth_alloc_cq(card))
  2200. goto out_freeoutq;
  2201. return 0;
  2202. out_freeoutqbufs:
  2203. while (j > 0) {
  2204. --j;
  2205. kmem_cache_free(qeth_qdio_outbuf_cache,
  2206. card->qdio.out_qs[i]->bufs[j]);
  2207. card->qdio.out_qs[i]->bufs[j] = NULL;
  2208. }
  2209. out_freeoutq:
  2210. while (i > 0) {
  2211. qeth_free_qdio_out_buf(card->qdio.out_qs[--i]);
  2212. qeth_clear_outq_buffers(card->qdio.out_qs[i], 1);
  2213. }
  2214. kfree(card->qdio.out_qs);
  2215. card->qdio.out_qs = NULL;
  2216. out_freepool:
  2217. qeth_free_buffer_pool(card);
  2218. out_freeinq:
  2219. qeth_free_qdio_queue(card->qdio.in_q);
  2220. card->qdio.in_q = NULL;
  2221. out_nomem:
  2222. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  2223. return -ENOMEM;
  2224. }
  2225. static void qeth_free_qdio_buffers(struct qeth_card *card)
  2226. {
  2227. int i, j;
  2228. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  2229. QETH_QDIO_UNINITIALIZED)
  2230. return;
  2231. qeth_free_cq(card);
  2232. cancel_delayed_work_sync(&card->buffer_reclaim_work);
  2233. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2234. if (card->qdio.in_q->bufs[j].rx_skb)
  2235. dev_kfree_skb_any(card->qdio.in_q->bufs[j].rx_skb);
  2236. }
  2237. qeth_free_qdio_queue(card->qdio.in_q);
  2238. card->qdio.in_q = NULL;
  2239. /* inbound buffer pool */
  2240. qeth_free_buffer_pool(card);
  2241. /* free outbound qdio_qs */
  2242. if (card->qdio.out_qs) {
  2243. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2244. qeth_clear_outq_buffers(card->qdio.out_qs[i], 1);
  2245. qeth_free_qdio_out_buf(card->qdio.out_qs[i]);
  2246. }
  2247. kfree(card->qdio.out_qs);
  2248. card->qdio.out_qs = NULL;
  2249. }
  2250. }
  2251. static void qeth_create_qib_param_field(struct qeth_card *card,
  2252. char *param_field)
  2253. {
  2254. param_field[0] = _ascebc['P'];
  2255. param_field[1] = _ascebc['C'];
  2256. param_field[2] = _ascebc['I'];
  2257. param_field[3] = _ascebc['T'];
  2258. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  2259. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  2260. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  2261. }
  2262. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  2263. char *param_field)
  2264. {
  2265. param_field[16] = _ascebc['B'];
  2266. param_field[17] = _ascebc['L'];
  2267. param_field[18] = _ascebc['K'];
  2268. param_field[19] = _ascebc['T'];
  2269. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  2270. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  2271. *((unsigned int *) (&param_field[28])) =
  2272. card->info.blkt.inter_packet_jumbo;
  2273. }
  2274. static int qeth_qdio_activate(struct qeth_card *card)
  2275. {
  2276. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  2277. return qdio_activate(CARD_DDEV(card));
  2278. }
  2279. static int qeth_dm_act(struct qeth_card *card)
  2280. {
  2281. int rc;
  2282. struct qeth_cmd_buffer *iob;
  2283. QETH_DBF_TEXT(SETUP, 2, "dmact");
  2284. iob = qeth_wait_for_buffer(&card->write);
  2285. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  2286. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  2287. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  2288. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  2289. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2290. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  2291. return rc;
  2292. }
  2293. static int qeth_mpc_initialize(struct qeth_card *card)
  2294. {
  2295. int rc;
  2296. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  2297. rc = qeth_issue_next_read(card);
  2298. if (rc) {
  2299. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2300. return rc;
  2301. }
  2302. rc = qeth_cm_enable(card);
  2303. if (rc) {
  2304. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  2305. goto out_qdio;
  2306. }
  2307. rc = qeth_cm_setup(card);
  2308. if (rc) {
  2309. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  2310. goto out_qdio;
  2311. }
  2312. rc = qeth_ulp_enable(card);
  2313. if (rc) {
  2314. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  2315. goto out_qdio;
  2316. }
  2317. rc = qeth_ulp_setup(card);
  2318. if (rc) {
  2319. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  2320. goto out_qdio;
  2321. }
  2322. rc = qeth_alloc_qdio_buffers(card);
  2323. if (rc) {
  2324. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  2325. goto out_qdio;
  2326. }
  2327. rc = qeth_qdio_establish(card);
  2328. if (rc) {
  2329. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  2330. qeth_free_qdio_buffers(card);
  2331. goto out_qdio;
  2332. }
  2333. rc = qeth_qdio_activate(card);
  2334. if (rc) {
  2335. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  2336. goto out_qdio;
  2337. }
  2338. rc = qeth_dm_act(card);
  2339. if (rc) {
  2340. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  2341. goto out_qdio;
  2342. }
  2343. return 0;
  2344. out_qdio:
  2345. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  2346. qdio_free(CARD_DDEV(card));
  2347. return rc;
  2348. }
  2349. static void qeth_print_status_with_portname(struct qeth_card *card)
  2350. {
  2351. char dbf_text[15];
  2352. int i;
  2353. sprintf(dbf_text, "%s", card->info.portname + 1);
  2354. for (i = 0; i < 8; i++)
  2355. dbf_text[i] =
  2356. (char) _ebcasc[(__u8) dbf_text[i]];
  2357. dbf_text[8] = 0;
  2358. dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
  2359. "with link type %s (portname: %s)\n",
  2360. qeth_get_cardname(card),
  2361. (card->info.mcl_level[0]) ? " (level: " : "",
  2362. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2363. (card->info.mcl_level[0]) ? ")" : "",
  2364. qeth_get_cardname_short(card),
  2365. dbf_text);
  2366. }
  2367. static void qeth_print_status_no_portname(struct qeth_card *card)
  2368. {
  2369. if (card->info.portname[0])
  2370. dev_info(&card->gdev->dev, "Device is a%s "
  2371. "card%s%s%s\nwith link type %s "
  2372. "(no portname needed by interface).\n",
  2373. qeth_get_cardname(card),
  2374. (card->info.mcl_level[0]) ? " (level: " : "",
  2375. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2376. (card->info.mcl_level[0]) ? ")" : "",
  2377. qeth_get_cardname_short(card));
  2378. else
  2379. dev_info(&card->gdev->dev, "Device is a%s "
  2380. "card%s%s%s\nwith link type %s.\n",
  2381. qeth_get_cardname(card),
  2382. (card->info.mcl_level[0]) ? " (level: " : "",
  2383. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2384. (card->info.mcl_level[0]) ? ")" : "",
  2385. qeth_get_cardname_short(card));
  2386. }
  2387. void qeth_print_status_message(struct qeth_card *card)
  2388. {
  2389. switch (card->info.type) {
  2390. case QETH_CARD_TYPE_OSD:
  2391. case QETH_CARD_TYPE_OSM:
  2392. case QETH_CARD_TYPE_OSX:
  2393. /* VM will use a non-zero first character
  2394. * to indicate a HiperSockets like reporting
  2395. * of the level OSA sets the first character to zero
  2396. * */
  2397. if (!card->info.mcl_level[0]) {
  2398. sprintf(card->info.mcl_level, "%02x%02x",
  2399. card->info.mcl_level[2],
  2400. card->info.mcl_level[3]);
  2401. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2402. break;
  2403. }
  2404. /* fallthrough */
  2405. case QETH_CARD_TYPE_IQD:
  2406. if ((card->info.guestlan) ||
  2407. (card->info.mcl_level[0] & 0x80)) {
  2408. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2409. card->info.mcl_level[0]];
  2410. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2411. card->info.mcl_level[1]];
  2412. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2413. card->info.mcl_level[2]];
  2414. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2415. card->info.mcl_level[3]];
  2416. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2417. }
  2418. break;
  2419. default:
  2420. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2421. }
  2422. if (card->info.portname_required)
  2423. qeth_print_status_with_portname(card);
  2424. else
  2425. qeth_print_status_no_portname(card);
  2426. }
  2427. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2428. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2429. {
  2430. struct qeth_buffer_pool_entry *entry;
  2431. QETH_CARD_TEXT(card, 5, "inwrklst");
  2432. list_for_each_entry(entry,
  2433. &card->qdio.init_pool.entry_list, init_list) {
  2434. qeth_put_buffer_pool_entry(card, entry);
  2435. }
  2436. }
  2437. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2438. struct qeth_card *card)
  2439. {
  2440. struct list_head *plh;
  2441. struct qeth_buffer_pool_entry *entry;
  2442. int i, free;
  2443. struct page *page;
  2444. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2445. return NULL;
  2446. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2447. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2448. free = 1;
  2449. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2450. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2451. free = 0;
  2452. break;
  2453. }
  2454. }
  2455. if (free) {
  2456. list_del_init(&entry->list);
  2457. return entry;
  2458. }
  2459. }
  2460. /* no free buffer in pool so take first one and swap pages */
  2461. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2462. struct qeth_buffer_pool_entry, list);
  2463. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2464. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2465. page = alloc_page(GFP_ATOMIC);
  2466. if (!page) {
  2467. return NULL;
  2468. } else {
  2469. free_page((unsigned long)entry->elements[i]);
  2470. entry->elements[i] = page_address(page);
  2471. if (card->options.performance_stats)
  2472. card->perf_stats.sg_alloc_page_rx++;
  2473. }
  2474. }
  2475. }
  2476. list_del_init(&entry->list);
  2477. return entry;
  2478. }
  2479. static int qeth_init_input_buffer(struct qeth_card *card,
  2480. struct qeth_qdio_buffer *buf)
  2481. {
  2482. struct qeth_buffer_pool_entry *pool_entry;
  2483. int i;
  2484. if ((card->options.cq == QETH_CQ_ENABLED) && (!buf->rx_skb)) {
  2485. buf->rx_skb = dev_alloc_skb(QETH_RX_PULL_LEN + ETH_HLEN);
  2486. if (!buf->rx_skb)
  2487. return 1;
  2488. }
  2489. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2490. if (!pool_entry)
  2491. return 1;
  2492. /*
  2493. * since the buffer is accessed only from the input_tasklet
  2494. * there shouldn't be a need to synchronize; also, since we use
  2495. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2496. * buffers
  2497. */
  2498. buf->pool_entry = pool_entry;
  2499. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2500. buf->buffer->element[i].length = PAGE_SIZE;
  2501. buf->buffer->element[i].addr = pool_entry->elements[i];
  2502. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2503. buf->buffer->element[i].eflags = SBAL_EFLAGS_LAST_ENTRY;
  2504. else
  2505. buf->buffer->element[i].eflags = 0;
  2506. buf->buffer->element[i].sflags = 0;
  2507. }
  2508. return 0;
  2509. }
  2510. int qeth_init_qdio_queues(struct qeth_card *card)
  2511. {
  2512. int i, j;
  2513. int rc;
  2514. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2515. /* inbound queue */
  2516. qdio_reset_buffers(card->qdio.in_q->qdio_bufs,
  2517. QDIO_MAX_BUFFERS_PER_Q);
  2518. qeth_initialize_working_pool_list(card);
  2519. /*give only as many buffers to hardware as we have buffer pool entries*/
  2520. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2521. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2522. card->qdio.in_q->next_buf_to_init =
  2523. card->qdio.in_buf_pool.buf_count - 1;
  2524. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2525. card->qdio.in_buf_pool.buf_count - 1);
  2526. if (rc) {
  2527. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2528. return rc;
  2529. }
  2530. /* completion */
  2531. rc = qeth_cq_init(card);
  2532. if (rc) {
  2533. return rc;
  2534. }
  2535. /* outbound queue */
  2536. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2537. qdio_reset_buffers(card->qdio.out_qs[i]->qdio_bufs,
  2538. QDIO_MAX_BUFFERS_PER_Q);
  2539. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2540. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2541. card->qdio.out_qs[i]->bufs[j],
  2542. QETH_QDIO_BUF_EMPTY);
  2543. }
  2544. card->qdio.out_qs[i]->card = card;
  2545. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2546. card->qdio.out_qs[i]->do_pack = 0;
  2547. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2548. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2549. atomic_set(&card->qdio.out_qs[i]->state,
  2550. QETH_OUT_Q_UNLOCKED);
  2551. }
  2552. return 0;
  2553. }
  2554. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2555. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2556. {
  2557. switch (link_type) {
  2558. case QETH_LINK_TYPE_HSTR:
  2559. return 2;
  2560. default:
  2561. return 1;
  2562. }
  2563. }
  2564. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2565. struct qeth_ipa_cmd *cmd, __u8 command,
  2566. enum qeth_prot_versions prot)
  2567. {
  2568. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2569. cmd->hdr.command = command;
  2570. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2571. cmd->hdr.seqno = card->seqno.ipa;
  2572. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2573. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2574. if (card->options.layer2)
  2575. cmd->hdr.prim_version_no = 2;
  2576. else
  2577. cmd->hdr.prim_version_no = 1;
  2578. cmd->hdr.param_count = 1;
  2579. cmd->hdr.prot_version = prot;
  2580. cmd->hdr.ipa_supported = 0;
  2581. cmd->hdr.ipa_enabled = 0;
  2582. }
  2583. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2584. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2585. {
  2586. struct qeth_cmd_buffer *iob;
  2587. struct qeth_ipa_cmd *cmd;
  2588. iob = qeth_wait_for_buffer(&card->write);
  2589. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2590. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2591. return iob;
  2592. }
  2593. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2594. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2595. char prot_type)
  2596. {
  2597. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2598. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2599. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2600. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2601. }
  2602. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2603. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2604. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2605. unsigned long),
  2606. void *reply_param)
  2607. {
  2608. int rc;
  2609. char prot_type;
  2610. QETH_CARD_TEXT(card, 4, "sendipa");
  2611. if (card->options.layer2)
  2612. if (card->info.type == QETH_CARD_TYPE_OSN)
  2613. prot_type = QETH_PROT_OSN2;
  2614. else
  2615. prot_type = QETH_PROT_LAYER2;
  2616. else
  2617. prot_type = QETH_PROT_TCPIP;
  2618. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2619. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2620. iob, reply_cb, reply_param);
  2621. if (rc == -ETIME) {
  2622. qeth_clear_ipacmd_list(card);
  2623. qeth_schedule_recovery(card);
  2624. }
  2625. return rc;
  2626. }
  2627. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2628. int qeth_send_startlan(struct qeth_card *card)
  2629. {
  2630. int rc;
  2631. struct qeth_cmd_buffer *iob;
  2632. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2633. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_STARTLAN, 0);
  2634. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2635. return rc;
  2636. }
  2637. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2638. static int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2639. struct qeth_reply *reply, unsigned long data)
  2640. {
  2641. struct qeth_ipa_cmd *cmd;
  2642. QETH_CARD_TEXT(card, 4, "defadpcb");
  2643. cmd = (struct qeth_ipa_cmd *) data;
  2644. if (cmd->hdr.return_code == 0)
  2645. cmd->hdr.return_code =
  2646. cmd->data.setadapterparms.hdr.return_code;
  2647. return 0;
  2648. }
  2649. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2650. struct qeth_reply *reply, unsigned long data)
  2651. {
  2652. struct qeth_ipa_cmd *cmd;
  2653. QETH_CARD_TEXT(card, 3, "quyadpcb");
  2654. cmd = (struct qeth_ipa_cmd *) data;
  2655. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f) {
  2656. card->info.link_type =
  2657. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2658. QETH_DBF_TEXT_(SETUP, 2, "lnk %d", card->info.link_type);
  2659. }
  2660. card->options.adp.supported_funcs =
  2661. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2662. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2663. }
  2664. static struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2665. __u32 command, __u32 cmdlen)
  2666. {
  2667. struct qeth_cmd_buffer *iob;
  2668. struct qeth_ipa_cmd *cmd;
  2669. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2670. QETH_PROT_IPV4);
  2671. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2672. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2673. cmd->data.setadapterparms.hdr.command_code = command;
  2674. cmd->data.setadapterparms.hdr.used_total = 1;
  2675. cmd->data.setadapterparms.hdr.seq_no = 1;
  2676. return iob;
  2677. }
  2678. int qeth_query_setadapterparms(struct qeth_card *card)
  2679. {
  2680. int rc;
  2681. struct qeth_cmd_buffer *iob;
  2682. QETH_CARD_TEXT(card, 3, "queryadp");
  2683. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2684. sizeof(struct qeth_ipacmd_setadpparms));
  2685. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2686. return rc;
  2687. }
  2688. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2689. static int qeth_query_ipassists_cb(struct qeth_card *card,
  2690. struct qeth_reply *reply, unsigned long data)
  2691. {
  2692. struct qeth_ipa_cmd *cmd;
  2693. QETH_DBF_TEXT(SETUP, 2, "qipasscb");
  2694. cmd = (struct qeth_ipa_cmd *) data;
  2695. switch (cmd->hdr.return_code) {
  2696. case IPA_RC_NOTSUPP:
  2697. case IPA_RC_L2_UNSUPPORTED_CMD:
  2698. QETH_DBF_TEXT(SETUP, 2, "ipaunsup");
  2699. card->options.ipa4.supported_funcs |= IPA_SETADAPTERPARMS;
  2700. card->options.ipa6.supported_funcs |= IPA_SETADAPTERPARMS;
  2701. return -0;
  2702. default:
  2703. if (cmd->hdr.return_code) {
  2704. QETH_DBF_MESSAGE(1, "%s IPA_CMD_QIPASSIST: Unhandled "
  2705. "rc=%d\n",
  2706. dev_name(&card->gdev->dev),
  2707. cmd->hdr.return_code);
  2708. return 0;
  2709. }
  2710. }
  2711. if (cmd->hdr.prot_version == QETH_PROT_IPV4) {
  2712. card->options.ipa4.supported_funcs = cmd->hdr.ipa_supported;
  2713. card->options.ipa4.enabled_funcs = cmd->hdr.ipa_enabled;
  2714. } else if (cmd->hdr.prot_version == QETH_PROT_IPV6) {
  2715. card->options.ipa6.supported_funcs = cmd->hdr.ipa_supported;
  2716. card->options.ipa6.enabled_funcs = cmd->hdr.ipa_enabled;
  2717. } else
  2718. QETH_DBF_MESSAGE(1, "%s IPA_CMD_QIPASSIST: Flawed LIC detected"
  2719. "\n", dev_name(&card->gdev->dev));
  2720. return 0;
  2721. }
  2722. int qeth_query_ipassists(struct qeth_card *card, enum qeth_prot_versions prot)
  2723. {
  2724. int rc;
  2725. struct qeth_cmd_buffer *iob;
  2726. QETH_DBF_TEXT_(SETUP, 2, "qipassi%i", prot);
  2727. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_QIPASSIST, prot);
  2728. rc = qeth_send_ipa_cmd(card, iob, qeth_query_ipassists_cb, NULL);
  2729. return rc;
  2730. }
  2731. EXPORT_SYMBOL_GPL(qeth_query_ipassists);
  2732. static int qeth_query_switch_attributes_cb(struct qeth_card *card,
  2733. struct qeth_reply *reply, unsigned long data)
  2734. {
  2735. struct qeth_ipa_cmd *cmd;
  2736. struct qeth_switch_info *sw_info;
  2737. struct qeth_query_switch_attributes *attrs;
  2738. QETH_CARD_TEXT(card, 2, "qswiatcb");
  2739. cmd = (struct qeth_ipa_cmd *) data;
  2740. sw_info = (struct qeth_switch_info *)reply->param;
  2741. if (cmd->data.setadapterparms.hdr.return_code == 0) {
  2742. attrs = &cmd->data.setadapterparms.data.query_switch_attributes;
  2743. sw_info->capabilities = attrs->capabilities;
  2744. sw_info->settings = attrs->settings;
  2745. QETH_CARD_TEXT_(card, 2, "%04x%04x", sw_info->capabilities,
  2746. sw_info->settings);
  2747. }
  2748. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  2749. return 0;
  2750. }
  2751. int qeth_query_switch_attributes(struct qeth_card *card,
  2752. struct qeth_switch_info *sw_info)
  2753. {
  2754. struct qeth_cmd_buffer *iob;
  2755. QETH_CARD_TEXT(card, 2, "qswiattr");
  2756. if (!qeth_adp_supported(card, IPA_SETADP_QUERY_SWITCH_ATTRIBUTES))
  2757. return -EOPNOTSUPP;
  2758. if (!netif_carrier_ok(card->dev))
  2759. return -ENOMEDIUM;
  2760. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_SWITCH_ATTRIBUTES,
  2761. sizeof(struct qeth_ipacmd_setadpparms_hdr));
  2762. return qeth_send_ipa_cmd(card, iob,
  2763. qeth_query_switch_attributes_cb, sw_info);
  2764. }
  2765. EXPORT_SYMBOL_GPL(qeth_query_switch_attributes);
  2766. static int qeth_query_setdiagass_cb(struct qeth_card *card,
  2767. struct qeth_reply *reply, unsigned long data)
  2768. {
  2769. struct qeth_ipa_cmd *cmd;
  2770. __u16 rc;
  2771. cmd = (struct qeth_ipa_cmd *)data;
  2772. rc = cmd->hdr.return_code;
  2773. if (rc)
  2774. QETH_CARD_TEXT_(card, 2, "diagq:%x", rc);
  2775. else
  2776. card->info.diagass_support = cmd->data.diagass.ext;
  2777. return 0;
  2778. }
  2779. static int qeth_query_setdiagass(struct qeth_card *card)
  2780. {
  2781. struct qeth_cmd_buffer *iob;
  2782. struct qeth_ipa_cmd *cmd;
  2783. QETH_DBF_TEXT(SETUP, 2, "qdiagass");
  2784. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SET_DIAG_ASS, 0);
  2785. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2786. cmd->data.diagass.subcmd_len = 16;
  2787. cmd->data.diagass.subcmd = QETH_DIAGS_CMD_QUERY;
  2788. return qeth_send_ipa_cmd(card, iob, qeth_query_setdiagass_cb, NULL);
  2789. }
  2790. static void qeth_get_trap_id(struct qeth_card *card, struct qeth_trap_id *tid)
  2791. {
  2792. unsigned long info = get_zeroed_page(GFP_KERNEL);
  2793. struct sysinfo_2_2_2 *info222 = (struct sysinfo_2_2_2 *)info;
  2794. struct sysinfo_3_2_2 *info322 = (struct sysinfo_3_2_2 *)info;
  2795. struct ccw_dev_id ccwid;
  2796. int level;
  2797. tid->chpid = card->info.chpid;
  2798. ccw_device_get_id(CARD_RDEV(card), &ccwid);
  2799. tid->ssid = ccwid.ssid;
  2800. tid->devno = ccwid.devno;
  2801. if (!info)
  2802. return;
  2803. level = stsi(NULL, 0, 0, 0);
  2804. if ((level >= 2) && (stsi(info222, 2, 2, 2) == 0))
  2805. tid->lparnr = info222->lpar_number;
  2806. if ((level >= 3) && (stsi(info322, 3, 2, 2) == 0)) {
  2807. EBCASC(info322->vm[0].name, sizeof(info322->vm[0].name));
  2808. memcpy(tid->vmname, info322->vm[0].name, sizeof(tid->vmname));
  2809. }
  2810. free_page(info);
  2811. return;
  2812. }
  2813. static int qeth_hw_trap_cb(struct qeth_card *card,
  2814. struct qeth_reply *reply, unsigned long data)
  2815. {
  2816. struct qeth_ipa_cmd *cmd;
  2817. __u16 rc;
  2818. cmd = (struct qeth_ipa_cmd *)data;
  2819. rc = cmd->hdr.return_code;
  2820. if (rc)
  2821. QETH_CARD_TEXT_(card, 2, "trapc:%x", rc);
  2822. return 0;
  2823. }
  2824. int qeth_hw_trap(struct qeth_card *card, enum qeth_diags_trap_action action)
  2825. {
  2826. struct qeth_cmd_buffer *iob;
  2827. struct qeth_ipa_cmd *cmd;
  2828. QETH_DBF_TEXT(SETUP, 2, "diagtrap");
  2829. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SET_DIAG_ASS, 0);
  2830. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2831. cmd->data.diagass.subcmd_len = 80;
  2832. cmd->data.diagass.subcmd = QETH_DIAGS_CMD_TRAP;
  2833. cmd->data.diagass.type = 1;
  2834. cmd->data.diagass.action = action;
  2835. switch (action) {
  2836. case QETH_DIAGS_TRAP_ARM:
  2837. cmd->data.diagass.options = 0x0003;
  2838. cmd->data.diagass.ext = 0x00010000 +
  2839. sizeof(struct qeth_trap_id);
  2840. qeth_get_trap_id(card,
  2841. (struct qeth_trap_id *)cmd->data.diagass.cdata);
  2842. break;
  2843. case QETH_DIAGS_TRAP_DISARM:
  2844. cmd->data.diagass.options = 0x0001;
  2845. break;
  2846. case QETH_DIAGS_TRAP_CAPTURE:
  2847. break;
  2848. }
  2849. return qeth_send_ipa_cmd(card, iob, qeth_hw_trap_cb, NULL);
  2850. }
  2851. EXPORT_SYMBOL_GPL(qeth_hw_trap);
  2852. int qeth_check_qdio_errors(struct qeth_card *card, struct qdio_buffer *buf,
  2853. unsigned int qdio_error, const char *dbftext)
  2854. {
  2855. if (qdio_error) {
  2856. QETH_CARD_TEXT(card, 2, dbftext);
  2857. QETH_CARD_TEXT_(card, 2, " F15=%02X",
  2858. buf->element[15].sflags);
  2859. QETH_CARD_TEXT_(card, 2, " F14=%02X",
  2860. buf->element[14].sflags);
  2861. QETH_CARD_TEXT_(card, 2, " qerr=%X", qdio_error);
  2862. if ((buf->element[15].sflags) == 0x12) {
  2863. card->stats.rx_dropped++;
  2864. return 0;
  2865. } else
  2866. return 1;
  2867. }
  2868. return 0;
  2869. }
  2870. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2871. void qeth_buffer_reclaim_work(struct work_struct *work)
  2872. {
  2873. struct qeth_card *card = container_of(work, struct qeth_card,
  2874. buffer_reclaim_work.work);
  2875. QETH_CARD_TEXT_(card, 2, "brw:%x", card->reclaim_index);
  2876. qeth_queue_input_buffer(card, card->reclaim_index);
  2877. }
  2878. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2879. {
  2880. struct qeth_qdio_q *queue = card->qdio.in_q;
  2881. struct list_head *lh;
  2882. int count;
  2883. int i;
  2884. int rc;
  2885. int newcount = 0;
  2886. count = (index < queue->next_buf_to_init)?
  2887. card->qdio.in_buf_pool.buf_count -
  2888. (queue->next_buf_to_init - index) :
  2889. card->qdio.in_buf_pool.buf_count -
  2890. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2891. /* only requeue at a certain threshold to avoid SIGAs */
  2892. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2893. for (i = queue->next_buf_to_init;
  2894. i < queue->next_buf_to_init + count; ++i) {
  2895. if (qeth_init_input_buffer(card,
  2896. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2897. break;
  2898. } else {
  2899. newcount++;
  2900. }
  2901. }
  2902. if (newcount < count) {
  2903. /* we are in memory shortage so we switch back to
  2904. traditional skb allocation and drop packages */
  2905. atomic_set(&card->force_alloc_skb, 3);
  2906. count = newcount;
  2907. } else {
  2908. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2909. }
  2910. if (!count) {
  2911. i = 0;
  2912. list_for_each(lh, &card->qdio.in_buf_pool.entry_list)
  2913. i++;
  2914. if (i == card->qdio.in_buf_pool.buf_count) {
  2915. QETH_CARD_TEXT(card, 2, "qsarbw");
  2916. card->reclaim_index = index;
  2917. schedule_delayed_work(
  2918. &card->buffer_reclaim_work,
  2919. QETH_RECLAIM_WORK_TIME);
  2920. }
  2921. return;
  2922. }
  2923. /*
  2924. * according to old code it should be avoided to requeue all
  2925. * 128 buffers in order to benefit from PCI avoidance.
  2926. * this function keeps at least one buffer (the buffer at
  2927. * 'index') un-requeued -> this buffer is the first buffer that
  2928. * will be requeued the next time
  2929. */
  2930. if (card->options.performance_stats) {
  2931. card->perf_stats.inbound_do_qdio_cnt++;
  2932. card->perf_stats.inbound_do_qdio_start_time =
  2933. qeth_get_micros();
  2934. }
  2935. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2936. queue->next_buf_to_init, count);
  2937. if (card->options.performance_stats)
  2938. card->perf_stats.inbound_do_qdio_time +=
  2939. qeth_get_micros() -
  2940. card->perf_stats.inbound_do_qdio_start_time;
  2941. if (rc) {
  2942. QETH_CARD_TEXT(card, 2, "qinberr");
  2943. }
  2944. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2945. QDIO_MAX_BUFFERS_PER_Q;
  2946. }
  2947. }
  2948. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2949. static int qeth_handle_send_error(struct qeth_card *card,
  2950. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2951. {
  2952. int sbalf15 = buffer->buffer->element[15].sflags;
  2953. QETH_CARD_TEXT(card, 6, "hdsnderr");
  2954. if (card->info.type == QETH_CARD_TYPE_IQD) {
  2955. if (sbalf15 == 0) {
  2956. qdio_err = 0;
  2957. } else {
  2958. qdio_err = 1;
  2959. }
  2960. }
  2961. qeth_check_qdio_errors(card, buffer->buffer, qdio_err, "qouterr");
  2962. if (!qdio_err)
  2963. return QETH_SEND_ERROR_NONE;
  2964. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2965. return QETH_SEND_ERROR_RETRY;
  2966. QETH_CARD_TEXT(card, 1, "lnkfail");
  2967. QETH_CARD_TEXT_(card, 1, "%04x %02x",
  2968. (u16)qdio_err, (u8)sbalf15);
  2969. return QETH_SEND_ERROR_LINK_FAILURE;
  2970. }
  2971. /*
  2972. * Switched to packing state if the number of used buffers on a queue
  2973. * reaches a certain limit.
  2974. */
  2975. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2976. {
  2977. if (!queue->do_pack) {
  2978. if (atomic_read(&queue->used_buffers)
  2979. >= QETH_HIGH_WATERMARK_PACK){
  2980. /* switch non-PACKING -> PACKING */
  2981. QETH_CARD_TEXT(queue->card, 6, "np->pack");
  2982. if (queue->card->options.performance_stats)
  2983. queue->card->perf_stats.sc_dp_p++;
  2984. queue->do_pack = 1;
  2985. }
  2986. }
  2987. }
  2988. /*
  2989. * Switches from packing to non-packing mode. If there is a packing
  2990. * buffer on the queue this buffer will be prepared to be flushed.
  2991. * In that case 1 is returned to inform the caller. If no buffer
  2992. * has to be flushed, zero is returned.
  2993. */
  2994. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2995. {
  2996. struct qeth_qdio_out_buffer *buffer;
  2997. int flush_count = 0;
  2998. if (queue->do_pack) {
  2999. if (atomic_read(&queue->used_buffers)
  3000. <= QETH_LOW_WATERMARK_PACK) {
  3001. /* switch PACKING -> non-PACKING */
  3002. QETH_CARD_TEXT(queue->card, 6, "pack->np");
  3003. if (queue->card->options.performance_stats)
  3004. queue->card->perf_stats.sc_p_dp++;
  3005. queue->do_pack = 0;
  3006. /* flush packing buffers */
  3007. buffer = queue->bufs[queue->next_buf_to_fill];
  3008. if ((atomic_read(&buffer->state) ==
  3009. QETH_QDIO_BUF_EMPTY) &&
  3010. (buffer->next_element_to_fill > 0)) {
  3011. atomic_set(&buffer->state,
  3012. QETH_QDIO_BUF_PRIMED);
  3013. flush_count++;
  3014. queue->next_buf_to_fill =
  3015. (queue->next_buf_to_fill + 1) %
  3016. QDIO_MAX_BUFFERS_PER_Q;
  3017. }
  3018. }
  3019. }
  3020. return flush_count;
  3021. }
  3022. /*
  3023. * Called to flush a packing buffer if no more pci flags are on the queue.
  3024. * Checks if there is a packing buffer and prepares it to be flushed.
  3025. * In that case returns 1, otherwise zero.
  3026. */
  3027. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  3028. {
  3029. struct qeth_qdio_out_buffer *buffer;
  3030. buffer = queue->bufs[queue->next_buf_to_fill];
  3031. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  3032. (buffer->next_element_to_fill > 0)) {
  3033. /* it's a packing buffer */
  3034. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  3035. queue->next_buf_to_fill =
  3036. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  3037. return 1;
  3038. }
  3039. return 0;
  3040. }
  3041. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  3042. int count)
  3043. {
  3044. struct qeth_qdio_out_buffer *buf;
  3045. int rc;
  3046. int i;
  3047. unsigned int qdio_flags;
  3048. for (i = index; i < index + count; ++i) {
  3049. int bidx = i % QDIO_MAX_BUFFERS_PER_Q;
  3050. buf = queue->bufs[bidx];
  3051. buf->buffer->element[buf->next_element_to_fill - 1].eflags |=
  3052. SBAL_EFLAGS_LAST_ENTRY;
  3053. if (queue->bufstates)
  3054. queue->bufstates[bidx].user = buf;
  3055. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  3056. continue;
  3057. if (!queue->do_pack) {
  3058. if ((atomic_read(&queue->used_buffers) >=
  3059. (QETH_HIGH_WATERMARK_PACK -
  3060. QETH_WATERMARK_PACK_FUZZ)) &&
  3061. !atomic_read(&queue->set_pci_flags_count)) {
  3062. /* it's likely that we'll go to packing
  3063. * mode soon */
  3064. atomic_inc(&queue->set_pci_flags_count);
  3065. buf->buffer->element[0].sflags |= SBAL_SFLAGS0_PCI_REQ;
  3066. }
  3067. } else {
  3068. if (!atomic_read(&queue->set_pci_flags_count)) {
  3069. /*
  3070. * there's no outstanding PCI any more, so we
  3071. * have to request a PCI to be sure the the PCI
  3072. * will wake at some time in the future then we
  3073. * can flush packed buffers that might still be
  3074. * hanging around, which can happen if no
  3075. * further send was requested by the stack
  3076. */
  3077. atomic_inc(&queue->set_pci_flags_count);
  3078. buf->buffer->element[0].sflags |= SBAL_SFLAGS0_PCI_REQ;
  3079. }
  3080. }
  3081. }
  3082. queue->card->dev->trans_start = jiffies;
  3083. if (queue->card->options.performance_stats) {
  3084. queue->card->perf_stats.outbound_do_qdio_cnt++;
  3085. queue->card->perf_stats.outbound_do_qdio_start_time =
  3086. qeth_get_micros();
  3087. }
  3088. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  3089. if (atomic_read(&queue->set_pci_flags_count))
  3090. qdio_flags |= QDIO_FLAG_PCI_OUT;
  3091. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  3092. queue->queue_no, index, count);
  3093. if (queue->card->options.performance_stats)
  3094. queue->card->perf_stats.outbound_do_qdio_time +=
  3095. qeth_get_micros() -
  3096. queue->card->perf_stats.outbound_do_qdio_start_time;
  3097. atomic_add(count, &queue->used_buffers);
  3098. if (rc) {
  3099. queue->card->stats.tx_errors += count;
  3100. /* ignore temporary SIGA errors without busy condition */
  3101. if (rc == -ENOBUFS)
  3102. return;
  3103. QETH_CARD_TEXT(queue->card, 2, "flushbuf");
  3104. QETH_CARD_TEXT_(queue->card, 2, " q%d", queue->queue_no);
  3105. QETH_CARD_TEXT_(queue->card, 2, " idx%d", index);
  3106. QETH_CARD_TEXT_(queue->card, 2, " c%d", count);
  3107. QETH_CARD_TEXT_(queue->card, 2, " err%d", rc);
  3108. /* this must not happen under normal circumstances. if it
  3109. * happens something is really wrong -> recover */
  3110. qeth_schedule_recovery(queue->card);
  3111. return;
  3112. }
  3113. if (queue->card->options.performance_stats)
  3114. queue->card->perf_stats.bufs_sent += count;
  3115. }
  3116. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  3117. {
  3118. int index;
  3119. int flush_cnt = 0;
  3120. int q_was_packing = 0;
  3121. /*
  3122. * check if weed have to switch to non-packing mode or if
  3123. * we have to get a pci flag out on the queue
  3124. */
  3125. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  3126. !atomic_read(&queue->set_pci_flags_count)) {
  3127. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  3128. QETH_OUT_Q_UNLOCKED) {
  3129. /*
  3130. * If we get in here, there was no action in
  3131. * do_send_packet. So, we check if there is a
  3132. * packing buffer to be flushed here.
  3133. */
  3134. netif_stop_queue(queue->card->dev);
  3135. index = queue->next_buf_to_fill;
  3136. q_was_packing = queue->do_pack;
  3137. /* queue->do_pack may change */
  3138. barrier();
  3139. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  3140. if (!flush_cnt &&
  3141. !atomic_read(&queue->set_pci_flags_count))
  3142. flush_cnt +=
  3143. qeth_flush_buffers_on_no_pci(queue);
  3144. if (queue->card->options.performance_stats &&
  3145. q_was_packing)
  3146. queue->card->perf_stats.bufs_sent_pack +=
  3147. flush_cnt;
  3148. if (flush_cnt)
  3149. qeth_flush_buffers(queue, index, flush_cnt);
  3150. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3151. }
  3152. }
  3153. }
  3154. void qeth_qdio_start_poll(struct ccw_device *ccwdev, int queue,
  3155. unsigned long card_ptr)
  3156. {
  3157. struct qeth_card *card = (struct qeth_card *)card_ptr;
  3158. if (card->dev && (card->dev->flags & IFF_UP))
  3159. napi_schedule(&card->napi);
  3160. }
  3161. EXPORT_SYMBOL_GPL(qeth_qdio_start_poll);
  3162. int qeth_configure_cq(struct qeth_card *card, enum qeth_cq cq)
  3163. {
  3164. int rc;
  3165. if (card->options.cq == QETH_CQ_NOTAVAILABLE) {
  3166. rc = -1;
  3167. goto out;
  3168. } else {
  3169. if (card->options.cq == cq) {
  3170. rc = 0;
  3171. goto out;
  3172. }
  3173. if (card->state != CARD_STATE_DOWN &&
  3174. card->state != CARD_STATE_RECOVER) {
  3175. rc = -1;
  3176. goto out;
  3177. }
  3178. qeth_free_qdio_buffers(card);
  3179. card->options.cq = cq;
  3180. rc = 0;
  3181. }
  3182. out:
  3183. return rc;
  3184. }
  3185. EXPORT_SYMBOL_GPL(qeth_configure_cq);
  3186. static void qeth_qdio_cq_handler(struct qeth_card *card,
  3187. unsigned int qdio_err,
  3188. unsigned int queue, int first_element, int count) {
  3189. struct qeth_qdio_q *cq = card->qdio.c_q;
  3190. int i;
  3191. int rc;
  3192. if (!qeth_is_cq(card, queue))
  3193. goto out;
  3194. QETH_CARD_TEXT_(card, 5, "qcqhe%d", first_element);
  3195. QETH_CARD_TEXT_(card, 5, "qcqhc%d", count);
  3196. QETH_CARD_TEXT_(card, 5, "qcqherr%d", qdio_err);
  3197. if (qdio_err) {
  3198. netif_stop_queue(card->dev);
  3199. qeth_schedule_recovery(card);
  3200. goto out;
  3201. }
  3202. if (card->options.performance_stats) {
  3203. card->perf_stats.cq_cnt++;
  3204. card->perf_stats.cq_start_time = qeth_get_micros();
  3205. }
  3206. for (i = first_element; i < first_element + count; ++i) {
  3207. int bidx = i % QDIO_MAX_BUFFERS_PER_Q;
  3208. struct qdio_buffer *buffer = cq->qdio_bufs[bidx];
  3209. int e;
  3210. e = 0;
  3211. while (buffer->element[e].addr) {
  3212. unsigned long phys_aob_addr;
  3213. phys_aob_addr = (unsigned long) buffer->element[e].addr;
  3214. qeth_qdio_handle_aob(card, phys_aob_addr);
  3215. buffer->element[e].addr = NULL;
  3216. buffer->element[e].eflags = 0;
  3217. buffer->element[e].sflags = 0;
  3218. buffer->element[e].length = 0;
  3219. ++e;
  3220. }
  3221. buffer->element[15].eflags = 0;
  3222. buffer->element[15].sflags = 0;
  3223. }
  3224. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, queue,
  3225. card->qdio.c_q->next_buf_to_init,
  3226. count);
  3227. if (rc) {
  3228. dev_warn(&card->gdev->dev,
  3229. "QDIO reported an error, rc=%i\n", rc);
  3230. QETH_CARD_TEXT(card, 2, "qcqherr");
  3231. }
  3232. card->qdio.c_q->next_buf_to_init = (card->qdio.c_q->next_buf_to_init
  3233. + count) % QDIO_MAX_BUFFERS_PER_Q;
  3234. netif_wake_queue(card->dev);
  3235. if (card->options.performance_stats) {
  3236. int delta_t = qeth_get_micros();
  3237. delta_t -= card->perf_stats.cq_start_time;
  3238. card->perf_stats.cq_time += delta_t;
  3239. }
  3240. out:
  3241. return;
  3242. }
  3243. void qeth_qdio_input_handler(struct ccw_device *ccwdev, unsigned int qdio_err,
  3244. unsigned int queue, int first_elem, int count,
  3245. unsigned long card_ptr)
  3246. {
  3247. struct qeth_card *card = (struct qeth_card *)card_ptr;
  3248. QETH_CARD_TEXT_(card, 2, "qihq%d", queue);
  3249. QETH_CARD_TEXT_(card, 2, "qiec%d", qdio_err);
  3250. if (qeth_is_cq(card, queue))
  3251. qeth_qdio_cq_handler(card, qdio_err, queue, first_elem, count);
  3252. else if (qdio_err)
  3253. qeth_schedule_recovery(card);
  3254. }
  3255. EXPORT_SYMBOL_GPL(qeth_qdio_input_handler);
  3256. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  3257. unsigned int qdio_error, int __queue, int first_element,
  3258. int count, unsigned long card_ptr)
  3259. {
  3260. struct qeth_card *card = (struct qeth_card *) card_ptr;
  3261. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  3262. struct qeth_qdio_out_buffer *buffer;
  3263. int i;
  3264. QETH_CARD_TEXT(card, 6, "qdouhdl");
  3265. if (qdio_error & QDIO_ERROR_FATAL) {
  3266. QETH_CARD_TEXT(card, 2, "achkcond");
  3267. netif_stop_queue(card->dev);
  3268. qeth_schedule_recovery(card);
  3269. return;
  3270. }
  3271. if (card->options.performance_stats) {
  3272. card->perf_stats.outbound_handler_cnt++;
  3273. card->perf_stats.outbound_handler_start_time =
  3274. qeth_get_micros();
  3275. }
  3276. for (i = first_element; i < (first_element + count); ++i) {
  3277. int bidx = i % QDIO_MAX_BUFFERS_PER_Q;
  3278. buffer = queue->bufs[bidx];
  3279. qeth_handle_send_error(card, buffer, qdio_error);
  3280. if (queue->bufstates &&
  3281. (queue->bufstates[bidx].flags &
  3282. QDIO_OUTBUF_STATE_FLAG_PENDING) != 0) {
  3283. WARN_ON_ONCE(card->options.cq != QETH_CQ_ENABLED);
  3284. if (atomic_cmpxchg(&buffer->state,
  3285. QETH_QDIO_BUF_PRIMED,
  3286. QETH_QDIO_BUF_PENDING) ==
  3287. QETH_QDIO_BUF_PRIMED) {
  3288. qeth_notify_skbs(queue, buffer,
  3289. TX_NOTIFY_PENDING);
  3290. }
  3291. buffer->aob = queue->bufstates[bidx].aob;
  3292. QETH_CARD_TEXT_(queue->card, 5, "pel%d", bidx);
  3293. QETH_CARD_TEXT(queue->card, 5, "aob");
  3294. QETH_CARD_TEXT_(queue->card, 5, "%lx",
  3295. virt_to_phys(buffer->aob));
  3296. if (qeth_init_qdio_out_buf(queue, bidx)) {
  3297. QETH_CARD_TEXT(card, 2, "outofbuf");
  3298. qeth_schedule_recovery(card);
  3299. }
  3300. } else {
  3301. if (card->options.cq == QETH_CQ_ENABLED) {
  3302. enum iucv_tx_notify n;
  3303. n = qeth_compute_cq_notification(
  3304. buffer->buffer->element[15].sflags, 0);
  3305. qeth_notify_skbs(queue, buffer, n);
  3306. }
  3307. qeth_clear_output_buffer(queue, buffer,
  3308. QETH_QDIO_BUF_EMPTY);
  3309. }
  3310. qeth_cleanup_handled_pending(queue, bidx, 0);
  3311. }
  3312. atomic_sub(count, &queue->used_buffers);
  3313. /* check if we need to do something on this outbound queue */
  3314. if (card->info.type != QETH_CARD_TYPE_IQD)
  3315. qeth_check_outbound_queue(queue);
  3316. netif_wake_queue(queue->card->dev);
  3317. if (card->options.performance_stats)
  3318. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  3319. card->perf_stats.outbound_handler_start_time;
  3320. }
  3321. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  3322. /**
  3323. * Note: Function assumes that we have 4 outbound queues.
  3324. */
  3325. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  3326. int ipv, int cast_type)
  3327. {
  3328. __be16 *tci;
  3329. u8 tos;
  3330. if (cast_type && card->info.is_multicast_different)
  3331. return card->info.is_multicast_different &
  3332. (card->qdio.no_out_queues - 1);
  3333. switch (card->qdio.do_prio_queueing) {
  3334. case QETH_PRIO_Q_ING_TOS:
  3335. case QETH_PRIO_Q_ING_PREC:
  3336. switch (ipv) {
  3337. case 4:
  3338. tos = ipv4_get_dsfield(ip_hdr(skb));
  3339. break;
  3340. case 6:
  3341. tos = ipv6_get_dsfield(ipv6_hdr(skb));
  3342. break;
  3343. default:
  3344. return card->qdio.default_out_queue;
  3345. }
  3346. if (card->qdio.do_prio_queueing == QETH_PRIO_Q_ING_PREC)
  3347. return ~tos >> 6 & 3;
  3348. if (tos & IPTOS_MINCOST)
  3349. return 3;
  3350. if (tos & IPTOS_RELIABILITY)
  3351. return 2;
  3352. if (tos & IPTOS_THROUGHPUT)
  3353. return 1;
  3354. if (tos & IPTOS_LOWDELAY)
  3355. return 0;
  3356. break;
  3357. case QETH_PRIO_Q_ING_SKB:
  3358. if (skb->priority > 5)
  3359. return 0;
  3360. return ~skb->priority >> 1 & 3;
  3361. case QETH_PRIO_Q_ING_VLAN:
  3362. tci = &((struct ethhdr *)skb->data)->h_proto;
  3363. if (*tci == ETH_P_8021Q)
  3364. return ~*(tci + 1) >> (VLAN_PRIO_SHIFT + 1) & 3;
  3365. break;
  3366. default:
  3367. break;
  3368. }
  3369. return card->qdio.default_out_queue;
  3370. }
  3371. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  3372. int qeth_get_elements_for_frags(struct sk_buff *skb)
  3373. {
  3374. int cnt, length, e, elements = 0;
  3375. struct skb_frag_struct *frag;
  3376. char *data;
  3377. for (cnt = 0; cnt < skb_shinfo(skb)->nr_frags; cnt++) {
  3378. frag = &skb_shinfo(skb)->frags[cnt];
  3379. data = (char *)page_to_phys(skb_frag_page(frag)) +
  3380. frag->page_offset;
  3381. length = frag->size;
  3382. e = PFN_UP((unsigned long)data + length - 1) -
  3383. PFN_DOWN((unsigned long)data);
  3384. elements += e;
  3385. }
  3386. return elements;
  3387. }
  3388. EXPORT_SYMBOL_GPL(qeth_get_elements_for_frags);
  3389. int qeth_get_elements_no(struct qeth_card *card,
  3390. struct sk_buff *skb, int elems)
  3391. {
  3392. int dlen = skb->len - skb->data_len;
  3393. int elements_needed = PFN_UP((unsigned long)skb->data + dlen - 1) -
  3394. PFN_DOWN((unsigned long)skb->data);
  3395. elements_needed += qeth_get_elements_for_frags(skb);
  3396. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  3397. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  3398. "(Number=%d / Length=%d). Discarded.\n",
  3399. (elements_needed+elems), skb->len);
  3400. return 0;
  3401. }
  3402. return elements_needed;
  3403. }
  3404. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  3405. int qeth_hdr_chk_and_bounce(struct sk_buff *skb, struct qeth_hdr **hdr, int len)
  3406. {
  3407. int hroom, inpage, rest;
  3408. if (((unsigned long)skb->data & PAGE_MASK) !=
  3409. (((unsigned long)skb->data + len - 1) & PAGE_MASK)) {
  3410. hroom = skb_headroom(skb);
  3411. inpage = PAGE_SIZE - ((unsigned long) skb->data % PAGE_SIZE);
  3412. rest = len - inpage;
  3413. if (rest > hroom)
  3414. return 1;
  3415. memmove(skb->data - rest, skb->data, skb->len - skb->data_len);
  3416. skb->data -= rest;
  3417. skb->tail -= rest;
  3418. *hdr = (struct qeth_hdr *)skb->data;
  3419. QETH_DBF_MESSAGE(2, "skb bounce len: %d rest: %d\n", len, rest);
  3420. }
  3421. return 0;
  3422. }
  3423. EXPORT_SYMBOL_GPL(qeth_hdr_chk_and_bounce);
  3424. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  3425. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  3426. int offset)
  3427. {
  3428. int length = skb->len - skb->data_len;
  3429. int length_here;
  3430. int element;
  3431. char *data;
  3432. int first_lap, cnt;
  3433. struct skb_frag_struct *frag;
  3434. element = *next_element_to_fill;
  3435. data = skb->data;
  3436. first_lap = (is_tso == 0 ? 1 : 0);
  3437. if (offset >= 0) {
  3438. data = skb->data + offset;
  3439. length -= offset;
  3440. first_lap = 0;
  3441. }
  3442. while (length > 0) {
  3443. /* length_here is the remaining amount of data in this page */
  3444. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  3445. if (length < length_here)
  3446. length_here = length;
  3447. buffer->element[element].addr = data;
  3448. buffer->element[element].length = length_here;
  3449. length -= length_here;
  3450. if (!length) {
  3451. if (first_lap)
  3452. if (skb_shinfo(skb)->nr_frags)
  3453. buffer->element[element].eflags =
  3454. SBAL_EFLAGS_FIRST_FRAG;
  3455. else
  3456. buffer->element[element].eflags = 0;
  3457. else
  3458. buffer->element[element].eflags =
  3459. SBAL_EFLAGS_MIDDLE_FRAG;
  3460. } else {
  3461. if (first_lap)
  3462. buffer->element[element].eflags =
  3463. SBAL_EFLAGS_FIRST_FRAG;
  3464. else
  3465. buffer->element[element].eflags =
  3466. SBAL_EFLAGS_MIDDLE_FRAG;
  3467. }
  3468. data += length_here;
  3469. element++;
  3470. first_lap = 0;
  3471. }
  3472. for (cnt = 0; cnt < skb_shinfo(skb)->nr_frags; cnt++) {
  3473. frag = &skb_shinfo(skb)->frags[cnt];
  3474. data = (char *)page_to_phys(skb_frag_page(frag)) +
  3475. frag->page_offset;
  3476. length = frag->size;
  3477. while (length > 0) {
  3478. length_here = PAGE_SIZE -
  3479. ((unsigned long) data % PAGE_SIZE);
  3480. if (length < length_here)
  3481. length_here = length;
  3482. buffer->element[element].addr = data;
  3483. buffer->element[element].length = length_here;
  3484. buffer->element[element].eflags =
  3485. SBAL_EFLAGS_MIDDLE_FRAG;
  3486. length -= length_here;
  3487. data += length_here;
  3488. element++;
  3489. }
  3490. }
  3491. if (buffer->element[element - 1].eflags)
  3492. buffer->element[element - 1].eflags = SBAL_EFLAGS_LAST_FRAG;
  3493. *next_element_to_fill = element;
  3494. }
  3495. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  3496. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  3497. struct qeth_hdr *hdr, int offset, int hd_len)
  3498. {
  3499. struct qdio_buffer *buffer;
  3500. int flush_cnt = 0, hdr_len, large_send = 0;
  3501. buffer = buf->buffer;
  3502. atomic_inc(&skb->users);
  3503. skb_queue_tail(&buf->skb_list, skb);
  3504. /*check first on TSO ....*/
  3505. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  3506. int element = buf->next_element_to_fill;
  3507. hdr_len = sizeof(struct qeth_hdr_tso) +
  3508. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  3509. /*fill first buffer entry only with header information */
  3510. buffer->element[element].addr = skb->data;
  3511. buffer->element[element].length = hdr_len;
  3512. buffer->element[element].eflags = SBAL_EFLAGS_FIRST_FRAG;
  3513. buf->next_element_to_fill++;
  3514. skb->data += hdr_len;
  3515. skb->len -= hdr_len;
  3516. large_send = 1;
  3517. }
  3518. if (offset >= 0) {
  3519. int element = buf->next_element_to_fill;
  3520. buffer->element[element].addr = hdr;
  3521. buffer->element[element].length = sizeof(struct qeth_hdr) +
  3522. hd_len;
  3523. buffer->element[element].eflags = SBAL_EFLAGS_FIRST_FRAG;
  3524. buf->is_header[element] = 1;
  3525. buf->next_element_to_fill++;
  3526. }
  3527. __qeth_fill_buffer(skb, buffer, large_send,
  3528. (int *)&buf->next_element_to_fill, offset);
  3529. if (!queue->do_pack) {
  3530. QETH_CARD_TEXT(queue->card, 6, "fillbfnp");
  3531. /* set state to PRIMED -> will be flushed */
  3532. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  3533. flush_cnt = 1;
  3534. } else {
  3535. QETH_CARD_TEXT(queue->card, 6, "fillbfpa");
  3536. if (queue->card->options.performance_stats)
  3537. queue->card->perf_stats.skbs_sent_pack++;
  3538. if (buf->next_element_to_fill >=
  3539. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  3540. /*
  3541. * packed buffer if full -> set state PRIMED
  3542. * -> will be flushed
  3543. */
  3544. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  3545. flush_cnt = 1;
  3546. }
  3547. }
  3548. return flush_cnt;
  3549. }
  3550. int qeth_do_send_packet_fast(struct qeth_card *card,
  3551. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  3552. struct qeth_hdr *hdr, int elements_needed,
  3553. int offset, int hd_len)
  3554. {
  3555. struct qeth_qdio_out_buffer *buffer;
  3556. int index;
  3557. /* spin until we get the queue ... */
  3558. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  3559. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  3560. /* ... now we've got the queue */
  3561. index = queue->next_buf_to_fill;
  3562. buffer = queue->bufs[queue->next_buf_to_fill];
  3563. /*
  3564. * check if buffer is empty to make sure that we do not 'overtake'
  3565. * ourselves and try to fill a buffer that is already primed
  3566. */
  3567. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  3568. goto out;
  3569. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  3570. QDIO_MAX_BUFFERS_PER_Q;
  3571. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3572. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  3573. qeth_flush_buffers(queue, index, 1);
  3574. return 0;
  3575. out:
  3576. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3577. return -EBUSY;
  3578. }
  3579. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  3580. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  3581. struct sk_buff *skb, struct qeth_hdr *hdr,
  3582. int elements_needed)
  3583. {
  3584. struct qeth_qdio_out_buffer *buffer;
  3585. int start_index;
  3586. int flush_count = 0;
  3587. int do_pack = 0;
  3588. int tmp;
  3589. int rc = 0;
  3590. /* spin until we get the queue ... */
  3591. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  3592. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  3593. start_index = queue->next_buf_to_fill;
  3594. buffer = queue->bufs[queue->next_buf_to_fill];
  3595. /*
  3596. * check if buffer is empty to make sure that we do not 'overtake'
  3597. * ourselves and try to fill a buffer that is already primed
  3598. */
  3599. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  3600. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3601. return -EBUSY;
  3602. }
  3603. /* check if we need to switch packing state of this queue */
  3604. qeth_switch_to_packing_if_needed(queue);
  3605. if (queue->do_pack) {
  3606. do_pack = 1;
  3607. /* does packet fit in current buffer? */
  3608. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  3609. buffer->next_element_to_fill) < elements_needed) {
  3610. /* ... no -> set state PRIMED */
  3611. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  3612. flush_count++;
  3613. queue->next_buf_to_fill =
  3614. (queue->next_buf_to_fill + 1) %
  3615. QDIO_MAX_BUFFERS_PER_Q;
  3616. buffer = queue->bufs[queue->next_buf_to_fill];
  3617. /* we did a step forward, so check buffer state
  3618. * again */
  3619. if (atomic_read(&buffer->state) !=
  3620. QETH_QDIO_BUF_EMPTY) {
  3621. qeth_flush_buffers(queue, start_index,
  3622. flush_count);
  3623. atomic_set(&queue->state,
  3624. QETH_OUT_Q_UNLOCKED);
  3625. return -EBUSY;
  3626. }
  3627. }
  3628. }
  3629. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  3630. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  3631. QDIO_MAX_BUFFERS_PER_Q;
  3632. flush_count += tmp;
  3633. if (flush_count)
  3634. qeth_flush_buffers(queue, start_index, flush_count);
  3635. else if (!atomic_read(&queue->set_pci_flags_count))
  3636. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  3637. /*
  3638. * queue->state will go from LOCKED -> UNLOCKED or from
  3639. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  3640. * (switch packing state or flush buffer to get another pci flag out).
  3641. * In that case we will enter this loop
  3642. */
  3643. while (atomic_dec_return(&queue->state)) {
  3644. flush_count = 0;
  3645. start_index = queue->next_buf_to_fill;
  3646. /* check if we can go back to non-packing state */
  3647. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  3648. /*
  3649. * check if we need to flush a packing buffer to get a pci
  3650. * flag out on the queue
  3651. */
  3652. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  3653. flush_count += qeth_flush_buffers_on_no_pci(queue);
  3654. if (flush_count)
  3655. qeth_flush_buffers(queue, start_index, flush_count);
  3656. }
  3657. /* at this point the queue is UNLOCKED again */
  3658. if (queue->card->options.performance_stats && do_pack)
  3659. queue->card->perf_stats.bufs_sent_pack += flush_count;
  3660. return rc;
  3661. }
  3662. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  3663. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  3664. struct qeth_reply *reply, unsigned long data)
  3665. {
  3666. struct qeth_ipa_cmd *cmd;
  3667. struct qeth_ipacmd_setadpparms *setparms;
  3668. QETH_CARD_TEXT(card, 4, "prmadpcb");
  3669. cmd = (struct qeth_ipa_cmd *) data;
  3670. setparms = &(cmd->data.setadapterparms);
  3671. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  3672. if (cmd->hdr.return_code) {
  3673. QETH_CARD_TEXT_(card, 4, "prmrc%2.2x", cmd->hdr.return_code);
  3674. setparms->data.mode = SET_PROMISC_MODE_OFF;
  3675. }
  3676. card->info.promisc_mode = setparms->data.mode;
  3677. return 0;
  3678. }
  3679. void qeth_setadp_promisc_mode(struct qeth_card *card)
  3680. {
  3681. enum qeth_ipa_promisc_modes mode;
  3682. struct net_device *dev = card->dev;
  3683. struct qeth_cmd_buffer *iob;
  3684. struct qeth_ipa_cmd *cmd;
  3685. QETH_CARD_TEXT(card, 4, "setprom");
  3686. if (((dev->flags & IFF_PROMISC) &&
  3687. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  3688. (!(dev->flags & IFF_PROMISC) &&
  3689. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  3690. return;
  3691. mode = SET_PROMISC_MODE_OFF;
  3692. if (dev->flags & IFF_PROMISC)
  3693. mode = SET_PROMISC_MODE_ON;
  3694. QETH_CARD_TEXT_(card, 4, "mode:%x", mode);
  3695. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  3696. sizeof(struct qeth_ipacmd_setadpparms));
  3697. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  3698. cmd->data.setadapterparms.data.mode = mode;
  3699. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  3700. }
  3701. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  3702. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  3703. {
  3704. struct qeth_card *card;
  3705. char dbf_text[15];
  3706. card = dev->ml_priv;
  3707. QETH_CARD_TEXT(card, 4, "chgmtu");
  3708. sprintf(dbf_text, "%8x", new_mtu);
  3709. QETH_CARD_TEXT(card, 4, dbf_text);
  3710. if (new_mtu < 64)
  3711. return -EINVAL;
  3712. if (new_mtu > 65535)
  3713. return -EINVAL;
  3714. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  3715. (!qeth_mtu_is_valid(card, new_mtu)))
  3716. return -EINVAL;
  3717. dev->mtu = new_mtu;
  3718. return 0;
  3719. }
  3720. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  3721. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  3722. {
  3723. struct qeth_card *card;
  3724. card = dev->ml_priv;
  3725. QETH_CARD_TEXT(card, 5, "getstat");
  3726. return &card->stats;
  3727. }
  3728. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3729. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3730. struct qeth_reply *reply, unsigned long data)
  3731. {
  3732. struct qeth_ipa_cmd *cmd;
  3733. QETH_CARD_TEXT(card, 4, "chgmaccb");
  3734. cmd = (struct qeth_ipa_cmd *) data;
  3735. if (!card->options.layer2 ||
  3736. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3737. memcpy(card->dev->dev_addr,
  3738. &cmd->data.setadapterparms.data.change_addr.addr,
  3739. OSA_ADDR_LEN);
  3740. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3741. }
  3742. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3743. return 0;
  3744. }
  3745. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3746. {
  3747. int rc;
  3748. struct qeth_cmd_buffer *iob;
  3749. struct qeth_ipa_cmd *cmd;
  3750. QETH_CARD_TEXT(card, 4, "chgmac");
  3751. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3752. sizeof(struct qeth_ipacmd_setadpparms));
  3753. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3754. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3755. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3756. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3757. card->dev->dev_addr, OSA_ADDR_LEN);
  3758. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3759. NULL);
  3760. return rc;
  3761. }
  3762. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3763. static int qeth_setadpparms_set_access_ctrl_cb(struct qeth_card *card,
  3764. struct qeth_reply *reply, unsigned long data)
  3765. {
  3766. struct qeth_ipa_cmd *cmd;
  3767. struct qeth_set_access_ctrl *access_ctrl_req;
  3768. int fallback = *(int *)reply->param;
  3769. QETH_CARD_TEXT(card, 4, "setaccb");
  3770. cmd = (struct qeth_ipa_cmd *) data;
  3771. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3772. QETH_DBF_TEXT_(SETUP, 2, "setaccb");
  3773. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3774. QETH_DBF_TEXT_(SETUP, 2, "rc=%d",
  3775. cmd->data.setadapterparms.hdr.return_code);
  3776. if (cmd->data.setadapterparms.hdr.return_code !=
  3777. SET_ACCESS_CTRL_RC_SUCCESS)
  3778. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_CTRL(%s,%d)==%d\n",
  3779. card->gdev->dev.kobj.name,
  3780. access_ctrl_req->subcmd_code,
  3781. cmd->data.setadapterparms.hdr.return_code);
  3782. switch (cmd->data.setadapterparms.hdr.return_code) {
  3783. case SET_ACCESS_CTRL_RC_SUCCESS:
  3784. if (card->options.isolation == ISOLATION_MODE_NONE) {
  3785. dev_info(&card->gdev->dev,
  3786. "QDIO data connection isolation is deactivated\n");
  3787. } else {
  3788. dev_info(&card->gdev->dev,
  3789. "QDIO data connection isolation is activated\n");
  3790. }
  3791. break;
  3792. case SET_ACCESS_CTRL_RC_ALREADY_NOT_ISOLATED:
  3793. QETH_DBF_MESSAGE(2, "%s QDIO data connection isolation already "
  3794. "deactivated\n", dev_name(&card->gdev->dev));
  3795. if (fallback)
  3796. card->options.isolation = card->options.prev_isolation;
  3797. break;
  3798. case SET_ACCESS_CTRL_RC_ALREADY_ISOLATED:
  3799. QETH_DBF_MESSAGE(2, "%s QDIO data connection isolation already"
  3800. " activated\n", dev_name(&card->gdev->dev));
  3801. if (fallback)
  3802. card->options.isolation = card->options.prev_isolation;
  3803. break;
  3804. case SET_ACCESS_CTRL_RC_NOT_SUPPORTED:
  3805. dev_err(&card->gdev->dev, "Adapter does not "
  3806. "support QDIO data connection isolation\n");
  3807. break;
  3808. case SET_ACCESS_CTRL_RC_NONE_SHARED_ADAPTER:
  3809. dev_err(&card->gdev->dev,
  3810. "Adapter is dedicated. "
  3811. "QDIO data connection isolation not supported\n");
  3812. if (fallback)
  3813. card->options.isolation = card->options.prev_isolation;
  3814. break;
  3815. case SET_ACCESS_CTRL_RC_ACTIVE_CHECKSUM_OFF:
  3816. dev_err(&card->gdev->dev,
  3817. "TSO does not permit QDIO data connection isolation\n");
  3818. if (fallback)
  3819. card->options.isolation = card->options.prev_isolation;
  3820. break;
  3821. case SET_ACCESS_CTRL_RC_REFLREL_UNSUPPORTED:
  3822. dev_err(&card->gdev->dev, "The adjacent switch port does not "
  3823. "support reflective relay mode\n");
  3824. if (fallback)
  3825. card->options.isolation = card->options.prev_isolation;
  3826. break;
  3827. case SET_ACCESS_CTRL_RC_REFLREL_FAILED:
  3828. dev_err(&card->gdev->dev, "The reflective relay mode cannot be "
  3829. "enabled at the adjacent switch port");
  3830. if (fallback)
  3831. card->options.isolation = card->options.prev_isolation;
  3832. break;
  3833. case SET_ACCESS_CTRL_RC_REFLREL_DEACT_FAILED:
  3834. dev_warn(&card->gdev->dev, "Turning off reflective relay mode "
  3835. "at the adjacent switch failed\n");
  3836. break;
  3837. default:
  3838. /* this should never happen */
  3839. if (fallback)
  3840. card->options.isolation = card->options.prev_isolation;
  3841. break;
  3842. }
  3843. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3844. return 0;
  3845. }
  3846. static int qeth_setadpparms_set_access_ctrl(struct qeth_card *card,
  3847. enum qeth_ipa_isolation_modes isolation, int fallback)
  3848. {
  3849. int rc;
  3850. struct qeth_cmd_buffer *iob;
  3851. struct qeth_ipa_cmd *cmd;
  3852. struct qeth_set_access_ctrl *access_ctrl_req;
  3853. QETH_CARD_TEXT(card, 4, "setacctl");
  3854. QETH_DBF_TEXT_(SETUP, 2, "setacctl");
  3855. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3856. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_ACCESS_CONTROL,
  3857. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  3858. sizeof(struct qeth_set_access_ctrl));
  3859. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3860. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3861. access_ctrl_req->subcmd_code = isolation;
  3862. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_set_access_ctrl_cb,
  3863. &fallback);
  3864. QETH_DBF_TEXT_(SETUP, 2, "rc=%d", rc);
  3865. return rc;
  3866. }
  3867. int qeth_set_access_ctrl_online(struct qeth_card *card, int fallback)
  3868. {
  3869. int rc = 0;
  3870. QETH_CARD_TEXT(card, 4, "setactlo");
  3871. if ((card->info.type == QETH_CARD_TYPE_OSD ||
  3872. card->info.type == QETH_CARD_TYPE_OSX) &&
  3873. qeth_adp_supported(card, IPA_SETADP_SET_ACCESS_CONTROL)) {
  3874. rc = qeth_setadpparms_set_access_ctrl(card,
  3875. card->options.isolation, fallback);
  3876. if (rc) {
  3877. QETH_DBF_MESSAGE(3,
  3878. "IPA(SET_ACCESS_CTRL,%s,%d) sent failed\n",
  3879. card->gdev->dev.kobj.name,
  3880. rc);
  3881. rc = -EOPNOTSUPP;
  3882. }
  3883. } else if (card->options.isolation != ISOLATION_MODE_NONE) {
  3884. card->options.isolation = ISOLATION_MODE_NONE;
  3885. dev_err(&card->gdev->dev, "Adapter does not "
  3886. "support QDIO data connection isolation\n");
  3887. rc = -EOPNOTSUPP;
  3888. }
  3889. return rc;
  3890. }
  3891. EXPORT_SYMBOL_GPL(qeth_set_access_ctrl_online);
  3892. void qeth_tx_timeout(struct net_device *dev)
  3893. {
  3894. struct qeth_card *card;
  3895. card = dev->ml_priv;
  3896. QETH_CARD_TEXT(card, 4, "txtimeo");
  3897. card->stats.tx_errors++;
  3898. qeth_schedule_recovery(card);
  3899. }
  3900. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3901. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3902. {
  3903. struct qeth_card *card = dev->ml_priv;
  3904. int rc = 0;
  3905. switch (regnum) {
  3906. case MII_BMCR: /* Basic mode control register */
  3907. rc = BMCR_FULLDPLX;
  3908. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3909. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3910. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3911. rc |= BMCR_SPEED100;
  3912. break;
  3913. case MII_BMSR: /* Basic mode status register */
  3914. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3915. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3916. BMSR_100BASE4;
  3917. break;
  3918. case MII_PHYSID1: /* PHYS ID 1 */
  3919. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3920. dev->dev_addr[2];
  3921. rc = (rc >> 5) & 0xFFFF;
  3922. break;
  3923. case MII_PHYSID2: /* PHYS ID 2 */
  3924. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3925. break;
  3926. case MII_ADVERTISE: /* Advertisement control reg */
  3927. rc = ADVERTISE_ALL;
  3928. break;
  3929. case MII_LPA: /* Link partner ability reg */
  3930. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3931. LPA_100BASE4 | LPA_LPACK;
  3932. break;
  3933. case MII_EXPANSION: /* Expansion register */
  3934. break;
  3935. case MII_DCOUNTER: /* disconnect counter */
  3936. break;
  3937. case MII_FCSCOUNTER: /* false carrier counter */
  3938. break;
  3939. case MII_NWAYTEST: /* N-way auto-neg test register */
  3940. break;
  3941. case MII_RERRCOUNTER: /* rx error counter */
  3942. rc = card->stats.rx_errors;
  3943. break;
  3944. case MII_SREVISION: /* silicon revision */
  3945. break;
  3946. case MII_RESV1: /* reserved 1 */
  3947. break;
  3948. case MII_LBRERROR: /* loopback, rx, bypass error */
  3949. break;
  3950. case MII_PHYADDR: /* physical address */
  3951. break;
  3952. case MII_RESV2: /* reserved 2 */
  3953. break;
  3954. case MII_TPISTATUS: /* TPI status for 10mbps */
  3955. break;
  3956. case MII_NCONFIG: /* network interface config */
  3957. break;
  3958. default:
  3959. break;
  3960. }
  3961. return rc;
  3962. }
  3963. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3964. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3965. struct qeth_cmd_buffer *iob, int len,
  3966. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3967. unsigned long),
  3968. void *reply_param)
  3969. {
  3970. u16 s1, s2;
  3971. QETH_CARD_TEXT(card, 4, "sendsnmp");
  3972. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3973. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3974. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3975. /* adjust PDU length fields in IPA_PDU_HEADER */
  3976. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3977. s2 = (u32) len;
  3978. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3979. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3980. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3981. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3982. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3983. reply_cb, reply_param);
  3984. }
  3985. static int qeth_snmp_command_cb(struct qeth_card *card,
  3986. struct qeth_reply *reply, unsigned long sdata)
  3987. {
  3988. struct qeth_ipa_cmd *cmd;
  3989. struct qeth_arp_query_info *qinfo;
  3990. struct qeth_snmp_cmd *snmp;
  3991. unsigned char *data;
  3992. __u16 data_len;
  3993. QETH_CARD_TEXT(card, 3, "snpcmdcb");
  3994. cmd = (struct qeth_ipa_cmd *) sdata;
  3995. data = (unsigned char *)((char *)cmd - reply->offset);
  3996. qinfo = (struct qeth_arp_query_info *) reply->param;
  3997. snmp = &cmd->data.setadapterparms.data.snmp;
  3998. if (cmd->hdr.return_code) {
  3999. QETH_CARD_TEXT_(card, 4, "scer1%i", cmd->hdr.return_code);
  4000. return 0;
  4001. }
  4002. if (cmd->data.setadapterparms.hdr.return_code) {
  4003. cmd->hdr.return_code =
  4004. cmd->data.setadapterparms.hdr.return_code;
  4005. QETH_CARD_TEXT_(card, 4, "scer2%i", cmd->hdr.return_code);
  4006. return 0;
  4007. }
  4008. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  4009. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  4010. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  4011. else
  4012. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  4013. /* check if there is enough room in userspace */
  4014. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  4015. QETH_CARD_TEXT_(card, 4, "scer3%i", -ENOMEM);
  4016. cmd->hdr.return_code = IPA_RC_ENOMEM;
  4017. return 0;
  4018. }
  4019. QETH_CARD_TEXT_(card, 4, "snore%i",
  4020. cmd->data.setadapterparms.hdr.used_total);
  4021. QETH_CARD_TEXT_(card, 4, "sseqn%i",
  4022. cmd->data.setadapterparms.hdr.seq_no);
  4023. /*copy entries to user buffer*/
  4024. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  4025. memcpy(qinfo->udata + qinfo->udata_offset,
  4026. (char *)snmp,
  4027. data_len + offsetof(struct qeth_snmp_cmd, data));
  4028. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  4029. } else {
  4030. memcpy(qinfo->udata + qinfo->udata_offset,
  4031. (char *)&snmp->request, data_len);
  4032. }
  4033. qinfo->udata_offset += data_len;
  4034. /* check if all replies received ... */
  4035. QETH_CARD_TEXT_(card, 4, "srtot%i",
  4036. cmd->data.setadapterparms.hdr.used_total);
  4037. QETH_CARD_TEXT_(card, 4, "srseq%i",
  4038. cmd->data.setadapterparms.hdr.seq_no);
  4039. if (cmd->data.setadapterparms.hdr.seq_no <
  4040. cmd->data.setadapterparms.hdr.used_total)
  4041. return 1;
  4042. return 0;
  4043. }
  4044. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  4045. {
  4046. struct qeth_cmd_buffer *iob;
  4047. struct qeth_ipa_cmd *cmd;
  4048. struct qeth_snmp_ureq *ureq;
  4049. unsigned int req_len;
  4050. struct qeth_arp_query_info qinfo = {0, };
  4051. int rc = 0;
  4052. QETH_CARD_TEXT(card, 3, "snmpcmd");
  4053. if (card->info.guestlan)
  4054. return -EOPNOTSUPP;
  4055. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  4056. (!card->options.layer2)) {
  4057. return -EOPNOTSUPP;
  4058. }
  4059. /* skip 4 bytes (data_len struct member) to get req_len */
  4060. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  4061. return -EFAULT;
  4062. if (req_len > (QETH_BUFSIZE - IPA_PDU_HEADER_SIZE -
  4063. sizeof(struct qeth_ipacmd_hdr) -
  4064. sizeof(struct qeth_ipacmd_setadpparms_hdr)))
  4065. return -EINVAL;
  4066. ureq = memdup_user(udata, req_len + sizeof(struct qeth_snmp_ureq_hdr));
  4067. if (IS_ERR(ureq)) {
  4068. QETH_CARD_TEXT(card, 2, "snmpnome");
  4069. return PTR_ERR(ureq);
  4070. }
  4071. qinfo.udata_len = ureq->hdr.data_len;
  4072. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  4073. if (!qinfo.udata) {
  4074. kfree(ureq);
  4075. return -ENOMEM;
  4076. }
  4077. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  4078. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  4079. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  4080. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  4081. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  4082. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  4083. qeth_snmp_command_cb, (void *)&qinfo);
  4084. if (rc)
  4085. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  4086. QETH_CARD_IFNAME(card), rc);
  4087. else {
  4088. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  4089. rc = -EFAULT;
  4090. }
  4091. kfree(ureq);
  4092. kfree(qinfo.udata);
  4093. return rc;
  4094. }
  4095. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  4096. static int qeth_setadpparms_query_oat_cb(struct qeth_card *card,
  4097. struct qeth_reply *reply, unsigned long data)
  4098. {
  4099. struct qeth_ipa_cmd *cmd;
  4100. struct qeth_qoat_priv *priv;
  4101. char *resdata;
  4102. int resdatalen;
  4103. QETH_CARD_TEXT(card, 3, "qoatcb");
  4104. cmd = (struct qeth_ipa_cmd *)data;
  4105. priv = (struct qeth_qoat_priv *)reply->param;
  4106. resdatalen = cmd->data.setadapterparms.hdr.cmdlength;
  4107. resdata = (char *)data + 28;
  4108. if (resdatalen > (priv->buffer_len - priv->response_len)) {
  4109. cmd->hdr.return_code = IPA_RC_FFFF;
  4110. return 0;
  4111. }
  4112. memcpy((priv->buffer + priv->response_len), resdata,
  4113. resdatalen);
  4114. priv->response_len += resdatalen;
  4115. if (cmd->data.setadapterparms.hdr.seq_no <
  4116. cmd->data.setadapterparms.hdr.used_total)
  4117. return 1;
  4118. return 0;
  4119. }
  4120. int qeth_query_oat_command(struct qeth_card *card, char __user *udata)
  4121. {
  4122. int rc = 0;
  4123. struct qeth_cmd_buffer *iob;
  4124. struct qeth_ipa_cmd *cmd;
  4125. struct qeth_query_oat *oat_req;
  4126. struct qeth_query_oat_data oat_data;
  4127. struct qeth_qoat_priv priv;
  4128. void __user *tmp;
  4129. QETH_CARD_TEXT(card, 3, "qoatcmd");
  4130. if (!qeth_adp_supported(card, IPA_SETADP_QUERY_OAT)) {
  4131. rc = -EOPNOTSUPP;
  4132. goto out;
  4133. }
  4134. if (copy_from_user(&oat_data, udata,
  4135. sizeof(struct qeth_query_oat_data))) {
  4136. rc = -EFAULT;
  4137. goto out;
  4138. }
  4139. priv.buffer_len = oat_data.buffer_len;
  4140. priv.response_len = 0;
  4141. priv.buffer = kzalloc(oat_data.buffer_len, GFP_KERNEL);
  4142. if (!priv.buffer) {
  4143. rc = -ENOMEM;
  4144. goto out;
  4145. }
  4146. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_OAT,
  4147. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  4148. sizeof(struct qeth_query_oat));
  4149. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  4150. oat_req = &cmd->data.setadapterparms.data.query_oat;
  4151. oat_req->subcmd_code = oat_data.command;
  4152. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_query_oat_cb,
  4153. &priv);
  4154. if (!rc) {
  4155. if (is_compat_task())
  4156. tmp = compat_ptr(oat_data.ptr);
  4157. else
  4158. tmp = (void __user *)(unsigned long)oat_data.ptr;
  4159. if (copy_to_user(tmp, priv.buffer,
  4160. priv.response_len)) {
  4161. rc = -EFAULT;
  4162. goto out_free;
  4163. }
  4164. oat_data.response_len = priv.response_len;
  4165. if (copy_to_user(udata, &oat_data,
  4166. sizeof(struct qeth_query_oat_data)))
  4167. rc = -EFAULT;
  4168. } else
  4169. if (rc == IPA_RC_FFFF)
  4170. rc = -EFAULT;
  4171. out_free:
  4172. kfree(priv.buffer);
  4173. out:
  4174. return rc;
  4175. }
  4176. EXPORT_SYMBOL_GPL(qeth_query_oat_command);
  4177. static int qeth_query_card_info_cb(struct qeth_card *card,
  4178. struct qeth_reply *reply, unsigned long data)
  4179. {
  4180. struct qeth_ipa_cmd *cmd;
  4181. struct qeth_query_card_info *card_info;
  4182. struct carrier_info *carrier_info;
  4183. QETH_CARD_TEXT(card, 2, "qcrdincb");
  4184. carrier_info = (struct carrier_info *)reply->param;
  4185. cmd = (struct qeth_ipa_cmd *)data;
  4186. card_info = &cmd->data.setadapterparms.data.card_info;
  4187. if (cmd->data.setadapterparms.hdr.return_code == 0) {
  4188. carrier_info->card_type = card_info->card_type;
  4189. carrier_info->port_mode = card_info->port_mode;
  4190. carrier_info->port_speed = card_info->port_speed;
  4191. }
  4192. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  4193. return 0;
  4194. }
  4195. int qeth_query_card_info(struct qeth_card *card,
  4196. struct carrier_info *carrier_info)
  4197. {
  4198. struct qeth_cmd_buffer *iob;
  4199. QETH_CARD_TEXT(card, 2, "qcrdinfo");
  4200. if (!qeth_adp_supported(card, IPA_SETADP_QUERY_CARD_INFO))
  4201. return -EOPNOTSUPP;
  4202. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_CARD_INFO,
  4203. sizeof(struct qeth_ipacmd_setadpparms_hdr));
  4204. return qeth_send_ipa_cmd(card, iob, qeth_query_card_info_cb,
  4205. (void *)carrier_info);
  4206. }
  4207. EXPORT_SYMBOL_GPL(qeth_query_card_info);
  4208. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  4209. {
  4210. switch (card->info.type) {
  4211. case QETH_CARD_TYPE_IQD:
  4212. return 2;
  4213. default:
  4214. return 0;
  4215. }
  4216. }
  4217. static void qeth_determine_capabilities(struct qeth_card *card)
  4218. {
  4219. int rc;
  4220. int length;
  4221. char *prcd;
  4222. struct ccw_device *ddev;
  4223. int ddev_offline = 0;
  4224. QETH_DBF_TEXT(SETUP, 2, "detcapab");
  4225. ddev = CARD_DDEV(card);
  4226. if (!ddev->online) {
  4227. ddev_offline = 1;
  4228. rc = ccw_device_set_online(ddev);
  4229. if (rc) {
  4230. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  4231. goto out;
  4232. }
  4233. }
  4234. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  4235. if (rc) {
  4236. QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
  4237. dev_name(&card->gdev->dev), rc);
  4238. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  4239. goto out_offline;
  4240. }
  4241. qeth_configure_unitaddr(card, prcd);
  4242. if (ddev_offline)
  4243. qeth_configure_blkt_default(card, prcd);
  4244. kfree(prcd);
  4245. rc = qdio_get_ssqd_desc(ddev, &card->ssqd);
  4246. if (rc)
  4247. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  4248. QETH_DBF_TEXT_(SETUP, 2, "qfmt%d", card->ssqd.qfmt);
  4249. QETH_DBF_TEXT_(SETUP, 2, "%d", card->ssqd.qdioac1);
  4250. QETH_DBF_TEXT_(SETUP, 2, "%d", card->ssqd.qdioac3);
  4251. QETH_DBF_TEXT_(SETUP, 2, "icnt%d", card->ssqd.icnt);
  4252. if (!((card->ssqd.qfmt != QDIO_IQDIO_QFMT) ||
  4253. ((card->ssqd.qdioac1 & CHSC_AC1_INITIATE_INPUTQ) == 0) ||
  4254. ((card->ssqd.qdioac3 & CHSC_AC3_FORMAT2_CQ_AVAILABLE) == 0))) {
  4255. dev_info(&card->gdev->dev,
  4256. "Completion Queueing supported\n");
  4257. } else {
  4258. card->options.cq = QETH_CQ_NOTAVAILABLE;
  4259. }
  4260. out_offline:
  4261. if (ddev_offline == 1)
  4262. ccw_device_set_offline(ddev);
  4263. out:
  4264. return;
  4265. }
  4266. static inline void qeth_qdio_establish_cq(struct qeth_card *card,
  4267. struct qdio_buffer **in_sbal_ptrs,
  4268. void (**queue_start_poll) (struct ccw_device *, int, unsigned long)) {
  4269. int i;
  4270. if (card->options.cq == QETH_CQ_ENABLED) {
  4271. int offset = QDIO_MAX_BUFFERS_PER_Q *
  4272. (card->qdio.no_in_queues - 1);
  4273. i = QDIO_MAX_BUFFERS_PER_Q * (card->qdio.no_in_queues - 1);
  4274. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  4275. in_sbal_ptrs[offset + i] = (struct qdio_buffer *)
  4276. virt_to_phys(card->qdio.c_q->bufs[i].buffer);
  4277. }
  4278. queue_start_poll[card->qdio.no_in_queues - 1] = NULL;
  4279. }
  4280. }
  4281. static int qeth_qdio_establish(struct qeth_card *card)
  4282. {
  4283. struct qdio_initialize init_data;
  4284. char *qib_param_field;
  4285. struct qdio_buffer **in_sbal_ptrs;
  4286. void (**queue_start_poll) (struct ccw_device *, int, unsigned long);
  4287. struct qdio_buffer **out_sbal_ptrs;
  4288. int i, j, k;
  4289. int rc = 0;
  4290. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  4291. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  4292. GFP_KERNEL);
  4293. if (!qib_param_field) {
  4294. rc = -ENOMEM;
  4295. goto out_free_nothing;
  4296. }
  4297. qeth_create_qib_param_field(card, qib_param_field);
  4298. qeth_create_qib_param_field_blkt(card, qib_param_field);
  4299. in_sbal_ptrs = kzalloc(card->qdio.no_in_queues *
  4300. QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  4301. GFP_KERNEL);
  4302. if (!in_sbal_ptrs) {
  4303. rc = -ENOMEM;
  4304. goto out_free_qib_param;
  4305. }
  4306. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  4307. in_sbal_ptrs[i] = (struct qdio_buffer *)
  4308. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  4309. }
  4310. queue_start_poll = kzalloc(sizeof(void *) * card->qdio.no_in_queues,
  4311. GFP_KERNEL);
  4312. if (!queue_start_poll) {
  4313. rc = -ENOMEM;
  4314. goto out_free_in_sbals;
  4315. }
  4316. for (i = 0; i < card->qdio.no_in_queues; ++i)
  4317. queue_start_poll[i] = card->discipline->start_poll;
  4318. qeth_qdio_establish_cq(card, in_sbal_ptrs, queue_start_poll);
  4319. out_sbal_ptrs =
  4320. kzalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  4321. sizeof(void *), GFP_KERNEL);
  4322. if (!out_sbal_ptrs) {
  4323. rc = -ENOMEM;
  4324. goto out_free_queue_start_poll;
  4325. }
  4326. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  4327. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  4328. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  4329. card->qdio.out_qs[i]->bufs[j]->buffer);
  4330. }
  4331. memset(&init_data, 0, sizeof(struct qdio_initialize));
  4332. init_data.cdev = CARD_DDEV(card);
  4333. init_data.q_format = qeth_get_qdio_q_format(card);
  4334. init_data.qib_param_field_format = 0;
  4335. init_data.qib_param_field = qib_param_field;
  4336. init_data.no_input_qs = card->qdio.no_in_queues;
  4337. init_data.no_output_qs = card->qdio.no_out_queues;
  4338. init_data.input_handler = card->discipline->input_handler;
  4339. init_data.output_handler = card->discipline->output_handler;
  4340. init_data.queue_start_poll_array = queue_start_poll;
  4341. init_data.int_parm = (unsigned long) card;
  4342. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  4343. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  4344. init_data.output_sbal_state_array = card->qdio.out_bufstates;
  4345. init_data.scan_threshold =
  4346. (card->info.type == QETH_CARD_TYPE_IQD) ? 1 : 32;
  4347. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  4348. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  4349. rc = qdio_allocate(&init_data);
  4350. if (rc) {
  4351. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  4352. goto out;
  4353. }
  4354. rc = qdio_establish(&init_data);
  4355. if (rc) {
  4356. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  4357. qdio_free(CARD_DDEV(card));
  4358. }
  4359. }
  4360. switch (card->options.cq) {
  4361. case QETH_CQ_ENABLED:
  4362. dev_info(&card->gdev->dev, "Completion Queue support enabled");
  4363. break;
  4364. case QETH_CQ_DISABLED:
  4365. dev_info(&card->gdev->dev, "Completion Queue support disabled");
  4366. break;
  4367. default:
  4368. break;
  4369. }
  4370. out:
  4371. kfree(out_sbal_ptrs);
  4372. out_free_queue_start_poll:
  4373. kfree(queue_start_poll);
  4374. out_free_in_sbals:
  4375. kfree(in_sbal_ptrs);
  4376. out_free_qib_param:
  4377. kfree(qib_param_field);
  4378. out_free_nothing:
  4379. return rc;
  4380. }
  4381. static void qeth_core_free_card(struct qeth_card *card)
  4382. {
  4383. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  4384. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  4385. qeth_clean_channel(&card->read);
  4386. qeth_clean_channel(&card->write);
  4387. if (card->dev)
  4388. free_netdev(card->dev);
  4389. kfree(card->ip_tbd_list);
  4390. qeth_free_qdio_buffers(card);
  4391. unregister_service_level(&card->qeth_service_level);
  4392. kfree(card);
  4393. }
  4394. void qeth_trace_features(struct qeth_card *card)
  4395. {
  4396. QETH_CARD_TEXT(card, 2, "features");
  4397. QETH_CARD_TEXT_(card, 2, "%x", card->options.ipa4.supported_funcs);
  4398. QETH_CARD_TEXT_(card, 2, "%x", card->options.ipa4.enabled_funcs);
  4399. QETH_CARD_TEXT_(card, 2, "%x", card->options.ipa6.supported_funcs);
  4400. QETH_CARD_TEXT_(card, 2, "%x", card->options.ipa6.enabled_funcs);
  4401. QETH_CARD_TEXT_(card, 2, "%x", card->options.adp.supported_funcs);
  4402. QETH_CARD_TEXT_(card, 2, "%x", card->options.adp.enabled_funcs);
  4403. QETH_CARD_TEXT_(card, 2, "%x", card->info.diagass_support);
  4404. }
  4405. EXPORT_SYMBOL_GPL(qeth_trace_features);
  4406. static struct ccw_device_id qeth_ids[] = {
  4407. {CCW_DEVICE_DEVTYPE(0x1731, 0x01, 0x1732, 0x01),
  4408. .driver_info = QETH_CARD_TYPE_OSD},
  4409. {CCW_DEVICE_DEVTYPE(0x1731, 0x05, 0x1732, 0x05),
  4410. .driver_info = QETH_CARD_TYPE_IQD},
  4411. {CCW_DEVICE_DEVTYPE(0x1731, 0x06, 0x1732, 0x06),
  4412. .driver_info = QETH_CARD_TYPE_OSN},
  4413. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x03),
  4414. .driver_info = QETH_CARD_TYPE_OSM},
  4415. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x02),
  4416. .driver_info = QETH_CARD_TYPE_OSX},
  4417. {},
  4418. };
  4419. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  4420. static struct ccw_driver qeth_ccw_driver = {
  4421. .driver = {
  4422. .owner = THIS_MODULE,
  4423. .name = "qeth",
  4424. },
  4425. .ids = qeth_ids,
  4426. .probe = ccwgroup_probe_ccwdev,
  4427. .remove = ccwgroup_remove_ccwdev,
  4428. };
  4429. int qeth_core_hardsetup_card(struct qeth_card *card)
  4430. {
  4431. int retries = 3;
  4432. int rc;
  4433. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  4434. atomic_set(&card->force_alloc_skb, 0);
  4435. qeth_update_from_chp_desc(card);
  4436. retry:
  4437. if (retries < 3)
  4438. QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
  4439. dev_name(&card->gdev->dev));
  4440. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  4441. ccw_device_set_offline(CARD_DDEV(card));
  4442. ccw_device_set_offline(CARD_WDEV(card));
  4443. ccw_device_set_offline(CARD_RDEV(card));
  4444. qdio_free(CARD_DDEV(card));
  4445. rc = ccw_device_set_online(CARD_RDEV(card));
  4446. if (rc)
  4447. goto retriable;
  4448. rc = ccw_device_set_online(CARD_WDEV(card));
  4449. if (rc)
  4450. goto retriable;
  4451. rc = ccw_device_set_online(CARD_DDEV(card));
  4452. if (rc)
  4453. goto retriable;
  4454. retriable:
  4455. if (rc == -ERESTARTSYS) {
  4456. QETH_DBF_TEXT(SETUP, 2, "break1");
  4457. return rc;
  4458. } else if (rc) {
  4459. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  4460. if (--retries < 0)
  4461. goto out;
  4462. else
  4463. goto retry;
  4464. }
  4465. qeth_determine_capabilities(card);
  4466. qeth_init_tokens(card);
  4467. qeth_init_func_level(card);
  4468. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  4469. if (rc == -ERESTARTSYS) {
  4470. QETH_DBF_TEXT(SETUP, 2, "break2");
  4471. return rc;
  4472. } else if (rc) {
  4473. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  4474. if (--retries < 0)
  4475. goto out;
  4476. else
  4477. goto retry;
  4478. }
  4479. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  4480. if (rc == -ERESTARTSYS) {
  4481. QETH_DBF_TEXT(SETUP, 2, "break3");
  4482. return rc;
  4483. } else if (rc) {
  4484. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  4485. if (--retries < 0)
  4486. goto out;
  4487. else
  4488. goto retry;
  4489. }
  4490. card->read_or_write_problem = 0;
  4491. rc = qeth_mpc_initialize(card);
  4492. if (rc) {
  4493. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  4494. goto out;
  4495. }
  4496. card->options.ipa4.supported_funcs = 0;
  4497. card->options.adp.supported_funcs = 0;
  4498. card->options.sbp.supported_funcs = 0;
  4499. card->info.diagass_support = 0;
  4500. qeth_query_ipassists(card, QETH_PROT_IPV4);
  4501. if (qeth_is_supported(card, IPA_SETADAPTERPARMS))
  4502. qeth_query_setadapterparms(card);
  4503. if (qeth_adp_supported(card, IPA_SETADP_SET_DIAG_ASSIST))
  4504. qeth_query_setdiagass(card);
  4505. return 0;
  4506. out:
  4507. dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
  4508. "an error on the device\n");
  4509. QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
  4510. dev_name(&card->gdev->dev), rc);
  4511. return rc;
  4512. }
  4513. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  4514. static inline int qeth_create_skb_frag(struct qeth_qdio_buffer *qethbuffer,
  4515. struct qdio_buffer_element *element,
  4516. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  4517. {
  4518. struct page *page = virt_to_page(element->addr);
  4519. if (*pskb == NULL) {
  4520. if (qethbuffer->rx_skb) {
  4521. /* only if qeth_card.options.cq == QETH_CQ_ENABLED */
  4522. *pskb = qethbuffer->rx_skb;
  4523. qethbuffer->rx_skb = NULL;
  4524. } else {
  4525. *pskb = dev_alloc_skb(QETH_RX_PULL_LEN + ETH_HLEN);
  4526. if (!(*pskb))
  4527. return -ENOMEM;
  4528. }
  4529. skb_reserve(*pskb, ETH_HLEN);
  4530. if (data_len <= QETH_RX_PULL_LEN) {
  4531. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  4532. data_len);
  4533. } else {
  4534. get_page(page);
  4535. memcpy(skb_put(*pskb, QETH_RX_PULL_LEN),
  4536. element->addr + offset, QETH_RX_PULL_LEN);
  4537. skb_fill_page_desc(*pskb, *pfrag, page,
  4538. offset + QETH_RX_PULL_LEN,
  4539. data_len - QETH_RX_PULL_LEN);
  4540. (*pskb)->data_len += data_len - QETH_RX_PULL_LEN;
  4541. (*pskb)->len += data_len - QETH_RX_PULL_LEN;
  4542. (*pskb)->truesize += data_len - QETH_RX_PULL_LEN;
  4543. (*pfrag)++;
  4544. }
  4545. } else {
  4546. get_page(page);
  4547. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  4548. (*pskb)->data_len += data_len;
  4549. (*pskb)->len += data_len;
  4550. (*pskb)->truesize += data_len;
  4551. (*pfrag)++;
  4552. }
  4553. return 0;
  4554. }
  4555. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  4556. struct qeth_qdio_buffer *qethbuffer,
  4557. struct qdio_buffer_element **__element, int *__offset,
  4558. struct qeth_hdr **hdr)
  4559. {
  4560. struct qdio_buffer_element *element = *__element;
  4561. struct qdio_buffer *buffer = qethbuffer->buffer;
  4562. int offset = *__offset;
  4563. struct sk_buff *skb = NULL;
  4564. int skb_len = 0;
  4565. void *data_ptr;
  4566. int data_len;
  4567. int headroom = 0;
  4568. int use_rx_sg = 0;
  4569. int frag = 0;
  4570. /* qeth_hdr must not cross element boundaries */
  4571. if (element->length < offset + sizeof(struct qeth_hdr)) {
  4572. if (qeth_is_last_sbale(element))
  4573. return NULL;
  4574. element++;
  4575. offset = 0;
  4576. if (element->length < sizeof(struct qeth_hdr))
  4577. return NULL;
  4578. }
  4579. *hdr = element->addr + offset;
  4580. offset += sizeof(struct qeth_hdr);
  4581. switch ((*hdr)->hdr.l2.id) {
  4582. case QETH_HEADER_TYPE_LAYER2:
  4583. skb_len = (*hdr)->hdr.l2.pkt_length;
  4584. break;
  4585. case QETH_HEADER_TYPE_LAYER3:
  4586. skb_len = (*hdr)->hdr.l3.length;
  4587. headroom = ETH_HLEN;
  4588. break;
  4589. case QETH_HEADER_TYPE_OSN:
  4590. skb_len = (*hdr)->hdr.osn.pdu_length;
  4591. headroom = sizeof(struct qeth_hdr);
  4592. break;
  4593. default:
  4594. break;
  4595. }
  4596. if (!skb_len)
  4597. return NULL;
  4598. if (((skb_len >= card->options.rx_sg_cb) &&
  4599. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  4600. (!atomic_read(&card->force_alloc_skb))) ||
  4601. (card->options.cq == QETH_CQ_ENABLED)) {
  4602. use_rx_sg = 1;
  4603. } else {
  4604. skb = dev_alloc_skb(skb_len + headroom);
  4605. if (!skb)
  4606. goto no_mem;
  4607. if (headroom)
  4608. skb_reserve(skb, headroom);
  4609. }
  4610. data_ptr = element->addr + offset;
  4611. while (skb_len) {
  4612. data_len = min(skb_len, (int)(element->length - offset));
  4613. if (data_len) {
  4614. if (use_rx_sg) {
  4615. if (qeth_create_skb_frag(qethbuffer, element,
  4616. &skb, offset, &frag, data_len))
  4617. goto no_mem;
  4618. } else {
  4619. memcpy(skb_put(skb, data_len), data_ptr,
  4620. data_len);
  4621. }
  4622. }
  4623. skb_len -= data_len;
  4624. if (skb_len) {
  4625. if (qeth_is_last_sbale(element)) {
  4626. QETH_CARD_TEXT(card, 4, "unexeob");
  4627. QETH_CARD_HEX(card, 2, buffer, sizeof(void *));
  4628. dev_kfree_skb_any(skb);
  4629. card->stats.rx_errors++;
  4630. return NULL;
  4631. }
  4632. element++;
  4633. offset = 0;
  4634. data_ptr = element->addr;
  4635. } else {
  4636. offset += data_len;
  4637. }
  4638. }
  4639. *__element = element;
  4640. *__offset = offset;
  4641. if (use_rx_sg && card->options.performance_stats) {
  4642. card->perf_stats.sg_skbs_rx++;
  4643. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  4644. }
  4645. return skb;
  4646. no_mem:
  4647. if (net_ratelimit()) {
  4648. QETH_CARD_TEXT(card, 2, "noskbmem");
  4649. }
  4650. card->stats.rx_dropped++;
  4651. return NULL;
  4652. }
  4653. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  4654. static void qeth_unregister_dbf_views(void)
  4655. {
  4656. int x;
  4657. for (x = 0; x < QETH_DBF_INFOS; x++) {
  4658. debug_unregister(qeth_dbf[x].id);
  4659. qeth_dbf[x].id = NULL;
  4660. }
  4661. }
  4662. void qeth_dbf_longtext(debug_info_t *id, int level, char *fmt, ...)
  4663. {
  4664. char dbf_txt_buf[32];
  4665. va_list args;
  4666. if (!debug_level_enabled(id, level))
  4667. return;
  4668. va_start(args, fmt);
  4669. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  4670. va_end(args);
  4671. debug_text_event(id, level, dbf_txt_buf);
  4672. }
  4673. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  4674. static int qeth_register_dbf_views(void)
  4675. {
  4676. int ret;
  4677. int x;
  4678. for (x = 0; x < QETH_DBF_INFOS; x++) {
  4679. /* register the areas */
  4680. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  4681. qeth_dbf[x].pages,
  4682. qeth_dbf[x].areas,
  4683. qeth_dbf[x].len);
  4684. if (qeth_dbf[x].id == NULL) {
  4685. qeth_unregister_dbf_views();
  4686. return -ENOMEM;
  4687. }
  4688. /* register a view */
  4689. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  4690. if (ret) {
  4691. qeth_unregister_dbf_views();
  4692. return ret;
  4693. }
  4694. /* set a passing level */
  4695. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  4696. }
  4697. return 0;
  4698. }
  4699. int qeth_core_load_discipline(struct qeth_card *card,
  4700. enum qeth_discipline_id discipline)
  4701. {
  4702. int rc = 0;
  4703. mutex_lock(&qeth_mod_mutex);
  4704. switch (discipline) {
  4705. case QETH_DISCIPLINE_LAYER3:
  4706. card->discipline = try_then_request_module(
  4707. symbol_get(qeth_l3_discipline), "qeth_l3");
  4708. break;
  4709. case QETH_DISCIPLINE_LAYER2:
  4710. card->discipline = try_then_request_module(
  4711. symbol_get(qeth_l2_discipline), "qeth_l2");
  4712. break;
  4713. }
  4714. if (!card->discipline) {
  4715. dev_err(&card->gdev->dev, "There is no kernel module to "
  4716. "support discipline %d\n", discipline);
  4717. rc = -EINVAL;
  4718. }
  4719. mutex_unlock(&qeth_mod_mutex);
  4720. return rc;
  4721. }
  4722. void qeth_core_free_discipline(struct qeth_card *card)
  4723. {
  4724. if (card->options.layer2)
  4725. symbol_put(qeth_l2_discipline);
  4726. else
  4727. symbol_put(qeth_l3_discipline);
  4728. card->discipline = NULL;
  4729. }
  4730. static const struct device_type qeth_generic_devtype = {
  4731. .name = "qeth_generic",
  4732. .groups = qeth_generic_attr_groups,
  4733. };
  4734. static const struct device_type qeth_osn_devtype = {
  4735. .name = "qeth_osn",
  4736. .groups = qeth_osn_attr_groups,
  4737. };
  4738. #define DBF_NAME_LEN 20
  4739. struct qeth_dbf_entry {
  4740. char dbf_name[DBF_NAME_LEN];
  4741. debug_info_t *dbf_info;
  4742. struct list_head dbf_list;
  4743. };
  4744. static LIST_HEAD(qeth_dbf_list);
  4745. static DEFINE_MUTEX(qeth_dbf_list_mutex);
  4746. static debug_info_t *qeth_get_dbf_entry(char *name)
  4747. {
  4748. struct qeth_dbf_entry *entry;
  4749. debug_info_t *rc = NULL;
  4750. mutex_lock(&qeth_dbf_list_mutex);
  4751. list_for_each_entry(entry, &qeth_dbf_list, dbf_list) {
  4752. if (strcmp(entry->dbf_name, name) == 0) {
  4753. rc = entry->dbf_info;
  4754. break;
  4755. }
  4756. }
  4757. mutex_unlock(&qeth_dbf_list_mutex);
  4758. return rc;
  4759. }
  4760. static int qeth_add_dbf_entry(struct qeth_card *card, char *name)
  4761. {
  4762. struct qeth_dbf_entry *new_entry;
  4763. card->debug = debug_register(name, 2, 1, 8);
  4764. if (!card->debug) {
  4765. QETH_DBF_TEXT_(SETUP, 2, "%s", "qcdbf");
  4766. goto err;
  4767. }
  4768. if (debug_register_view(card->debug, &debug_hex_ascii_view))
  4769. goto err_dbg;
  4770. new_entry = kzalloc(sizeof(struct qeth_dbf_entry), GFP_KERNEL);
  4771. if (!new_entry)
  4772. goto err_dbg;
  4773. strncpy(new_entry->dbf_name, name, DBF_NAME_LEN);
  4774. new_entry->dbf_info = card->debug;
  4775. mutex_lock(&qeth_dbf_list_mutex);
  4776. list_add(&new_entry->dbf_list, &qeth_dbf_list);
  4777. mutex_unlock(&qeth_dbf_list_mutex);
  4778. return 0;
  4779. err_dbg:
  4780. debug_unregister(card->debug);
  4781. err:
  4782. return -ENOMEM;
  4783. }
  4784. static void qeth_clear_dbf_list(void)
  4785. {
  4786. struct qeth_dbf_entry *entry, *tmp;
  4787. mutex_lock(&qeth_dbf_list_mutex);
  4788. list_for_each_entry_safe(entry, tmp, &qeth_dbf_list, dbf_list) {
  4789. list_del(&entry->dbf_list);
  4790. debug_unregister(entry->dbf_info);
  4791. kfree(entry);
  4792. }
  4793. mutex_unlock(&qeth_dbf_list_mutex);
  4794. }
  4795. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  4796. {
  4797. struct qeth_card *card;
  4798. struct device *dev;
  4799. int rc;
  4800. unsigned long flags;
  4801. char dbf_name[DBF_NAME_LEN];
  4802. QETH_DBF_TEXT(SETUP, 2, "probedev");
  4803. dev = &gdev->dev;
  4804. if (!get_device(dev))
  4805. return -ENODEV;
  4806. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  4807. card = qeth_alloc_card();
  4808. if (!card) {
  4809. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  4810. rc = -ENOMEM;
  4811. goto err_dev;
  4812. }
  4813. snprintf(dbf_name, sizeof(dbf_name), "qeth_card_%s",
  4814. dev_name(&gdev->dev));
  4815. card->debug = qeth_get_dbf_entry(dbf_name);
  4816. if (!card->debug) {
  4817. rc = qeth_add_dbf_entry(card, dbf_name);
  4818. if (rc)
  4819. goto err_card;
  4820. }
  4821. card->read.ccwdev = gdev->cdev[0];
  4822. card->write.ccwdev = gdev->cdev[1];
  4823. card->data.ccwdev = gdev->cdev[2];
  4824. dev_set_drvdata(&gdev->dev, card);
  4825. card->gdev = gdev;
  4826. gdev->cdev[0]->handler = qeth_irq;
  4827. gdev->cdev[1]->handler = qeth_irq;
  4828. gdev->cdev[2]->handler = qeth_irq;
  4829. rc = qeth_determine_card_type(card);
  4830. if (rc) {
  4831. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  4832. goto err_card;
  4833. }
  4834. rc = qeth_setup_card(card);
  4835. if (rc) {
  4836. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  4837. goto err_card;
  4838. }
  4839. if (card->info.type == QETH_CARD_TYPE_OSN)
  4840. gdev->dev.type = &qeth_osn_devtype;
  4841. else
  4842. gdev->dev.type = &qeth_generic_devtype;
  4843. switch (card->info.type) {
  4844. case QETH_CARD_TYPE_OSN:
  4845. case QETH_CARD_TYPE_OSM:
  4846. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  4847. if (rc)
  4848. goto err_card;
  4849. rc = card->discipline->setup(card->gdev);
  4850. if (rc)
  4851. goto err_disc;
  4852. case QETH_CARD_TYPE_OSD:
  4853. case QETH_CARD_TYPE_OSX:
  4854. default:
  4855. break;
  4856. }
  4857. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  4858. list_add_tail(&card->list, &qeth_core_card_list.list);
  4859. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  4860. qeth_determine_capabilities(card);
  4861. return 0;
  4862. err_disc:
  4863. qeth_core_free_discipline(card);
  4864. err_card:
  4865. qeth_core_free_card(card);
  4866. err_dev:
  4867. put_device(dev);
  4868. return rc;
  4869. }
  4870. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  4871. {
  4872. unsigned long flags;
  4873. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4874. QETH_DBF_TEXT(SETUP, 2, "removedv");
  4875. if (card->discipline) {
  4876. card->discipline->remove(gdev);
  4877. qeth_core_free_discipline(card);
  4878. }
  4879. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  4880. list_del(&card->list);
  4881. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  4882. qeth_core_free_card(card);
  4883. dev_set_drvdata(&gdev->dev, NULL);
  4884. put_device(&gdev->dev);
  4885. return;
  4886. }
  4887. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  4888. {
  4889. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4890. int rc = 0;
  4891. int def_discipline;
  4892. if (!card->discipline) {
  4893. if (card->info.type == QETH_CARD_TYPE_IQD)
  4894. def_discipline = QETH_DISCIPLINE_LAYER3;
  4895. else
  4896. def_discipline = QETH_DISCIPLINE_LAYER2;
  4897. rc = qeth_core_load_discipline(card, def_discipline);
  4898. if (rc)
  4899. goto err;
  4900. rc = card->discipline->setup(card->gdev);
  4901. if (rc)
  4902. goto err;
  4903. }
  4904. rc = card->discipline->set_online(gdev);
  4905. err:
  4906. return rc;
  4907. }
  4908. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  4909. {
  4910. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4911. return card->discipline->set_offline(gdev);
  4912. }
  4913. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  4914. {
  4915. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4916. if (card->discipline && card->discipline->shutdown)
  4917. card->discipline->shutdown(gdev);
  4918. }
  4919. static int qeth_core_prepare(struct ccwgroup_device *gdev)
  4920. {
  4921. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4922. if (card->discipline && card->discipline->prepare)
  4923. return card->discipline->prepare(gdev);
  4924. return 0;
  4925. }
  4926. static void qeth_core_complete(struct ccwgroup_device *gdev)
  4927. {
  4928. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4929. if (card->discipline && card->discipline->complete)
  4930. card->discipline->complete(gdev);
  4931. }
  4932. static int qeth_core_freeze(struct ccwgroup_device *gdev)
  4933. {
  4934. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4935. if (card->discipline && card->discipline->freeze)
  4936. return card->discipline->freeze(gdev);
  4937. return 0;
  4938. }
  4939. static int qeth_core_thaw(struct ccwgroup_device *gdev)
  4940. {
  4941. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4942. if (card->discipline && card->discipline->thaw)
  4943. return card->discipline->thaw(gdev);
  4944. return 0;
  4945. }
  4946. static int qeth_core_restore(struct ccwgroup_device *gdev)
  4947. {
  4948. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4949. if (card->discipline && card->discipline->restore)
  4950. return card->discipline->restore(gdev);
  4951. return 0;
  4952. }
  4953. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  4954. .driver = {
  4955. .owner = THIS_MODULE,
  4956. .name = "qeth",
  4957. },
  4958. .setup = qeth_core_probe_device,
  4959. .remove = qeth_core_remove_device,
  4960. .set_online = qeth_core_set_online,
  4961. .set_offline = qeth_core_set_offline,
  4962. .shutdown = qeth_core_shutdown,
  4963. .prepare = qeth_core_prepare,
  4964. .complete = qeth_core_complete,
  4965. .freeze = qeth_core_freeze,
  4966. .thaw = qeth_core_thaw,
  4967. .restore = qeth_core_restore,
  4968. };
  4969. static ssize_t qeth_core_driver_group_store(struct device_driver *ddrv,
  4970. const char *buf, size_t count)
  4971. {
  4972. int err;
  4973. err = ccwgroup_create_dev(qeth_core_root_dev,
  4974. &qeth_core_ccwgroup_driver, 3, buf);
  4975. return err ? err : count;
  4976. }
  4977. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  4978. static struct attribute *qeth_drv_attrs[] = {
  4979. &driver_attr_group.attr,
  4980. NULL,
  4981. };
  4982. static struct attribute_group qeth_drv_attr_group = {
  4983. .attrs = qeth_drv_attrs,
  4984. };
  4985. static const struct attribute_group *qeth_drv_attr_groups[] = {
  4986. &qeth_drv_attr_group,
  4987. NULL,
  4988. };
  4989. static struct {
  4990. const char str[ETH_GSTRING_LEN];
  4991. } qeth_ethtool_stats_keys[] = {
  4992. /* 0 */{"rx skbs"},
  4993. {"rx buffers"},
  4994. {"tx skbs"},
  4995. {"tx buffers"},
  4996. {"tx skbs no packing"},
  4997. {"tx buffers no packing"},
  4998. {"tx skbs packing"},
  4999. {"tx buffers packing"},
  5000. {"tx sg skbs"},
  5001. {"tx sg frags"},
  5002. /* 10 */{"rx sg skbs"},
  5003. {"rx sg frags"},
  5004. {"rx sg page allocs"},
  5005. {"tx large kbytes"},
  5006. {"tx large count"},
  5007. {"tx pk state ch n->p"},
  5008. {"tx pk state ch p->n"},
  5009. {"tx pk watermark low"},
  5010. {"tx pk watermark high"},
  5011. {"queue 0 buffer usage"},
  5012. /* 20 */{"queue 1 buffer usage"},
  5013. {"queue 2 buffer usage"},
  5014. {"queue 3 buffer usage"},
  5015. {"rx poll time"},
  5016. {"rx poll count"},
  5017. {"rx do_QDIO time"},
  5018. {"rx do_QDIO count"},
  5019. {"tx handler time"},
  5020. {"tx handler count"},
  5021. {"tx time"},
  5022. /* 30 */{"tx count"},
  5023. {"tx do_QDIO time"},
  5024. {"tx do_QDIO count"},
  5025. {"tx csum"},
  5026. {"tx lin"},
  5027. {"cq handler count"},
  5028. {"cq handler time"}
  5029. };
  5030. int qeth_core_get_sset_count(struct net_device *dev, int stringset)
  5031. {
  5032. switch (stringset) {
  5033. case ETH_SS_STATS:
  5034. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  5035. default:
  5036. return -EINVAL;
  5037. }
  5038. }
  5039. EXPORT_SYMBOL_GPL(qeth_core_get_sset_count);
  5040. void qeth_core_get_ethtool_stats(struct net_device *dev,
  5041. struct ethtool_stats *stats, u64 *data)
  5042. {
  5043. struct qeth_card *card = dev->ml_priv;
  5044. data[0] = card->stats.rx_packets -
  5045. card->perf_stats.initial_rx_packets;
  5046. data[1] = card->perf_stats.bufs_rec;
  5047. data[2] = card->stats.tx_packets -
  5048. card->perf_stats.initial_tx_packets;
  5049. data[3] = card->perf_stats.bufs_sent;
  5050. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  5051. - card->perf_stats.skbs_sent_pack;
  5052. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  5053. data[6] = card->perf_stats.skbs_sent_pack;
  5054. data[7] = card->perf_stats.bufs_sent_pack;
  5055. data[8] = card->perf_stats.sg_skbs_sent;
  5056. data[9] = card->perf_stats.sg_frags_sent;
  5057. data[10] = card->perf_stats.sg_skbs_rx;
  5058. data[11] = card->perf_stats.sg_frags_rx;
  5059. data[12] = card->perf_stats.sg_alloc_page_rx;
  5060. data[13] = (card->perf_stats.large_send_bytes >> 10);
  5061. data[14] = card->perf_stats.large_send_cnt;
  5062. data[15] = card->perf_stats.sc_dp_p;
  5063. data[16] = card->perf_stats.sc_p_dp;
  5064. data[17] = QETH_LOW_WATERMARK_PACK;
  5065. data[18] = QETH_HIGH_WATERMARK_PACK;
  5066. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  5067. data[20] = (card->qdio.no_out_queues > 1) ?
  5068. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  5069. data[21] = (card->qdio.no_out_queues > 2) ?
  5070. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  5071. data[22] = (card->qdio.no_out_queues > 3) ?
  5072. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  5073. data[23] = card->perf_stats.inbound_time;
  5074. data[24] = card->perf_stats.inbound_cnt;
  5075. data[25] = card->perf_stats.inbound_do_qdio_time;
  5076. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  5077. data[27] = card->perf_stats.outbound_handler_time;
  5078. data[28] = card->perf_stats.outbound_handler_cnt;
  5079. data[29] = card->perf_stats.outbound_time;
  5080. data[30] = card->perf_stats.outbound_cnt;
  5081. data[31] = card->perf_stats.outbound_do_qdio_time;
  5082. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  5083. data[33] = card->perf_stats.tx_csum;
  5084. data[34] = card->perf_stats.tx_lin;
  5085. data[35] = card->perf_stats.cq_cnt;
  5086. data[36] = card->perf_stats.cq_time;
  5087. }
  5088. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  5089. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  5090. {
  5091. switch (stringset) {
  5092. case ETH_SS_STATS:
  5093. memcpy(data, &qeth_ethtool_stats_keys,
  5094. sizeof(qeth_ethtool_stats_keys));
  5095. break;
  5096. default:
  5097. WARN_ON(1);
  5098. break;
  5099. }
  5100. }
  5101. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  5102. void qeth_core_get_drvinfo(struct net_device *dev,
  5103. struct ethtool_drvinfo *info)
  5104. {
  5105. struct qeth_card *card = dev->ml_priv;
  5106. strlcpy(info->driver, card->options.layer2 ? "qeth_l2" : "qeth_l3",
  5107. sizeof(info->driver));
  5108. strlcpy(info->version, "1.0", sizeof(info->version));
  5109. strlcpy(info->fw_version, card->info.mcl_level,
  5110. sizeof(info->fw_version));
  5111. snprintf(info->bus_info, sizeof(info->bus_info), "%s/%s/%s",
  5112. CARD_RDEV_ID(card), CARD_WDEV_ID(card), CARD_DDEV_ID(card));
  5113. }
  5114. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  5115. /* Helper function to fill 'advertizing' and 'supported' which are the same. */
  5116. /* Autoneg and full-duplex are supported and advertized uncondionally. */
  5117. /* Always advertize and support all speeds up to specified, and only one */
  5118. /* specified port type. */
  5119. static void qeth_set_ecmd_adv_sup(struct ethtool_cmd *ecmd,
  5120. int maxspeed, int porttype)
  5121. {
  5122. int port_sup, port_adv, spd_sup, spd_adv;
  5123. switch (porttype) {
  5124. case PORT_TP:
  5125. port_sup = SUPPORTED_TP;
  5126. port_adv = ADVERTISED_TP;
  5127. break;
  5128. case PORT_FIBRE:
  5129. port_sup = SUPPORTED_FIBRE;
  5130. port_adv = ADVERTISED_FIBRE;
  5131. break;
  5132. default:
  5133. port_sup = SUPPORTED_TP;
  5134. port_adv = ADVERTISED_TP;
  5135. WARN_ON_ONCE(1);
  5136. }
  5137. /* "Fallthrough" case'es ordered from high to low result in setting */
  5138. /* flags cumulatively, starting from the specified speed and down to */
  5139. /* the lowest possible. */
  5140. spd_sup = 0;
  5141. spd_adv = 0;
  5142. switch (maxspeed) {
  5143. case SPEED_10000:
  5144. spd_sup |= SUPPORTED_10000baseT_Full;
  5145. spd_adv |= ADVERTISED_10000baseT_Full;
  5146. case SPEED_1000:
  5147. spd_sup |= SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full;
  5148. spd_adv |= ADVERTISED_1000baseT_Half |
  5149. ADVERTISED_1000baseT_Full;
  5150. case SPEED_100:
  5151. spd_sup |= SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full;
  5152. spd_adv |= ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
  5153. case SPEED_10:
  5154. spd_sup |= SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full;
  5155. spd_adv |= ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
  5156. break;
  5157. default:
  5158. spd_sup = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full;
  5159. spd_adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
  5160. WARN_ON_ONCE(1);
  5161. }
  5162. ecmd->advertising = ADVERTISED_Autoneg | port_adv | spd_adv;
  5163. ecmd->supported = SUPPORTED_Autoneg | port_sup | spd_sup;
  5164. }
  5165. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  5166. struct ethtool_cmd *ecmd)
  5167. {
  5168. struct qeth_card *card = netdev->ml_priv;
  5169. enum qeth_link_types link_type;
  5170. struct carrier_info carrier_info;
  5171. u32 speed;
  5172. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  5173. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  5174. else
  5175. link_type = card->info.link_type;
  5176. ecmd->transceiver = XCVR_INTERNAL;
  5177. ecmd->duplex = DUPLEX_FULL;
  5178. ecmd->autoneg = AUTONEG_ENABLE;
  5179. switch (link_type) {
  5180. case QETH_LINK_TYPE_FAST_ETH:
  5181. case QETH_LINK_TYPE_LANE_ETH100:
  5182. qeth_set_ecmd_adv_sup(ecmd, SPEED_100, PORT_TP);
  5183. speed = SPEED_100;
  5184. ecmd->port = PORT_TP;
  5185. break;
  5186. case QETH_LINK_TYPE_GBIT_ETH:
  5187. case QETH_LINK_TYPE_LANE_ETH1000:
  5188. qeth_set_ecmd_adv_sup(ecmd, SPEED_1000, PORT_FIBRE);
  5189. speed = SPEED_1000;
  5190. ecmd->port = PORT_FIBRE;
  5191. break;
  5192. case QETH_LINK_TYPE_10GBIT_ETH:
  5193. qeth_set_ecmd_adv_sup(ecmd, SPEED_10000, PORT_FIBRE);
  5194. speed = SPEED_10000;
  5195. ecmd->port = PORT_FIBRE;
  5196. break;
  5197. default:
  5198. qeth_set_ecmd_adv_sup(ecmd, SPEED_10, PORT_TP);
  5199. speed = SPEED_10;
  5200. ecmd->port = PORT_TP;
  5201. }
  5202. ethtool_cmd_speed_set(ecmd, speed);
  5203. /* Check if we can obtain more accurate information. */
  5204. /* If QUERY_CARD_INFO command is not supported or fails, */
  5205. /* just return the heuristics that was filled above. */
  5206. if (qeth_query_card_info(card, &carrier_info) != 0)
  5207. return 0;
  5208. netdev_dbg(netdev,
  5209. "card info: card_type=0x%02x, port_mode=0x%04x, port_speed=0x%08x\n",
  5210. carrier_info.card_type,
  5211. carrier_info.port_mode,
  5212. carrier_info.port_speed);
  5213. /* Update attributes for which we've obtained more authoritative */
  5214. /* information, leave the rest the way they where filled above. */
  5215. switch (carrier_info.card_type) {
  5216. case CARD_INFO_TYPE_1G_COPPER_A:
  5217. case CARD_INFO_TYPE_1G_COPPER_B:
  5218. qeth_set_ecmd_adv_sup(ecmd, SPEED_1000, PORT_TP);
  5219. ecmd->port = PORT_TP;
  5220. break;
  5221. case CARD_INFO_TYPE_1G_FIBRE_A:
  5222. case CARD_INFO_TYPE_1G_FIBRE_B:
  5223. qeth_set_ecmd_adv_sup(ecmd, SPEED_1000, PORT_FIBRE);
  5224. ecmd->port = PORT_FIBRE;
  5225. break;
  5226. case CARD_INFO_TYPE_10G_FIBRE_A:
  5227. case CARD_INFO_TYPE_10G_FIBRE_B:
  5228. qeth_set_ecmd_adv_sup(ecmd, SPEED_10000, PORT_FIBRE);
  5229. ecmd->port = PORT_FIBRE;
  5230. break;
  5231. }
  5232. switch (carrier_info.port_mode) {
  5233. case CARD_INFO_PORTM_FULLDUPLEX:
  5234. ecmd->duplex = DUPLEX_FULL;
  5235. break;
  5236. case CARD_INFO_PORTM_HALFDUPLEX:
  5237. ecmd->duplex = DUPLEX_HALF;
  5238. break;
  5239. }
  5240. switch (carrier_info.port_speed) {
  5241. case CARD_INFO_PORTS_10M:
  5242. speed = SPEED_10;
  5243. break;
  5244. case CARD_INFO_PORTS_100M:
  5245. speed = SPEED_100;
  5246. break;
  5247. case CARD_INFO_PORTS_1G:
  5248. speed = SPEED_1000;
  5249. break;
  5250. case CARD_INFO_PORTS_10G:
  5251. speed = SPEED_10000;
  5252. break;
  5253. }
  5254. ethtool_cmd_speed_set(ecmd, speed);
  5255. return 0;
  5256. }
  5257. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  5258. static int __init qeth_core_init(void)
  5259. {
  5260. int rc;
  5261. pr_info("loading core functions\n");
  5262. INIT_LIST_HEAD(&qeth_core_card_list.list);
  5263. INIT_LIST_HEAD(&qeth_dbf_list);
  5264. rwlock_init(&qeth_core_card_list.rwlock);
  5265. mutex_init(&qeth_mod_mutex);
  5266. qeth_wq = create_singlethread_workqueue("qeth_wq");
  5267. rc = qeth_register_dbf_views();
  5268. if (rc)
  5269. goto out_err;
  5270. qeth_core_root_dev = root_device_register("qeth");
  5271. rc = PTR_ERR_OR_ZERO(qeth_core_root_dev);
  5272. if (rc)
  5273. goto register_err;
  5274. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  5275. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  5276. if (!qeth_core_header_cache) {
  5277. rc = -ENOMEM;
  5278. goto slab_err;
  5279. }
  5280. qeth_qdio_outbuf_cache = kmem_cache_create("qeth_buf",
  5281. sizeof(struct qeth_qdio_out_buffer), 0, 0, NULL);
  5282. if (!qeth_qdio_outbuf_cache) {
  5283. rc = -ENOMEM;
  5284. goto cqslab_err;
  5285. }
  5286. rc = ccw_driver_register(&qeth_ccw_driver);
  5287. if (rc)
  5288. goto ccw_err;
  5289. qeth_core_ccwgroup_driver.driver.groups = qeth_drv_attr_groups;
  5290. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  5291. if (rc)
  5292. goto ccwgroup_err;
  5293. return 0;
  5294. ccwgroup_err:
  5295. ccw_driver_unregister(&qeth_ccw_driver);
  5296. ccw_err:
  5297. kmem_cache_destroy(qeth_qdio_outbuf_cache);
  5298. cqslab_err:
  5299. kmem_cache_destroy(qeth_core_header_cache);
  5300. slab_err:
  5301. root_device_unregister(qeth_core_root_dev);
  5302. register_err:
  5303. qeth_unregister_dbf_views();
  5304. out_err:
  5305. pr_err("Initializing the qeth device driver failed\n");
  5306. return rc;
  5307. }
  5308. static void __exit qeth_core_exit(void)
  5309. {
  5310. qeth_clear_dbf_list();
  5311. destroy_workqueue(qeth_wq);
  5312. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  5313. ccw_driver_unregister(&qeth_ccw_driver);
  5314. kmem_cache_destroy(qeth_qdio_outbuf_cache);
  5315. kmem_cache_destroy(qeth_core_header_cache);
  5316. root_device_unregister(qeth_core_root_dev);
  5317. qeth_unregister_dbf_views();
  5318. pr_info("core functions removed\n");
  5319. }
  5320. module_init(qeth_core_init);
  5321. module_exit(qeth_core_exit);
  5322. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  5323. MODULE_DESCRIPTION("qeth core functions");
  5324. MODULE_LICENSE("GPL");