sw.c 13 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2014 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * The full GNU General Public License is included in this distribution in the
  15. * file called LICENSE.
  16. *
  17. * Contact Information:
  18. * wlanfae <wlanfae@realtek.com>
  19. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20. * Hsinchu 300, Taiwan.
  21. *
  22. * Larry Finger <Larry.Finger@lwfinger.net>
  23. *
  24. *****************************************************************************/
  25. #include "../wifi.h"
  26. #include "../core.h"
  27. #include "../pci.h"
  28. #include "reg.h"
  29. #include "def.h"
  30. #include "phy.h"
  31. #include "../rtl8723com/phy_common.h"
  32. #include "dm.h"
  33. #include "../rtl8723com/dm_common.h"
  34. #include "hw.h"
  35. #include "fw.h"
  36. #include "../rtl8723com/fw_common.h"
  37. #include "sw.h"
  38. #include "trx.h"
  39. #include "led.h"
  40. #include "table.h"
  41. #include "../btcoexist/rtl_btc.h"
  42. #include <linux/vmalloc.h>
  43. #include <linux/module.h>
  44. static void rtl8723be_init_aspm_vars(struct ieee80211_hw *hw)
  45. {
  46. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  47. /*close ASPM for AMD defaultly */
  48. rtlpci->const_amdpci_aspm = 0;
  49. /* ASPM PS mode.
  50. * 0 - Disable ASPM,
  51. * 1 - Enable ASPM without Clock Req,
  52. * 2 - Enable ASPM with Clock Req,
  53. * 3 - Alwyas Enable ASPM with Clock Req,
  54. * 4 - Always Enable ASPM without Clock Req.
  55. * set defult to RTL8192CE:3 RTL8192E:2
  56. */
  57. rtlpci->const_pci_aspm = 3;
  58. /*Setting for PCI-E device */
  59. rtlpci->const_devicepci_aspm_setting = 0x03;
  60. /*Setting for PCI-E bridge */
  61. rtlpci->const_hostpci_aspm_setting = 0x02;
  62. /* In Hw/Sw Radio Off situation.
  63. * 0 - Default,
  64. * 1 - From ASPM setting without low Mac Pwr,
  65. * 2 - From ASPM setting with low Mac Pwr,
  66. * 3 - Bus D3
  67. * set default to RTL8192CE:0 RTL8192SE:2
  68. */
  69. rtlpci->const_hwsw_rfoff_d3 = 0;
  70. /* This setting works for those device with
  71. * backdoor ASPM setting such as EPHY setting.
  72. * 0 - Not support ASPM,
  73. * 1 - Support ASPM,
  74. * 2 - According to chipset.
  75. */
  76. rtlpci->const_support_pciaspm = 1;
  77. }
  78. int rtl8723be_init_sw_vars(struct ieee80211_hw *hw)
  79. {
  80. int err = 0;
  81. struct rtl_priv *rtlpriv = rtl_priv(hw);
  82. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  83. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  84. rtl8723be_bt_reg_init(hw);
  85. rtlpriv->btcoexist.btc_ops = rtl_btc_get_ops_pointer();
  86. rtlpriv->dm.dm_initialgain_enable = 1;
  87. rtlpriv->dm.dm_flag = 0;
  88. rtlpriv->dm.disable_framebursting = 0;
  89. rtlpriv->dm.thermalvalue = 0;
  90. rtlpci->transmit_config = CFENDFORM | BIT(15) | BIT(24) | BIT(25);
  91. rtlpriv->phy.lck_inprogress = false;
  92. mac->ht_enable = true;
  93. /* compatible 5G band 88ce just 2.4G band & smsp */
  94. rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
  95. rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
  96. rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
  97. rtlpci->receive_config = (RCR_APPFCS |
  98. RCR_APP_MIC |
  99. RCR_APP_ICV |
  100. RCR_APP_PHYST_RXFF |
  101. RCR_HTC_LOC_CTRL |
  102. RCR_AMF |
  103. RCR_ACF |
  104. RCR_ADF |
  105. RCR_AICV |
  106. RCR_AB |
  107. RCR_AM |
  108. RCR_APM |
  109. 0);
  110. rtlpci->irq_mask[0] = (u32) (IMR_PSTIMEOUT |
  111. IMR_HSISR_IND_ON_INT |
  112. IMR_C2HCMD |
  113. IMR_HIGHDOK |
  114. IMR_MGNTDOK |
  115. IMR_BKDOK |
  116. IMR_BEDOK |
  117. IMR_VIDOK |
  118. IMR_VODOK |
  119. IMR_RDU |
  120. IMR_ROK |
  121. 0);
  122. rtlpci->irq_mask[1] = (u32)(IMR_RXFOVW | 0);
  123. rtlpci->sys_irq_mask = (u32)(HSIMR_PDN_INT_EN |
  124. HSIMR_RON_INT_EN |
  125. 0);
  126. /* for debug level */
  127. rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
  128. /* for LPS & IPS */
  129. rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
  130. rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
  131. rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
  132. rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
  133. rtlpriv->cfg->mod_params->sw_crypto =
  134. rtlpriv->cfg->mod_params->sw_crypto;
  135. rtlpriv->cfg->mod_params->disable_watchdog =
  136. rtlpriv->cfg->mod_params->disable_watchdog;
  137. if (rtlpriv->cfg->mod_params->disable_watchdog)
  138. pr_info("watchdog disabled\n");
  139. rtlpriv->psc.reg_fwctrl_lps = 3;
  140. rtlpriv->psc.reg_max_lps_awakeintvl = 5;
  141. /* for ASPM, you can close aspm through
  142. * set const_support_pciaspm = 0
  143. */
  144. rtl8723be_init_aspm_vars(hw);
  145. if (rtlpriv->psc.reg_fwctrl_lps == 1)
  146. rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
  147. else if (rtlpriv->psc.reg_fwctrl_lps == 2)
  148. rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
  149. else if (rtlpriv->psc.reg_fwctrl_lps == 3)
  150. rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
  151. /*low power: Disable 32k */
  152. rtlpriv->psc.low_power_enable = false;
  153. rtlpriv->rtlhal.earlymode_enable = false;
  154. /* for firmware buf */
  155. rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
  156. if (!rtlpriv->rtlhal.pfirmware) {
  157. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  158. "Can't alloc buffer for fw.\n");
  159. return 1;
  160. }
  161. rtlpriv->max_fw_size = 0x8000;
  162. pr_info("Using firmware %s\n", rtlpriv->cfg->fw_name);
  163. err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name,
  164. rtlpriv->io.dev, GFP_KERNEL, hw,
  165. rtl_fw_cb);
  166. if (err) {
  167. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  168. "Failed to request firmware!\n");
  169. return 1;
  170. }
  171. return 0;
  172. }
  173. void rtl8723be_deinit_sw_vars(struct ieee80211_hw *hw)
  174. {
  175. struct rtl_priv *rtlpriv = rtl_priv(hw);
  176. if (rtlpriv->rtlhal.pfirmware) {
  177. vfree(rtlpriv->rtlhal.pfirmware);
  178. rtlpriv->rtlhal.pfirmware = NULL;
  179. }
  180. }
  181. /* get bt coexist status */
  182. bool rtl8723be_get_btc_status(void)
  183. {
  184. return true;
  185. }
  186. static bool is_fw_header(struct rtlwifi_firmware_header *hdr)
  187. {
  188. return (le16_to_cpu(hdr->signature) & 0xfff0) == 0x5300;
  189. }
  190. static struct rtl_hal_ops rtl8723be_hal_ops = {
  191. .init_sw_vars = rtl8723be_init_sw_vars,
  192. .deinit_sw_vars = rtl8723be_deinit_sw_vars,
  193. .read_eeprom_info = rtl8723be_read_eeprom_info,
  194. .interrupt_recognized = rtl8723be_interrupt_recognized,
  195. .hw_init = rtl8723be_hw_init,
  196. .hw_disable = rtl8723be_card_disable,
  197. .hw_suspend = rtl8723be_suspend,
  198. .hw_resume = rtl8723be_resume,
  199. .enable_interrupt = rtl8723be_enable_interrupt,
  200. .disable_interrupt = rtl8723be_disable_interrupt,
  201. .set_network_type = rtl8723be_set_network_type,
  202. .set_chk_bssid = rtl8723be_set_check_bssid,
  203. .set_qos = rtl8723be_set_qos,
  204. .set_bcn_reg = rtl8723be_set_beacon_related_registers,
  205. .set_bcn_intv = rtl8723be_set_beacon_interval,
  206. .update_interrupt_mask = rtl8723be_update_interrupt_mask,
  207. .get_hw_reg = rtl8723be_get_hw_reg,
  208. .set_hw_reg = rtl8723be_set_hw_reg,
  209. .update_rate_tbl = rtl8723be_update_hal_rate_tbl,
  210. .fill_tx_desc = rtl8723be_tx_fill_desc,
  211. .fill_tx_cmddesc = rtl8723be_tx_fill_cmddesc,
  212. .query_rx_desc = rtl8723be_rx_query_desc,
  213. .set_channel_access = rtl8723be_update_channel_access_setting,
  214. .radio_onoff_checking = rtl8723be_gpio_radio_on_off_checking,
  215. .set_bw_mode = rtl8723be_phy_set_bw_mode,
  216. .switch_channel = rtl8723be_phy_sw_chnl,
  217. .dm_watchdog = rtl8723be_dm_watchdog,
  218. .scan_operation_backup = rtl8723be_phy_scan_operation_backup,
  219. .set_rf_power_state = rtl8723be_phy_set_rf_power_state,
  220. .led_control = rtl8723be_led_control,
  221. .set_desc = rtl8723be_set_desc,
  222. .get_desc = rtl8723be_get_desc,
  223. .is_tx_desc_closed = rtl8723be_is_tx_desc_closed,
  224. .tx_polling = rtl8723be_tx_polling,
  225. .enable_hw_sec = rtl8723be_enable_hw_security_config,
  226. .set_key = rtl8723be_set_key,
  227. .init_sw_leds = rtl8723be_init_sw_leds,
  228. .get_bbreg = rtl8723_phy_query_bb_reg,
  229. .set_bbreg = rtl8723_phy_set_bb_reg,
  230. .get_rfreg = rtl8723be_phy_query_rf_reg,
  231. .set_rfreg = rtl8723be_phy_set_rf_reg,
  232. .fill_h2c_cmd = rtl8723be_fill_h2c_cmd,
  233. .get_btc_status = rtl8723be_get_btc_status,
  234. .rx_command_packet = rtl8723be_rx_command_packet,
  235. .is_fw_header = is_fw_header,
  236. };
  237. static struct rtl_mod_params rtl8723be_mod_params = {
  238. .sw_crypto = false,
  239. .inactiveps = true,
  240. .swctrl_lps = false,
  241. .fwctrl_lps = true,
  242. .msi_support = false,
  243. .disable_watchdog = false,
  244. .debug = DBG_EMERG,
  245. };
  246. static struct rtl_hal_cfg rtl8723be_hal_cfg = {
  247. .bar_id = 2,
  248. .write_readback = true,
  249. .name = "rtl8723be_pci",
  250. .fw_name = "rtlwifi/rtl8723befw.bin",
  251. .ops = &rtl8723be_hal_ops,
  252. .mod_params = &rtl8723be_mod_params,
  253. .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
  254. .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
  255. .maps[SYS_CLK] = REG_SYS_CLKR,
  256. .maps[MAC_RCR_AM] = AM,
  257. .maps[MAC_RCR_AB] = AB,
  258. .maps[MAC_RCR_ACRC32] = ACRC32,
  259. .maps[MAC_RCR_ACF] = ACF,
  260. .maps[MAC_RCR_AAP] = AAP,
  261. .maps[MAC_HIMR] = REG_HIMR,
  262. .maps[MAC_HIMRE] = REG_HIMRE,
  263. .maps[MAC_HSISR] = REG_HSISR,
  264. .maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,
  265. .maps[EFUSE_TEST] = REG_EFUSE_TEST,
  266. .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
  267. .maps[EFUSE_CLK] = 0,
  268. .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
  269. .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
  270. .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
  271. .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
  272. .maps[EFUSE_ANA8M] = ANA8M,
  273. .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
  274. .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
  275. .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
  276. .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
  277. .maps[RWCAM] = REG_CAMCMD,
  278. .maps[WCAMI] = REG_CAMWRITE,
  279. .maps[RCAMO] = REG_CAMREAD,
  280. .maps[CAMDBG] = REG_CAMDBG,
  281. .maps[SECR] = REG_SECCFG,
  282. .maps[SEC_CAM_NONE] = CAM_NONE,
  283. .maps[SEC_CAM_WEP40] = CAM_WEP40,
  284. .maps[SEC_CAM_TKIP] = CAM_TKIP,
  285. .maps[SEC_CAM_AES] = CAM_AES,
  286. .maps[SEC_CAM_WEP104] = CAM_WEP104,
  287. .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
  288. .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
  289. .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
  290. .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
  291. .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
  292. .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
  293. /* .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, */ /*need check*/
  294. .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
  295. .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
  296. .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
  297. .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
  298. .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
  299. .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
  300. .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
  301. /* .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,*/
  302. /* .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,*/
  303. .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
  304. .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
  305. .maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0,
  306. .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
  307. .maps[RTL_IMR_RDU] = IMR_RDU,
  308. .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
  309. .maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
  310. .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
  311. .maps[RTL_IMR_TBDER] = IMR_TBDER,
  312. .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
  313. .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
  314. .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
  315. .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
  316. .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
  317. .maps[RTL_IMR_VODOK] = IMR_VODOK,
  318. .maps[RTL_IMR_ROK] = IMR_ROK,
  319. .maps[RTL_IMR_HSISR_IND] = IMR_HSISR_IND_ON_INT,
  320. .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
  321. .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
  322. .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
  323. .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
  324. .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
  325. .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
  326. .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
  327. .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
  328. .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
  329. .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
  330. .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
  331. .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
  332. .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
  333. .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
  334. .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
  335. };
  336. static struct pci_device_id rtl8723be_pci_ids[] = {
  337. {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0xB723, rtl8723be_hal_cfg)},
  338. {},
  339. };
  340. MODULE_DEVICE_TABLE(pci, rtl8723be_pci_ids);
  341. MODULE_AUTHOR("PageHe <page_he@realsil.com.cn>");
  342. MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
  343. MODULE_LICENSE("GPL");
  344. MODULE_DESCRIPTION("Realtek 8723BE 802.11n PCI wireless");
  345. MODULE_FIRMWARE("rtlwifi/rtl8723befw.bin");
  346. module_param_named(swenc, rtl8723be_mod_params.sw_crypto, bool, 0444);
  347. module_param_named(debug, rtl8723be_mod_params.debug, int, 0444);
  348. module_param_named(ips, rtl8723be_mod_params.inactiveps, bool, 0444);
  349. module_param_named(swlps, rtl8723be_mod_params.swctrl_lps, bool, 0444);
  350. module_param_named(fwlps, rtl8723be_mod_params.fwctrl_lps, bool, 0444);
  351. module_param_named(msi, rtl8723be_mod_params.msi_support, bool, 0444);
  352. module_param_named(disable_watchdog, rtl8723be_mod_params.disable_watchdog,
  353. bool, 0444);
  354. MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
  355. MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
  356. MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
  357. MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
  358. MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 0)\n");
  359. MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
  360. MODULE_PARM_DESC(disable_watchdog,
  361. "Set to 1 to disable the watchdog (default 0)\n");
  362. static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
  363. static struct pci_driver rtl8723be_driver = {
  364. .name = KBUILD_MODNAME,
  365. .id_table = rtl8723be_pci_ids,
  366. .probe = rtl_pci_probe,
  367. .remove = rtl_pci_disconnect,
  368. .driver.pm = &rtlwifi_pm_ops,
  369. };
  370. module_pci_driver(rtl8723be_driver);