qed_l2.c 56 KB

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  1. /* QLogic qed NIC Driver
  2. * Copyright (c) 2015 QLogic Corporation
  3. *
  4. * This software is available under the terms of the GNU General Public License
  5. * (GPL) Version 2, available from the file COPYING in the main directory of
  6. * this source tree.
  7. */
  8. #include <linux/types.h>
  9. #include <asm/byteorder.h>
  10. #include <asm/param.h>
  11. #include <linux/delay.h>
  12. #include <linux/dma-mapping.h>
  13. #include <linux/etherdevice.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/kernel.h>
  16. #include <linux/module.h>
  17. #include <linux/pci.h>
  18. #include <linux/slab.h>
  19. #include <linux/stddef.h>
  20. #include <linux/string.h>
  21. #include <linux/version.h>
  22. #include <linux/workqueue.h>
  23. #include <linux/bitops.h>
  24. #include <linux/bug.h>
  25. #include "qed.h"
  26. #include <linux/qed/qed_chain.h>
  27. #include "qed_cxt.h"
  28. #include "qed_dev_api.h"
  29. #include <linux/qed/qed_eth_if.h>
  30. #include "qed_hsi.h"
  31. #include "qed_hw.h"
  32. #include "qed_int.h"
  33. #include "qed_mcp.h"
  34. #include "qed_reg_addr.h"
  35. #include "qed_sp.h"
  36. enum qed_rss_caps {
  37. QED_RSS_IPV4 = 0x1,
  38. QED_RSS_IPV6 = 0x2,
  39. QED_RSS_IPV4_TCP = 0x4,
  40. QED_RSS_IPV6_TCP = 0x8,
  41. QED_RSS_IPV4_UDP = 0x10,
  42. QED_RSS_IPV6_UDP = 0x20,
  43. };
  44. /* Should be the same as ETH_RSS_IND_TABLE_ENTRIES_NUM */
  45. #define QED_RSS_IND_TABLE_SIZE 128
  46. #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */
  47. struct qed_rss_params {
  48. u8 update_rss_config;
  49. u8 rss_enable;
  50. u8 rss_eng_id;
  51. u8 update_rss_capabilities;
  52. u8 update_rss_ind_table;
  53. u8 update_rss_key;
  54. u8 rss_caps;
  55. u8 rss_table_size_log;
  56. u16 rss_ind_table[QED_RSS_IND_TABLE_SIZE];
  57. u32 rss_key[QED_RSS_KEY_SIZE];
  58. };
  59. enum qed_filter_opcode {
  60. QED_FILTER_ADD,
  61. QED_FILTER_REMOVE,
  62. QED_FILTER_MOVE,
  63. QED_FILTER_REPLACE, /* Delete all MACs and add new one instead */
  64. QED_FILTER_FLUSH, /* Removes all filters */
  65. };
  66. enum qed_filter_ucast_type {
  67. QED_FILTER_MAC,
  68. QED_FILTER_VLAN,
  69. QED_FILTER_MAC_VLAN,
  70. QED_FILTER_INNER_MAC,
  71. QED_FILTER_INNER_VLAN,
  72. QED_FILTER_INNER_PAIR,
  73. QED_FILTER_INNER_MAC_VNI_PAIR,
  74. QED_FILTER_MAC_VNI_PAIR,
  75. QED_FILTER_VNI,
  76. };
  77. struct qed_filter_ucast {
  78. enum qed_filter_opcode opcode;
  79. enum qed_filter_ucast_type type;
  80. u8 is_rx_filter;
  81. u8 is_tx_filter;
  82. u8 vport_to_add_to;
  83. u8 vport_to_remove_from;
  84. unsigned char mac[ETH_ALEN];
  85. u8 assert_on_error;
  86. u16 vlan;
  87. u32 vni;
  88. };
  89. struct qed_filter_mcast {
  90. /* MOVE is not supported for multicast */
  91. enum qed_filter_opcode opcode;
  92. u8 vport_to_add_to;
  93. u8 vport_to_remove_from;
  94. u8 num_mc_addrs;
  95. #define QED_MAX_MC_ADDRS 64
  96. unsigned char mac[QED_MAX_MC_ADDRS][ETH_ALEN];
  97. };
  98. struct qed_filter_accept_flags {
  99. u8 update_rx_mode_config;
  100. u8 update_tx_mode_config;
  101. u8 rx_accept_filter;
  102. u8 tx_accept_filter;
  103. #define QED_ACCEPT_NONE 0x01
  104. #define QED_ACCEPT_UCAST_MATCHED 0x02
  105. #define QED_ACCEPT_UCAST_UNMATCHED 0x04
  106. #define QED_ACCEPT_MCAST_MATCHED 0x08
  107. #define QED_ACCEPT_MCAST_UNMATCHED 0x10
  108. #define QED_ACCEPT_BCAST 0x20
  109. };
  110. struct qed_sp_vport_update_params {
  111. u16 opaque_fid;
  112. u8 vport_id;
  113. u8 update_vport_active_rx_flg;
  114. u8 vport_active_rx_flg;
  115. u8 update_vport_active_tx_flg;
  116. u8 vport_active_tx_flg;
  117. u8 update_approx_mcast_flg;
  118. u8 update_accept_any_vlan_flg;
  119. u8 accept_any_vlan;
  120. unsigned long bins[8];
  121. struct qed_rss_params *rss_params;
  122. struct qed_filter_accept_flags accept_flags;
  123. };
  124. enum qed_tpa_mode {
  125. QED_TPA_MODE_NONE,
  126. QED_TPA_MODE_UNUSED,
  127. QED_TPA_MODE_GRO,
  128. QED_TPA_MODE_MAX
  129. };
  130. struct qed_sp_vport_start_params {
  131. enum qed_tpa_mode tpa_mode;
  132. bool remove_inner_vlan;
  133. bool drop_ttl0;
  134. u8 max_buffers_per_cqe;
  135. u32 concrete_fid;
  136. u16 opaque_fid;
  137. u8 vport_id;
  138. u16 mtu;
  139. };
  140. #define QED_MAX_SGES_NUM 16
  141. #define CRC32_POLY 0x1edc6f41
  142. static int qed_sp_vport_start(struct qed_hwfn *p_hwfn,
  143. struct qed_sp_vport_start_params *p_params)
  144. {
  145. struct vport_start_ramrod_data *p_ramrod = NULL;
  146. struct qed_spq_entry *p_ent = NULL;
  147. struct qed_sp_init_data init_data;
  148. int rc = -EINVAL;
  149. u16 rx_mode = 0;
  150. u8 abs_vport_id = 0;
  151. rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
  152. if (rc != 0)
  153. return rc;
  154. memset(&init_data, 0, sizeof(init_data));
  155. init_data.cid = qed_spq_get_cid(p_hwfn);
  156. init_data.opaque_fid = p_params->opaque_fid;
  157. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  158. rc = qed_sp_init_request(p_hwfn, &p_ent,
  159. ETH_RAMROD_VPORT_START,
  160. PROTOCOLID_ETH, &init_data);
  161. if (rc)
  162. return rc;
  163. p_ramrod = &p_ent->ramrod.vport_start;
  164. p_ramrod->vport_id = abs_vport_id;
  165. p_ramrod->mtu = cpu_to_le16(p_params->mtu);
  166. p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan;
  167. p_ramrod->drop_ttl0_en = p_params->drop_ttl0;
  168. SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
  169. SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
  170. p_ramrod->rx_mode.state = cpu_to_le16(rx_mode);
  171. /* TPA related fields */
  172. memset(&p_ramrod->tpa_param, 0,
  173. sizeof(struct eth_vport_tpa_param));
  174. p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
  175. switch (p_params->tpa_mode) {
  176. case QED_TPA_MODE_GRO:
  177. p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
  178. p_ramrod->tpa_param.tpa_max_size = (u16)-1;
  179. p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
  180. p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
  181. p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
  182. p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
  183. p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
  184. p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
  185. break;
  186. default:
  187. break;
  188. }
  189. /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
  190. p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev,
  191. p_params->concrete_fid);
  192. return qed_spq_post(p_hwfn, p_ent, NULL);
  193. }
  194. static int
  195. qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn,
  196. struct vport_update_ramrod_data *p_ramrod,
  197. struct qed_rss_params *p_params)
  198. {
  199. struct eth_vport_rss_config *rss = &p_ramrod->rss_config;
  200. u16 abs_l2_queue = 0, capabilities = 0;
  201. int rc = 0, i;
  202. if (!p_params) {
  203. p_ramrod->common.update_rss_flg = 0;
  204. return rc;
  205. }
  206. BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE !=
  207. ETH_RSS_IND_TABLE_ENTRIES_NUM);
  208. rc = qed_fw_rss_eng(p_hwfn, p_params->rss_eng_id, &rss->rss_id);
  209. if (rc)
  210. return rc;
  211. p_ramrod->common.update_rss_flg = p_params->update_rss_config;
  212. rss->update_rss_capabilities = p_params->update_rss_capabilities;
  213. rss->update_rss_ind_table = p_params->update_rss_ind_table;
  214. rss->update_rss_key = p_params->update_rss_key;
  215. rss->rss_mode = p_params->rss_enable ?
  216. ETH_VPORT_RSS_MODE_REGULAR :
  217. ETH_VPORT_RSS_MODE_DISABLED;
  218. SET_FIELD(capabilities,
  219. ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
  220. !!(p_params->rss_caps & QED_RSS_IPV4));
  221. SET_FIELD(capabilities,
  222. ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
  223. !!(p_params->rss_caps & QED_RSS_IPV6));
  224. SET_FIELD(capabilities,
  225. ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
  226. !!(p_params->rss_caps & QED_RSS_IPV4_TCP));
  227. SET_FIELD(capabilities,
  228. ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
  229. !!(p_params->rss_caps & QED_RSS_IPV6_TCP));
  230. SET_FIELD(capabilities,
  231. ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
  232. !!(p_params->rss_caps & QED_RSS_IPV4_UDP));
  233. SET_FIELD(capabilities,
  234. ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
  235. !!(p_params->rss_caps & QED_RSS_IPV6_UDP));
  236. rss->tbl_size = p_params->rss_table_size_log;
  237. rss->capabilities = cpu_to_le16(capabilities);
  238. DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
  239. "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
  240. p_ramrod->common.update_rss_flg,
  241. rss->rss_mode, rss->update_rss_capabilities,
  242. capabilities, rss->update_rss_ind_table,
  243. rss->update_rss_key);
  244. for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
  245. rc = qed_fw_l2_queue(p_hwfn,
  246. (u8)p_params->rss_ind_table[i],
  247. &abs_l2_queue);
  248. if (rc)
  249. return rc;
  250. rss->indirection_table[i] = cpu_to_le16(abs_l2_queue);
  251. DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, "i= %d, queue = %d\n",
  252. i, rss->indirection_table[i]);
  253. }
  254. for (i = 0; i < 10; i++)
  255. rss->rss_key[i] = cpu_to_le32(p_params->rss_key[i]);
  256. return rc;
  257. }
  258. static void
  259. qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn,
  260. struct vport_update_ramrod_data *p_ramrod,
  261. struct qed_filter_accept_flags accept_flags)
  262. {
  263. p_ramrod->common.update_rx_mode_flg =
  264. accept_flags.update_rx_mode_config;
  265. p_ramrod->common.update_tx_mode_flg =
  266. accept_flags.update_tx_mode_config;
  267. /* Set Rx mode accept flags */
  268. if (p_ramrod->common.update_rx_mode_flg) {
  269. u8 accept_filter = accept_flags.rx_accept_filter;
  270. u16 state = 0;
  271. SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
  272. !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) ||
  273. !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)));
  274. SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
  275. !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED));
  276. SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
  277. !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) ||
  278. !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
  279. SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
  280. (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
  281. !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
  282. SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
  283. !!(accept_filter & QED_ACCEPT_BCAST));
  284. p_ramrod->rx_mode.state = cpu_to_le16(state);
  285. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  286. "p_ramrod->rx_mode.state = 0x%x\n", state);
  287. }
  288. /* Set Tx mode accept flags */
  289. if (p_ramrod->common.update_tx_mode_flg) {
  290. u8 accept_filter = accept_flags.tx_accept_filter;
  291. u16 state = 0;
  292. SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
  293. !!(accept_filter & QED_ACCEPT_NONE));
  294. SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL,
  295. (!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) &&
  296. !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)));
  297. SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
  298. !!(accept_filter & QED_ACCEPT_NONE));
  299. SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
  300. (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
  301. !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
  302. SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
  303. !!(accept_filter & QED_ACCEPT_BCAST));
  304. p_ramrod->tx_mode.state = cpu_to_le16(state);
  305. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  306. "p_ramrod->tx_mode.state = 0x%x\n", state);
  307. }
  308. }
  309. static void
  310. qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn,
  311. struct vport_update_ramrod_data *p_ramrod,
  312. struct qed_sp_vport_update_params *p_params)
  313. {
  314. int i;
  315. memset(&p_ramrod->approx_mcast.bins, 0,
  316. sizeof(p_ramrod->approx_mcast.bins));
  317. if (p_params->update_approx_mcast_flg) {
  318. p_ramrod->common.update_approx_mcast_flg = 1;
  319. for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
  320. u32 *p_bins = (u32 *)p_params->bins;
  321. __le32 val = cpu_to_le32(p_bins[i]);
  322. p_ramrod->approx_mcast.bins[i] = val;
  323. }
  324. }
  325. }
  326. static int
  327. qed_sp_vport_update(struct qed_hwfn *p_hwfn,
  328. struct qed_sp_vport_update_params *p_params,
  329. enum spq_mode comp_mode,
  330. struct qed_spq_comp_cb *p_comp_data)
  331. {
  332. struct qed_rss_params *p_rss_params = p_params->rss_params;
  333. struct vport_update_ramrod_data_cmn *p_cmn;
  334. struct qed_sp_init_data init_data;
  335. struct vport_update_ramrod_data *p_ramrod = NULL;
  336. struct qed_spq_entry *p_ent = NULL;
  337. u8 abs_vport_id = 0;
  338. int rc = -EINVAL;
  339. rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
  340. if (rc != 0)
  341. return rc;
  342. memset(&init_data, 0, sizeof(init_data));
  343. init_data.cid = qed_spq_get_cid(p_hwfn);
  344. init_data.opaque_fid = p_params->opaque_fid;
  345. init_data.comp_mode = comp_mode;
  346. init_data.p_comp_data = p_comp_data;
  347. rc = qed_sp_init_request(p_hwfn, &p_ent,
  348. ETH_RAMROD_VPORT_UPDATE,
  349. PROTOCOLID_ETH, &init_data);
  350. if (rc)
  351. return rc;
  352. /* Copy input params to ramrod according to FW struct */
  353. p_ramrod = &p_ent->ramrod.vport_update;
  354. p_cmn = &p_ramrod->common;
  355. p_cmn->vport_id = abs_vport_id;
  356. p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
  357. p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
  358. p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
  359. p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
  360. p_cmn->accept_any_vlan = p_params->accept_any_vlan;
  361. p_cmn->update_accept_any_vlan_flg =
  362. p_params->update_accept_any_vlan_flg;
  363. rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
  364. if (rc) {
  365. /* Return spq entry which is taken in qed_sp_init_request()*/
  366. qed_spq_return_entry(p_hwfn, p_ent);
  367. return rc;
  368. }
  369. /* Update mcast bins for VFs, PF doesn't use this functionality */
  370. qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
  371. qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
  372. return qed_spq_post(p_hwfn, p_ent, NULL);
  373. }
  374. static int qed_sp_vport_stop(struct qed_hwfn *p_hwfn,
  375. u16 opaque_fid,
  376. u8 vport_id)
  377. {
  378. struct vport_stop_ramrod_data *p_ramrod;
  379. struct qed_sp_init_data init_data;
  380. struct qed_spq_entry *p_ent;
  381. u8 abs_vport_id = 0;
  382. int rc;
  383. rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id);
  384. if (rc != 0)
  385. return rc;
  386. memset(&init_data, 0, sizeof(init_data));
  387. init_data.cid = qed_spq_get_cid(p_hwfn);
  388. init_data.opaque_fid = opaque_fid;
  389. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  390. rc = qed_sp_init_request(p_hwfn, &p_ent,
  391. ETH_RAMROD_VPORT_STOP,
  392. PROTOCOLID_ETH, &init_data);
  393. if (rc)
  394. return rc;
  395. p_ramrod = &p_ent->ramrod.vport_stop;
  396. p_ramrod->vport_id = abs_vport_id;
  397. return qed_spq_post(p_hwfn, p_ent, NULL);
  398. }
  399. static int qed_filter_accept_cmd(struct qed_dev *cdev,
  400. u8 vport,
  401. struct qed_filter_accept_flags accept_flags,
  402. u8 update_accept_any_vlan,
  403. u8 accept_any_vlan,
  404. enum spq_mode comp_mode,
  405. struct qed_spq_comp_cb *p_comp_data)
  406. {
  407. struct qed_sp_vport_update_params vport_update_params;
  408. int i, rc;
  409. /* Prepare and send the vport rx_mode change */
  410. memset(&vport_update_params, 0, sizeof(vport_update_params));
  411. vport_update_params.vport_id = vport;
  412. vport_update_params.accept_flags = accept_flags;
  413. vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
  414. vport_update_params.accept_any_vlan = accept_any_vlan;
  415. for_each_hwfn(cdev, i) {
  416. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  417. vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
  418. rc = qed_sp_vport_update(p_hwfn, &vport_update_params,
  419. comp_mode, p_comp_data);
  420. if (rc != 0) {
  421. DP_ERR(cdev, "Update rx_mode failed %d\n", rc);
  422. return rc;
  423. }
  424. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  425. "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
  426. accept_flags.rx_accept_filter,
  427. accept_flags.tx_accept_filter);
  428. if (update_accept_any_vlan)
  429. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  430. "accept_any_vlan=%d configured\n",
  431. accept_any_vlan);
  432. }
  433. return 0;
  434. }
  435. static int qed_sp_release_queue_cid(
  436. struct qed_hwfn *p_hwfn,
  437. struct qed_hw_cid_data *p_cid_data)
  438. {
  439. if (!p_cid_data->b_cid_allocated)
  440. return 0;
  441. qed_cxt_release_cid(p_hwfn, p_cid_data->cid);
  442. p_cid_data->b_cid_allocated = false;
  443. return 0;
  444. }
  445. static int
  446. qed_sp_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn,
  447. u16 opaque_fid,
  448. u32 cid,
  449. struct qed_queue_start_common_params *params,
  450. u8 stats_id,
  451. u16 bd_max_bytes,
  452. dma_addr_t bd_chain_phys_addr,
  453. dma_addr_t cqe_pbl_addr,
  454. u16 cqe_pbl_size)
  455. {
  456. struct rx_queue_start_ramrod_data *p_ramrod = NULL;
  457. struct qed_spq_entry *p_ent = NULL;
  458. struct qed_sp_init_data init_data;
  459. struct qed_hw_cid_data *p_rx_cid;
  460. u16 abs_rx_q_id = 0;
  461. u8 abs_vport_id = 0;
  462. int rc = -EINVAL;
  463. /* Store information for the stop */
  464. p_rx_cid = &p_hwfn->p_rx_cids[params->queue_id];
  465. p_rx_cid->cid = cid;
  466. p_rx_cid->opaque_fid = opaque_fid;
  467. p_rx_cid->vport_id = params->vport_id;
  468. rc = qed_fw_vport(p_hwfn, params->vport_id, &abs_vport_id);
  469. if (rc != 0)
  470. return rc;
  471. rc = qed_fw_l2_queue(p_hwfn, params->queue_id, &abs_rx_q_id);
  472. if (rc != 0)
  473. return rc;
  474. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  475. "opaque_fid=0x%x, cid=0x%x, rx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
  476. opaque_fid, cid, params->queue_id, params->vport_id,
  477. params->sb);
  478. /* Get SPQ entry */
  479. memset(&init_data, 0, sizeof(init_data));
  480. init_data.cid = cid;
  481. init_data.opaque_fid = opaque_fid;
  482. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  483. rc = qed_sp_init_request(p_hwfn, &p_ent,
  484. ETH_RAMROD_RX_QUEUE_START,
  485. PROTOCOLID_ETH, &init_data);
  486. if (rc)
  487. return rc;
  488. p_ramrod = &p_ent->ramrod.rx_queue_start;
  489. p_ramrod->sb_id = cpu_to_le16(params->sb);
  490. p_ramrod->sb_index = params->sb_idx;
  491. p_ramrod->vport_id = abs_vport_id;
  492. p_ramrod->stats_counter_id = stats_id;
  493. p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id);
  494. p_ramrod->complete_cqe_flg = 0;
  495. p_ramrod->complete_event_flg = 1;
  496. p_ramrod->bd_max_bytes = cpu_to_le16(bd_max_bytes);
  497. DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
  498. p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size);
  499. DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
  500. rc = qed_spq_post(p_hwfn, p_ent, NULL);
  501. return rc;
  502. }
  503. static int
  504. qed_sp_eth_rx_queue_start(struct qed_hwfn *p_hwfn,
  505. u16 opaque_fid,
  506. struct qed_queue_start_common_params *params,
  507. u16 bd_max_bytes,
  508. dma_addr_t bd_chain_phys_addr,
  509. dma_addr_t cqe_pbl_addr,
  510. u16 cqe_pbl_size,
  511. void __iomem **pp_prod)
  512. {
  513. struct qed_hw_cid_data *p_rx_cid;
  514. u64 init_prod_val = 0;
  515. u16 abs_l2_queue = 0;
  516. u8 abs_stats_id = 0;
  517. int rc;
  518. rc = qed_fw_l2_queue(p_hwfn, params->queue_id, &abs_l2_queue);
  519. if (rc != 0)
  520. return rc;
  521. rc = qed_fw_vport(p_hwfn, params->vport_id, &abs_stats_id);
  522. if (rc != 0)
  523. return rc;
  524. *pp_prod = (u8 __iomem *)p_hwfn->regview +
  525. GTT_BAR0_MAP_REG_MSDM_RAM +
  526. MSTORM_PRODS_OFFSET(abs_l2_queue);
  527. /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
  528. __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u64),
  529. (u32 *)(&init_prod_val));
  530. /* Allocate a CID for the queue */
  531. p_rx_cid = &p_hwfn->p_rx_cids[params->queue_id];
  532. rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH,
  533. &p_rx_cid->cid);
  534. if (rc) {
  535. DP_NOTICE(p_hwfn, "Failed to acquire cid\n");
  536. return rc;
  537. }
  538. p_rx_cid->b_cid_allocated = true;
  539. rc = qed_sp_eth_rxq_start_ramrod(p_hwfn,
  540. opaque_fid,
  541. p_rx_cid->cid,
  542. params,
  543. abs_stats_id,
  544. bd_max_bytes,
  545. bd_chain_phys_addr,
  546. cqe_pbl_addr,
  547. cqe_pbl_size);
  548. if (rc != 0)
  549. qed_sp_release_queue_cid(p_hwfn, p_rx_cid);
  550. return rc;
  551. }
  552. static int qed_sp_eth_rx_queue_stop(struct qed_hwfn *p_hwfn,
  553. u16 rx_queue_id,
  554. bool eq_completion_only,
  555. bool cqe_completion)
  556. {
  557. struct qed_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
  558. struct rx_queue_stop_ramrod_data *p_ramrod = NULL;
  559. struct qed_spq_entry *p_ent = NULL;
  560. struct qed_sp_init_data init_data;
  561. u16 abs_rx_q_id = 0;
  562. int rc = -EINVAL;
  563. /* Get SPQ entry */
  564. memset(&init_data, 0, sizeof(init_data));
  565. init_data.cid = p_rx_cid->cid;
  566. init_data.opaque_fid = p_rx_cid->opaque_fid;
  567. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  568. rc = qed_sp_init_request(p_hwfn, &p_ent,
  569. ETH_RAMROD_RX_QUEUE_STOP,
  570. PROTOCOLID_ETH, &init_data);
  571. if (rc)
  572. return rc;
  573. p_ramrod = &p_ent->ramrod.rx_queue_stop;
  574. qed_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
  575. qed_fw_l2_queue(p_hwfn, rx_queue_id, &abs_rx_q_id);
  576. p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id);
  577. /* Cleaning the queue requires the completion to arrive there.
  578. * In addition, VFs require the answer to come as eqe to PF.
  579. */
  580. p_ramrod->complete_cqe_flg =
  581. (!!(p_rx_cid->opaque_fid == p_hwfn->hw_info.opaque_fid) &&
  582. !eq_completion_only) || cqe_completion;
  583. p_ramrod->complete_event_flg =
  584. !(p_rx_cid->opaque_fid == p_hwfn->hw_info.opaque_fid) ||
  585. eq_completion_only;
  586. rc = qed_spq_post(p_hwfn, p_ent, NULL);
  587. if (rc)
  588. return rc;
  589. return qed_sp_release_queue_cid(p_hwfn, p_rx_cid);
  590. }
  591. static int
  592. qed_sp_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn,
  593. u16 opaque_fid,
  594. u32 cid,
  595. struct qed_queue_start_common_params *p_params,
  596. u8 stats_id,
  597. dma_addr_t pbl_addr,
  598. u16 pbl_size,
  599. union qed_qm_pq_params *p_pq_params)
  600. {
  601. struct tx_queue_start_ramrod_data *p_ramrod = NULL;
  602. struct qed_spq_entry *p_ent = NULL;
  603. struct qed_sp_init_data init_data;
  604. struct qed_hw_cid_data *p_tx_cid;
  605. u8 abs_vport_id;
  606. int rc = -EINVAL;
  607. u16 pq_id;
  608. /* Store information for the stop */
  609. p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id];
  610. p_tx_cid->cid = cid;
  611. p_tx_cid->opaque_fid = opaque_fid;
  612. rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
  613. if (rc)
  614. return rc;
  615. /* Get SPQ entry */
  616. memset(&init_data, 0, sizeof(init_data));
  617. init_data.cid = cid;
  618. init_data.opaque_fid = opaque_fid;
  619. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  620. rc = qed_sp_init_request(p_hwfn, &p_ent,
  621. ETH_RAMROD_TX_QUEUE_START,
  622. PROTOCOLID_ETH, &init_data);
  623. if (rc)
  624. return rc;
  625. p_ramrod = &p_ent->ramrod.tx_queue_start;
  626. p_ramrod->vport_id = abs_vport_id;
  627. p_ramrod->sb_id = cpu_to_le16(p_params->sb);
  628. p_ramrod->sb_index = p_params->sb_idx;
  629. p_ramrod->stats_counter_id = stats_id;
  630. p_ramrod->pbl_size = cpu_to_le16(pbl_size);
  631. DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr);
  632. pq_id = qed_get_qm_pq(p_hwfn,
  633. PROTOCOLID_ETH,
  634. p_pq_params);
  635. p_ramrod->qm_pq_id = cpu_to_le16(pq_id);
  636. return qed_spq_post(p_hwfn, p_ent, NULL);
  637. }
  638. static int
  639. qed_sp_eth_tx_queue_start(struct qed_hwfn *p_hwfn,
  640. u16 opaque_fid,
  641. struct qed_queue_start_common_params *p_params,
  642. dma_addr_t pbl_addr,
  643. u16 pbl_size,
  644. void __iomem **pp_doorbell)
  645. {
  646. struct qed_hw_cid_data *p_tx_cid;
  647. union qed_qm_pq_params pq_params;
  648. u8 abs_stats_id = 0;
  649. int rc;
  650. rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_stats_id);
  651. if (rc)
  652. return rc;
  653. p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id];
  654. memset(p_tx_cid, 0, sizeof(*p_tx_cid));
  655. memset(&pq_params, 0, sizeof(pq_params));
  656. /* Allocate a CID for the queue */
  657. rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH,
  658. &p_tx_cid->cid);
  659. if (rc) {
  660. DP_NOTICE(p_hwfn, "Failed to acquire cid\n");
  661. return rc;
  662. }
  663. p_tx_cid->b_cid_allocated = true;
  664. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  665. "opaque_fid=0x%x, cid=0x%x, tx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
  666. opaque_fid, p_tx_cid->cid,
  667. p_params->queue_id, p_params->vport_id, p_params->sb);
  668. rc = qed_sp_eth_txq_start_ramrod(p_hwfn,
  669. opaque_fid,
  670. p_tx_cid->cid,
  671. p_params,
  672. abs_stats_id,
  673. pbl_addr,
  674. pbl_size,
  675. &pq_params);
  676. *pp_doorbell = (u8 __iomem *)p_hwfn->doorbells +
  677. qed_db_addr(p_tx_cid->cid, DQ_DEMS_LEGACY);
  678. if (rc)
  679. qed_sp_release_queue_cid(p_hwfn, p_tx_cid);
  680. return rc;
  681. }
  682. static int qed_sp_eth_tx_queue_stop(struct qed_hwfn *p_hwfn,
  683. u16 tx_queue_id)
  684. {
  685. struct qed_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
  686. struct qed_spq_entry *p_ent = NULL;
  687. struct qed_sp_init_data init_data;
  688. int rc = -EINVAL;
  689. /* Get SPQ entry */
  690. memset(&init_data, 0, sizeof(init_data));
  691. init_data.cid = p_tx_cid->cid;
  692. init_data.opaque_fid = p_tx_cid->opaque_fid;
  693. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  694. rc = qed_sp_init_request(p_hwfn, &p_ent,
  695. ETH_RAMROD_TX_QUEUE_STOP,
  696. PROTOCOLID_ETH, &init_data);
  697. if (rc)
  698. return rc;
  699. rc = qed_spq_post(p_hwfn, p_ent, NULL);
  700. if (rc)
  701. return rc;
  702. return qed_sp_release_queue_cid(p_hwfn, p_tx_cid);
  703. }
  704. static enum eth_filter_action
  705. qed_filter_action(enum qed_filter_opcode opcode)
  706. {
  707. enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
  708. switch (opcode) {
  709. case QED_FILTER_ADD:
  710. action = ETH_FILTER_ACTION_ADD;
  711. break;
  712. case QED_FILTER_REMOVE:
  713. action = ETH_FILTER_ACTION_REMOVE;
  714. break;
  715. case QED_FILTER_FLUSH:
  716. action = ETH_FILTER_ACTION_REMOVE_ALL;
  717. break;
  718. default:
  719. action = MAX_ETH_FILTER_ACTION;
  720. }
  721. return action;
  722. }
  723. static void qed_set_fw_mac_addr(__le16 *fw_msb,
  724. __le16 *fw_mid,
  725. __le16 *fw_lsb,
  726. u8 *mac)
  727. {
  728. ((u8 *)fw_msb)[0] = mac[1];
  729. ((u8 *)fw_msb)[1] = mac[0];
  730. ((u8 *)fw_mid)[0] = mac[3];
  731. ((u8 *)fw_mid)[1] = mac[2];
  732. ((u8 *)fw_lsb)[0] = mac[5];
  733. ((u8 *)fw_lsb)[1] = mac[4];
  734. }
  735. static int
  736. qed_filter_ucast_common(struct qed_hwfn *p_hwfn,
  737. u16 opaque_fid,
  738. struct qed_filter_ucast *p_filter_cmd,
  739. struct vport_filter_update_ramrod_data **pp_ramrod,
  740. struct qed_spq_entry **pp_ent,
  741. enum spq_mode comp_mode,
  742. struct qed_spq_comp_cb *p_comp_data)
  743. {
  744. u8 vport_to_add_to = 0, vport_to_remove_from = 0;
  745. struct vport_filter_update_ramrod_data *p_ramrod;
  746. struct eth_filter_cmd *p_first_filter;
  747. struct eth_filter_cmd *p_second_filter;
  748. struct qed_sp_init_data init_data;
  749. enum eth_filter_action action;
  750. int rc;
  751. rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
  752. &vport_to_remove_from);
  753. if (rc)
  754. return rc;
  755. rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
  756. &vport_to_add_to);
  757. if (rc)
  758. return rc;
  759. /* Get SPQ entry */
  760. memset(&init_data, 0, sizeof(init_data));
  761. init_data.cid = qed_spq_get_cid(p_hwfn);
  762. init_data.opaque_fid = opaque_fid;
  763. init_data.comp_mode = comp_mode;
  764. init_data.p_comp_data = p_comp_data;
  765. rc = qed_sp_init_request(p_hwfn, pp_ent,
  766. ETH_RAMROD_FILTERS_UPDATE,
  767. PROTOCOLID_ETH, &init_data);
  768. if (rc)
  769. return rc;
  770. *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
  771. p_ramrod = *pp_ramrod;
  772. p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
  773. p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
  774. switch (p_filter_cmd->opcode) {
  775. case QED_FILTER_REPLACE:
  776. case QED_FILTER_MOVE:
  777. p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break;
  778. default:
  779. p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break;
  780. }
  781. p_first_filter = &p_ramrod->filter_cmds[0];
  782. p_second_filter = &p_ramrod->filter_cmds[1];
  783. switch (p_filter_cmd->type) {
  784. case QED_FILTER_MAC:
  785. p_first_filter->type = ETH_FILTER_TYPE_MAC; break;
  786. case QED_FILTER_VLAN:
  787. p_first_filter->type = ETH_FILTER_TYPE_VLAN; break;
  788. case QED_FILTER_MAC_VLAN:
  789. p_first_filter->type = ETH_FILTER_TYPE_PAIR; break;
  790. case QED_FILTER_INNER_MAC:
  791. p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break;
  792. case QED_FILTER_INNER_VLAN:
  793. p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break;
  794. case QED_FILTER_INNER_PAIR:
  795. p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break;
  796. case QED_FILTER_INNER_MAC_VNI_PAIR:
  797. p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
  798. break;
  799. case QED_FILTER_MAC_VNI_PAIR:
  800. p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break;
  801. case QED_FILTER_VNI:
  802. p_first_filter->type = ETH_FILTER_TYPE_VNI; break;
  803. }
  804. if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
  805. (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
  806. (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
  807. (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
  808. (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
  809. (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) {
  810. qed_set_fw_mac_addr(&p_first_filter->mac_msb,
  811. &p_first_filter->mac_mid,
  812. &p_first_filter->mac_lsb,
  813. (u8 *)p_filter_cmd->mac);
  814. }
  815. if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
  816. (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
  817. (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
  818. (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
  819. p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan);
  820. if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
  821. (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
  822. (p_first_filter->type == ETH_FILTER_TYPE_VNI))
  823. p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni);
  824. if (p_filter_cmd->opcode == QED_FILTER_MOVE) {
  825. p_second_filter->type = p_first_filter->type;
  826. p_second_filter->mac_msb = p_first_filter->mac_msb;
  827. p_second_filter->mac_mid = p_first_filter->mac_mid;
  828. p_second_filter->mac_lsb = p_first_filter->mac_lsb;
  829. p_second_filter->vlan_id = p_first_filter->vlan_id;
  830. p_second_filter->vni = p_first_filter->vni;
  831. p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
  832. p_first_filter->vport_id = vport_to_remove_from;
  833. p_second_filter->action = ETH_FILTER_ACTION_ADD;
  834. p_second_filter->vport_id = vport_to_add_to;
  835. } else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) {
  836. p_first_filter->vport_id = vport_to_add_to;
  837. memcpy(p_second_filter, p_first_filter,
  838. sizeof(*p_second_filter));
  839. p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL;
  840. p_second_filter->action = ETH_FILTER_ACTION_ADD;
  841. } else {
  842. action = qed_filter_action(p_filter_cmd->opcode);
  843. if (action == MAX_ETH_FILTER_ACTION) {
  844. DP_NOTICE(p_hwfn,
  845. "%d is not supported yet\n",
  846. p_filter_cmd->opcode);
  847. return -EINVAL;
  848. }
  849. p_first_filter->action = action;
  850. p_first_filter->vport_id = (p_filter_cmd->opcode ==
  851. QED_FILTER_REMOVE) ?
  852. vport_to_remove_from :
  853. vport_to_add_to;
  854. }
  855. return 0;
  856. }
  857. static int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn,
  858. u16 opaque_fid,
  859. struct qed_filter_ucast *p_filter_cmd,
  860. enum spq_mode comp_mode,
  861. struct qed_spq_comp_cb *p_comp_data)
  862. {
  863. struct vport_filter_update_ramrod_data *p_ramrod = NULL;
  864. struct qed_spq_entry *p_ent = NULL;
  865. struct eth_filter_cmd_header *p_header;
  866. int rc;
  867. rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
  868. &p_ramrod, &p_ent,
  869. comp_mode, p_comp_data);
  870. if (rc != 0) {
  871. DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
  872. return rc;
  873. }
  874. p_header = &p_ramrod->filter_cmd_hdr;
  875. p_header->assert_on_error = p_filter_cmd->assert_on_error;
  876. rc = qed_spq_post(p_hwfn, p_ent, NULL);
  877. if (rc != 0) {
  878. DP_ERR(p_hwfn,
  879. "Unicast filter ADD command failed %d\n",
  880. rc);
  881. return rc;
  882. }
  883. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  884. "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
  885. (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" :
  886. ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ?
  887. "REMOVE" :
  888. ((p_filter_cmd->opcode == QED_FILTER_MOVE) ?
  889. "MOVE" : "REPLACE")),
  890. (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" :
  891. ((p_filter_cmd->type == QED_FILTER_VLAN) ?
  892. "VLAN" : "MAC & VLAN"),
  893. p_ramrod->filter_cmd_hdr.cmd_cnt,
  894. p_filter_cmd->is_rx_filter,
  895. p_filter_cmd->is_tx_filter);
  896. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  897. "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
  898. p_filter_cmd->vport_to_add_to,
  899. p_filter_cmd->vport_to_remove_from,
  900. p_filter_cmd->mac[0],
  901. p_filter_cmd->mac[1],
  902. p_filter_cmd->mac[2],
  903. p_filter_cmd->mac[3],
  904. p_filter_cmd->mac[4],
  905. p_filter_cmd->mac[5],
  906. p_filter_cmd->vlan);
  907. return 0;
  908. }
  909. /*******************************************************************************
  910. * Description:
  911. * Calculates crc 32 on a buffer
  912. * Note: crc32_length MUST be aligned to 8
  913. * Return:
  914. ******************************************************************************/
  915. static u32 qed_calc_crc32c(u8 *crc32_packet,
  916. u32 crc32_length,
  917. u32 crc32_seed,
  918. u8 complement)
  919. {
  920. u32 byte = 0;
  921. u32 bit = 0;
  922. u8 msb = 0;
  923. u8 current_byte = 0;
  924. u32 crc32_result = crc32_seed;
  925. if ((!crc32_packet) ||
  926. (crc32_length == 0) ||
  927. ((crc32_length % 8) != 0))
  928. return crc32_result;
  929. for (byte = 0; byte < crc32_length; byte++) {
  930. current_byte = crc32_packet[byte];
  931. for (bit = 0; bit < 8; bit++) {
  932. msb = (u8)(crc32_result >> 31);
  933. crc32_result = crc32_result << 1;
  934. if (msb != (0x1 & (current_byte >> bit))) {
  935. crc32_result = crc32_result ^ CRC32_POLY;
  936. crc32_result |= 1; /*crc32_result[0] = 1;*/
  937. }
  938. }
  939. }
  940. return crc32_result;
  941. }
  942. static inline u32 qed_crc32c_le(u32 seed,
  943. u8 *mac,
  944. u32 len)
  945. {
  946. u32 packet_buf[2] = { 0 };
  947. memcpy((u8 *)(&packet_buf[0]), &mac[0], 6);
  948. return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
  949. }
  950. static u8 qed_mcast_bin_from_mac(u8 *mac)
  951. {
  952. u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
  953. mac, ETH_ALEN);
  954. return crc & 0xff;
  955. }
  956. static int
  957. qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn,
  958. u16 opaque_fid,
  959. struct qed_filter_mcast *p_filter_cmd,
  960. enum spq_mode comp_mode,
  961. struct qed_spq_comp_cb *p_comp_data)
  962. {
  963. unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
  964. struct vport_update_ramrod_data *p_ramrod = NULL;
  965. struct qed_spq_entry *p_ent = NULL;
  966. struct qed_sp_init_data init_data;
  967. u8 abs_vport_id = 0;
  968. int rc, i;
  969. if (p_filter_cmd->opcode == QED_FILTER_ADD) {
  970. rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
  971. &abs_vport_id);
  972. if (rc)
  973. return rc;
  974. } else {
  975. rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
  976. &abs_vport_id);
  977. if (rc)
  978. return rc;
  979. }
  980. /* Get SPQ entry */
  981. memset(&init_data, 0, sizeof(init_data));
  982. init_data.cid = qed_spq_get_cid(p_hwfn);
  983. init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
  984. init_data.comp_mode = comp_mode;
  985. init_data.p_comp_data = p_comp_data;
  986. rc = qed_sp_init_request(p_hwfn, &p_ent,
  987. ETH_RAMROD_VPORT_UPDATE,
  988. PROTOCOLID_ETH, &init_data);
  989. if (rc) {
  990. DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
  991. return rc;
  992. }
  993. p_ramrod = &p_ent->ramrod.vport_update;
  994. p_ramrod->common.update_approx_mcast_flg = 1;
  995. /* explicitly clear out the entire vector */
  996. memset(&p_ramrod->approx_mcast.bins, 0,
  997. sizeof(p_ramrod->approx_mcast.bins));
  998. memset(bins, 0, sizeof(unsigned long) *
  999. ETH_MULTICAST_MAC_BINS_IN_REGS);
  1000. /* filter ADD op is explicit set op and it removes
  1001. * any existing filters for the vport
  1002. */
  1003. if (p_filter_cmd->opcode == QED_FILTER_ADD) {
  1004. for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
  1005. u32 bit;
  1006. bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]);
  1007. __set_bit(bit, bins);
  1008. }
  1009. /* Convert to correct endianity */
  1010. for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
  1011. u32 *p_bins = (u32 *)bins;
  1012. struct vport_update_ramrod_mcast *approx_mcast;
  1013. approx_mcast = &p_ramrod->approx_mcast;
  1014. approx_mcast->bins[i] = cpu_to_le32(p_bins[i]);
  1015. }
  1016. }
  1017. p_ramrod->common.vport_id = abs_vport_id;
  1018. return qed_spq_post(p_hwfn, p_ent, NULL);
  1019. }
  1020. static int
  1021. qed_filter_mcast_cmd(struct qed_dev *cdev,
  1022. struct qed_filter_mcast *p_filter_cmd,
  1023. enum spq_mode comp_mode,
  1024. struct qed_spq_comp_cb *p_comp_data)
  1025. {
  1026. int rc = 0;
  1027. int i;
  1028. /* only ADD and REMOVE operations are supported for multi-cast */
  1029. if ((p_filter_cmd->opcode != QED_FILTER_ADD &&
  1030. (p_filter_cmd->opcode != QED_FILTER_REMOVE)) ||
  1031. (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS))
  1032. return -EINVAL;
  1033. for_each_hwfn(cdev, i) {
  1034. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1035. u16 opaque_fid;
  1036. if (rc != 0)
  1037. break;
  1038. opaque_fid = p_hwfn->hw_info.opaque_fid;
  1039. rc = qed_sp_eth_filter_mcast(p_hwfn,
  1040. opaque_fid,
  1041. p_filter_cmd,
  1042. comp_mode,
  1043. p_comp_data);
  1044. }
  1045. return rc;
  1046. }
  1047. static int qed_filter_ucast_cmd(struct qed_dev *cdev,
  1048. struct qed_filter_ucast *p_filter_cmd,
  1049. enum spq_mode comp_mode,
  1050. struct qed_spq_comp_cb *p_comp_data)
  1051. {
  1052. int rc = 0;
  1053. int i;
  1054. for_each_hwfn(cdev, i) {
  1055. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1056. u16 opaque_fid;
  1057. if (rc != 0)
  1058. break;
  1059. opaque_fid = p_hwfn->hw_info.opaque_fid;
  1060. rc = qed_sp_eth_filter_ucast(p_hwfn,
  1061. opaque_fid,
  1062. p_filter_cmd,
  1063. comp_mode,
  1064. p_comp_data);
  1065. }
  1066. return rc;
  1067. }
  1068. /* Statistics related code */
  1069. static void __qed_get_vport_pstats_addrlen(struct qed_hwfn *p_hwfn,
  1070. u32 *p_addr,
  1071. u32 *p_len,
  1072. u16 statistics_bin)
  1073. {
  1074. *p_addr = BAR0_MAP_REG_PSDM_RAM +
  1075. PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
  1076. *p_len = sizeof(struct eth_pstorm_per_queue_stat);
  1077. }
  1078. static void __qed_get_vport_pstats(struct qed_hwfn *p_hwfn,
  1079. struct qed_ptt *p_ptt,
  1080. struct qed_eth_stats *p_stats,
  1081. u16 statistics_bin)
  1082. {
  1083. struct eth_pstorm_per_queue_stat pstats;
  1084. u32 pstats_addr = 0, pstats_len = 0;
  1085. __qed_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
  1086. statistics_bin);
  1087. memset(&pstats, 0, sizeof(pstats));
  1088. qed_memcpy_from(p_hwfn, p_ptt, &pstats,
  1089. pstats_addr, pstats_len);
  1090. p_stats->tx_ucast_bytes +=
  1091. HILO_64_REGPAIR(pstats.sent_ucast_bytes);
  1092. p_stats->tx_mcast_bytes +=
  1093. HILO_64_REGPAIR(pstats.sent_mcast_bytes);
  1094. p_stats->tx_bcast_bytes +=
  1095. HILO_64_REGPAIR(pstats.sent_bcast_bytes);
  1096. p_stats->tx_ucast_pkts +=
  1097. HILO_64_REGPAIR(pstats.sent_ucast_pkts);
  1098. p_stats->tx_mcast_pkts +=
  1099. HILO_64_REGPAIR(pstats.sent_mcast_pkts);
  1100. p_stats->tx_bcast_pkts +=
  1101. HILO_64_REGPAIR(pstats.sent_bcast_pkts);
  1102. p_stats->tx_err_drop_pkts +=
  1103. HILO_64_REGPAIR(pstats.error_drop_pkts);
  1104. }
  1105. static void __qed_get_vport_tstats_addrlen(struct qed_hwfn *p_hwfn,
  1106. u32 *p_addr,
  1107. u32 *p_len)
  1108. {
  1109. *p_addr = BAR0_MAP_REG_TSDM_RAM +
  1110. TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
  1111. *p_len = sizeof(struct tstorm_per_port_stat);
  1112. }
  1113. static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn,
  1114. struct qed_ptt *p_ptt,
  1115. struct qed_eth_stats *p_stats,
  1116. u16 statistics_bin)
  1117. {
  1118. u32 tstats_addr = 0, tstats_len = 0;
  1119. struct tstorm_per_port_stat tstats;
  1120. __qed_get_vport_tstats_addrlen(p_hwfn, &tstats_addr, &tstats_len);
  1121. memset(&tstats, 0, sizeof(tstats));
  1122. qed_memcpy_from(p_hwfn, p_ptt, &tstats,
  1123. tstats_addr, tstats_len);
  1124. p_stats->mftag_filter_discards +=
  1125. HILO_64_REGPAIR(tstats.mftag_filter_discard);
  1126. p_stats->mac_filter_discards +=
  1127. HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
  1128. }
  1129. static void __qed_get_vport_ustats_addrlen(struct qed_hwfn *p_hwfn,
  1130. u32 *p_addr,
  1131. u32 *p_len,
  1132. u16 statistics_bin)
  1133. {
  1134. *p_addr = BAR0_MAP_REG_USDM_RAM +
  1135. USTORM_QUEUE_STAT_OFFSET(statistics_bin);
  1136. *p_len = sizeof(struct eth_ustorm_per_queue_stat);
  1137. }
  1138. static void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn,
  1139. struct qed_ptt *p_ptt,
  1140. struct qed_eth_stats *p_stats,
  1141. u16 statistics_bin)
  1142. {
  1143. struct eth_ustorm_per_queue_stat ustats;
  1144. u32 ustats_addr = 0, ustats_len = 0;
  1145. __qed_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
  1146. statistics_bin);
  1147. memset(&ustats, 0, sizeof(ustats));
  1148. qed_memcpy_from(p_hwfn, p_ptt, &ustats,
  1149. ustats_addr, ustats_len);
  1150. p_stats->rx_ucast_bytes +=
  1151. HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
  1152. p_stats->rx_mcast_bytes +=
  1153. HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
  1154. p_stats->rx_bcast_bytes +=
  1155. HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
  1156. p_stats->rx_ucast_pkts +=
  1157. HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
  1158. p_stats->rx_mcast_pkts +=
  1159. HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
  1160. p_stats->rx_bcast_pkts +=
  1161. HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
  1162. }
  1163. static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn,
  1164. u32 *p_addr,
  1165. u32 *p_len,
  1166. u16 statistics_bin)
  1167. {
  1168. *p_addr = BAR0_MAP_REG_MSDM_RAM +
  1169. MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
  1170. *p_len = sizeof(struct eth_mstorm_per_queue_stat);
  1171. }
  1172. static void __qed_get_vport_mstats(struct qed_hwfn *p_hwfn,
  1173. struct qed_ptt *p_ptt,
  1174. struct qed_eth_stats *p_stats,
  1175. u16 statistics_bin)
  1176. {
  1177. struct eth_mstorm_per_queue_stat mstats;
  1178. u32 mstats_addr = 0, mstats_len = 0;
  1179. __qed_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
  1180. statistics_bin);
  1181. memset(&mstats, 0, sizeof(mstats));
  1182. qed_memcpy_from(p_hwfn, p_ptt, &mstats,
  1183. mstats_addr, mstats_len);
  1184. p_stats->no_buff_discards +=
  1185. HILO_64_REGPAIR(mstats.no_buff_discard);
  1186. p_stats->packet_too_big_discard +=
  1187. HILO_64_REGPAIR(mstats.packet_too_big_discard);
  1188. p_stats->ttl0_discard +=
  1189. HILO_64_REGPAIR(mstats.ttl0_discard);
  1190. p_stats->tpa_coalesced_pkts +=
  1191. HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
  1192. p_stats->tpa_coalesced_events +=
  1193. HILO_64_REGPAIR(mstats.tpa_coalesced_events);
  1194. p_stats->tpa_aborts_num +=
  1195. HILO_64_REGPAIR(mstats.tpa_aborts_num);
  1196. p_stats->tpa_coalesced_bytes +=
  1197. HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
  1198. }
  1199. static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn,
  1200. struct qed_ptt *p_ptt,
  1201. struct qed_eth_stats *p_stats)
  1202. {
  1203. struct port_stats port_stats;
  1204. int j;
  1205. memset(&port_stats, 0, sizeof(port_stats));
  1206. qed_memcpy_from(p_hwfn, p_ptt, &port_stats,
  1207. p_hwfn->mcp_info->port_addr +
  1208. offsetof(struct public_port, stats),
  1209. sizeof(port_stats));
  1210. p_stats->rx_64_byte_packets += port_stats.pmm.r64;
  1211. p_stats->rx_127_byte_packets += port_stats.pmm.r127;
  1212. p_stats->rx_255_byte_packets += port_stats.pmm.r255;
  1213. p_stats->rx_511_byte_packets += port_stats.pmm.r511;
  1214. p_stats->rx_1023_byte_packets += port_stats.pmm.r1023;
  1215. p_stats->rx_1518_byte_packets += port_stats.pmm.r1518;
  1216. p_stats->rx_1522_byte_packets += port_stats.pmm.r1522;
  1217. p_stats->rx_2047_byte_packets += port_stats.pmm.r2047;
  1218. p_stats->rx_4095_byte_packets += port_stats.pmm.r4095;
  1219. p_stats->rx_9216_byte_packets += port_stats.pmm.r9216;
  1220. p_stats->rx_16383_byte_packets += port_stats.pmm.r16383;
  1221. p_stats->rx_crc_errors += port_stats.pmm.rfcs;
  1222. p_stats->rx_mac_crtl_frames += port_stats.pmm.rxcf;
  1223. p_stats->rx_pause_frames += port_stats.pmm.rxpf;
  1224. p_stats->rx_pfc_frames += port_stats.pmm.rxpp;
  1225. p_stats->rx_align_errors += port_stats.pmm.raln;
  1226. p_stats->rx_carrier_errors += port_stats.pmm.rfcr;
  1227. p_stats->rx_oversize_packets += port_stats.pmm.rovr;
  1228. p_stats->rx_jabbers += port_stats.pmm.rjbr;
  1229. p_stats->rx_undersize_packets += port_stats.pmm.rund;
  1230. p_stats->rx_fragments += port_stats.pmm.rfrg;
  1231. p_stats->tx_64_byte_packets += port_stats.pmm.t64;
  1232. p_stats->tx_65_to_127_byte_packets += port_stats.pmm.t127;
  1233. p_stats->tx_128_to_255_byte_packets += port_stats.pmm.t255;
  1234. p_stats->tx_256_to_511_byte_packets += port_stats.pmm.t511;
  1235. p_stats->tx_512_to_1023_byte_packets += port_stats.pmm.t1023;
  1236. p_stats->tx_1024_to_1518_byte_packets += port_stats.pmm.t1518;
  1237. p_stats->tx_1519_to_2047_byte_packets += port_stats.pmm.t2047;
  1238. p_stats->tx_2048_to_4095_byte_packets += port_stats.pmm.t4095;
  1239. p_stats->tx_4096_to_9216_byte_packets += port_stats.pmm.t9216;
  1240. p_stats->tx_9217_to_16383_byte_packets += port_stats.pmm.t16383;
  1241. p_stats->tx_pause_frames += port_stats.pmm.txpf;
  1242. p_stats->tx_pfc_frames += port_stats.pmm.txpp;
  1243. p_stats->tx_lpi_entry_count += port_stats.pmm.tlpiec;
  1244. p_stats->tx_total_collisions += port_stats.pmm.tncl;
  1245. p_stats->rx_mac_bytes += port_stats.pmm.rbyte;
  1246. p_stats->rx_mac_uc_packets += port_stats.pmm.rxuca;
  1247. p_stats->rx_mac_mc_packets += port_stats.pmm.rxmca;
  1248. p_stats->rx_mac_bc_packets += port_stats.pmm.rxbca;
  1249. p_stats->rx_mac_frames_ok += port_stats.pmm.rxpok;
  1250. p_stats->tx_mac_bytes += port_stats.pmm.tbyte;
  1251. p_stats->tx_mac_uc_packets += port_stats.pmm.txuca;
  1252. p_stats->tx_mac_mc_packets += port_stats.pmm.txmca;
  1253. p_stats->tx_mac_bc_packets += port_stats.pmm.txbca;
  1254. p_stats->tx_mac_ctrl_frames += port_stats.pmm.txcf;
  1255. for (j = 0; j < 8; j++) {
  1256. p_stats->brb_truncates += port_stats.brb.brb_truncate[j];
  1257. p_stats->brb_discards += port_stats.brb.brb_discard[j];
  1258. }
  1259. }
  1260. static void __qed_get_vport_stats(struct qed_hwfn *p_hwfn,
  1261. struct qed_ptt *p_ptt,
  1262. struct qed_eth_stats *stats,
  1263. u16 statistics_bin)
  1264. {
  1265. __qed_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
  1266. __qed_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
  1267. __qed_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin);
  1268. __qed_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
  1269. if (p_hwfn->mcp_info)
  1270. __qed_get_vport_port_stats(p_hwfn, p_ptt, stats);
  1271. }
  1272. static void _qed_get_vport_stats(struct qed_dev *cdev,
  1273. struct qed_eth_stats *stats)
  1274. {
  1275. u8 fw_vport = 0;
  1276. int i;
  1277. memset(stats, 0, sizeof(*stats));
  1278. for_each_hwfn(cdev, i) {
  1279. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1280. struct qed_ptt *p_ptt;
  1281. /* The main vport index is relative first */
  1282. if (qed_fw_vport(p_hwfn, 0, &fw_vport)) {
  1283. DP_ERR(p_hwfn, "No vport available!\n");
  1284. continue;
  1285. }
  1286. p_ptt = qed_ptt_acquire(p_hwfn);
  1287. if (!p_ptt) {
  1288. DP_ERR(p_hwfn, "Failed to acquire ptt\n");
  1289. continue;
  1290. }
  1291. __qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport);
  1292. qed_ptt_release(p_hwfn, p_ptt);
  1293. }
  1294. }
  1295. void qed_get_vport_stats(struct qed_dev *cdev,
  1296. struct qed_eth_stats *stats)
  1297. {
  1298. u32 i;
  1299. if (!cdev) {
  1300. memset(stats, 0, sizeof(*stats));
  1301. return;
  1302. }
  1303. _qed_get_vport_stats(cdev, stats);
  1304. if (!cdev->reset_stats)
  1305. return;
  1306. /* Reduce the statistics baseline */
  1307. for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++)
  1308. ((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i];
  1309. }
  1310. /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
  1311. void qed_reset_vport_stats(struct qed_dev *cdev)
  1312. {
  1313. int i;
  1314. for_each_hwfn(cdev, i) {
  1315. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1316. struct eth_mstorm_per_queue_stat mstats;
  1317. struct eth_ustorm_per_queue_stat ustats;
  1318. struct eth_pstorm_per_queue_stat pstats;
  1319. struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
  1320. u32 addr = 0, len = 0;
  1321. if (!p_ptt) {
  1322. DP_ERR(p_hwfn, "Failed to acquire ptt\n");
  1323. continue;
  1324. }
  1325. memset(&mstats, 0, sizeof(mstats));
  1326. __qed_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
  1327. qed_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
  1328. memset(&ustats, 0, sizeof(ustats));
  1329. __qed_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
  1330. qed_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
  1331. memset(&pstats, 0, sizeof(pstats));
  1332. __qed_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
  1333. qed_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
  1334. qed_ptt_release(p_hwfn, p_ptt);
  1335. }
  1336. /* PORT statistics are not necessarily reset, so we need to
  1337. * read and create a baseline for future statistics.
  1338. */
  1339. if (!cdev->reset_stats)
  1340. DP_INFO(cdev, "Reset stats not allocated\n");
  1341. else
  1342. _qed_get_vport_stats(cdev, cdev->reset_stats);
  1343. }
  1344. static int qed_fill_eth_dev_info(struct qed_dev *cdev,
  1345. struct qed_dev_eth_info *info)
  1346. {
  1347. int i;
  1348. memset(info, 0, sizeof(*info));
  1349. info->num_tc = 1;
  1350. if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
  1351. for_each_hwfn(cdev, i)
  1352. info->num_queues += FEAT_NUM(&cdev->hwfns[i],
  1353. QED_PF_L2_QUE);
  1354. if (cdev->int_params.fp_msix_cnt)
  1355. info->num_queues = min_t(u8, info->num_queues,
  1356. cdev->int_params.fp_msix_cnt);
  1357. } else {
  1358. info->num_queues = cdev->num_hwfns;
  1359. }
  1360. info->num_vlan_filters = RESC_NUM(&cdev->hwfns[0], QED_VLAN);
  1361. ether_addr_copy(info->port_mac,
  1362. cdev->hwfns[0].hw_info.hw_mac_addr);
  1363. qed_fill_dev_info(cdev, &info->common);
  1364. return 0;
  1365. }
  1366. static void qed_register_eth_ops(struct qed_dev *cdev,
  1367. struct qed_eth_cb_ops *ops,
  1368. void *cookie)
  1369. {
  1370. cdev->protocol_ops.eth = ops;
  1371. cdev->ops_cookie = cookie;
  1372. }
  1373. static int qed_start_vport(struct qed_dev *cdev,
  1374. struct qed_start_vport_params *params)
  1375. {
  1376. int rc, i;
  1377. for_each_hwfn(cdev, i) {
  1378. struct qed_sp_vport_start_params start = { 0 };
  1379. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1380. start.tpa_mode = params->gro_enable ? QED_TPA_MODE_GRO :
  1381. QED_TPA_MODE_NONE;
  1382. start.remove_inner_vlan = params->remove_inner_vlan;
  1383. start.drop_ttl0 = params->drop_ttl0;
  1384. start.opaque_fid = p_hwfn->hw_info.opaque_fid;
  1385. start.concrete_fid = p_hwfn->hw_info.concrete_fid;
  1386. start.vport_id = params->vport_id;
  1387. start.max_buffers_per_cqe = 16;
  1388. start.mtu = params->mtu;
  1389. rc = qed_sp_vport_start(p_hwfn, &start);
  1390. if (rc) {
  1391. DP_ERR(cdev, "Failed to start VPORT\n");
  1392. return rc;
  1393. }
  1394. qed_hw_start_fastpath(p_hwfn);
  1395. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  1396. "Started V-PORT %d with MTU %d\n",
  1397. start.vport_id, start.mtu);
  1398. }
  1399. qed_reset_vport_stats(cdev);
  1400. return 0;
  1401. }
  1402. static int qed_stop_vport(struct qed_dev *cdev,
  1403. u8 vport_id)
  1404. {
  1405. int rc, i;
  1406. for_each_hwfn(cdev, i) {
  1407. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1408. rc = qed_sp_vport_stop(p_hwfn,
  1409. p_hwfn->hw_info.opaque_fid,
  1410. vport_id);
  1411. if (rc) {
  1412. DP_ERR(cdev, "Failed to stop VPORT\n");
  1413. return rc;
  1414. }
  1415. }
  1416. return 0;
  1417. }
  1418. static int qed_update_vport(struct qed_dev *cdev,
  1419. struct qed_update_vport_params *params)
  1420. {
  1421. struct qed_sp_vport_update_params sp_params;
  1422. struct qed_rss_params sp_rss_params;
  1423. int rc, i;
  1424. if (!cdev)
  1425. return -ENODEV;
  1426. memset(&sp_params, 0, sizeof(sp_params));
  1427. memset(&sp_rss_params, 0, sizeof(sp_rss_params));
  1428. /* Translate protocol params into sp params */
  1429. sp_params.vport_id = params->vport_id;
  1430. sp_params.update_vport_active_rx_flg =
  1431. params->update_vport_active_flg;
  1432. sp_params.update_vport_active_tx_flg =
  1433. params->update_vport_active_flg;
  1434. sp_params.vport_active_rx_flg = params->vport_active_flg;
  1435. sp_params.vport_active_tx_flg = params->vport_active_flg;
  1436. sp_params.accept_any_vlan = params->accept_any_vlan;
  1437. sp_params.update_accept_any_vlan_flg =
  1438. params->update_accept_any_vlan_flg;
  1439. /* RSS - is a bit tricky, since upper-layer isn't familiar with hwfns.
  1440. * We need to re-fix the rss values per engine for CMT.
  1441. */
  1442. if (cdev->num_hwfns > 1 && params->update_rss_flg) {
  1443. struct qed_update_vport_rss_params *rss =
  1444. &params->rss_params;
  1445. int k, max = 0;
  1446. /* Find largest entry, since it's possible RSS needs to
  1447. * be disabled [in case only 1 queue per-hwfn]
  1448. */
  1449. for (k = 0; k < QED_RSS_IND_TABLE_SIZE; k++)
  1450. max = (max > rss->rss_ind_table[k]) ?
  1451. max : rss->rss_ind_table[k];
  1452. /* Either fix RSS values or disable RSS */
  1453. if (cdev->num_hwfns < max + 1) {
  1454. int divisor = (max + cdev->num_hwfns - 1) /
  1455. cdev->num_hwfns;
  1456. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  1457. "CMT - fixing RSS values (modulo %02x)\n",
  1458. divisor);
  1459. for (k = 0; k < QED_RSS_IND_TABLE_SIZE; k++)
  1460. rss->rss_ind_table[k] =
  1461. rss->rss_ind_table[k] % divisor;
  1462. } else {
  1463. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  1464. "CMT - 1 queue per-hwfn; Disabling RSS\n");
  1465. params->update_rss_flg = 0;
  1466. }
  1467. }
  1468. /* Now, update the RSS configuration for actual configuration */
  1469. if (params->update_rss_flg) {
  1470. sp_rss_params.update_rss_config = 1;
  1471. sp_rss_params.rss_enable = 1;
  1472. sp_rss_params.update_rss_capabilities = 1;
  1473. sp_rss_params.update_rss_ind_table = 1;
  1474. sp_rss_params.update_rss_key = 1;
  1475. sp_rss_params.rss_caps = QED_RSS_IPV4 |
  1476. QED_RSS_IPV6 |
  1477. QED_RSS_IPV4_TCP | QED_RSS_IPV6_TCP;
  1478. sp_rss_params.rss_table_size_log = 7; /* 2^7 = 128 */
  1479. memcpy(sp_rss_params.rss_ind_table,
  1480. params->rss_params.rss_ind_table,
  1481. QED_RSS_IND_TABLE_SIZE * sizeof(u16));
  1482. memcpy(sp_rss_params.rss_key, params->rss_params.rss_key,
  1483. QED_RSS_KEY_SIZE * sizeof(u32));
  1484. }
  1485. sp_params.rss_params = &sp_rss_params;
  1486. for_each_hwfn(cdev, i) {
  1487. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1488. sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
  1489. rc = qed_sp_vport_update(p_hwfn, &sp_params,
  1490. QED_SPQ_MODE_EBLOCK,
  1491. NULL);
  1492. if (rc) {
  1493. DP_ERR(cdev, "Failed to update VPORT\n");
  1494. return rc;
  1495. }
  1496. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  1497. "Updated V-PORT %d: active_flag %d [update %d]\n",
  1498. params->vport_id, params->vport_active_flg,
  1499. params->update_vport_active_flg);
  1500. }
  1501. return 0;
  1502. }
  1503. static int qed_start_rxq(struct qed_dev *cdev,
  1504. struct qed_queue_start_common_params *params,
  1505. u16 bd_max_bytes,
  1506. dma_addr_t bd_chain_phys_addr,
  1507. dma_addr_t cqe_pbl_addr,
  1508. u16 cqe_pbl_size,
  1509. void __iomem **pp_prod)
  1510. {
  1511. int rc, hwfn_index;
  1512. struct qed_hwfn *p_hwfn;
  1513. hwfn_index = params->rss_id % cdev->num_hwfns;
  1514. p_hwfn = &cdev->hwfns[hwfn_index];
  1515. /* Fix queue ID in 100g mode */
  1516. params->queue_id /= cdev->num_hwfns;
  1517. rc = qed_sp_eth_rx_queue_start(p_hwfn,
  1518. p_hwfn->hw_info.opaque_fid,
  1519. params,
  1520. bd_max_bytes,
  1521. bd_chain_phys_addr,
  1522. cqe_pbl_addr,
  1523. cqe_pbl_size,
  1524. pp_prod);
  1525. if (rc) {
  1526. DP_ERR(cdev, "Failed to start RXQ#%d\n", params->queue_id);
  1527. return rc;
  1528. }
  1529. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  1530. "Started RX-Q %d [rss %d] on V-PORT %d and SB %d\n",
  1531. params->queue_id, params->rss_id, params->vport_id,
  1532. params->sb);
  1533. return 0;
  1534. }
  1535. static int qed_stop_rxq(struct qed_dev *cdev,
  1536. struct qed_stop_rxq_params *params)
  1537. {
  1538. int rc, hwfn_index;
  1539. struct qed_hwfn *p_hwfn;
  1540. hwfn_index = params->rss_id % cdev->num_hwfns;
  1541. p_hwfn = &cdev->hwfns[hwfn_index];
  1542. rc = qed_sp_eth_rx_queue_stop(p_hwfn,
  1543. params->rx_queue_id / cdev->num_hwfns,
  1544. params->eq_completion_only,
  1545. false);
  1546. if (rc) {
  1547. DP_ERR(cdev, "Failed to stop RXQ#%d\n", params->rx_queue_id);
  1548. return rc;
  1549. }
  1550. return 0;
  1551. }
  1552. static int qed_start_txq(struct qed_dev *cdev,
  1553. struct qed_queue_start_common_params *p_params,
  1554. dma_addr_t pbl_addr,
  1555. u16 pbl_size,
  1556. void __iomem **pp_doorbell)
  1557. {
  1558. struct qed_hwfn *p_hwfn;
  1559. int rc, hwfn_index;
  1560. hwfn_index = p_params->rss_id % cdev->num_hwfns;
  1561. p_hwfn = &cdev->hwfns[hwfn_index];
  1562. /* Fix queue ID in 100g mode */
  1563. p_params->queue_id /= cdev->num_hwfns;
  1564. rc = qed_sp_eth_tx_queue_start(p_hwfn,
  1565. p_hwfn->hw_info.opaque_fid,
  1566. p_params,
  1567. pbl_addr,
  1568. pbl_size,
  1569. pp_doorbell);
  1570. if (rc) {
  1571. DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id);
  1572. return rc;
  1573. }
  1574. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  1575. "Started TX-Q %d [rss %d] on V-PORT %d and SB %d\n",
  1576. p_params->queue_id, p_params->rss_id, p_params->vport_id,
  1577. p_params->sb);
  1578. return 0;
  1579. }
  1580. #define QED_HW_STOP_RETRY_LIMIT (10)
  1581. static int qed_fastpath_stop(struct qed_dev *cdev)
  1582. {
  1583. qed_hw_stop_fastpath(cdev);
  1584. return 0;
  1585. }
  1586. static int qed_stop_txq(struct qed_dev *cdev,
  1587. struct qed_stop_txq_params *params)
  1588. {
  1589. struct qed_hwfn *p_hwfn;
  1590. int rc, hwfn_index;
  1591. hwfn_index = params->rss_id % cdev->num_hwfns;
  1592. p_hwfn = &cdev->hwfns[hwfn_index];
  1593. rc = qed_sp_eth_tx_queue_stop(p_hwfn,
  1594. params->tx_queue_id / cdev->num_hwfns);
  1595. if (rc) {
  1596. DP_ERR(cdev, "Failed to stop TXQ#%d\n", params->tx_queue_id);
  1597. return rc;
  1598. }
  1599. return 0;
  1600. }
  1601. static int qed_configure_filter_rx_mode(struct qed_dev *cdev,
  1602. enum qed_filter_rx_mode_type type)
  1603. {
  1604. struct qed_filter_accept_flags accept_flags;
  1605. memset(&accept_flags, 0, sizeof(accept_flags));
  1606. accept_flags.update_rx_mode_config = 1;
  1607. accept_flags.update_tx_mode_config = 1;
  1608. accept_flags.rx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
  1609. QED_ACCEPT_MCAST_MATCHED |
  1610. QED_ACCEPT_BCAST;
  1611. accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
  1612. QED_ACCEPT_MCAST_MATCHED |
  1613. QED_ACCEPT_BCAST;
  1614. if (type == QED_FILTER_RX_MODE_TYPE_PROMISC)
  1615. accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED |
  1616. QED_ACCEPT_MCAST_UNMATCHED;
  1617. else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC)
  1618. accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
  1619. return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false,
  1620. QED_SPQ_MODE_CB, NULL);
  1621. }
  1622. static int qed_configure_filter_ucast(struct qed_dev *cdev,
  1623. struct qed_filter_ucast_params *params)
  1624. {
  1625. struct qed_filter_ucast ucast;
  1626. if (!params->vlan_valid && !params->mac_valid) {
  1627. DP_NOTICE(
  1628. cdev,
  1629. "Tried configuring a unicast filter, but both MAC and VLAN are not set\n");
  1630. return -EINVAL;
  1631. }
  1632. memset(&ucast, 0, sizeof(ucast));
  1633. switch (params->type) {
  1634. case QED_FILTER_XCAST_TYPE_ADD:
  1635. ucast.opcode = QED_FILTER_ADD;
  1636. break;
  1637. case QED_FILTER_XCAST_TYPE_DEL:
  1638. ucast.opcode = QED_FILTER_REMOVE;
  1639. break;
  1640. case QED_FILTER_XCAST_TYPE_REPLACE:
  1641. ucast.opcode = QED_FILTER_REPLACE;
  1642. break;
  1643. default:
  1644. DP_NOTICE(cdev, "Unknown unicast filter type %d\n",
  1645. params->type);
  1646. }
  1647. if (params->vlan_valid && params->mac_valid) {
  1648. ucast.type = QED_FILTER_MAC_VLAN;
  1649. ether_addr_copy(ucast.mac, params->mac);
  1650. ucast.vlan = params->vlan;
  1651. } else if (params->mac_valid) {
  1652. ucast.type = QED_FILTER_MAC;
  1653. ether_addr_copy(ucast.mac, params->mac);
  1654. } else {
  1655. ucast.type = QED_FILTER_VLAN;
  1656. ucast.vlan = params->vlan;
  1657. }
  1658. ucast.is_rx_filter = true;
  1659. ucast.is_tx_filter = true;
  1660. return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL);
  1661. }
  1662. static int qed_configure_filter_mcast(struct qed_dev *cdev,
  1663. struct qed_filter_mcast_params *params)
  1664. {
  1665. struct qed_filter_mcast mcast;
  1666. int i;
  1667. memset(&mcast, 0, sizeof(mcast));
  1668. switch (params->type) {
  1669. case QED_FILTER_XCAST_TYPE_ADD:
  1670. mcast.opcode = QED_FILTER_ADD;
  1671. break;
  1672. case QED_FILTER_XCAST_TYPE_DEL:
  1673. mcast.opcode = QED_FILTER_REMOVE;
  1674. break;
  1675. default:
  1676. DP_NOTICE(cdev, "Unknown multicast filter type %d\n",
  1677. params->type);
  1678. }
  1679. mcast.num_mc_addrs = params->num;
  1680. for (i = 0; i < mcast.num_mc_addrs; i++)
  1681. ether_addr_copy(mcast.mac[i], params->mac[i]);
  1682. return qed_filter_mcast_cmd(cdev, &mcast,
  1683. QED_SPQ_MODE_CB, NULL);
  1684. }
  1685. static int qed_configure_filter(struct qed_dev *cdev,
  1686. struct qed_filter_params *params)
  1687. {
  1688. enum qed_filter_rx_mode_type accept_flags;
  1689. switch (params->type) {
  1690. case QED_FILTER_TYPE_UCAST:
  1691. return qed_configure_filter_ucast(cdev, &params->filter.ucast);
  1692. case QED_FILTER_TYPE_MCAST:
  1693. return qed_configure_filter_mcast(cdev, &params->filter.mcast);
  1694. case QED_FILTER_TYPE_RX_MODE:
  1695. accept_flags = params->filter.accept_flags;
  1696. return qed_configure_filter_rx_mode(cdev, accept_flags);
  1697. default:
  1698. DP_NOTICE(cdev, "Unknown filter type %d\n",
  1699. (int)params->type);
  1700. return -EINVAL;
  1701. }
  1702. }
  1703. static int qed_fp_cqe_completion(struct qed_dev *dev,
  1704. u8 rss_id,
  1705. struct eth_slow_path_rx_cqe *cqe)
  1706. {
  1707. return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns],
  1708. cqe);
  1709. }
  1710. static const struct qed_eth_ops qed_eth_ops_pass = {
  1711. .common = &qed_common_ops_pass,
  1712. .fill_dev_info = &qed_fill_eth_dev_info,
  1713. .register_ops = &qed_register_eth_ops,
  1714. .vport_start = &qed_start_vport,
  1715. .vport_stop = &qed_stop_vport,
  1716. .vport_update = &qed_update_vport,
  1717. .q_rx_start = &qed_start_rxq,
  1718. .q_rx_stop = &qed_stop_rxq,
  1719. .q_tx_start = &qed_start_txq,
  1720. .q_tx_stop = &qed_stop_txq,
  1721. .filter_config = &qed_configure_filter,
  1722. .fastpath_stop = &qed_fastpath_stop,
  1723. .eth_cqe_completion = &qed_fp_cqe_completion,
  1724. .get_vport_stats = &qed_get_vport_stats,
  1725. };
  1726. const struct qed_eth_ops *qed_get_eth_ops(u32 version)
  1727. {
  1728. if (version != QED_ETH_INTERFACE_VERSION) {
  1729. pr_notice("Cannot supply ethtool operations [%08x != %08x]\n",
  1730. version, QED_ETH_INTERFACE_VERSION);
  1731. return NULL;
  1732. }
  1733. return &qed_eth_ops_pass;
  1734. }
  1735. EXPORT_SYMBOL(qed_get_eth_ops);
  1736. void qed_put_eth_ops(void)
  1737. {
  1738. /* TODO - reference count for module? */
  1739. }
  1740. EXPORT_SYMBOL(qed_put_eth_ops);