i40iw_verbs.c 66 KB

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  1. /*******************************************************************************
  2. *
  3. * Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenFabrics.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. *
  33. *******************************************************************************/
  34. #include <linux/module.h>
  35. #include <linux/moduleparam.h>
  36. #include <linux/random.h>
  37. #include <linux/highmem.h>
  38. #include <linux/time.h>
  39. #include <asm/byteorder.h>
  40. #include <net/ip.h>
  41. #include <rdma/ib_verbs.h>
  42. #include <rdma/iw_cm.h>
  43. #include <rdma/ib_user_verbs.h>
  44. #include <rdma/ib_umem.h>
  45. #include "i40iw.h"
  46. /**
  47. * i40iw_query_device - get device attributes
  48. * @ibdev: device pointer from stack
  49. * @props: returning device attributes
  50. * @udata: user data
  51. */
  52. static int i40iw_query_device(struct ib_device *ibdev,
  53. struct ib_device_attr *props,
  54. struct ib_udata *udata)
  55. {
  56. struct i40iw_device *iwdev = to_iwdev(ibdev);
  57. if (udata->inlen || udata->outlen)
  58. return -EINVAL;
  59. memset(props, 0, sizeof(*props));
  60. ether_addr_copy((u8 *)&props->sys_image_guid, iwdev->netdev->dev_addr);
  61. props->fw_ver = I40IW_FW_VERSION;
  62. props->device_cap_flags = iwdev->device_cap_flags;
  63. props->vendor_id = iwdev->vendor_id;
  64. props->vendor_part_id = iwdev->vendor_part_id;
  65. props->hw_ver = (u32)iwdev->sc_dev.hw_rev;
  66. props->max_mr_size = I40IW_MAX_OUTBOUND_MESSAGE_SIZE;
  67. props->max_qp = iwdev->max_qp;
  68. props->max_qp_wr = (I40IW_MAX_WQ_ENTRIES >> 2) - 1;
  69. props->max_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
  70. props->max_cq = iwdev->max_cq;
  71. props->max_cqe = iwdev->max_cqe;
  72. props->max_mr = iwdev->max_mr;
  73. props->max_pd = iwdev->max_pd;
  74. props->max_sge_rd = 1;
  75. props->max_qp_rd_atom = I40IW_MAX_IRD_SIZE;
  76. props->max_qp_init_rd_atom = props->max_qp_rd_atom;
  77. props->atomic_cap = IB_ATOMIC_NONE;
  78. props->max_map_per_fmr = 1;
  79. return 0;
  80. }
  81. /**
  82. * i40iw_query_port - get port attrubutes
  83. * @ibdev: device pointer from stack
  84. * @port: port number for query
  85. * @props: returning device attributes
  86. */
  87. static int i40iw_query_port(struct ib_device *ibdev,
  88. u8 port,
  89. struct ib_port_attr *props)
  90. {
  91. struct i40iw_device *iwdev = to_iwdev(ibdev);
  92. struct net_device *netdev = iwdev->netdev;
  93. memset(props, 0, sizeof(*props));
  94. props->max_mtu = IB_MTU_4096;
  95. if (netdev->mtu >= 4096)
  96. props->active_mtu = IB_MTU_4096;
  97. else if (netdev->mtu >= 2048)
  98. props->active_mtu = IB_MTU_2048;
  99. else if (netdev->mtu >= 1024)
  100. props->active_mtu = IB_MTU_1024;
  101. else if (netdev->mtu >= 512)
  102. props->active_mtu = IB_MTU_512;
  103. else
  104. props->active_mtu = IB_MTU_256;
  105. props->lid = 1;
  106. if (netif_carrier_ok(iwdev->netdev))
  107. props->state = IB_PORT_ACTIVE;
  108. else
  109. props->state = IB_PORT_DOWN;
  110. props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
  111. IB_PORT_VENDOR_CLASS_SUP | IB_PORT_BOOT_MGMT_SUP;
  112. props->gid_tbl_len = 1;
  113. props->pkey_tbl_len = 1;
  114. props->active_width = IB_WIDTH_4X;
  115. props->active_speed = 1;
  116. props->max_msg_sz = 0x80000000;
  117. return 0;
  118. }
  119. /**
  120. * i40iw_alloc_ucontext - Allocate the user context data structure
  121. * @ibdev: device pointer from stack
  122. * @udata: user data
  123. *
  124. * This keeps track of all objects associated with a particular
  125. * user-mode client.
  126. */
  127. static struct ib_ucontext *i40iw_alloc_ucontext(struct ib_device *ibdev,
  128. struct ib_udata *udata)
  129. {
  130. struct i40iw_device *iwdev = to_iwdev(ibdev);
  131. struct i40iw_alloc_ucontext_req req;
  132. struct i40iw_alloc_ucontext_resp uresp;
  133. struct i40iw_ucontext *ucontext;
  134. if (ib_copy_from_udata(&req, udata, sizeof(req)))
  135. return ERR_PTR(-EINVAL);
  136. if (req.userspace_ver != I40IW_ABI_USERSPACE_VER) {
  137. i40iw_pr_err("Invalid userspace driver version detected. Detected version %d, should be %d\n",
  138. req.userspace_ver, I40IW_ABI_USERSPACE_VER);
  139. return ERR_PTR(-EINVAL);
  140. }
  141. memset(&uresp, 0, sizeof(uresp));
  142. uresp.max_qps = iwdev->max_qp;
  143. uresp.max_pds = iwdev->max_pd;
  144. uresp.wq_size = iwdev->max_qp_wr * 2;
  145. uresp.kernel_ver = I40IW_ABI_KERNEL_VER;
  146. ucontext = kzalloc(sizeof(*ucontext), GFP_KERNEL);
  147. if (!ucontext)
  148. return ERR_PTR(-ENOMEM);
  149. ucontext->iwdev = iwdev;
  150. if (ib_copy_to_udata(udata, &uresp, sizeof(uresp))) {
  151. kfree(ucontext);
  152. return ERR_PTR(-EFAULT);
  153. }
  154. INIT_LIST_HEAD(&ucontext->cq_reg_mem_list);
  155. spin_lock_init(&ucontext->cq_reg_mem_list_lock);
  156. INIT_LIST_HEAD(&ucontext->qp_reg_mem_list);
  157. spin_lock_init(&ucontext->qp_reg_mem_list_lock);
  158. return &ucontext->ibucontext;
  159. }
  160. /**
  161. * i40iw_dealloc_ucontext - deallocate the user context data structure
  162. * @context: user context created during alloc
  163. */
  164. static int i40iw_dealloc_ucontext(struct ib_ucontext *context)
  165. {
  166. struct i40iw_ucontext *ucontext = to_ucontext(context);
  167. unsigned long flags;
  168. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  169. if (!list_empty(&ucontext->cq_reg_mem_list)) {
  170. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  171. return -EBUSY;
  172. }
  173. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  174. spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
  175. if (!list_empty(&ucontext->qp_reg_mem_list)) {
  176. spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
  177. return -EBUSY;
  178. }
  179. spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
  180. kfree(ucontext);
  181. return 0;
  182. }
  183. /**
  184. * i40iw_mmap - user memory map
  185. * @context: context created during alloc
  186. * @vma: kernel info for user memory map
  187. */
  188. static int i40iw_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
  189. {
  190. struct i40iw_ucontext *ucontext;
  191. u64 db_addr_offset;
  192. u64 push_offset;
  193. ucontext = to_ucontext(context);
  194. if (ucontext->iwdev->sc_dev.is_pf) {
  195. db_addr_offset = I40IW_DB_ADDR_OFFSET;
  196. push_offset = I40IW_PUSH_OFFSET;
  197. if (vma->vm_pgoff)
  198. vma->vm_pgoff += I40IW_PF_FIRST_PUSH_PAGE_INDEX - 1;
  199. } else {
  200. db_addr_offset = I40IW_VF_DB_ADDR_OFFSET;
  201. push_offset = I40IW_VF_PUSH_OFFSET;
  202. if (vma->vm_pgoff)
  203. vma->vm_pgoff += I40IW_VF_FIRST_PUSH_PAGE_INDEX - 1;
  204. }
  205. vma->vm_pgoff += db_addr_offset >> PAGE_SHIFT;
  206. if (vma->vm_pgoff == (db_addr_offset >> PAGE_SHIFT)) {
  207. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  208. vma->vm_private_data = ucontext;
  209. } else {
  210. if ((vma->vm_pgoff - (push_offset >> PAGE_SHIFT)) % 2)
  211. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  212. else
  213. vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
  214. }
  215. if (io_remap_pfn_range(vma, vma->vm_start,
  216. vma->vm_pgoff + (pci_resource_start(ucontext->iwdev->ldev->pcidev, 0) >> PAGE_SHIFT),
  217. PAGE_SIZE, vma->vm_page_prot))
  218. return -EAGAIN;
  219. return 0;
  220. }
  221. /**
  222. * i40iw_alloc_push_page - allocate a push page for qp
  223. * @iwdev: iwarp device
  224. * @qp: hardware control qp
  225. */
  226. static void i40iw_alloc_push_page(struct i40iw_device *iwdev, struct i40iw_sc_qp *qp)
  227. {
  228. struct i40iw_cqp_request *cqp_request;
  229. struct cqp_commands_info *cqp_info;
  230. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  231. enum i40iw_status_code status;
  232. if (qp->push_idx != I40IW_INVALID_PUSH_PAGE_INDEX)
  233. return;
  234. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
  235. if (!cqp_request)
  236. return;
  237. atomic_inc(&cqp_request->refcount);
  238. cqp_info = &cqp_request->info;
  239. cqp_info->cqp_cmd = OP_MANAGE_PUSH_PAGE;
  240. cqp_info->post_sq = 1;
  241. cqp_info->in.u.manage_push_page.info.qs_handle = dev->qs_handle;
  242. cqp_info->in.u.manage_push_page.info.free_page = 0;
  243. cqp_info->in.u.manage_push_page.cqp = &iwdev->cqp.sc_cqp;
  244. cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request;
  245. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  246. if (!status)
  247. qp->push_idx = cqp_request->compl_info.op_ret_val;
  248. else
  249. i40iw_pr_err("CQP-OP Push page fail");
  250. i40iw_put_cqp_request(&iwdev->cqp, cqp_request);
  251. }
  252. /**
  253. * i40iw_dealloc_push_page - free a push page for qp
  254. * @iwdev: iwarp device
  255. * @qp: hardware control qp
  256. */
  257. static void i40iw_dealloc_push_page(struct i40iw_device *iwdev, struct i40iw_sc_qp *qp)
  258. {
  259. struct i40iw_cqp_request *cqp_request;
  260. struct cqp_commands_info *cqp_info;
  261. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  262. enum i40iw_status_code status;
  263. if (qp->push_idx == I40IW_INVALID_PUSH_PAGE_INDEX)
  264. return;
  265. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, false);
  266. if (!cqp_request)
  267. return;
  268. cqp_info = &cqp_request->info;
  269. cqp_info->cqp_cmd = OP_MANAGE_PUSH_PAGE;
  270. cqp_info->post_sq = 1;
  271. cqp_info->in.u.manage_push_page.info.push_idx = qp->push_idx;
  272. cqp_info->in.u.manage_push_page.info.qs_handle = dev->qs_handle;
  273. cqp_info->in.u.manage_push_page.info.free_page = 1;
  274. cqp_info->in.u.manage_push_page.cqp = &iwdev->cqp.sc_cqp;
  275. cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request;
  276. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  277. if (!status)
  278. qp->push_idx = I40IW_INVALID_PUSH_PAGE_INDEX;
  279. else
  280. i40iw_pr_err("CQP-OP Push page fail");
  281. }
  282. /**
  283. * i40iw_alloc_pd - allocate protection domain
  284. * @ibdev: device pointer from stack
  285. * @context: user context created during alloc
  286. * @udata: user data
  287. */
  288. static struct ib_pd *i40iw_alloc_pd(struct ib_device *ibdev,
  289. struct ib_ucontext *context,
  290. struct ib_udata *udata)
  291. {
  292. struct i40iw_pd *iwpd;
  293. struct i40iw_device *iwdev = to_iwdev(ibdev);
  294. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  295. struct i40iw_alloc_pd_resp uresp;
  296. struct i40iw_sc_pd *sc_pd;
  297. u32 pd_id = 0;
  298. int err;
  299. err = i40iw_alloc_resource(iwdev, iwdev->allocated_pds,
  300. iwdev->max_pd, &pd_id, &iwdev->next_pd);
  301. if (err) {
  302. i40iw_pr_err("alloc resource failed\n");
  303. return ERR_PTR(err);
  304. }
  305. iwpd = kzalloc(sizeof(*iwpd), GFP_KERNEL);
  306. if (!iwpd) {
  307. err = -ENOMEM;
  308. goto free_res;
  309. }
  310. sc_pd = &iwpd->sc_pd;
  311. dev->iw_pd_ops->pd_init(dev, sc_pd, pd_id);
  312. if (context) {
  313. memset(&uresp, 0, sizeof(uresp));
  314. uresp.pd_id = pd_id;
  315. if (ib_copy_to_udata(udata, &uresp, sizeof(uresp))) {
  316. err = -EFAULT;
  317. goto error;
  318. }
  319. }
  320. i40iw_add_pdusecount(iwpd);
  321. return &iwpd->ibpd;
  322. error:
  323. kfree(iwpd);
  324. free_res:
  325. i40iw_free_resource(iwdev, iwdev->allocated_pds, pd_id);
  326. return ERR_PTR(err);
  327. }
  328. /**
  329. * i40iw_dealloc_pd - deallocate pd
  330. * @ibpd: ptr of pd to be deallocated
  331. */
  332. static int i40iw_dealloc_pd(struct ib_pd *ibpd)
  333. {
  334. struct i40iw_pd *iwpd = to_iwpd(ibpd);
  335. struct i40iw_device *iwdev = to_iwdev(ibpd->device);
  336. i40iw_rem_pdusecount(iwpd, iwdev);
  337. return 0;
  338. }
  339. /**
  340. * i40iw_qp_roundup - return round up qp ring size
  341. * @wr_ring_size: ring size to round up
  342. */
  343. static int i40iw_qp_roundup(u32 wr_ring_size)
  344. {
  345. int scount = 1;
  346. if (wr_ring_size < I40IWQP_SW_MIN_WQSIZE)
  347. wr_ring_size = I40IWQP_SW_MIN_WQSIZE;
  348. for (wr_ring_size--; scount <= 16; scount *= 2)
  349. wr_ring_size |= wr_ring_size >> scount;
  350. return ++wr_ring_size;
  351. }
  352. /**
  353. * i40iw_get_pbl - Retrieve pbl from a list given a virtual
  354. * address
  355. * @va: user virtual address
  356. * @pbl_list: pbl list to search in (QP's or CQ's)
  357. */
  358. static struct i40iw_pbl *i40iw_get_pbl(unsigned long va,
  359. struct list_head *pbl_list)
  360. {
  361. struct i40iw_pbl *iwpbl;
  362. list_for_each_entry(iwpbl, pbl_list, list) {
  363. if (iwpbl->user_base == va) {
  364. list_del(&iwpbl->list);
  365. return iwpbl;
  366. }
  367. }
  368. return NULL;
  369. }
  370. /**
  371. * i40iw_free_qp_resources - free up memory resources for qp
  372. * @iwdev: iwarp device
  373. * @iwqp: qp ptr (user or kernel)
  374. * @qp_num: qp number assigned
  375. */
  376. void i40iw_free_qp_resources(struct i40iw_device *iwdev,
  377. struct i40iw_qp *iwqp,
  378. u32 qp_num)
  379. {
  380. i40iw_dealloc_push_page(iwdev, &iwqp->sc_qp);
  381. if (qp_num)
  382. i40iw_free_resource(iwdev, iwdev->allocated_qps, qp_num);
  383. i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwqp->q2_ctx_mem);
  384. i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwqp->kqp.dma_mem);
  385. kfree(iwqp->kqp.wrid_mem);
  386. iwqp->kqp.wrid_mem = NULL;
  387. kfree(iwqp->allocated_buffer);
  388. iwqp->allocated_buffer = NULL;
  389. }
  390. /**
  391. * i40iw_clean_cqes - clean cq entries for qp
  392. * @iwqp: qp ptr (user or kernel)
  393. * @iwcq: cq ptr
  394. */
  395. static void i40iw_clean_cqes(struct i40iw_qp *iwqp, struct i40iw_cq *iwcq)
  396. {
  397. struct i40iw_cq_uk *ukcq = &iwcq->sc_cq.cq_uk;
  398. ukcq->ops.iw_cq_clean(&iwqp->sc_qp.qp_uk, ukcq);
  399. }
  400. /**
  401. * i40iw_destroy_qp - destroy qp
  402. * @ibqp: qp's ib pointer also to get to device's qp address
  403. */
  404. static int i40iw_destroy_qp(struct ib_qp *ibqp)
  405. {
  406. struct i40iw_qp *iwqp = to_iwqp(ibqp);
  407. iwqp->destroyed = 1;
  408. if (iwqp->ibqp_state >= IB_QPS_INIT && iwqp->ibqp_state < IB_QPS_RTS)
  409. i40iw_next_iw_state(iwqp, I40IW_QP_STATE_ERROR, 0, 0, 0);
  410. if (!iwqp->user_mode) {
  411. if (iwqp->iwscq) {
  412. i40iw_clean_cqes(iwqp, iwqp->iwscq);
  413. if (iwqp->iwrcq != iwqp->iwscq)
  414. i40iw_clean_cqes(iwqp, iwqp->iwrcq);
  415. }
  416. }
  417. i40iw_rem_ref(&iwqp->ibqp);
  418. return 0;
  419. }
  420. /**
  421. * i40iw_setup_virt_qp - setup for allocation of virtual qp
  422. * @dev: iwarp device
  423. * @qp: qp ptr
  424. * @init_info: initialize info to return
  425. */
  426. static int i40iw_setup_virt_qp(struct i40iw_device *iwdev,
  427. struct i40iw_qp *iwqp,
  428. struct i40iw_qp_init_info *init_info)
  429. {
  430. struct i40iw_pbl *iwpbl = iwqp->iwpbl;
  431. struct i40iw_qp_mr *qpmr = &iwpbl->qp_mr;
  432. iwqp->page = qpmr->sq_page;
  433. init_info->shadow_area_pa = cpu_to_le64(qpmr->shadow);
  434. if (iwpbl->pbl_allocated) {
  435. init_info->virtual_map = true;
  436. init_info->sq_pa = qpmr->sq_pbl.idx;
  437. init_info->rq_pa = qpmr->rq_pbl.idx;
  438. } else {
  439. init_info->sq_pa = qpmr->sq_pbl.addr;
  440. init_info->rq_pa = qpmr->rq_pbl.addr;
  441. }
  442. return 0;
  443. }
  444. /**
  445. * i40iw_setup_kmode_qp - setup initialization for kernel mode qp
  446. * @iwdev: iwarp device
  447. * @iwqp: qp ptr (user or kernel)
  448. * @info: initialize info to return
  449. */
  450. static int i40iw_setup_kmode_qp(struct i40iw_device *iwdev,
  451. struct i40iw_qp *iwqp,
  452. struct i40iw_qp_init_info *info)
  453. {
  454. struct i40iw_dma_mem *mem = &iwqp->kqp.dma_mem;
  455. u32 sqdepth, rqdepth;
  456. u32 sq_size, rq_size;
  457. u8 sqshift, rqshift;
  458. u32 size;
  459. enum i40iw_status_code status;
  460. struct i40iw_qp_uk_init_info *ukinfo = &info->qp_uk_init_info;
  461. ukinfo->max_sq_frag_cnt = I40IW_MAX_WQ_FRAGMENT_COUNT;
  462. sq_size = i40iw_qp_roundup(ukinfo->sq_size + 1);
  463. rq_size = i40iw_qp_roundup(ukinfo->rq_size + 1);
  464. status = i40iw_get_wqe_shift(sq_size, ukinfo->max_sq_frag_cnt, &sqshift);
  465. if (!status)
  466. status = i40iw_get_wqe_shift(rq_size, ukinfo->max_rq_frag_cnt, &rqshift);
  467. if (status)
  468. return -ENOSYS;
  469. sqdepth = sq_size << sqshift;
  470. rqdepth = rq_size << rqshift;
  471. size = sqdepth * sizeof(struct i40iw_sq_uk_wr_trk_info) + (rqdepth << 3);
  472. iwqp->kqp.wrid_mem = kzalloc(size, GFP_KERNEL);
  473. ukinfo->sq_wrtrk_array = (struct i40iw_sq_uk_wr_trk_info *)iwqp->kqp.wrid_mem;
  474. if (!ukinfo->sq_wrtrk_array)
  475. return -ENOMEM;
  476. ukinfo->rq_wrid_array = (u64 *)&ukinfo->sq_wrtrk_array[sqdepth];
  477. size = (sqdepth + rqdepth) * I40IW_QP_WQE_MIN_SIZE;
  478. size += (I40IW_SHADOW_AREA_SIZE << 3);
  479. status = i40iw_allocate_dma_mem(iwdev->sc_dev.hw, mem, size, 256);
  480. if (status) {
  481. kfree(ukinfo->sq_wrtrk_array);
  482. ukinfo->sq_wrtrk_array = NULL;
  483. return -ENOMEM;
  484. }
  485. ukinfo->sq = mem->va;
  486. info->sq_pa = mem->pa;
  487. ukinfo->rq = &ukinfo->sq[sqdepth];
  488. info->rq_pa = info->sq_pa + (sqdepth * I40IW_QP_WQE_MIN_SIZE);
  489. ukinfo->shadow_area = ukinfo->rq[rqdepth].elem;
  490. info->shadow_area_pa = info->rq_pa + (rqdepth * I40IW_QP_WQE_MIN_SIZE);
  491. ukinfo->sq_size = sq_size;
  492. ukinfo->rq_size = rq_size;
  493. ukinfo->qp_id = iwqp->ibqp.qp_num;
  494. return 0;
  495. }
  496. /**
  497. * i40iw_create_qp - create qp
  498. * @ibpd: ptr of pd
  499. * @init_attr: attributes for qp
  500. * @udata: user data for create qp
  501. */
  502. static struct ib_qp *i40iw_create_qp(struct ib_pd *ibpd,
  503. struct ib_qp_init_attr *init_attr,
  504. struct ib_udata *udata)
  505. {
  506. struct i40iw_pd *iwpd = to_iwpd(ibpd);
  507. struct i40iw_device *iwdev = to_iwdev(ibpd->device);
  508. struct i40iw_cqp *iwcqp = &iwdev->cqp;
  509. struct i40iw_qp *iwqp;
  510. struct i40iw_ucontext *ucontext;
  511. struct i40iw_create_qp_req req;
  512. struct i40iw_create_qp_resp uresp;
  513. u32 qp_num = 0;
  514. void *mem;
  515. enum i40iw_status_code ret;
  516. int err_code;
  517. int sq_size;
  518. int rq_size;
  519. struct i40iw_sc_qp *qp;
  520. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  521. struct i40iw_qp_init_info init_info;
  522. struct i40iw_create_qp_info *qp_info;
  523. struct i40iw_cqp_request *cqp_request;
  524. struct cqp_commands_info *cqp_info;
  525. struct i40iw_qp_host_ctx_info *ctx_info;
  526. struct i40iwarp_offload_info *iwarp_info;
  527. unsigned long flags;
  528. if (init_attr->create_flags)
  529. return ERR_PTR(-EINVAL);
  530. if (init_attr->cap.max_inline_data > I40IW_MAX_INLINE_DATA_SIZE)
  531. init_attr->cap.max_inline_data = I40IW_MAX_INLINE_DATA_SIZE;
  532. memset(&init_info, 0, sizeof(init_info));
  533. sq_size = init_attr->cap.max_send_wr;
  534. rq_size = init_attr->cap.max_recv_wr;
  535. init_info.qp_uk_init_info.sq_size = sq_size;
  536. init_info.qp_uk_init_info.rq_size = rq_size;
  537. init_info.qp_uk_init_info.max_sq_frag_cnt = init_attr->cap.max_send_sge;
  538. init_info.qp_uk_init_info.max_rq_frag_cnt = init_attr->cap.max_recv_sge;
  539. mem = kzalloc(sizeof(*iwqp), GFP_KERNEL);
  540. if (!mem)
  541. return ERR_PTR(-ENOMEM);
  542. iwqp = (struct i40iw_qp *)mem;
  543. qp = &iwqp->sc_qp;
  544. qp->back_qp = (void *)iwqp;
  545. qp->push_idx = I40IW_INVALID_PUSH_PAGE_INDEX;
  546. iwqp->ctx_info.iwarp_info = &iwqp->iwarp_info;
  547. if (i40iw_allocate_dma_mem(dev->hw,
  548. &iwqp->q2_ctx_mem,
  549. I40IW_Q2_BUFFER_SIZE + I40IW_QP_CTX_SIZE,
  550. 256)) {
  551. i40iw_pr_err("dma_mem failed\n");
  552. err_code = -ENOMEM;
  553. goto error;
  554. }
  555. init_info.q2 = iwqp->q2_ctx_mem.va;
  556. init_info.q2_pa = iwqp->q2_ctx_mem.pa;
  557. init_info.host_ctx = (void *)init_info.q2 + I40IW_Q2_BUFFER_SIZE;
  558. init_info.host_ctx_pa = init_info.q2_pa + I40IW_Q2_BUFFER_SIZE;
  559. err_code = i40iw_alloc_resource(iwdev, iwdev->allocated_qps, iwdev->max_qp,
  560. &qp_num, &iwdev->next_qp);
  561. if (err_code) {
  562. i40iw_pr_err("qp resource\n");
  563. goto error;
  564. }
  565. iwqp->allocated_buffer = mem;
  566. iwqp->iwdev = iwdev;
  567. iwqp->iwpd = iwpd;
  568. iwqp->ibqp.qp_num = qp_num;
  569. qp = &iwqp->sc_qp;
  570. iwqp->iwscq = to_iwcq(init_attr->send_cq);
  571. iwqp->iwrcq = to_iwcq(init_attr->recv_cq);
  572. iwqp->host_ctx.va = init_info.host_ctx;
  573. iwqp->host_ctx.pa = init_info.host_ctx_pa;
  574. iwqp->host_ctx.size = I40IW_QP_CTX_SIZE;
  575. init_info.pd = &iwpd->sc_pd;
  576. init_info.qp_uk_init_info.qp_id = iwqp->ibqp.qp_num;
  577. iwqp->ctx_info.qp_compl_ctx = (uintptr_t)qp;
  578. if (init_attr->qp_type != IB_QPT_RC) {
  579. err_code = -ENOSYS;
  580. goto error;
  581. }
  582. if (iwdev->push_mode)
  583. i40iw_alloc_push_page(iwdev, qp);
  584. if (udata) {
  585. err_code = ib_copy_from_udata(&req, udata, sizeof(req));
  586. if (err_code) {
  587. i40iw_pr_err("ib_copy_from_data\n");
  588. goto error;
  589. }
  590. iwqp->ctx_info.qp_compl_ctx = req.user_compl_ctx;
  591. if (ibpd->uobject && ibpd->uobject->context) {
  592. iwqp->user_mode = 1;
  593. ucontext = to_ucontext(ibpd->uobject->context);
  594. if (req.user_wqe_buffers) {
  595. spin_lock_irqsave(
  596. &ucontext->qp_reg_mem_list_lock, flags);
  597. iwqp->iwpbl = i40iw_get_pbl(
  598. (unsigned long)req.user_wqe_buffers,
  599. &ucontext->qp_reg_mem_list);
  600. spin_unlock_irqrestore(
  601. &ucontext->qp_reg_mem_list_lock, flags);
  602. if (!iwqp->iwpbl) {
  603. err_code = -ENODATA;
  604. i40iw_pr_err("no pbl info\n");
  605. goto error;
  606. }
  607. }
  608. }
  609. err_code = i40iw_setup_virt_qp(iwdev, iwqp, &init_info);
  610. } else {
  611. err_code = i40iw_setup_kmode_qp(iwdev, iwqp, &init_info);
  612. }
  613. if (err_code) {
  614. i40iw_pr_err("setup qp failed\n");
  615. goto error;
  616. }
  617. init_info.type = I40IW_QP_TYPE_IWARP;
  618. ret = dev->iw_priv_qp_ops->qp_init(qp, &init_info);
  619. if (ret) {
  620. err_code = -EPROTO;
  621. i40iw_pr_err("qp_init fail\n");
  622. goto error;
  623. }
  624. ctx_info = &iwqp->ctx_info;
  625. iwarp_info = &iwqp->iwarp_info;
  626. iwarp_info->rd_enable = true;
  627. iwarp_info->wr_rdresp_en = true;
  628. if (!iwqp->user_mode)
  629. iwarp_info->priv_mode_en = true;
  630. iwarp_info->ddp_ver = 1;
  631. iwarp_info->rdmap_ver = 1;
  632. ctx_info->iwarp_info_valid = true;
  633. ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id;
  634. ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id;
  635. if (qp->push_idx == I40IW_INVALID_PUSH_PAGE_INDEX) {
  636. ctx_info->push_mode_en = false;
  637. } else {
  638. ctx_info->push_mode_en = true;
  639. ctx_info->push_idx = qp->push_idx;
  640. }
  641. ret = dev->iw_priv_qp_ops->qp_setctx(&iwqp->sc_qp,
  642. (u64 *)iwqp->host_ctx.va,
  643. ctx_info);
  644. ctx_info->iwarp_info_valid = false;
  645. cqp_request = i40iw_get_cqp_request(iwcqp, true);
  646. if (!cqp_request) {
  647. err_code = -ENOMEM;
  648. goto error;
  649. }
  650. cqp_info = &cqp_request->info;
  651. qp_info = &cqp_request->info.in.u.qp_create.info;
  652. memset(qp_info, 0, sizeof(*qp_info));
  653. qp_info->cq_num_valid = true;
  654. qp_info->next_iwarp_state = I40IW_QP_STATE_IDLE;
  655. cqp_info->cqp_cmd = OP_QP_CREATE;
  656. cqp_info->post_sq = 1;
  657. cqp_info->in.u.qp_create.qp = qp;
  658. cqp_info->in.u.qp_create.scratch = (uintptr_t)cqp_request;
  659. ret = i40iw_handle_cqp_op(iwdev, cqp_request);
  660. if (ret) {
  661. i40iw_pr_err("CQP-OP QP create fail");
  662. err_code = -EACCES;
  663. goto error;
  664. }
  665. i40iw_add_ref(&iwqp->ibqp);
  666. spin_lock_init(&iwqp->lock);
  667. iwqp->sig_all = (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) ? 1 : 0;
  668. iwdev->qp_table[qp_num] = iwqp;
  669. i40iw_add_pdusecount(iwqp->iwpd);
  670. if (ibpd->uobject && udata) {
  671. memset(&uresp, 0, sizeof(uresp));
  672. uresp.actual_sq_size = sq_size;
  673. uresp.actual_rq_size = rq_size;
  674. uresp.qp_id = qp_num;
  675. uresp.push_idx = qp->push_idx;
  676. err_code = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
  677. if (err_code) {
  678. i40iw_pr_err("copy_to_udata failed\n");
  679. i40iw_destroy_qp(&iwqp->ibqp);
  680. /* let the completion of the qp destroy free the qp */
  681. return ERR_PTR(err_code);
  682. }
  683. }
  684. return &iwqp->ibqp;
  685. error:
  686. i40iw_free_qp_resources(iwdev, iwqp, qp_num);
  687. kfree(mem);
  688. return ERR_PTR(err_code);
  689. }
  690. /**
  691. * i40iw_query - query qp attributes
  692. * @ibqp: qp pointer
  693. * @attr: attributes pointer
  694. * @attr_mask: Not used
  695. * @init_attr: qp attributes to return
  696. */
  697. static int i40iw_query_qp(struct ib_qp *ibqp,
  698. struct ib_qp_attr *attr,
  699. int attr_mask,
  700. struct ib_qp_init_attr *init_attr)
  701. {
  702. struct i40iw_qp *iwqp = to_iwqp(ibqp);
  703. struct i40iw_sc_qp *qp = &iwqp->sc_qp;
  704. attr->qp_access_flags = 0;
  705. attr->cap.max_send_wr = qp->qp_uk.sq_size;
  706. attr->cap.max_recv_wr = qp->qp_uk.rq_size;
  707. attr->cap.max_recv_sge = 1;
  708. attr->cap.max_inline_data = I40IW_MAX_INLINE_DATA_SIZE;
  709. init_attr->event_handler = iwqp->ibqp.event_handler;
  710. init_attr->qp_context = iwqp->ibqp.qp_context;
  711. init_attr->send_cq = iwqp->ibqp.send_cq;
  712. init_attr->recv_cq = iwqp->ibqp.recv_cq;
  713. init_attr->srq = iwqp->ibqp.srq;
  714. init_attr->cap = attr->cap;
  715. return 0;
  716. }
  717. /**
  718. * i40iw_hw_modify_qp - setup cqp for modify qp
  719. * @iwdev: iwarp device
  720. * @iwqp: qp ptr (user or kernel)
  721. * @info: info for modify qp
  722. * @wait: flag to wait or not for modify qp completion
  723. */
  724. void i40iw_hw_modify_qp(struct i40iw_device *iwdev, struct i40iw_qp *iwqp,
  725. struct i40iw_modify_qp_info *info, bool wait)
  726. {
  727. enum i40iw_status_code status;
  728. struct i40iw_cqp_request *cqp_request;
  729. struct cqp_commands_info *cqp_info;
  730. struct i40iw_modify_qp_info *m_info;
  731. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, wait);
  732. if (!cqp_request)
  733. return;
  734. cqp_info = &cqp_request->info;
  735. m_info = &cqp_info->in.u.qp_modify.info;
  736. memcpy(m_info, info, sizeof(*m_info));
  737. cqp_info->cqp_cmd = OP_QP_MODIFY;
  738. cqp_info->post_sq = 1;
  739. cqp_info->in.u.qp_modify.qp = &iwqp->sc_qp;
  740. cqp_info->in.u.qp_modify.scratch = (uintptr_t)cqp_request;
  741. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  742. if (status)
  743. i40iw_pr_err("CQP-OP Modify QP fail");
  744. }
  745. /**
  746. * i40iw_modify_qp - modify qp request
  747. * @ibqp: qp's pointer for modify
  748. * @attr: access attributes
  749. * @attr_mask: state mask
  750. * @udata: user data
  751. */
  752. int i40iw_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
  753. int attr_mask, struct ib_udata *udata)
  754. {
  755. struct i40iw_qp *iwqp = to_iwqp(ibqp);
  756. struct i40iw_device *iwdev = iwqp->iwdev;
  757. struct i40iw_qp_host_ctx_info *ctx_info;
  758. struct i40iwarp_offload_info *iwarp_info;
  759. struct i40iw_modify_qp_info info;
  760. u8 issue_modify_qp = 0;
  761. u8 dont_wait = 0;
  762. u32 err;
  763. unsigned long flags;
  764. memset(&info, 0, sizeof(info));
  765. ctx_info = &iwqp->ctx_info;
  766. iwarp_info = &iwqp->iwarp_info;
  767. spin_lock_irqsave(&iwqp->lock, flags);
  768. if (attr_mask & IB_QP_STATE) {
  769. switch (attr->qp_state) {
  770. case IB_QPS_INIT:
  771. case IB_QPS_RTR:
  772. if (iwqp->iwarp_state > (u32)I40IW_QP_STATE_IDLE) {
  773. err = -EINVAL;
  774. goto exit;
  775. }
  776. if (iwqp->iwarp_state == I40IW_QP_STATE_INVALID) {
  777. info.next_iwarp_state = I40IW_QP_STATE_IDLE;
  778. issue_modify_qp = 1;
  779. }
  780. break;
  781. case IB_QPS_RTS:
  782. if ((iwqp->iwarp_state > (u32)I40IW_QP_STATE_RTS) ||
  783. (!iwqp->cm_id)) {
  784. err = -EINVAL;
  785. goto exit;
  786. }
  787. issue_modify_qp = 1;
  788. iwqp->hw_tcp_state = I40IW_TCP_STATE_ESTABLISHED;
  789. iwqp->hte_added = 1;
  790. info.next_iwarp_state = I40IW_QP_STATE_RTS;
  791. info.tcp_ctx_valid = true;
  792. info.ord_valid = true;
  793. info.arp_cache_idx_valid = true;
  794. info.cq_num_valid = true;
  795. break;
  796. case IB_QPS_SQD:
  797. if (iwqp->hw_iwarp_state > (u32)I40IW_QP_STATE_RTS) {
  798. err = 0;
  799. goto exit;
  800. }
  801. if ((iwqp->iwarp_state == (u32)I40IW_QP_STATE_CLOSING) ||
  802. (iwqp->iwarp_state < (u32)I40IW_QP_STATE_RTS)) {
  803. err = 0;
  804. goto exit;
  805. }
  806. if (iwqp->iwarp_state > (u32)I40IW_QP_STATE_CLOSING) {
  807. err = -EINVAL;
  808. goto exit;
  809. }
  810. info.next_iwarp_state = I40IW_QP_STATE_CLOSING;
  811. issue_modify_qp = 1;
  812. break;
  813. case IB_QPS_SQE:
  814. if (iwqp->iwarp_state >= (u32)I40IW_QP_STATE_TERMINATE) {
  815. err = -EINVAL;
  816. goto exit;
  817. }
  818. info.next_iwarp_state = I40IW_QP_STATE_TERMINATE;
  819. issue_modify_qp = 1;
  820. break;
  821. case IB_QPS_ERR:
  822. case IB_QPS_RESET:
  823. if (iwqp->iwarp_state == (u32)I40IW_QP_STATE_ERROR) {
  824. err = -EINVAL;
  825. goto exit;
  826. }
  827. if (iwqp->sc_qp.term_flags)
  828. del_timer(&iwqp->terminate_timer);
  829. info.next_iwarp_state = I40IW_QP_STATE_ERROR;
  830. if ((iwqp->hw_tcp_state > I40IW_TCP_STATE_CLOSED) &&
  831. iwdev->iw_status &&
  832. (iwqp->hw_tcp_state != I40IW_TCP_STATE_TIME_WAIT))
  833. info.reset_tcp_conn = true;
  834. else
  835. dont_wait = 1;
  836. issue_modify_qp = 1;
  837. info.next_iwarp_state = I40IW_QP_STATE_ERROR;
  838. break;
  839. default:
  840. err = -EINVAL;
  841. goto exit;
  842. }
  843. iwqp->ibqp_state = attr->qp_state;
  844. if (issue_modify_qp)
  845. iwqp->iwarp_state = info.next_iwarp_state;
  846. else
  847. info.next_iwarp_state = iwqp->iwarp_state;
  848. }
  849. if (attr_mask & IB_QP_ACCESS_FLAGS) {
  850. ctx_info->iwarp_info_valid = true;
  851. if (attr->qp_access_flags & IB_ACCESS_LOCAL_WRITE)
  852. iwarp_info->wr_rdresp_en = true;
  853. if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
  854. iwarp_info->wr_rdresp_en = true;
  855. if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
  856. iwarp_info->rd_enable = true;
  857. if (attr->qp_access_flags & IB_ACCESS_MW_BIND)
  858. iwarp_info->bind_en = true;
  859. if (iwqp->user_mode) {
  860. iwarp_info->rd_enable = true;
  861. iwarp_info->wr_rdresp_en = true;
  862. iwarp_info->priv_mode_en = false;
  863. }
  864. }
  865. if (ctx_info->iwarp_info_valid) {
  866. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  867. int ret;
  868. ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id;
  869. ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id;
  870. ret = dev->iw_priv_qp_ops->qp_setctx(&iwqp->sc_qp,
  871. (u64 *)iwqp->host_ctx.va,
  872. ctx_info);
  873. if (ret) {
  874. i40iw_pr_err("setting QP context\n");
  875. err = -EINVAL;
  876. goto exit;
  877. }
  878. }
  879. spin_unlock_irqrestore(&iwqp->lock, flags);
  880. if (issue_modify_qp)
  881. i40iw_hw_modify_qp(iwdev, iwqp, &info, true);
  882. if (issue_modify_qp && (iwqp->ibqp_state > IB_QPS_RTS)) {
  883. if (dont_wait) {
  884. if (iwqp->cm_id && iwqp->hw_tcp_state) {
  885. spin_lock_irqsave(&iwqp->lock, flags);
  886. iwqp->hw_tcp_state = I40IW_TCP_STATE_CLOSED;
  887. iwqp->last_aeq = I40IW_AE_RESET_SENT;
  888. spin_unlock_irqrestore(&iwqp->lock, flags);
  889. }
  890. }
  891. }
  892. return 0;
  893. exit:
  894. spin_unlock_irqrestore(&iwqp->lock, flags);
  895. return err;
  896. }
  897. /**
  898. * cq_free_resources - free up recources for cq
  899. * @iwdev: iwarp device
  900. * @iwcq: cq ptr
  901. */
  902. static void cq_free_resources(struct i40iw_device *iwdev, struct i40iw_cq *iwcq)
  903. {
  904. struct i40iw_sc_cq *cq = &iwcq->sc_cq;
  905. if (!iwcq->user_mode)
  906. i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwcq->kmem);
  907. i40iw_free_resource(iwdev, iwdev->allocated_cqs, cq->cq_uk.cq_id);
  908. }
  909. /**
  910. * cq_wq_destroy - send cq destroy cqp
  911. * @iwdev: iwarp device
  912. * @cq: hardware control cq
  913. */
  914. static void cq_wq_destroy(struct i40iw_device *iwdev, struct i40iw_sc_cq *cq)
  915. {
  916. enum i40iw_status_code status;
  917. struct i40iw_cqp_request *cqp_request;
  918. struct cqp_commands_info *cqp_info;
  919. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
  920. if (!cqp_request)
  921. return;
  922. cqp_info = &cqp_request->info;
  923. cqp_info->cqp_cmd = OP_CQ_DESTROY;
  924. cqp_info->post_sq = 1;
  925. cqp_info->in.u.cq_destroy.cq = cq;
  926. cqp_info->in.u.cq_destroy.scratch = (uintptr_t)cqp_request;
  927. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  928. if (status)
  929. i40iw_pr_err("CQP-OP Destroy QP fail");
  930. }
  931. /**
  932. * i40iw_destroy_cq - destroy cq
  933. * @ib_cq: cq pointer
  934. */
  935. static int i40iw_destroy_cq(struct ib_cq *ib_cq)
  936. {
  937. struct i40iw_cq *iwcq;
  938. struct i40iw_device *iwdev;
  939. struct i40iw_sc_cq *cq;
  940. if (!ib_cq) {
  941. i40iw_pr_err("ib_cq == NULL\n");
  942. return 0;
  943. }
  944. iwcq = to_iwcq(ib_cq);
  945. iwdev = to_iwdev(ib_cq->device);
  946. cq = &iwcq->sc_cq;
  947. cq_wq_destroy(iwdev, cq);
  948. cq_free_resources(iwdev, iwcq);
  949. kfree(iwcq);
  950. return 0;
  951. }
  952. /**
  953. * i40iw_create_cq - create cq
  954. * @ibdev: device pointer from stack
  955. * @attr: attributes for cq
  956. * @context: user context created during alloc
  957. * @udata: user data
  958. */
  959. static struct ib_cq *i40iw_create_cq(struct ib_device *ibdev,
  960. const struct ib_cq_init_attr *attr,
  961. struct ib_ucontext *context,
  962. struct ib_udata *udata)
  963. {
  964. struct i40iw_device *iwdev = to_iwdev(ibdev);
  965. struct i40iw_cq *iwcq;
  966. struct i40iw_pbl *iwpbl;
  967. u32 cq_num = 0;
  968. struct i40iw_sc_cq *cq;
  969. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  970. struct i40iw_cq_init_info info;
  971. enum i40iw_status_code status;
  972. struct i40iw_cqp_request *cqp_request;
  973. struct cqp_commands_info *cqp_info;
  974. struct i40iw_cq_uk_init_info *ukinfo = &info.cq_uk_init_info;
  975. unsigned long flags;
  976. int err_code;
  977. int entries = attr->cqe;
  978. if (entries > iwdev->max_cqe)
  979. return ERR_PTR(-EINVAL);
  980. iwcq = kzalloc(sizeof(*iwcq), GFP_KERNEL);
  981. if (!iwcq)
  982. return ERR_PTR(-ENOMEM);
  983. memset(&info, 0, sizeof(info));
  984. err_code = i40iw_alloc_resource(iwdev, iwdev->allocated_cqs,
  985. iwdev->max_cq, &cq_num,
  986. &iwdev->next_cq);
  987. if (err_code)
  988. goto error;
  989. cq = &iwcq->sc_cq;
  990. cq->back_cq = (void *)iwcq;
  991. spin_lock_init(&iwcq->lock);
  992. info.dev = dev;
  993. ukinfo->cq_size = max(entries, 4);
  994. ukinfo->cq_id = cq_num;
  995. iwcq->ibcq.cqe = info.cq_uk_init_info.cq_size;
  996. info.ceqe_mask = 0;
  997. info.ceq_id = 0;
  998. info.ceq_id_valid = true;
  999. info.ceqe_mask = 1;
  1000. info.type = I40IW_CQ_TYPE_IWARP;
  1001. if (context) {
  1002. struct i40iw_ucontext *ucontext;
  1003. struct i40iw_create_cq_req req;
  1004. struct i40iw_cq_mr *cqmr;
  1005. memset(&req, 0, sizeof(req));
  1006. iwcq->user_mode = true;
  1007. ucontext = to_ucontext(context);
  1008. if (ib_copy_from_udata(&req, udata, sizeof(struct i40iw_create_cq_req)))
  1009. goto cq_free_resources;
  1010. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  1011. iwpbl = i40iw_get_pbl((unsigned long)req.user_cq_buffer,
  1012. &ucontext->cq_reg_mem_list);
  1013. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  1014. if (!iwpbl) {
  1015. err_code = -EPROTO;
  1016. goto cq_free_resources;
  1017. }
  1018. iwcq->iwpbl = iwpbl;
  1019. iwcq->cq_mem_size = 0;
  1020. cqmr = &iwpbl->cq_mr;
  1021. info.shadow_area_pa = cpu_to_le64(cqmr->shadow);
  1022. if (iwpbl->pbl_allocated) {
  1023. info.virtual_map = true;
  1024. info.pbl_chunk_size = 1;
  1025. info.first_pm_pbl_idx = cqmr->cq_pbl.idx;
  1026. } else {
  1027. info.cq_base_pa = cqmr->cq_pbl.addr;
  1028. }
  1029. } else {
  1030. /* Kmode allocations */
  1031. int rsize;
  1032. int shadow;
  1033. rsize = info.cq_uk_init_info.cq_size * sizeof(struct i40iw_cqe);
  1034. rsize = round_up(rsize, 256);
  1035. shadow = I40IW_SHADOW_AREA_SIZE << 3;
  1036. status = i40iw_allocate_dma_mem(dev->hw, &iwcq->kmem,
  1037. rsize + shadow, 256);
  1038. if (status) {
  1039. err_code = -ENOMEM;
  1040. goto cq_free_resources;
  1041. }
  1042. ukinfo->cq_base = iwcq->kmem.va;
  1043. info.cq_base_pa = iwcq->kmem.pa;
  1044. info.shadow_area_pa = info.cq_base_pa + rsize;
  1045. ukinfo->shadow_area = iwcq->kmem.va + rsize;
  1046. }
  1047. if (dev->iw_priv_cq_ops->cq_init(cq, &info)) {
  1048. i40iw_pr_err("init cq fail\n");
  1049. err_code = -EPROTO;
  1050. goto cq_free_resources;
  1051. }
  1052. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
  1053. if (!cqp_request) {
  1054. err_code = -ENOMEM;
  1055. goto cq_free_resources;
  1056. }
  1057. cqp_info = &cqp_request->info;
  1058. cqp_info->cqp_cmd = OP_CQ_CREATE;
  1059. cqp_info->post_sq = 1;
  1060. cqp_info->in.u.cq_create.cq = cq;
  1061. cqp_info->in.u.cq_create.scratch = (uintptr_t)cqp_request;
  1062. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  1063. if (status) {
  1064. i40iw_pr_err("CQP-OP Create QP fail");
  1065. err_code = -EPROTO;
  1066. goto cq_free_resources;
  1067. }
  1068. if (context) {
  1069. struct i40iw_create_cq_resp resp;
  1070. memset(&resp, 0, sizeof(resp));
  1071. resp.cq_id = info.cq_uk_init_info.cq_id;
  1072. resp.cq_size = info.cq_uk_init_info.cq_size;
  1073. if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
  1074. i40iw_pr_err("copy to user data\n");
  1075. err_code = -EPROTO;
  1076. goto cq_destroy;
  1077. }
  1078. }
  1079. return (struct ib_cq *)iwcq;
  1080. cq_destroy:
  1081. cq_wq_destroy(iwdev, cq);
  1082. cq_free_resources:
  1083. cq_free_resources(iwdev, iwcq);
  1084. error:
  1085. kfree(iwcq);
  1086. return ERR_PTR(err_code);
  1087. }
  1088. /**
  1089. * i40iw_get_user_access - get hw access from IB access
  1090. * @acc: IB access to return hw access
  1091. */
  1092. static inline u16 i40iw_get_user_access(int acc)
  1093. {
  1094. u16 access = 0;
  1095. access |= (acc & IB_ACCESS_LOCAL_WRITE) ? I40IW_ACCESS_FLAGS_LOCALWRITE : 0;
  1096. access |= (acc & IB_ACCESS_REMOTE_WRITE) ? I40IW_ACCESS_FLAGS_REMOTEWRITE : 0;
  1097. access |= (acc & IB_ACCESS_REMOTE_READ) ? I40IW_ACCESS_FLAGS_REMOTEREAD : 0;
  1098. access |= (acc & IB_ACCESS_MW_BIND) ? I40IW_ACCESS_FLAGS_BIND_WINDOW : 0;
  1099. return access;
  1100. }
  1101. /**
  1102. * i40iw_free_stag - free stag resource
  1103. * @iwdev: iwarp device
  1104. * @stag: stag to free
  1105. */
  1106. static void i40iw_free_stag(struct i40iw_device *iwdev, u32 stag)
  1107. {
  1108. u32 stag_idx;
  1109. stag_idx = (stag & iwdev->mr_stagmask) >> I40IW_CQPSQ_STAG_IDX_SHIFT;
  1110. i40iw_free_resource(iwdev, iwdev->allocated_mrs, stag_idx);
  1111. }
  1112. /**
  1113. * i40iw_create_stag - create random stag
  1114. * @iwdev: iwarp device
  1115. */
  1116. static u32 i40iw_create_stag(struct i40iw_device *iwdev)
  1117. {
  1118. u32 stag = 0;
  1119. u32 stag_index = 0;
  1120. u32 next_stag_index;
  1121. u32 driver_key;
  1122. u32 random;
  1123. u8 consumer_key;
  1124. int ret;
  1125. get_random_bytes(&random, sizeof(random));
  1126. consumer_key = (u8)random;
  1127. driver_key = random & ~iwdev->mr_stagmask;
  1128. next_stag_index = (random & iwdev->mr_stagmask) >> 8;
  1129. next_stag_index %= iwdev->max_mr;
  1130. ret = i40iw_alloc_resource(iwdev,
  1131. iwdev->allocated_mrs, iwdev->max_mr,
  1132. &stag_index, &next_stag_index);
  1133. if (!ret) {
  1134. stag = stag_index << I40IW_CQPSQ_STAG_IDX_SHIFT;
  1135. stag |= driver_key;
  1136. stag += (u32)consumer_key;
  1137. }
  1138. return stag;
  1139. }
  1140. /**
  1141. * i40iw_next_pbl_addr - Get next pbl address
  1142. * @palloc: Poiner to allocated pbles
  1143. * @pbl: pointer to a pble
  1144. * @pinfo: info pointer
  1145. * @idx: index
  1146. */
  1147. static inline u64 *i40iw_next_pbl_addr(struct i40iw_pble_alloc *palloc,
  1148. u64 *pbl,
  1149. struct i40iw_pble_info **pinfo,
  1150. u32 *idx)
  1151. {
  1152. *idx += 1;
  1153. if ((!(*pinfo)) || (*idx != (*pinfo)->cnt))
  1154. return ++pbl;
  1155. *idx = 0;
  1156. (*pinfo)++;
  1157. return (u64 *)(*pinfo)->addr;
  1158. }
  1159. /**
  1160. * i40iw_copy_user_pgaddrs - copy user page address to pble's os locally
  1161. * @iwmr: iwmr for IB's user page addresses
  1162. * @pbl: ple pointer to save 1 level or 0 level pble
  1163. * @level: indicated level 0, 1 or 2
  1164. */
  1165. static void i40iw_copy_user_pgaddrs(struct i40iw_mr *iwmr,
  1166. u64 *pbl,
  1167. enum i40iw_pble_level level)
  1168. {
  1169. struct ib_umem *region = iwmr->region;
  1170. struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
  1171. int chunk_pages, entry, pg_shift, i;
  1172. struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
  1173. struct i40iw_pble_info *pinfo;
  1174. struct scatterlist *sg;
  1175. u32 idx = 0;
  1176. pinfo = (level == I40IW_LEVEL_1) ? NULL : palloc->level2.leaf;
  1177. pg_shift = ffs(region->page_size) - 1;
  1178. for_each_sg(region->sg_head.sgl, sg, region->nmap, entry) {
  1179. chunk_pages = sg_dma_len(sg) >> pg_shift;
  1180. if ((iwmr->type == IW_MEMREG_TYPE_QP) &&
  1181. !iwpbl->qp_mr.sq_page)
  1182. iwpbl->qp_mr.sq_page = sg_page(sg);
  1183. for (i = 0; i < chunk_pages; i++) {
  1184. *pbl = cpu_to_le64(sg_dma_address(sg) + region->page_size * i);
  1185. pbl = i40iw_next_pbl_addr(palloc, pbl, &pinfo, &idx);
  1186. }
  1187. }
  1188. }
  1189. /**
  1190. * i40iw_setup_pbles - copy user pg address to pble's
  1191. * @iwdev: iwarp device
  1192. * @iwmr: mr pointer for this memory registration
  1193. * @use_pbles: flag if to use pble's or memory (level 0)
  1194. */
  1195. static int i40iw_setup_pbles(struct i40iw_device *iwdev,
  1196. struct i40iw_mr *iwmr,
  1197. bool use_pbles)
  1198. {
  1199. struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
  1200. struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
  1201. struct i40iw_pble_info *pinfo;
  1202. u64 *pbl;
  1203. enum i40iw_status_code status;
  1204. enum i40iw_pble_level level = I40IW_LEVEL_1;
  1205. if (!use_pbles && (iwmr->page_cnt > MAX_SAVE_PAGE_ADDRS))
  1206. return -ENOMEM;
  1207. if (use_pbles) {
  1208. mutex_lock(&iwdev->pbl_mutex);
  1209. status = i40iw_get_pble(&iwdev->sc_dev, iwdev->pble_rsrc, palloc, iwmr->page_cnt);
  1210. mutex_unlock(&iwdev->pbl_mutex);
  1211. if (status)
  1212. return -ENOMEM;
  1213. iwpbl->pbl_allocated = true;
  1214. level = palloc->level;
  1215. pinfo = (level == I40IW_LEVEL_1) ? &palloc->level1 : palloc->level2.leaf;
  1216. pbl = (u64 *)pinfo->addr;
  1217. } else {
  1218. pbl = iwmr->pgaddrmem;
  1219. }
  1220. i40iw_copy_user_pgaddrs(iwmr, pbl, level);
  1221. return 0;
  1222. }
  1223. /**
  1224. * i40iw_handle_q_mem - handle memory for qp and cq
  1225. * @iwdev: iwarp device
  1226. * @req: information for q memory management
  1227. * @iwpbl: pble struct
  1228. * @use_pbles: flag to use pble
  1229. */
  1230. static int i40iw_handle_q_mem(struct i40iw_device *iwdev,
  1231. struct i40iw_mem_reg_req *req,
  1232. struct i40iw_pbl *iwpbl,
  1233. bool use_pbles)
  1234. {
  1235. struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
  1236. struct i40iw_mr *iwmr = iwpbl->iwmr;
  1237. struct i40iw_qp_mr *qpmr = &iwpbl->qp_mr;
  1238. struct i40iw_cq_mr *cqmr = &iwpbl->cq_mr;
  1239. struct i40iw_hmc_pble *hmc_p;
  1240. u64 *arr = iwmr->pgaddrmem;
  1241. int err;
  1242. int total;
  1243. total = req->sq_pages + req->rq_pages + req->cq_pages;
  1244. err = i40iw_setup_pbles(iwdev, iwmr, use_pbles);
  1245. if (err)
  1246. return err;
  1247. if (use_pbles && (palloc->level != I40IW_LEVEL_1)) {
  1248. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1249. iwpbl->pbl_allocated = false;
  1250. return -ENOMEM;
  1251. }
  1252. if (use_pbles)
  1253. arr = (u64 *)palloc->level1.addr;
  1254. if (req->reg_type == IW_MEMREG_TYPE_QP) {
  1255. hmc_p = &qpmr->sq_pbl;
  1256. qpmr->shadow = (dma_addr_t)arr[total];
  1257. if (use_pbles) {
  1258. hmc_p->idx = palloc->level1.idx;
  1259. hmc_p = &qpmr->rq_pbl;
  1260. hmc_p->idx = palloc->level1.idx + req->sq_pages;
  1261. } else {
  1262. hmc_p->addr = arr[0];
  1263. hmc_p = &qpmr->rq_pbl;
  1264. hmc_p->addr = arr[1];
  1265. }
  1266. } else { /* CQ */
  1267. hmc_p = &cqmr->cq_pbl;
  1268. cqmr->shadow = (dma_addr_t)arr[total];
  1269. if (use_pbles)
  1270. hmc_p->idx = palloc->level1.idx;
  1271. else
  1272. hmc_p->addr = arr[0];
  1273. }
  1274. return err;
  1275. }
  1276. /**
  1277. * i40iw_hwreg_mr - send cqp command for memory registration
  1278. * @iwdev: iwarp device
  1279. * @iwmr: iwarp mr pointer
  1280. * @access: access for MR
  1281. */
  1282. static int i40iw_hwreg_mr(struct i40iw_device *iwdev,
  1283. struct i40iw_mr *iwmr,
  1284. u16 access)
  1285. {
  1286. struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
  1287. struct i40iw_reg_ns_stag_info *stag_info;
  1288. struct i40iw_pd *iwpd = to_iwpd(iwmr->ibmr.pd);
  1289. struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
  1290. enum i40iw_status_code status;
  1291. int err = 0;
  1292. struct i40iw_cqp_request *cqp_request;
  1293. struct cqp_commands_info *cqp_info;
  1294. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
  1295. if (!cqp_request)
  1296. return -ENOMEM;
  1297. cqp_info = &cqp_request->info;
  1298. stag_info = &cqp_info->in.u.mr_reg_non_shared.info;
  1299. memset(stag_info, 0, sizeof(*stag_info));
  1300. stag_info->va = (void *)(unsigned long)iwpbl->user_base;
  1301. stag_info->stag_idx = iwmr->stag >> I40IW_CQPSQ_STAG_IDX_SHIFT;
  1302. stag_info->stag_key = (u8)iwmr->stag;
  1303. stag_info->total_len = iwmr->length;
  1304. stag_info->access_rights = access;
  1305. stag_info->pd_id = iwpd->sc_pd.pd_id;
  1306. stag_info->addr_type = I40IW_ADDR_TYPE_VA_BASED;
  1307. if (iwmr->page_cnt > 1) {
  1308. if (palloc->level == I40IW_LEVEL_1) {
  1309. stag_info->first_pm_pbl_index = palloc->level1.idx;
  1310. stag_info->chunk_size = 1;
  1311. } else {
  1312. stag_info->first_pm_pbl_index = palloc->level2.root.idx;
  1313. stag_info->chunk_size = 3;
  1314. }
  1315. } else {
  1316. stag_info->reg_addr_pa = iwmr->pgaddrmem[0];
  1317. }
  1318. cqp_info->cqp_cmd = OP_MR_REG_NON_SHARED;
  1319. cqp_info->post_sq = 1;
  1320. cqp_info->in.u.mr_reg_non_shared.dev = &iwdev->sc_dev;
  1321. cqp_info->in.u.mr_reg_non_shared.scratch = (uintptr_t)cqp_request;
  1322. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  1323. if (status) {
  1324. err = -ENOMEM;
  1325. i40iw_pr_err("CQP-OP MR Reg fail");
  1326. }
  1327. return err;
  1328. }
  1329. /**
  1330. * i40iw_reg_user_mr - Register a user memory region
  1331. * @pd: ptr of pd
  1332. * @start: virtual start address
  1333. * @length: length of mr
  1334. * @virt: virtual address
  1335. * @acc: access of mr
  1336. * @udata: user data
  1337. */
  1338. static struct ib_mr *i40iw_reg_user_mr(struct ib_pd *pd,
  1339. u64 start,
  1340. u64 length,
  1341. u64 virt,
  1342. int acc,
  1343. struct ib_udata *udata)
  1344. {
  1345. struct i40iw_pd *iwpd = to_iwpd(pd);
  1346. struct i40iw_device *iwdev = to_iwdev(pd->device);
  1347. struct i40iw_ucontext *ucontext;
  1348. struct i40iw_pble_alloc *palloc;
  1349. struct i40iw_pbl *iwpbl;
  1350. struct i40iw_mr *iwmr;
  1351. struct ib_umem *region;
  1352. struct i40iw_mem_reg_req req;
  1353. u32 pbl_depth = 0;
  1354. u32 stag = 0;
  1355. u16 access;
  1356. u32 region_length;
  1357. bool use_pbles = false;
  1358. unsigned long flags;
  1359. int err = -ENOSYS;
  1360. region = ib_umem_get(pd->uobject->context, start, length, acc, 0);
  1361. if (IS_ERR(region))
  1362. return (struct ib_mr *)region;
  1363. if (ib_copy_from_udata(&req, udata, sizeof(req))) {
  1364. ib_umem_release(region);
  1365. return ERR_PTR(-EFAULT);
  1366. }
  1367. iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
  1368. if (!iwmr) {
  1369. ib_umem_release(region);
  1370. return ERR_PTR(-ENOMEM);
  1371. }
  1372. iwpbl = &iwmr->iwpbl;
  1373. iwpbl->iwmr = iwmr;
  1374. iwmr->region = region;
  1375. iwmr->ibmr.pd = pd;
  1376. iwmr->ibmr.device = pd->device;
  1377. ucontext = to_ucontext(pd->uobject->context);
  1378. region_length = region->length + (start & 0xfff);
  1379. pbl_depth = region_length >> 12;
  1380. pbl_depth += (region_length & (4096 - 1)) ? 1 : 0;
  1381. iwmr->length = region->length;
  1382. iwpbl->user_base = virt;
  1383. palloc = &iwpbl->pble_alloc;
  1384. iwmr->type = req.reg_type;
  1385. iwmr->page_cnt = pbl_depth;
  1386. switch (req.reg_type) {
  1387. case IW_MEMREG_TYPE_QP:
  1388. use_pbles = ((req.sq_pages + req.rq_pages) > 2);
  1389. err = i40iw_handle_q_mem(iwdev, &req, iwpbl, use_pbles);
  1390. if (err)
  1391. goto error;
  1392. spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
  1393. list_add_tail(&iwpbl->list, &ucontext->qp_reg_mem_list);
  1394. spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
  1395. break;
  1396. case IW_MEMREG_TYPE_CQ:
  1397. use_pbles = (req.cq_pages > 1);
  1398. err = i40iw_handle_q_mem(iwdev, &req, iwpbl, use_pbles);
  1399. if (err)
  1400. goto error;
  1401. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  1402. list_add_tail(&iwpbl->list, &ucontext->cq_reg_mem_list);
  1403. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  1404. break;
  1405. case IW_MEMREG_TYPE_MEM:
  1406. access = I40IW_ACCESS_FLAGS_LOCALREAD;
  1407. use_pbles = (iwmr->page_cnt != 1);
  1408. err = i40iw_setup_pbles(iwdev, iwmr, use_pbles);
  1409. if (err)
  1410. goto error;
  1411. access |= i40iw_get_user_access(acc);
  1412. stag = i40iw_create_stag(iwdev);
  1413. if (!stag) {
  1414. err = -ENOMEM;
  1415. goto error;
  1416. }
  1417. iwmr->stag = stag;
  1418. iwmr->ibmr.rkey = stag;
  1419. iwmr->ibmr.lkey = stag;
  1420. err = i40iw_hwreg_mr(iwdev, iwmr, access);
  1421. if (err) {
  1422. i40iw_free_stag(iwdev, stag);
  1423. goto error;
  1424. }
  1425. break;
  1426. default:
  1427. goto error;
  1428. }
  1429. iwmr->type = req.reg_type;
  1430. if (req.reg_type == IW_MEMREG_TYPE_MEM)
  1431. i40iw_add_pdusecount(iwpd);
  1432. return &iwmr->ibmr;
  1433. error:
  1434. if (palloc->level != I40IW_LEVEL_0)
  1435. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1436. ib_umem_release(region);
  1437. kfree(iwmr);
  1438. return ERR_PTR(err);
  1439. }
  1440. /**
  1441. * i40iw_reg_phys_mr - register kernel physical memory
  1442. * @pd: ibpd pointer
  1443. * @addr: physical address of memory to register
  1444. * @size: size of memory to register
  1445. * @acc: Access rights
  1446. * @iova_start: start of virtual address for physical buffers
  1447. */
  1448. struct ib_mr *i40iw_reg_phys_mr(struct ib_pd *pd,
  1449. u64 addr,
  1450. u64 size,
  1451. int acc,
  1452. u64 *iova_start)
  1453. {
  1454. struct i40iw_pd *iwpd = to_iwpd(pd);
  1455. struct i40iw_device *iwdev = to_iwdev(pd->device);
  1456. struct i40iw_pbl *iwpbl;
  1457. struct i40iw_mr *iwmr;
  1458. enum i40iw_status_code status;
  1459. u32 stag;
  1460. u16 access = I40IW_ACCESS_FLAGS_LOCALREAD;
  1461. int ret;
  1462. iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
  1463. if (!iwmr)
  1464. return ERR_PTR(-ENOMEM);
  1465. iwmr->ibmr.pd = pd;
  1466. iwmr->ibmr.device = pd->device;
  1467. iwpbl = &iwmr->iwpbl;
  1468. iwpbl->iwmr = iwmr;
  1469. iwmr->type = IW_MEMREG_TYPE_MEM;
  1470. iwpbl->user_base = *iova_start;
  1471. stag = i40iw_create_stag(iwdev);
  1472. if (!stag) {
  1473. ret = -EOVERFLOW;
  1474. goto err;
  1475. }
  1476. access |= i40iw_get_user_access(acc);
  1477. iwmr->stag = stag;
  1478. iwmr->ibmr.rkey = stag;
  1479. iwmr->ibmr.lkey = stag;
  1480. iwmr->page_cnt = 1;
  1481. iwmr->pgaddrmem[0] = addr;
  1482. status = i40iw_hwreg_mr(iwdev, iwmr, access);
  1483. if (status) {
  1484. i40iw_free_stag(iwdev, stag);
  1485. ret = -ENOMEM;
  1486. goto err;
  1487. }
  1488. i40iw_add_pdusecount(iwpd);
  1489. return &iwmr->ibmr;
  1490. err:
  1491. kfree(iwmr);
  1492. return ERR_PTR(ret);
  1493. }
  1494. /**
  1495. * i40iw_get_dma_mr - register physical mem
  1496. * @pd: ptr of pd
  1497. * @acc: access for memory
  1498. */
  1499. static struct ib_mr *i40iw_get_dma_mr(struct ib_pd *pd, int acc)
  1500. {
  1501. u64 kva = 0;
  1502. return i40iw_reg_phys_mr(pd, 0, 0xffffffffffULL, acc, &kva);
  1503. }
  1504. /**
  1505. * i40iw_del_mem_list - Deleting pbl list entries for CQ/QP
  1506. * @iwmr: iwmr for IB's user page addresses
  1507. * @ucontext: ptr to user context
  1508. */
  1509. static void i40iw_del_memlist(struct i40iw_mr *iwmr,
  1510. struct i40iw_ucontext *ucontext)
  1511. {
  1512. struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
  1513. unsigned long flags;
  1514. switch (iwmr->type) {
  1515. case IW_MEMREG_TYPE_CQ:
  1516. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  1517. if (!list_empty(&ucontext->cq_reg_mem_list))
  1518. list_del(&iwpbl->list);
  1519. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  1520. break;
  1521. case IW_MEMREG_TYPE_QP:
  1522. spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
  1523. if (!list_empty(&ucontext->qp_reg_mem_list))
  1524. list_del(&iwpbl->list);
  1525. spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
  1526. break;
  1527. default:
  1528. break;
  1529. }
  1530. }
  1531. /**
  1532. * i40iw_dereg_mr - deregister mr
  1533. * @ib_mr: mr ptr for dereg
  1534. */
  1535. static int i40iw_dereg_mr(struct ib_mr *ib_mr)
  1536. {
  1537. struct ib_pd *ibpd = ib_mr->pd;
  1538. struct i40iw_pd *iwpd = to_iwpd(ibpd);
  1539. struct i40iw_mr *iwmr = to_iwmr(ib_mr);
  1540. struct i40iw_device *iwdev = to_iwdev(ib_mr->device);
  1541. enum i40iw_status_code status;
  1542. struct i40iw_dealloc_stag_info *info;
  1543. struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
  1544. struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
  1545. struct i40iw_cqp_request *cqp_request;
  1546. struct cqp_commands_info *cqp_info;
  1547. u32 stag_idx;
  1548. if (iwmr->region)
  1549. ib_umem_release(iwmr->region);
  1550. if (iwmr->type != IW_MEMREG_TYPE_MEM) {
  1551. if (ibpd->uobject) {
  1552. struct i40iw_ucontext *ucontext;
  1553. ucontext = to_ucontext(ibpd->uobject->context);
  1554. i40iw_del_memlist(iwmr, ucontext);
  1555. }
  1556. if (iwpbl->pbl_allocated)
  1557. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1558. kfree(iwpbl->iwmr);
  1559. iwpbl->iwmr = NULL;
  1560. return 0;
  1561. }
  1562. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
  1563. if (!cqp_request)
  1564. return -ENOMEM;
  1565. cqp_info = &cqp_request->info;
  1566. info = &cqp_info->in.u.dealloc_stag.info;
  1567. memset(info, 0, sizeof(*info));
  1568. info->pd_id = cpu_to_le32(iwpd->sc_pd.pd_id & 0x00007fff);
  1569. info->stag_idx = RS_64_1(ib_mr->rkey, I40IW_CQPSQ_STAG_IDX_SHIFT);
  1570. stag_idx = info->stag_idx;
  1571. info->mr = true;
  1572. if (iwpbl->pbl_allocated)
  1573. info->dealloc_pbl = true;
  1574. cqp_info->cqp_cmd = OP_DEALLOC_STAG;
  1575. cqp_info->post_sq = 1;
  1576. cqp_info->in.u.dealloc_stag.dev = &iwdev->sc_dev;
  1577. cqp_info->in.u.dealloc_stag.scratch = (uintptr_t)cqp_request;
  1578. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  1579. if (status)
  1580. i40iw_pr_err("CQP-OP dealloc failed for stag_idx = 0x%x\n", stag_idx);
  1581. i40iw_rem_pdusecount(iwpd, iwdev);
  1582. i40iw_free_stag(iwdev, iwmr->stag);
  1583. if (iwpbl->pbl_allocated)
  1584. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1585. kfree(iwmr);
  1586. return 0;
  1587. }
  1588. /**
  1589. * i40iw_show_rev
  1590. */
  1591. static ssize_t i40iw_show_rev(struct device *dev,
  1592. struct device_attribute *attr, char *buf)
  1593. {
  1594. struct i40iw_ib_device *iwibdev = container_of(dev,
  1595. struct i40iw_ib_device,
  1596. ibdev.dev);
  1597. u32 hw_rev = iwibdev->iwdev->sc_dev.hw_rev;
  1598. return sprintf(buf, "%x\n", hw_rev);
  1599. }
  1600. /**
  1601. * i40iw_show_fw_ver
  1602. */
  1603. static ssize_t i40iw_show_fw_ver(struct device *dev,
  1604. struct device_attribute *attr, char *buf)
  1605. {
  1606. u32 firmware_version = I40IW_FW_VERSION;
  1607. return sprintf(buf, "%u.%u\n", firmware_version,
  1608. (firmware_version & 0x000000ff));
  1609. }
  1610. /**
  1611. * i40iw_show_hca
  1612. */
  1613. static ssize_t i40iw_show_hca(struct device *dev,
  1614. struct device_attribute *attr, char *buf)
  1615. {
  1616. return sprintf(buf, "I40IW\n");
  1617. }
  1618. /**
  1619. * i40iw_show_board
  1620. */
  1621. static ssize_t i40iw_show_board(struct device *dev,
  1622. struct device_attribute *attr,
  1623. char *buf)
  1624. {
  1625. return sprintf(buf, "%.*s\n", 32, "I40IW Board ID");
  1626. }
  1627. static DEVICE_ATTR(hw_rev, S_IRUGO, i40iw_show_rev, NULL);
  1628. static DEVICE_ATTR(fw_ver, S_IRUGO, i40iw_show_fw_ver, NULL);
  1629. static DEVICE_ATTR(hca_type, S_IRUGO, i40iw_show_hca, NULL);
  1630. static DEVICE_ATTR(board_id, S_IRUGO, i40iw_show_board, NULL);
  1631. static struct device_attribute *i40iw_dev_attributes[] = {
  1632. &dev_attr_hw_rev,
  1633. &dev_attr_fw_ver,
  1634. &dev_attr_hca_type,
  1635. &dev_attr_board_id
  1636. };
  1637. /**
  1638. * i40iw_copy_sg_list - copy sg list for qp
  1639. * @sg_list: copied into sg_list
  1640. * @sgl: copy from sgl
  1641. * @num_sges: count of sg entries
  1642. */
  1643. static void i40iw_copy_sg_list(struct i40iw_sge *sg_list, struct ib_sge *sgl, int num_sges)
  1644. {
  1645. unsigned int i;
  1646. for (i = 0; (i < num_sges) && (i < I40IW_MAX_WQ_FRAGMENT_COUNT); i++) {
  1647. sg_list[i].tag_off = sgl[i].addr;
  1648. sg_list[i].len = sgl[i].length;
  1649. sg_list[i].stag = sgl[i].lkey;
  1650. }
  1651. }
  1652. /**
  1653. * i40iw_post_send - kernel application wr
  1654. * @ibqp: qp ptr for wr
  1655. * @ib_wr: work request ptr
  1656. * @bad_wr: return of bad wr if err
  1657. */
  1658. static int i40iw_post_send(struct ib_qp *ibqp,
  1659. struct ib_send_wr *ib_wr,
  1660. struct ib_send_wr **bad_wr)
  1661. {
  1662. struct i40iw_qp *iwqp;
  1663. struct i40iw_qp_uk *ukqp;
  1664. struct i40iw_post_sq_info info;
  1665. enum i40iw_status_code ret;
  1666. int err = 0;
  1667. unsigned long flags;
  1668. iwqp = (struct i40iw_qp *)ibqp;
  1669. ukqp = &iwqp->sc_qp.qp_uk;
  1670. spin_lock_irqsave(&iwqp->lock, flags);
  1671. while (ib_wr) {
  1672. memset(&info, 0, sizeof(info));
  1673. info.wr_id = (u64)(ib_wr->wr_id);
  1674. if ((ib_wr->send_flags & IB_SEND_SIGNALED) || iwqp->sig_all)
  1675. info.signaled = true;
  1676. if (ib_wr->send_flags & IB_SEND_FENCE)
  1677. info.read_fence = true;
  1678. switch (ib_wr->opcode) {
  1679. case IB_WR_SEND:
  1680. if (ib_wr->send_flags & IB_SEND_SOLICITED)
  1681. info.op_type = I40IW_OP_TYPE_SEND_SOL;
  1682. else
  1683. info.op_type = I40IW_OP_TYPE_SEND;
  1684. if (ib_wr->send_flags & IB_SEND_INLINE) {
  1685. info.op.inline_send.data = (void *)(unsigned long)ib_wr->sg_list[0].addr;
  1686. info.op.inline_send.len = ib_wr->sg_list[0].length;
  1687. ret = ukqp->ops.iw_inline_send(ukqp, &info, rdma_wr(ib_wr)->rkey, false);
  1688. } else {
  1689. info.op.send.num_sges = ib_wr->num_sge;
  1690. info.op.send.sg_list = (struct i40iw_sge *)ib_wr->sg_list;
  1691. ret = ukqp->ops.iw_send(ukqp, &info, rdma_wr(ib_wr)->rkey, false);
  1692. }
  1693. if (ret)
  1694. err = -EIO;
  1695. break;
  1696. case IB_WR_RDMA_WRITE:
  1697. info.op_type = I40IW_OP_TYPE_RDMA_WRITE;
  1698. if (ib_wr->send_flags & IB_SEND_INLINE) {
  1699. info.op.inline_rdma_write.data = (void *)(unsigned long)ib_wr->sg_list[0].addr;
  1700. info.op.inline_rdma_write.len = ib_wr->sg_list[0].length;
  1701. info.op.inline_rdma_write.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr;
  1702. info.op.inline_rdma_write.rem_addr.stag = rdma_wr(ib_wr)->rkey;
  1703. info.op.inline_rdma_write.rem_addr.len = ib_wr->sg_list->length;
  1704. ret = ukqp->ops.iw_inline_rdma_write(ukqp, &info, false);
  1705. } else {
  1706. info.op.rdma_write.lo_sg_list = (void *)ib_wr->sg_list;
  1707. info.op.rdma_write.num_lo_sges = ib_wr->num_sge;
  1708. info.op.rdma_write.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr;
  1709. info.op.rdma_write.rem_addr.stag = rdma_wr(ib_wr)->rkey;
  1710. info.op.rdma_write.rem_addr.len = ib_wr->sg_list->length;
  1711. ret = ukqp->ops.iw_rdma_write(ukqp, &info, false);
  1712. }
  1713. if (ret)
  1714. err = -EIO;
  1715. break;
  1716. case IB_WR_RDMA_READ:
  1717. info.op_type = I40IW_OP_TYPE_RDMA_READ;
  1718. info.op.rdma_read.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr;
  1719. info.op.rdma_read.rem_addr.stag = rdma_wr(ib_wr)->rkey;
  1720. info.op.rdma_read.rem_addr.len = ib_wr->sg_list->length;
  1721. info.op.rdma_read.lo_addr.tag_off = ib_wr->sg_list->addr;
  1722. info.op.rdma_read.lo_addr.stag = ib_wr->sg_list->lkey;
  1723. info.op.rdma_read.lo_addr.len = ib_wr->sg_list->length;
  1724. ret = ukqp->ops.iw_rdma_read(ukqp, &info, false, false);
  1725. if (ret)
  1726. err = -EIO;
  1727. break;
  1728. default:
  1729. err = -EINVAL;
  1730. i40iw_pr_err(" upost_send bad opcode = 0x%x\n",
  1731. ib_wr->opcode);
  1732. break;
  1733. }
  1734. if (err)
  1735. break;
  1736. ib_wr = ib_wr->next;
  1737. }
  1738. if (err)
  1739. *bad_wr = ib_wr;
  1740. else
  1741. ukqp->ops.iw_qp_post_wr(ukqp);
  1742. spin_unlock_irqrestore(&iwqp->lock, flags);
  1743. return err;
  1744. }
  1745. /**
  1746. * i40iw_post_recv - post receive wr for kernel application
  1747. * @ibqp: ib qp pointer
  1748. * @ib_wr: work request for receive
  1749. * @bad_wr: bad wr caused an error
  1750. */
  1751. static int i40iw_post_recv(struct ib_qp *ibqp,
  1752. struct ib_recv_wr *ib_wr,
  1753. struct ib_recv_wr **bad_wr)
  1754. {
  1755. struct i40iw_qp *iwqp;
  1756. struct i40iw_qp_uk *ukqp;
  1757. struct i40iw_post_rq_info post_recv;
  1758. struct i40iw_sge sg_list[I40IW_MAX_WQ_FRAGMENT_COUNT];
  1759. enum i40iw_status_code ret = 0;
  1760. unsigned long flags;
  1761. iwqp = (struct i40iw_qp *)ibqp;
  1762. ukqp = &iwqp->sc_qp.qp_uk;
  1763. memset(&post_recv, 0, sizeof(post_recv));
  1764. spin_lock_irqsave(&iwqp->lock, flags);
  1765. while (ib_wr) {
  1766. post_recv.num_sges = ib_wr->num_sge;
  1767. post_recv.wr_id = ib_wr->wr_id;
  1768. i40iw_copy_sg_list(sg_list, ib_wr->sg_list, ib_wr->num_sge);
  1769. post_recv.sg_list = sg_list;
  1770. ret = ukqp->ops.iw_post_receive(ukqp, &post_recv);
  1771. if (ret) {
  1772. i40iw_pr_err(" post_recv err %d\n", ret);
  1773. *bad_wr = ib_wr;
  1774. goto out;
  1775. }
  1776. ib_wr = ib_wr->next;
  1777. }
  1778. out:
  1779. spin_unlock_irqrestore(&iwqp->lock, flags);
  1780. if (ret)
  1781. return -ENOSYS;
  1782. return 0;
  1783. }
  1784. /**
  1785. * i40iw_poll_cq - poll cq for completion (kernel apps)
  1786. * @ibcq: cq to poll
  1787. * @num_entries: number of entries to poll
  1788. * @entry: wr of entry completed
  1789. */
  1790. static int i40iw_poll_cq(struct ib_cq *ibcq,
  1791. int num_entries,
  1792. struct ib_wc *entry)
  1793. {
  1794. struct i40iw_cq *iwcq;
  1795. int cqe_count = 0;
  1796. struct i40iw_cq_poll_info cq_poll_info;
  1797. enum i40iw_status_code ret;
  1798. struct i40iw_cq_uk *ukcq;
  1799. struct i40iw_sc_qp *qp;
  1800. unsigned long flags;
  1801. iwcq = (struct i40iw_cq *)ibcq;
  1802. ukcq = &iwcq->sc_cq.cq_uk;
  1803. spin_lock_irqsave(&iwcq->lock, flags);
  1804. while (cqe_count < num_entries) {
  1805. ret = ukcq->ops.iw_cq_poll_completion(ukcq, &cq_poll_info, true);
  1806. if (ret == I40IW_ERR_QUEUE_EMPTY) {
  1807. break;
  1808. } else if (ret) {
  1809. if (!cqe_count)
  1810. cqe_count = -1;
  1811. break;
  1812. }
  1813. entry->wc_flags = 0;
  1814. entry->wr_id = cq_poll_info.wr_id;
  1815. if (!cq_poll_info.error)
  1816. entry->status = IB_WC_SUCCESS;
  1817. else
  1818. entry->status = IB_WC_WR_FLUSH_ERR;
  1819. switch (cq_poll_info.op_type) {
  1820. case I40IW_OP_TYPE_RDMA_WRITE:
  1821. entry->opcode = IB_WC_RDMA_WRITE;
  1822. break;
  1823. case I40IW_OP_TYPE_RDMA_READ_INV_STAG:
  1824. case I40IW_OP_TYPE_RDMA_READ:
  1825. entry->opcode = IB_WC_RDMA_READ;
  1826. break;
  1827. case I40IW_OP_TYPE_SEND_SOL:
  1828. case I40IW_OP_TYPE_SEND_SOL_INV:
  1829. case I40IW_OP_TYPE_SEND_INV:
  1830. case I40IW_OP_TYPE_SEND:
  1831. entry->opcode = IB_WC_SEND;
  1832. break;
  1833. case I40IW_OP_TYPE_REC:
  1834. entry->opcode = IB_WC_RECV;
  1835. break;
  1836. default:
  1837. entry->opcode = IB_WC_RECV;
  1838. break;
  1839. }
  1840. entry->vendor_err =
  1841. cq_poll_info.major_err << 16 | cq_poll_info.minor_err;
  1842. entry->ex.imm_data = 0;
  1843. qp = (struct i40iw_sc_qp *)cq_poll_info.qp_handle;
  1844. entry->qp = (struct ib_qp *)qp->back_qp;
  1845. entry->src_qp = cq_poll_info.qp_id;
  1846. entry->byte_len = cq_poll_info.bytes_xfered;
  1847. entry++;
  1848. cqe_count++;
  1849. }
  1850. spin_unlock_irqrestore(&iwcq->lock, flags);
  1851. return cqe_count;
  1852. }
  1853. /**
  1854. * i40iw_req_notify_cq - arm cq kernel application
  1855. * @ibcq: cq to arm
  1856. * @notify_flags: notofication flags
  1857. */
  1858. static int i40iw_req_notify_cq(struct ib_cq *ibcq,
  1859. enum ib_cq_notify_flags notify_flags)
  1860. {
  1861. struct i40iw_cq *iwcq;
  1862. struct i40iw_cq_uk *ukcq;
  1863. enum i40iw_completion_notify cq_notify = IW_CQ_COMPL_SOLICITED;
  1864. iwcq = (struct i40iw_cq *)ibcq;
  1865. ukcq = &iwcq->sc_cq.cq_uk;
  1866. if (notify_flags == IB_CQ_NEXT_COMP)
  1867. cq_notify = IW_CQ_COMPL_EVENT;
  1868. ukcq->ops.iw_cq_request_notification(ukcq, cq_notify);
  1869. return 0;
  1870. }
  1871. /**
  1872. * i40iw_port_immutable - return port's immutable data
  1873. * @ibdev: ib dev struct
  1874. * @port_num: port number
  1875. * @immutable: immutable data for the port return
  1876. */
  1877. static int i40iw_port_immutable(struct ib_device *ibdev, u8 port_num,
  1878. struct ib_port_immutable *immutable)
  1879. {
  1880. struct ib_port_attr attr;
  1881. int err;
  1882. err = i40iw_query_port(ibdev, port_num, &attr);
  1883. if (err)
  1884. return err;
  1885. immutable->pkey_tbl_len = attr.pkey_tbl_len;
  1886. immutable->gid_tbl_len = attr.gid_tbl_len;
  1887. immutable->core_cap_flags = RDMA_CORE_PORT_IWARP;
  1888. return 0;
  1889. }
  1890. /**
  1891. * i40iw_get_protocol_stats - Populates the rdma_stats structure
  1892. * @ibdev: ib dev struct
  1893. * @stats: iw protocol stats struct
  1894. */
  1895. static int i40iw_get_protocol_stats(struct ib_device *ibdev,
  1896. union rdma_protocol_stats *stats)
  1897. {
  1898. struct i40iw_device *iwdev = to_iwdev(ibdev);
  1899. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  1900. struct i40iw_dev_pestat *devstat = &dev->dev_pestat;
  1901. struct i40iw_dev_hw_stats *hw_stats = &devstat->hw_stats;
  1902. struct timespec curr_time;
  1903. static struct timespec last_rd_time = {0, 0};
  1904. enum i40iw_status_code status = 0;
  1905. unsigned long flags;
  1906. curr_time = current_kernel_time();
  1907. memset(stats, 0, sizeof(*stats));
  1908. if (dev->is_pf) {
  1909. spin_lock_irqsave(&devstat->stats_lock, flags);
  1910. devstat->ops.iw_hw_stat_read_all(devstat,
  1911. &devstat->hw_stats);
  1912. spin_unlock_irqrestore(&devstat->stats_lock, flags);
  1913. } else {
  1914. if (((u64)curr_time.tv_sec - (u64)last_rd_time.tv_sec) > 1)
  1915. status = i40iw_vchnl_vf_get_pe_stats(dev,
  1916. &devstat->hw_stats);
  1917. if (status)
  1918. return -ENOSYS;
  1919. }
  1920. stats->iw.ipInReceives = hw_stats->stat_value_64[I40IW_HW_STAT_INDEX_IP4RXPKTS] +
  1921. hw_stats->stat_value_64[I40IW_HW_STAT_INDEX_IP6RXPKTS];
  1922. stats->iw.ipInTruncatedPkts = hw_stats->stat_value_32[I40IW_HW_STAT_INDEX_IP4RXTRUNC] +
  1923. hw_stats->stat_value_32[I40IW_HW_STAT_INDEX_IP6RXTRUNC];
  1924. stats->iw.ipInDiscards = hw_stats->stat_value_32[I40IW_HW_STAT_INDEX_IP4RXDISCARD] +
  1925. hw_stats->stat_value_32[I40IW_HW_STAT_INDEX_IP6RXDISCARD];
  1926. stats->iw.ipOutNoRoutes = hw_stats->stat_value_32[I40IW_HW_STAT_INDEX_IP4TXNOROUTE] +
  1927. hw_stats->stat_value_32[I40IW_HW_STAT_INDEX_IP6TXNOROUTE];
  1928. stats->iw.ipReasmReqds = hw_stats->stat_value_64[I40IW_HW_STAT_INDEX_IP4RXFRAGS] +
  1929. hw_stats->stat_value_64[I40IW_HW_STAT_INDEX_IP6RXFRAGS];
  1930. stats->iw.ipFragCreates = hw_stats->stat_value_64[I40IW_HW_STAT_INDEX_IP4TXFRAGS] +
  1931. hw_stats->stat_value_64[I40IW_HW_STAT_INDEX_IP6TXFRAGS];
  1932. stats->iw.ipInMcastPkts = hw_stats->stat_value_64[I40IW_HW_STAT_INDEX_IP4RXMCPKTS] +
  1933. hw_stats->stat_value_64[I40IW_HW_STAT_INDEX_IP6RXMCPKTS];
  1934. stats->iw.ipOutMcastPkts = hw_stats->stat_value_64[I40IW_HW_STAT_INDEX_IP4TXMCPKTS] +
  1935. hw_stats->stat_value_64[I40IW_HW_STAT_INDEX_IP6TXMCPKTS];
  1936. stats->iw.tcpOutSegs = hw_stats->stat_value_64[I40IW_HW_STAT_INDEX_TCPTXSEG];
  1937. stats->iw.tcpInSegs = hw_stats->stat_value_64[I40IW_HW_STAT_INDEX_TCPRXSEGS];
  1938. stats->iw.tcpRetransSegs = hw_stats->stat_value_32[I40IW_HW_STAT_INDEX_TCPRTXSEG];
  1939. last_rd_time = curr_time;
  1940. return 0;
  1941. }
  1942. /**
  1943. * i40iw_query_gid - Query port GID
  1944. * @ibdev: device pointer from stack
  1945. * @port: port number
  1946. * @index: Entry index
  1947. * @gid: Global ID
  1948. */
  1949. static int i40iw_query_gid(struct ib_device *ibdev,
  1950. u8 port,
  1951. int index,
  1952. union ib_gid *gid)
  1953. {
  1954. struct i40iw_device *iwdev = to_iwdev(ibdev);
  1955. memset(gid->raw, 0, sizeof(gid->raw));
  1956. ether_addr_copy(gid->raw, iwdev->netdev->dev_addr);
  1957. return 0;
  1958. }
  1959. /**
  1960. * i40iw_modify_port Modify port properties
  1961. * @ibdev: device pointer from stack
  1962. * @port: port number
  1963. * @port_modify_mask: mask for port modifications
  1964. * @props: port properties
  1965. */
  1966. static int i40iw_modify_port(struct ib_device *ibdev,
  1967. u8 port,
  1968. int port_modify_mask,
  1969. struct ib_port_modify *props)
  1970. {
  1971. return 0;
  1972. }
  1973. /**
  1974. * i40iw_query_pkey - Query partition key
  1975. * @ibdev: device pointer from stack
  1976. * @port: port number
  1977. * @index: index of pkey
  1978. * @pkey: pointer to store the pkey
  1979. */
  1980. static int i40iw_query_pkey(struct ib_device *ibdev,
  1981. u8 port,
  1982. u16 index,
  1983. u16 *pkey)
  1984. {
  1985. *pkey = 0;
  1986. return 0;
  1987. }
  1988. /**
  1989. * i40iw_create_ah - create address handle
  1990. * @ibpd: ptr of pd
  1991. * @ah_attr: address handle attributes
  1992. */
  1993. static struct ib_ah *i40iw_create_ah(struct ib_pd *ibpd,
  1994. struct ib_ah_attr *attr)
  1995. {
  1996. return ERR_PTR(-ENOSYS);
  1997. }
  1998. /**
  1999. * i40iw_destroy_ah - Destroy address handle
  2000. * @ah: pointer to address handle
  2001. */
  2002. static int i40iw_destroy_ah(struct ib_ah *ah)
  2003. {
  2004. return -ENOSYS;
  2005. }
  2006. /**
  2007. * i40iw_init_rdma_device - initialization of iwarp device
  2008. * @iwdev: iwarp device
  2009. */
  2010. static struct i40iw_ib_device *i40iw_init_rdma_device(struct i40iw_device *iwdev)
  2011. {
  2012. struct i40iw_ib_device *iwibdev;
  2013. struct net_device *netdev = iwdev->netdev;
  2014. struct pci_dev *pcidev = (struct pci_dev *)iwdev->hw.dev_context;
  2015. iwibdev = (struct i40iw_ib_device *)ib_alloc_device(sizeof(*iwibdev));
  2016. if (!iwibdev) {
  2017. i40iw_pr_err("iwdev == NULL\n");
  2018. return NULL;
  2019. }
  2020. strlcpy(iwibdev->ibdev.name, "i40iw%d", IB_DEVICE_NAME_MAX);
  2021. iwibdev->ibdev.owner = THIS_MODULE;
  2022. iwdev->iwibdev = iwibdev;
  2023. iwibdev->iwdev = iwdev;
  2024. iwibdev->ibdev.node_type = RDMA_NODE_RNIC;
  2025. ether_addr_copy((u8 *)&iwibdev->ibdev.node_guid, netdev->dev_addr);
  2026. iwibdev->ibdev.uverbs_cmd_mask =
  2027. (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
  2028. (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
  2029. (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
  2030. (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
  2031. (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
  2032. (1ull << IB_USER_VERBS_CMD_REG_MR) |
  2033. (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
  2034. (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
  2035. (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
  2036. (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
  2037. (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ) |
  2038. (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
  2039. (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
  2040. (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
  2041. (1ull << IB_USER_VERBS_CMD_POLL_CQ) |
  2042. (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
  2043. (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
  2044. (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
  2045. (1ull << IB_USER_VERBS_CMD_POST_RECV) |
  2046. (1ull << IB_USER_VERBS_CMD_POST_SEND);
  2047. iwibdev->ibdev.phys_port_cnt = 1;
  2048. iwibdev->ibdev.num_comp_vectors = 1;
  2049. iwibdev->ibdev.dma_device = &pcidev->dev;
  2050. iwibdev->ibdev.dev.parent = &pcidev->dev;
  2051. iwibdev->ibdev.query_port = i40iw_query_port;
  2052. iwibdev->ibdev.modify_port = i40iw_modify_port;
  2053. iwibdev->ibdev.query_pkey = i40iw_query_pkey;
  2054. iwibdev->ibdev.query_gid = i40iw_query_gid;
  2055. iwibdev->ibdev.alloc_ucontext = i40iw_alloc_ucontext;
  2056. iwibdev->ibdev.dealloc_ucontext = i40iw_dealloc_ucontext;
  2057. iwibdev->ibdev.mmap = i40iw_mmap;
  2058. iwibdev->ibdev.alloc_pd = i40iw_alloc_pd;
  2059. iwibdev->ibdev.dealloc_pd = i40iw_dealloc_pd;
  2060. iwibdev->ibdev.create_qp = i40iw_create_qp;
  2061. iwibdev->ibdev.modify_qp = i40iw_modify_qp;
  2062. iwibdev->ibdev.query_qp = i40iw_query_qp;
  2063. iwibdev->ibdev.destroy_qp = i40iw_destroy_qp;
  2064. iwibdev->ibdev.create_cq = i40iw_create_cq;
  2065. iwibdev->ibdev.destroy_cq = i40iw_destroy_cq;
  2066. iwibdev->ibdev.get_dma_mr = i40iw_get_dma_mr;
  2067. iwibdev->ibdev.reg_user_mr = i40iw_reg_user_mr;
  2068. iwibdev->ibdev.dereg_mr = i40iw_dereg_mr;
  2069. iwibdev->ibdev.get_protocol_stats = i40iw_get_protocol_stats;
  2070. iwibdev->ibdev.query_device = i40iw_query_device;
  2071. iwibdev->ibdev.create_ah = i40iw_create_ah;
  2072. iwibdev->ibdev.destroy_ah = i40iw_destroy_ah;
  2073. iwibdev->ibdev.iwcm = kzalloc(sizeof(*iwibdev->ibdev.iwcm), GFP_KERNEL);
  2074. if (!iwibdev->ibdev.iwcm) {
  2075. ib_dealloc_device(&iwibdev->ibdev);
  2076. i40iw_pr_err("iwcm == NULL\n");
  2077. return NULL;
  2078. }
  2079. iwibdev->ibdev.iwcm->add_ref = i40iw_add_ref;
  2080. iwibdev->ibdev.iwcm->rem_ref = i40iw_rem_ref;
  2081. iwibdev->ibdev.iwcm->get_qp = i40iw_get_qp;
  2082. iwibdev->ibdev.iwcm->connect = i40iw_connect;
  2083. iwibdev->ibdev.iwcm->accept = i40iw_accept;
  2084. iwibdev->ibdev.iwcm->reject = i40iw_reject;
  2085. iwibdev->ibdev.iwcm->create_listen = i40iw_create_listen;
  2086. iwibdev->ibdev.iwcm->destroy_listen = i40iw_destroy_listen;
  2087. memcpy(iwibdev->ibdev.iwcm->ifname, netdev->name,
  2088. sizeof(iwibdev->ibdev.iwcm->ifname));
  2089. iwibdev->ibdev.get_port_immutable = i40iw_port_immutable;
  2090. iwibdev->ibdev.poll_cq = i40iw_poll_cq;
  2091. iwibdev->ibdev.req_notify_cq = i40iw_req_notify_cq;
  2092. iwibdev->ibdev.post_send = i40iw_post_send;
  2093. iwibdev->ibdev.post_recv = i40iw_post_recv;
  2094. return iwibdev;
  2095. }
  2096. /**
  2097. * i40iw_port_ibevent - indicate port event
  2098. * @iwdev: iwarp device
  2099. */
  2100. void i40iw_port_ibevent(struct i40iw_device *iwdev)
  2101. {
  2102. struct i40iw_ib_device *iwibdev = iwdev->iwibdev;
  2103. struct ib_event event;
  2104. event.device = &iwibdev->ibdev;
  2105. event.element.port_num = 1;
  2106. event.event = iwdev->iw_status ? IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
  2107. ib_dispatch_event(&event);
  2108. }
  2109. /**
  2110. * i40iw_unregister_rdma_device - unregister of iwarp from IB
  2111. * @iwibdev: rdma device ptr
  2112. */
  2113. static void i40iw_unregister_rdma_device(struct i40iw_ib_device *iwibdev)
  2114. {
  2115. int i;
  2116. for (i = 0; i < ARRAY_SIZE(i40iw_dev_attributes); ++i)
  2117. device_remove_file(&iwibdev->ibdev.dev,
  2118. i40iw_dev_attributes[i]);
  2119. ib_unregister_device(&iwibdev->ibdev);
  2120. }
  2121. /**
  2122. * i40iw_destroy_rdma_device - destroy rdma device and free resources
  2123. * @iwibdev: IB device ptr
  2124. */
  2125. void i40iw_destroy_rdma_device(struct i40iw_ib_device *iwibdev)
  2126. {
  2127. if (!iwibdev)
  2128. return;
  2129. i40iw_unregister_rdma_device(iwibdev);
  2130. kfree(iwibdev->ibdev.iwcm);
  2131. iwibdev->ibdev.iwcm = NULL;
  2132. ib_dealloc_device(&iwibdev->ibdev);
  2133. }
  2134. /**
  2135. * i40iw_register_rdma_device - register iwarp device to IB
  2136. * @iwdev: iwarp device
  2137. */
  2138. int i40iw_register_rdma_device(struct i40iw_device *iwdev)
  2139. {
  2140. int i, ret;
  2141. struct i40iw_ib_device *iwibdev;
  2142. iwdev->iwibdev = i40iw_init_rdma_device(iwdev);
  2143. if (!iwdev->iwibdev)
  2144. return -ENOSYS;
  2145. iwibdev = iwdev->iwibdev;
  2146. ret = ib_register_device(&iwibdev->ibdev, NULL);
  2147. if (ret)
  2148. goto error;
  2149. for (i = 0; i < ARRAY_SIZE(i40iw_dev_attributes); ++i) {
  2150. ret =
  2151. device_create_file(&iwibdev->ibdev.dev,
  2152. i40iw_dev_attributes[i]);
  2153. if (ret) {
  2154. while (i > 0) {
  2155. i--;
  2156. device_remove_file(&iwibdev->ibdev.dev, i40iw_dev_attributes[i]);
  2157. }
  2158. ib_unregister_device(&iwibdev->ibdev);
  2159. goto error;
  2160. }
  2161. }
  2162. return 0;
  2163. error:
  2164. kfree(iwdev->iwibdev->ibdev.iwcm);
  2165. iwdev->iwibdev->ibdev.iwcm = NULL;
  2166. ib_dealloc_device(&iwdev->iwibdev->ibdev);
  2167. return -ENOSYS;
  2168. }