mxs-lradc.c 48 KB

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  1. /*
  2. * Freescale MXS LRADC driver
  3. *
  4. * Copyright (c) 2012 DENX Software Engineering, GmbH.
  5. * Marek Vasut <marex@denx.de>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. */
  17. #include <linux/bitops.h>
  18. #include <linux/clk.h>
  19. #include <linux/completion.h>
  20. #include <linux/device.h>
  21. #include <linux/err.h>
  22. #include <linux/input.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/io.h>
  25. #include <linux/kernel.h>
  26. #include <linux/module.h>
  27. #include <linux/mutex.h>
  28. #include <linux/of.h>
  29. #include <linux/of_device.h>
  30. #include <linux/platform_device.h>
  31. #include <linux/slab.h>
  32. #include <linux/stmp_device.h>
  33. #include <linux/sysfs.h>
  34. #include <linux/iio/buffer.h>
  35. #include <linux/iio/iio.h>
  36. #include <linux/iio/trigger.h>
  37. #include <linux/iio/trigger_consumer.h>
  38. #include <linux/iio/triggered_buffer.h>
  39. #include <linux/iio/sysfs.h>
  40. #define DRIVER_NAME "mxs-lradc"
  41. #define LRADC_MAX_DELAY_CHANS 4
  42. #define LRADC_MAX_MAPPED_CHANS 8
  43. #define LRADC_MAX_TOTAL_CHANS 16
  44. #define LRADC_DELAY_TIMER_HZ 2000
  45. /*
  46. * Make this runtime configurable if necessary. Currently, if the buffered mode
  47. * is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before
  48. * triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000)
  49. * seconds. The result is that the samples arrive every 500mS.
  50. */
  51. #define LRADC_DELAY_TIMER_PER 200
  52. #define LRADC_DELAY_TIMER_LOOP 5
  53. /*
  54. * Once the pen touches the touchscreen, the touchscreen switches from
  55. * IRQ-driven mode to polling mode to prevent interrupt storm. The polling
  56. * is realized by worker thread, which is called every 20 or so milliseconds.
  57. * This gives the touchscreen enough fluency and does not strain the system
  58. * too much.
  59. */
  60. #define LRADC_TS_SAMPLE_DELAY_MS 5
  61. /*
  62. * The LRADC reads the following amount of samples from each touchscreen
  63. * channel and the driver then computes average of these.
  64. */
  65. #define LRADC_TS_SAMPLE_AMOUNT 4
  66. enum mxs_lradc_id {
  67. IMX23_LRADC,
  68. IMX28_LRADC,
  69. };
  70. static const char * const mx23_lradc_irq_names[] = {
  71. "mxs-lradc-touchscreen",
  72. "mxs-lradc-channel0",
  73. "mxs-lradc-channel1",
  74. "mxs-lradc-channel2",
  75. "mxs-lradc-channel3",
  76. "mxs-lradc-channel4",
  77. "mxs-lradc-channel5",
  78. "mxs-lradc-channel6",
  79. "mxs-lradc-channel7",
  80. };
  81. static const char * const mx28_lradc_irq_names[] = {
  82. "mxs-lradc-touchscreen",
  83. "mxs-lradc-thresh0",
  84. "mxs-lradc-thresh1",
  85. "mxs-lradc-channel0",
  86. "mxs-lradc-channel1",
  87. "mxs-lradc-channel2",
  88. "mxs-lradc-channel3",
  89. "mxs-lradc-channel4",
  90. "mxs-lradc-channel5",
  91. "mxs-lradc-channel6",
  92. "mxs-lradc-channel7",
  93. "mxs-lradc-button0",
  94. "mxs-lradc-button1",
  95. };
  96. struct mxs_lradc_of_config {
  97. const int irq_count;
  98. const char * const *irq_name;
  99. const u32 *vref_mv;
  100. };
  101. #define VREF_MV_BASE 1850
  102. static const u32 mx23_vref_mv[LRADC_MAX_TOTAL_CHANS] = {
  103. VREF_MV_BASE, /* CH0 */
  104. VREF_MV_BASE, /* CH1 */
  105. VREF_MV_BASE, /* CH2 */
  106. VREF_MV_BASE, /* CH3 */
  107. VREF_MV_BASE, /* CH4 */
  108. VREF_MV_BASE, /* CH5 */
  109. VREF_MV_BASE * 2, /* CH6 VDDIO */
  110. VREF_MV_BASE * 4, /* CH7 VBATT */
  111. VREF_MV_BASE, /* CH8 Temp sense 0 */
  112. VREF_MV_BASE, /* CH9 Temp sense 1 */
  113. VREF_MV_BASE, /* CH10 */
  114. VREF_MV_BASE, /* CH11 */
  115. VREF_MV_BASE, /* CH12 USB_DP */
  116. VREF_MV_BASE, /* CH13 USB_DN */
  117. VREF_MV_BASE, /* CH14 VBG */
  118. VREF_MV_BASE * 4, /* CH15 VDD5V */
  119. };
  120. static const u32 mx28_vref_mv[LRADC_MAX_TOTAL_CHANS] = {
  121. VREF_MV_BASE, /* CH0 */
  122. VREF_MV_BASE, /* CH1 */
  123. VREF_MV_BASE, /* CH2 */
  124. VREF_MV_BASE, /* CH3 */
  125. VREF_MV_BASE, /* CH4 */
  126. VREF_MV_BASE, /* CH5 */
  127. VREF_MV_BASE, /* CH6 */
  128. VREF_MV_BASE * 4, /* CH7 VBATT */
  129. VREF_MV_BASE, /* CH8 Temp sense 0 */
  130. VREF_MV_BASE, /* CH9 Temp sense 1 */
  131. VREF_MV_BASE * 2, /* CH10 VDDIO */
  132. VREF_MV_BASE, /* CH11 VTH */
  133. VREF_MV_BASE * 2, /* CH12 VDDA */
  134. VREF_MV_BASE, /* CH13 VDDD */
  135. VREF_MV_BASE, /* CH14 VBG */
  136. VREF_MV_BASE * 4, /* CH15 VDD5V */
  137. };
  138. static const struct mxs_lradc_of_config mxs_lradc_of_config[] = {
  139. [IMX23_LRADC] = {
  140. .irq_count = ARRAY_SIZE(mx23_lradc_irq_names),
  141. .irq_name = mx23_lradc_irq_names,
  142. .vref_mv = mx23_vref_mv,
  143. },
  144. [IMX28_LRADC] = {
  145. .irq_count = ARRAY_SIZE(mx28_lradc_irq_names),
  146. .irq_name = mx28_lradc_irq_names,
  147. .vref_mv = mx28_vref_mv,
  148. },
  149. };
  150. enum mxs_lradc_ts {
  151. MXS_LRADC_TOUCHSCREEN_NONE = 0,
  152. MXS_LRADC_TOUCHSCREEN_4WIRE,
  153. MXS_LRADC_TOUCHSCREEN_5WIRE,
  154. };
  155. /*
  156. * Touchscreen handling
  157. */
  158. enum lradc_ts_plate {
  159. LRADC_TOUCH = 0,
  160. LRADC_SAMPLE_X,
  161. LRADC_SAMPLE_Y,
  162. LRADC_SAMPLE_PRESSURE,
  163. LRADC_SAMPLE_VALID,
  164. };
  165. enum mxs_lradc_divbytwo {
  166. MXS_LRADC_DIV_DISABLED = 0,
  167. MXS_LRADC_DIV_ENABLED,
  168. };
  169. struct mxs_lradc_scale {
  170. unsigned int integer;
  171. unsigned int nano;
  172. };
  173. struct mxs_lradc {
  174. struct device *dev;
  175. void __iomem *base;
  176. int irq[13];
  177. struct clk *clk;
  178. u32 *buffer;
  179. struct iio_trigger *trig;
  180. struct mutex lock;
  181. struct completion completion;
  182. const u32 *vref_mv;
  183. struct mxs_lradc_scale scale_avail[LRADC_MAX_TOTAL_CHANS][2];
  184. unsigned long is_divided;
  185. /*
  186. * When the touchscreen is enabled, we give it two private virtual
  187. * channels: #6 and #7. This means that only 6 virtual channels (instead
  188. * of 8) will be available for buffered capture.
  189. */
  190. #define TOUCHSCREEN_VCHANNEL1 7
  191. #define TOUCHSCREEN_VCHANNEL2 6
  192. #define BUFFER_VCHANS_LIMITED 0x3f
  193. #define BUFFER_VCHANS_ALL 0xff
  194. u8 buffer_vchans;
  195. /*
  196. * Furthermore, certain LRADC channels are shared between touchscreen
  197. * and/or touch-buttons and generic LRADC block. Therefore when using
  198. * either of these, these channels are not available for the regular
  199. * sampling. The shared channels are as follows:
  200. *
  201. * CH0 -- Touch button #0
  202. * CH1 -- Touch button #1
  203. * CH2 -- Touch screen XPUL
  204. * CH3 -- Touch screen YPLL
  205. * CH4 -- Touch screen XNUL
  206. * CH5 -- Touch screen YNLR
  207. * CH6 -- Touch screen WIPER (5-wire only)
  208. *
  209. * The bit fields below represents which parts of the LRADC block are
  210. * switched into special mode of operation. These channels can not
  211. * be sampled as regular LRADC channels. The driver will refuse any
  212. * attempt to sample these channels.
  213. */
  214. #define CHAN_MASK_TOUCHBUTTON (BIT(1) | BIT(0))
  215. #define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 2)
  216. #define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 2)
  217. enum mxs_lradc_ts use_touchscreen;
  218. bool use_touchbutton;
  219. struct input_dev *ts_input;
  220. enum mxs_lradc_id soc;
  221. enum lradc_ts_plate cur_plate; /* state machine */
  222. bool ts_valid;
  223. unsigned ts_x_pos;
  224. unsigned ts_y_pos;
  225. unsigned ts_pressure;
  226. /* handle touchscreen's physical behaviour */
  227. /* samples per coordinate */
  228. unsigned over_sample_cnt;
  229. /* time clocks between samples */
  230. unsigned over_sample_delay;
  231. /* time in clocks to wait after the plates where switched */
  232. unsigned settling_delay;
  233. };
  234. #define LRADC_CTRL0 0x00
  235. # define LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE BIT(23)
  236. # define LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE BIT(22)
  237. # define LRADC_CTRL0_MX28_YNNSW /* YM */ BIT(21)
  238. # define LRADC_CTRL0_MX28_YPNSW /* YP */ BIT(20)
  239. # define LRADC_CTRL0_MX28_YPPSW /* YP */ BIT(19)
  240. # define LRADC_CTRL0_MX28_XNNSW /* XM */ BIT(18)
  241. # define LRADC_CTRL0_MX28_XNPSW /* XM */ BIT(17)
  242. # define LRADC_CTRL0_MX28_XPPSW /* XP */ BIT(16)
  243. # define LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE BIT(20)
  244. # define LRADC_CTRL0_MX23_YM BIT(19)
  245. # define LRADC_CTRL0_MX23_XM BIT(18)
  246. # define LRADC_CTRL0_MX23_YP BIT(17)
  247. # define LRADC_CTRL0_MX23_XP BIT(16)
  248. # define LRADC_CTRL0_MX28_PLATE_MASK \
  249. (LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE | \
  250. LRADC_CTRL0_MX28_YNNSW | LRADC_CTRL0_MX28_YPNSW | \
  251. LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW | \
  252. LRADC_CTRL0_MX28_XNPSW | LRADC_CTRL0_MX28_XPPSW)
  253. # define LRADC_CTRL0_MX23_PLATE_MASK \
  254. (LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE | \
  255. LRADC_CTRL0_MX23_YM | LRADC_CTRL0_MX23_XM | \
  256. LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_XP)
  257. #define LRADC_CTRL1 0x10
  258. #define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN BIT(24)
  259. #define LRADC_CTRL1_LRADC_IRQ_EN(n) (1 << ((n) + 16))
  260. #define LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK (0x1fff << 16)
  261. #define LRADC_CTRL1_MX23_LRADC_IRQ_EN_MASK (0x01ff << 16)
  262. #define LRADC_CTRL1_LRADC_IRQ_EN_OFFSET 16
  263. #define LRADC_CTRL1_TOUCH_DETECT_IRQ BIT(8)
  264. #define LRADC_CTRL1_LRADC_IRQ(n) (1 << (n))
  265. #define LRADC_CTRL1_MX28_LRADC_IRQ_MASK 0x1fff
  266. #define LRADC_CTRL1_MX23_LRADC_IRQ_MASK 0x01ff
  267. #define LRADC_CTRL1_LRADC_IRQ_OFFSET 0
  268. #define LRADC_CTRL2 0x20
  269. #define LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET 24
  270. #define LRADC_CTRL2_TEMPSENSE_PWD BIT(15)
  271. #define LRADC_STATUS 0x40
  272. #define LRADC_STATUS_TOUCH_DETECT_RAW BIT(0)
  273. #define LRADC_CH(n) (0x50 + (0x10 * (n)))
  274. #define LRADC_CH_ACCUMULATE BIT(29)
  275. #define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24)
  276. #define LRADC_CH_NUM_SAMPLES_OFFSET 24
  277. #define LRADC_CH_NUM_SAMPLES(x) \
  278. ((x) << LRADC_CH_NUM_SAMPLES_OFFSET)
  279. #define LRADC_CH_VALUE_MASK 0x3ffff
  280. #define LRADC_CH_VALUE_OFFSET 0
  281. #define LRADC_DELAY(n) (0xd0 + (0x10 * (n)))
  282. #define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xffUL << 24)
  283. #define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24
  284. #define LRADC_DELAY_TRIGGER(x) \
  285. (((x) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) & \
  286. LRADC_DELAY_TRIGGER_LRADCS_MASK)
  287. #define LRADC_DELAY_KICK BIT(20)
  288. #define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16)
  289. #define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16
  290. #define LRADC_DELAY_TRIGGER_DELAYS(x) \
  291. (((x) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) & \
  292. LRADC_DELAY_TRIGGER_DELAYS_MASK)
  293. #define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11)
  294. #define LRADC_DELAY_LOOP_COUNT_OFFSET 11
  295. #define LRADC_DELAY_LOOP(x) \
  296. (((x) << LRADC_DELAY_LOOP_COUNT_OFFSET) & \
  297. LRADC_DELAY_LOOP_COUNT_MASK)
  298. #define LRADC_DELAY_DELAY_MASK 0x7ff
  299. #define LRADC_DELAY_DELAY_OFFSET 0
  300. #define LRADC_DELAY_DELAY(x) \
  301. (((x) << LRADC_DELAY_DELAY_OFFSET) & \
  302. LRADC_DELAY_DELAY_MASK)
  303. #define LRADC_CTRL4 0x140
  304. #define LRADC_CTRL4_LRADCSELECT_MASK(n) (0xf << ((n) * 4))
  305. #define LRADC_CTRL4_LRADCSELECT_OFFSET(n) ((n) * 4)
  306. #define LRADC_CTRL4_LRADCSELECT(n, x) \
  307. (((x) << LRADC_CTRL4_LRADCSELECT_OFFSET(n)) & \
  308. LRADC_CTRL4_LRADCSELECT_MASK(n))
  309. #define LRADC_RESOLUTION 12
  310. #define LRADC_SINGLE_SAMPLE_MASK ((1 << LRADC_RESOLUTION) - 1)
  311. static void mxs_lradc_reg_set(struct mxs_lradc *lradc, u32 val, u32 reg)
  312. {
  313. writel(val, lradc->base + reg + STMP_OFFSET_REG_SET);
  314. }
  315. static void mxs_lradc_reg_clear(struct mxs_lradc *lradc, u32 val, u32 reg)
  316. {
  317. writel(val, lradc->base + reg + STMP_OFFSET_REG_CLR);
  318. }
  319. static void mxs_lradc_reg_wrt(struct mxs_lradc *lradc, u32 val, u32 reg)
  320. {
  321. writel(val, lradc->base + reg);
  322. }
  323. static u32 mxs_lradc_plate_mask(struct mxs_lradc *lradc)
  324. {
  325. if (lradc->soc == IMX23_LRADC)
  326. return LRADC_CTRL0_MX23_PLATE_MASK;
  327. return LRADC_CTRL0_MX28_PLATE_MASK;
  328. }
  329. static u32 mxs_lradc_irq_en_mask(struct mxs_lradc *lradc)
  330. {
  331. if (lradc->soc == IMX23_LRADC)
  332. return LRADC_CTRL1_MX23_LRADC_IRQ_EN_MASK;
  333. return LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK;
  334. }
  335. static u32 mxs_lradc_irq_mask(struct mxs_lradc *lradc)
  336. {
  337. if (lradc->soc == IMX23_LRADC)
  338. return LRADC_CTRL1_MX23_LRADC_IRQ_MASK;
  339. return LRADC_CTRL1_MX28_LRADC_IRQ_MASK;
  340. }
  341. static u32 mxs_lradc_touch_detect_bit(struct mxs_lradc *lradc)
  342. {
  343. if (lradc->soc == IMX23_LRADC)
  344. return LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE;
  345. return LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE;
  346. }
  347. static u32 mxs_lradc_drive_x_plate(struct mxs_lradc *lradc)
  348. {
  349. if (lradc->soc == IMX23_LRADC)
  350. return LRADC_CTRL0_MX23_XP | LRADC_CTRL0_MX23_XM;
  351. return LRADC_CTRL0_MX28_XPPSW | LRADC_CTRL0_MX28_XNNSW;
  352. }
  353. static u32 mxs_lradc_drive_y_plate(struct mxs_lradc *lradc)
  354. {
  355. if (lradc->soc == IMX23_LRADC)
  356. return LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_YM;
  357. return LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_YNNSW;
  358. }
  359. static u32 mxs_lradc_drive_pressure(struct mxs_lradc *lradc)
  360. {
  361. if (lradc->soc == IMX23_LRADC)
  362. return LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_XM;
  363. return LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW;
  364. }
  365. static bool mxs_lradc_check_touch_event(struct mxs_lradc *lradc)
  366. {
  367. return !!(readl(lradc->base + LRADC_STATUS) &
  368. LRADC_STATUS_TOUCH_DETECT_RAW);
  369. }
  370. static void mxs_lradc_map_channel(struct mxs_lradc *lradc, unsigned vch,
  371. unsigned ch)
  372. {
  373. mxs_lradc_reg_clear(lradc, LRADC_CTRL4_LRADCSELECT_MASK(vch),
  374. LRADC_CTRL4);
  375. mxs_lradc_reg_set(lradc, LRADC_CTRL4_LRADCSELECT(vch, ch), LRADC_CTRL4);
  376. }
  377. static void mxs_lradc_setup_ts_channel(struct mxs_lradc *lradc, unsigned ch)
  378. {
  379. /*
  380. * prepare for oversampling conversion
  381. *
  382. * from the datasheet:
  383. * "The ACCUMULATE bit in the appropriate channel register
  384. * HW_LRADC_CHn must be set to 1 if NUM_SAMPLES is greater then 0;
  385. * otherwise, the IRQs will not fire."
  386. */
  387. mxs_lradc_reg_wrt(lradc, LRADC_CH_ACCUMULATE |
  388. LRADC_CH_NUM_SAMPLES(lradc->over_sample_cnt - 1),
  389. LRADC_CH(ch));
  390. /*
  391. * from the datasheet:
  392. * "Software must clear this register in preparation for a
  393. * multi-cycle accumulation.
  394. */
  395. mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch));
  396. /*
  397. * prepare the delay/loop unit according to the oversampling count
  398. *
  399. * from the datasheet:
  400. * "The DELAY fields in HW_LRADC_DELAY0, HW_LRADC_DELAY1,
  401. * HW_LRADC_DELAY2, and HW_LRADC_DELAY3 must be non-zero; otherwise,
  402. * the LRADC will not trigger the delay group."
  403. */
  404. mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(1 << ch) |
  405. LRADC_DELAY_TRIGGER_DELAYS(0) |
  406. LRADC_DELAY_LOOP(lradc->over_sample_cnt - 1) |
  407. LRADC_DELAY_DELAY(lradc->over_sample_delay - 1),
  408. LRADC_DELAY(3));
  409. mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(ch), LRADC_CTRL1);
  410. /*
  411. * after changing the touchscreen plates setting
  412. * the signals need some initial time to settle. Start the
  413. * SoC's delay unit and start the conversion later
  414. * and automatically.
  415. */
  416. mxs_lradc_reg_wrt(
  417. lradc,
  418. LRADC_DELAY_TRIGGER(0) | /* don't trigger ADC */
  419. LRADC_DELAY_TRIGGER_DELAYS(BIT(3)) | /* trigger DELAY unit#3 */
  420. LRADC_DELAY_KICK |
  421. LRADC_DELAY_DELAY(lradc->settling_delay),
  422. LRADC_DELAY(2));
  423. }
  424. /*
  425. * Pressure detection is special:
  426. * We want to do both required measurements for the pressure detection in
  427. * one turn. Use the hardware features to chain both conversions and let the
  428. * hardware report one interrupt if both conversions are done
  429. */
  430. static void mxs_lradc_setup_ts_pressure(struct mxs_lradc *lradc, unsigned ch1,
  431. unsigned ch2)
  432. {
  433. u32 reg;
  434. /*
  435. * prepare for oversampling conversion
  436. *
  437. * from the datasheet:
  438. * "The ACCUMULATE bit in the appropriate channel register
  439. * HW_LRADC_CHn must be set to 1 if NUM_SAMPLES is greater then 0;
  440. * otherwise, the IRQs will not fire."
  441. */
  442. reg = LRADC_CH_ACCUMULATE |
  443. LRADC_CH_NUM_SAMPLES(lradc->over_sample_cnt - 1);
  444. mxs_lradc_reg_wrt(lradc, reg, LRADC_CH(ch1));
  445. mxs_lradc_reg_wrt(lradc, reg, LRADC_CH(ch2));
  446. /*
  447. * from the datasheet:
  448. * "Software must clear this register in preparation for a
  449. * multi-cycle accumulation.
  450. */
  451. mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch1));
  452. mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch2));
  453. /* prepare the delay/loop unit according to the oversampling count */
  454. mxs_lradc_reg_wrt(
  455. lradc,
  456. LRADC_DELAY_TRIGGER(1 << ch1) |
  457. LRADC_DELAY_TRIGGER(1 << ch2) | /* start both channels */
  458. LRADC_DELAY_TRIGGER_DELAYS(0) |
  459. LRADC_DELAY_LOOP(lradc->over_sample_cnt - 1) |
  460. LRADC_DELAY_DELAY(lradc->over_sample_delay - 1),
  461. LRADC_DELAY(3));
  462. mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(ch2), LRADC_CTRL1);
  463. /*
  464. * after changing the touchscreen plates setting
  465. * the signals need some initial time to settle. Start the
  466. * SoC's delay unit and start the conversion later
  467. * and automatically.
  468. */
  469. mxs_lradc_reg_wrt(
  470. lradc,
  471. LRADC_DELAY_TRIGGER(0) | /* don't trigger ADC */
  472. LRADC_DELAY_TRIGGER_DELAYS(BIT(3)) | /* trigger DELAY unit#3 */
  473. LRADC_DELAY_KICK |
  474. LRADC_DELAY_DELAY(lradc->settling_delay), LRADC_DELAY(2));
  475. }
  476. static unsigned mxs_lradc_read_raw_channel(struct mxs_lradc *lradc,
  477. unsigned channel)
  478. {
  479. u32 reg;
  480. unsigned num_samples, val;
  481. reg = readl(lradc->base + LRADC_CH(channel));
  482. if (reg & LRADC_CH_ACCUMULATE)
  483. num_samples = lradc->over_sample_cnt;
  484. else
  485. num_samples = 1;
  486. val = (reg & LRADC_CH_VALUE_MASK) >> LRADC_CH_VALUE_OFFSET;
  487. return val / num_samples;
  488. }
  489. static unsigned mxs_lradc_read_ts_pressure(struct mxs_lradc *lradc,
  490. unsigned ch1, unsigned ch2)
  491. {
  492. u32 reg, mask;
  493. unsigned pressure, m1, m2;
  494. mask = LRADC_CTRL1_LRADC_IRQ(ch1) | LRADC_CTRL1_LRADC_IRQ(ch2);
  495. reg = readl(lradc->base + LRADC_CTRL1) & mask;
  496. while (reg != mask) {
  497. reg = readl(lradc->base + LRADC_CTRL1) & mask;
  498. dev_dbg(lradc->dev, "One channel is still busy: %X\n", reg);
  499. }
  500. m1 = mxs_lradc_read_raw_channel(lradc, ch1);
  501. m2 = mxs_lradc_read_raw_channel(lradc, ch2);
  502. if (m2 == 0) {
  503. dev_warn(lradc->dev, "Cannot calculate pressure\n");
  504. return 1 << (LRADC_RESOLUTION - 1);
  505. }
  506. /* simply scale the value from 0 ... max ADC resolution */
  507. pressure = m1;
  508. pressure *= (1 << LRADC_RESOLUTION);
  509. pressure /= m2;
  510. dev_dbg(lradc->dev, "Pressure = %u\n", pressure);
  511. return pressure;
  512. }
  513. #define TS_CH_XP 2
  514. #define TS_CH_YP 3
  515. #define TS_CH_XM 4
  516. #define TS_CH_YM 5
  517. /*
  518. * YP(open)--+-------------+
  519. * | |--+
  520. * | | |
  521. * YM(-)--+-------------+ |
  522. * +--------------+
  523. * | |
  524. * XP(weak+) XM(open)
  525. *
  526. * "weak+" means 200k Ohm VDDIO
  527. * (-) means GND
  528. */
  529. static void mxs_lradc_setup_touch_detection(struct mxs_lradc *lradc)
  530. {
  531. /*
  532. * In order to detect a touch event the 'touch detect enable' bit
  533. * enables:
  534. * - a weak pullup to the X+ connector
  535. * - a strong ground at the Y- connector
  536. */
  537. mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
  538. mxs_lradc_reg_set(lradc, mxs_lradc_touch_detect_bit(lradc),
  539. LRADC_CTRL0);
  540. }
  541. /*
  542. * YP(meas)--+-------------+
  543. * | |--+
  544. * | | |
  545. * YM(open)--+-------------+ |
  546. * +--------------+
  547. * | |
  548. * XP(+) XM(-)
  549. *
  550. * (+) means here 1.85 V
  551. * (-) means here GND
  552. */
  553. static void mxs_lradc_prepare_x_pos(struct mxs_lradc *lradc)
  554. {
  555. mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
  556. mxs_lradc_reg_set(lradc, mxs_lradc_drive_x_plate(lradc), LRADC_CTRL0);
  557. lradc->cur_plate = LRADC_SAMPLE_X;
  558. mxs_lradc_map_channel(lradc, TOUCHSCREEN_VCHANNEL1, TS_CH_YP);
  559. mxs_lradc_setup_ts_channel(lradc, TOUCHSCREEN_VCHANNEL1);
  560. }
  561. /*
  562. * YP(+)--+-------------+
  563. * | |--+
  564. * | | |
  565. * YM(-)--+-------------+ |
  566. * +--------------+
  567. * | |
  568. * XP(open) XM(meas)
  569. *
  570. * (+) means here 1.85 V
  571. * (-) means here GND
  572. */
  573. static void mxs_lradc_prepare_y_pos(struct mxs_lradc *lradc)
  574. {
  575. mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
  576. mxs_lradc_reg_set(lradc, mxs_lradc_drive_y_plate(lradc), LRADC_CTRL0);
  577. lradc->cur_plate = LRADC_SAMPLE_Y;
  578. mxs_lradc_map_channel(lradc, TOUCHSCREEN_VCHANNEL1, TS_CH_XM);
  579. mxs_lradc_setup_ts_channel(lradc, TOUCHSCREEN_VCHANNEL1);
  580. }
  581. /*
  582. * YP(+)--+-------------+
  583. * | |--+
  584. * | | |
  585. * YM(meas)--+-------------+ |
  586. * +--------------+
  587. * | |
  588. * XP(meas) XM(-)
  589. *
  590. * (+) means here 1.85 V
  591. * (-) means here GND
  592. */
  593. static void mxs_lradc_prepare_pressure(struct mxs_lradc *lradc)
  594. {
  595. mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
  596. mxs_lradc_reg_set(lradc, mxs_lradc_drive_pressure(lradc), LRADC_CTRL0);
  597. lradc->cur_plate = LRADC_SAMPLE_PRESSURE;
  598. mxs_lradc_map_channel(lradc, TOUCHSCREEN_VCHANNEL1, TS_CH_YM);
  599. mxs_lradc_map_channel(lradc, TOUCHSCREEN_VCHANNEL2, TS_CH_XP);
  600. mxs_lradc_setup_ts_pressure(lradc, TOUCHSCREEN_VCHANNEL2,
  601. TOUCHSCREEN_VCHANNEL1);
  602. }
  603. static void mxs_lradc_enable_touch_detection(struct mxs_lradc *lradc)
  604. {
  605. mxs_lradc_setup_touch_detection(lradc);
  606. lradc->cur_plate = LRADC_TOUCH;
  607. mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ |
  608. LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
  609. mxs_lradc_reg_set(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
  610. }
  611. static void mxs_lradc_start_touch_event(struct mxs_lradc *lradc)
  612. {
  613. mxs_lradc_reg_clear(lradc,
  614. LRADC_CTRL1_TOUCH_DETECT_IRQ_EN,
  615. LRADC_CTRL1);
  616. mxs_lradc_reg_set(lradc,
  617. LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL1),
  618. LRADC_CTRL1);
  619. /*
  620. * start with the Y-pos, because it uses nearly the same plate
  621. * settings like the touch detection
  622. */
  623. mxs_lradc_prepare_y_pos(lradc);
  624. }
  625. static void mxs_lradc_report_ts_event(struct mxs_lradc *lradc)
  626. {
  627. input_report_abs(lradc->ts_input, ABS_X, lradc->ts_x_pos);
  628. input_report_abs(lradc->ts_input, ABS_Y, lradc->ts_y_pos);
  629. input_report_abs(lradc->ts_input, ABS_PRESSURE, lradc->ts_pressure);
  630. input_report_key(lradc->ts_input, BTN_TOUCH, 1);
  631. input_sync(lradc->ts_input);
  632. }
  633. static void mxs_lradc_complete_touch_event(struct mxs_lradc *lradc)
  634. {
  635. mxs_lradc_setup_touch_detection(lradc);
  636. lradc->cur_plate = LRADC_SAMPLE_VALID;
  637. /*
  638. * start a dummy conversion to burn time to settle the signals
  639. * note: we are not interested in the conversion's value
  640. */
  641. mxs_lradc_reg_wrt(lradc, 0, LRADC_CH(TOUCHSCREEN_VCHANNEL1));
  642. mxs_lradc_reg_clear(lradc,
  643. LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1) |
  644. LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL2),
  645. LRADC_CTRL1);
  646. mxs_lradc_reg_wrt(
  647. lradc,
  648. LRADC_DELAY_TRIGGER(1 << TOUCHSCREEN_VCHANNEL1) |
  649. LRADC_DELAY_KICK | LRADC_DELAY_DELAY(10), /* waste 5 ms */
  650. LRADC_DELAY(2));
  651. }
  652. /*
  653. * in order to avoid false measurements, report only samples where
  654. * the surface is still touched after the position measurement
  655. */
  656. static void mxs_lradc_finish_touch_event(struct mxs_lradc *lradc, bool valid)
  657. {
  658. /* if it is still touched, report the sample */
  659. if (valid && mxs_lradc_check_touch_event(lradc)) {
  660. lradc->ts_valid = true;
  661. mxs_lradc_report_ts_event(lradc);
  662. }
  663. /* if it is even still touched, continue with the next measurement */
  664. if (mxs_lradc_check_touch_event(lradc)) {
  665. mxs_lradc_prepare_y_pos(lradc);
  666. return;
  667. }
  668. if (lradc->ts_valid) {
  669. /* signal the release */
  670. lradc->ts_valid = false;
  671. input_report_key(lradc->ts_input, BTN_TOUCH, 0);
  672. input_sync(lradc->ts_input);
  673. }
  674. /* if it is released, wait for the next touch via IRQ */
  675. lradc->cur_plate = LRADC_TOUCH;
  676. mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(2));
  677. mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(3));
  678. mxs_lradc_reg_clear(lradc,
  679. LRADC_CTRL1_TOUCH_DETECT_IRQ |
  680. LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL1) |
  681. LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1),
  682. LRADC_CTRL1);
  683. mxs_lradc_reg_set(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
  684. }
  685. /* touchscreen's state machine */
  686. static void mxs_lradc_handle_touch(struct mxs_lradc *lradc)
  687. {
  688. switch (lradc->cur_plate) {
  689. case LRADC_TOUCH:
  690. if (mxs_lradc_check_touch_event(lradc))
  691. mxs_lradc_start_touch_event(lradc);
  692. mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ,
  693. LRADC_CTRL1);
  694. return;
  695. case LRADC_SAMPLE_Y:
  696. lradc->ts_y_pos =
  697. mxs_lradc_read_raw_channel(lradc,
  698. TOUCHSCREEN_VCHANNEL1);
  699. mxs_lradc_prepare_x_pos(lradc);
  700. return;
  701. case LRADC_SAMPLE_X:
  702. lradc->ts_x_pos =
  703. mxs_lradc_read_raw_channel(lradc,
  704. TOUCHSCREEN_VCHANNEL1);
  705. mxs_lradc_prepare_pressure(lradc);
  706. return;
  707. case LRADC_SAMPLE_PRESSURE:
  708. lradc->ts_pressure =
  709. mxs_lradc_read_ts_pressure(lradc,
  710. TOUCHSCREEN_VCHANNEL2,
  711. TOUCHSCREEN_VCHANNEL1);
  712. mxs_lradc_complete_touch_event(lradc);
  713. return;
  714. case LRADC_SAMPLE_VALID:
  715. mxs_lradc_finish_touch_event(lradc, 1);
  716. break;
  717. }
  718. }
  719. /*
  720. * Raw I/O operations
  721. */
  722. static int mxs_lradc_read_single(struct iio_dev *iio_dev, int chan, int *val)
  723. {
  724. struct mxs_lradc *lradc = iio_priv(iio_dev);
  725. int ret;
  726. /*
  727. * See if there is no buffered operation in progress. If there is, simply
  728. * bail out. This can be improved to support both buffered and raw IO at
  729. * the same time, yet the code becomes horribly complicated. Therefore I
  730. * applied KISS principle here.
  731. */
  732. ret = mutex_trylock(&lradc->lock);
  733. if (!ret)
  734. return -EBUSY;
  735. reinit_completion(&lradc->completion);
  736. /*
  737. * No buffered operation in progress, map the channel and trigger it.
  738. * Virtual channel 0 is always used here as the others are always not
  739. * used if doing raw sampling.
  740. */
  741. if (lradc->soc == IMX28_LRADC)
  742. mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0),
  743. LRADC_CTRL1);
  744. mxs_lradc_reg_clear(lradc, 0x1, LRADC_CTRL0);
  745. /* Enable / disable the divider per requirement */
  746. if (test_bit(chan, &lradc->is_divided))
  747. mxs_lradc_reg_set(lradc,
  748. 1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
  749. LRADC_CTRL2);
  750. else
  751. mxs_lradc_reg_clear(lradc,
  752. 1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
  753. LRADC_CTRL2);
  754. /* Clean the slot's previous content, then set new one. */
  755. mxs_lradc_reg_clear(lradc, LRADC_CTRL4_LRADCSELECT_MASK(0),
  756. LRADC_CTRL4);
  757. mxs_lradc_reg_set(lradc, chan, LRADC_CTRL4);
  758. mxs_lradc_reg_wrt(lradc, 0, LRADC_CH(0));
  759. /* Enable the IRQ and start sampling the channel. */
  760. mxs_lradc_reg_set(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0), LRADC_CTRL1);
  761. mxs_lradc_reg_set(lradc, BIT(0), LRADC_CTRL0);
  762. /* Wait for completion on the channel, 1 second max. */
  763. ret = wait_for_completion_killable_timeout(&lradc->completion, HZ);
  764. if (!ret)
  765. ret = -ETIMEDOUT;
  766. if (ret < 0)
  767. goto err;
  768. /* Read the data. */
  769. *val = readl(lradc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK;
  770. ret = IIO_VAL_INT;
  771. err:
  772. mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0), LRADC_CTRL1);
  773. mutex_unlock(&lradc->lock);
  774. return ret;
  775. }
  776. static int mxs_lradc_read_temp(struct iio_dev *iio_dev, int *val)
  777. {
  778. int ret, min, max;
  779. ret = mxs_lradc_read_single(iio_dev, 8, &min);
  780. if (ret != IIO_VAL_INT)
  781. return ret;
  782. ret = mxs_lradc_read_single(iio_dev, 9, &max);
  783. if (ret != IIO_VAL_INT)
  784. return ret;
  785. *val = max - min;
  786. return IIO_VAL_INT;
  787. }
  788. static int mxs_lradc_read_raw(struct iio_dev *iio_dev,
  789. const struct iio_chan_spec *chan,
  790. int *val, int *val2, long m)
  791. {
  792. struct mxs_lradc *lradc = iio_priv(iio_dev);
  793. switch (m) {
  794. case IIO_CHAN_INFO_RAW:
  795. if (chan->type == IIO_TEMP)
  796. return mxs_lradc_read_temp(iio_dev, val);
  797. return mxs_lradc_read_single(iio_dev, chan->channel, val);
  798. case IIO_CHAN_INFO_SCALE:
  799. if (chan->type == IIO_TEMP) {
  800. /*
  801. * From the datasheet, we have to multiply by 1.012 and
  802. * divide by 4
  803. */
  804. *val = 0;
  805. *val2 = 253000;
  806. return IIO_VAL_INT_PLUS_MICRO;
  807. }
  808. *val = lradc->vref_mv[chan->channel];
  809. *val2 = chan->scan_type.realbits -
  810. test_bit(chan->channel, &lradc->is_divided);
  811. return IIO_VAL_FRACTIONAL_LOG2;
  812. case IIO_CHAN_INFO_OFFSET:
  813. if (chan->type == IIO_TEMP) {
  814. /*
  815. * The calculated value from the ADC is in Kelvin, we
  816. * want Celsius for hwmon so the offset is -273.15
  817. * The offset is applied before scaling so it is
  818. * actually -213.15 * 4 / 1.012 = -1079.644268
  819. */
  820. *val = -1079;
  821. *val2 = 644268;
  822. return IIO_VAL_INT_PLUS_MICRO;
  823. }
  824. return -EINVAL;
  825. default:
  826. break;
  827. }
  828. return -EINVAL;
  829. }
  830. static int mxs_lradc_write_raw(struct iio_dev *iio_dev,
  831. const struct iio_chan_spec *chan,
  832. int val, int val2, long m)
  833. {
  834. struct mxs_lradc *lradc = iio_priv(iio_dev);
  835. struct mxs_lradc_scale *scale_avail =
  836. lradc->scale_avail[chan->channel];
  837. int ret;
  838. ret = mutex_trylock(&lradc->lock);
  839. if (!ret)
  840. return -EBUSY;
  841. switch (m) {
  842. case IIO_CHAN_INFO_SCALE:
  843. ret = -EINVAL;
  844. if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer &&
  845. val2 == scale_avail[MXS_LRADC_DIV_DISABLED].nano) {
  846. /* divider by two disabled */
  847. clear_bit(chan->channel, &lradc->is_divided);
  848. ret = 0;
  849. } else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer &&
  850. val2 == scale_avail[MXS_LRADC_DIV_ENABLED].nano) {
  851. /* divider by two enabled */
  852. set_bit(chan->channel, &lradc->is_divided);
  853. ret = 0;
  854. }
  855. break;
  856. default:
  857. ret = -EINVAL;
  858. break;
  859. }
  860. mutex_unlock(&lradc->lock);
  861. return ret;
  862. }
  863. static int mxs_lradc_write_raw_get_fmt(struct iio_dev *iio_dev,
  864. const struct iio_chan_spec *chan,
  865. long m)
  866. {
  867. return IIO_VAL_INT_PLUS_NANO;
  868. }
  869. static ssize_t mxs_lradc_show_scale_available_ch(struct device *dev,
  870. struct device_attribute *attr,
  871. char *buf,
  872. int ch)
  873. {
  874. struct iio_dev *iio = dev_to_iio_dev(dev);
  875. struct mxs_lradc *lradc = iio_priv(iio);
  876. int i, len = 0;
  877. for (i = 0; i < ARRAY_SIZE(lradc->scale_avail[ch]); i++)
  878. len += sprintf(buf + len, "%u.%09u ",
  879. lradc->scale_avail[ch][i].integer,
  880. lradc->scale_avail[ch][i].nano);
  881. len += sprintf(buf + len, "\n");
  882. return len;
  883. }
  884. static ssize_t mxs_lradc_show_scale_available(struct device *dev,
  885. struct device_attribute *attr,
  886. char *buf)
  887. {
  888. struct iio_dev_attr *iio_attr = to_iio_dev_attr(attr);
  889. return mxs_lradc_show_scale_available_ch(dev, attr, buf,
  890. iio_attr->address);
  891. }
  892. #define SHOW_SCALE_AVAILABLE_ATTR(ch) \
  893. static IIO_DEVICE_ATTR(in_voltage##ch##_scale_available, S_IRUGO, \
  894. mxs_lradc_show_scale_available, NULL, ch)
  895. SHOW_SCALE_AVAILABLE_ATTR(0);
  896. SHOW_SCALE_AVAILABLE_ATTR(1);
  897. SHOW_SCALE_AVAILABLE_ATTR(2);
  898. SHOW_SCALE_AVAILABLE_ATTR(3);
  899. SHOW_SCALE_AVAILABLE_ATTR(4);
  900. SHOW_SCALE_AVAILABLE_ATTR(5);
  901. SHOW_SCALE_AVAILABLE_ATTR(6);
  902. SHOW_SCALE_AVAILABLE_ATTR(7);
  903. SHOW_SCALE_AVAILABLE_ATTR(10);
  904. SHOW_SCALE_AVAILABLE_ATTR(11);
  905. SHOW_SCALE_AVAILABLE_ATTR(12);
  906. SHOW_SCALE_AVAILABLE_ATTR(13);
  907. SHOW_SCALE_AVAILABLE_ATTR(14);
  908. SHOW_SCALE_AVAILABLE_ATTR(15);
  909. static struct attribute *mxs_lradc_attributes[] = {
  910. &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
  911. &iio_dev_attr_in_voltage1_scale_available.dev_attr.attr,
  912. &iio_dev_attr_in_voltage2_scale_available.dev_attr.attr,
  913. &iio_dev_attr_in_voltage3_scale_available.dev_attr.attr,
  914. &iio_dev_attr_in_voltage4_scale_available.dev_attr.attr,
  915. &iio_dev_attr_in_voltage5_scale_available.dev_attr.attr,
  916. &iio_dev_attr_in_voltage6_scale_available.dev_attr.attr,
  917. &iio_dev_attr_in_voltage7_scale_available.dev_attr.attr,
  918. &iio_dev_attr_in_voltage10_scale_available.dev_attr.attr,
  919. &iio_dev_attr_in_voltage11_scale_available.dev_attr.attr,
  920. &iio_dev_attr_in_voltage12_scale_available.dev_attr.attr,
  921. &iio_dev_attr_in_voltage13_scale_available.dev_attr.attr,
  922. &iio_dev_attr_in_voltage14_scale_available.dev_attr.attr,
  923. &iio_dev_attr_in_voltage15_scale_available.dev_attr.attr,
  924. NULL
  925. };
  926. static const struct attribute_group mxs_lradc_attribute_group = {
  927. .attrs = mxs_lradc_attributes,
  928. };
  929. static const struct iio_info mxs_lradc_iio_info = {
  930. .driver_module = THIS_MODULE,
  931. .read_raw = mxs_lradc_read_raw,
  932. .write_raw = mxs_lradc_write_raw,
  933. .write_raw_get_fmt = mxs_lradc_write_raw_get_fmt,
  934. .attrs = &mxs_lradc_attribute_group,
  935. };
  936. static int mxs_lradc_ts_open(struct input_dev *dev)
  937. {
  938. struct mxs_lradc *lradc = input_get_drvdata(dev);
  939. /* Enable the touch-detect circuitry. */
  940. mxs_lradc_enable_touch_detection(lradc);
  941. return 0;
  942. }
  943. static void mxs_lradc_disable_ts(struct mxs_lradc *lradc)
  944. {
  945. /* stop all interrupts from firing */
  946. mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN |
  947. LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL1) |
  948. LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL2), LRADC_CTRL1);
  949. /* Power-down touchscreen touch-detect circuitry. */
  950. mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
  951. }
  952. static void mxs_lradc_ts_close(struct input_dev *dev)
  953. {
  954. struct mxs_lradc *lradc = input_get_drvdata(dev);
  955. mxs_lradc_disable_ts(lradc);
  956. }
  957. static int mxs_lradc_ts_register(struct mxs_lradc *lradc)
  958. {
  959. struct input_dev *input;
  960. struct device *dev = lradc->dev;
  961. int ret;
  962. if (!lradc->use_touchscreen)
  963. return 0;
  964. input = input_allocate_device();
  965. if (!input)
  966. return -ENOMEM;
  967. input->name = DRIVER_NAME;
  968. input->id.bustype = BUS_HOST;
  969. input->dev.parent = dev;
  970. input->open = mxs_lradc_ts_open;
  971. input->close = mxs_lradc_ts_close;
  972. __set_bit(EV_ABS, input->evbit);
  973. __set_bit(EV_KEY, input->evbit);
  974. __set_bit(BTN_TOUCH, input->keybit);
  975. input_set_abs_params(input, ABS_X, 0, LRADC_SINGLE_SAMPLE_MASK, 0, 0);
  976. input_set_abs_params(input, ABS_Y, 0, LRADC_SINGLE_SAMPLE_MASK, 0, 0);
  977. input_set_abs_params(input, ABS_PRESSURE, 0, LRADC_SINGLE_SAMPLE_MASK,
  978. 0, 0);
  979. lradc->ts_input = input;
  980. input_set_drvdata(input, lradc);
  981. ret = input_register_device(input);
  982. if (ret)
  983. input_free_device(lradc->ts_input);
  984. return ret;
  985. }
  986. static void mxs_lradc_ts_unregister(struct mxs_lradc *lradc)
  987. {
  988. if (!lradc->use_touchscreen)
  989. return;
  990. mxs_lradc_disable_ts(lradc);
  991. input_unregister_device(lradc->ts_input);
  992. }
  993. /*
  994. * IRQ Handling
  995. */
  996. static irqreturn_t mxs_lradc_handle_irq(int irq, void *data)
  997. {
  998. struct iio_dev *iio = data;
  999. struct mxs_lradc *lradc = iio_priv(iio);
  1000. unsigned long reg = readl(lradc->base + LRADC_CTRL1);
  1001. u32 clr_irq = mxs_lradc_irq_mask(lradc);
  1002. const u32 ts_irq_mask =
  1003. LRADC_CTRL1_TOUCH_DETECT_IRQ |
  1004. LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1) |
  1005. LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL2);
  1006. if (!(reg & mxs_lradc_irq_mask(lradc)))
  1007. return IRQ_NONE;
  1008. if (lradc->use_touchscreen && (reg & ts_irq_mask)) {
  1009. mxs_lradc_handle_touch(lradc);
  1010. /* Make sure we don't clear the next conversion's interrupt. */
  1011. clr_irq &= ~(LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1) |
  1012. LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL2));
  1013. }
  1014. if (iio_buffer_enabled(iio)) {
  1015. if (reg & lradc->buffer_vchans)
  1016. iio_trigger_poll(iio->trig);
  1017. } else if (reg & LRADC_CTRL1_LRADC_IRQ(0)) {
  1018. complete(&lradc->completion);
  1019. }
  1020. mxs_lradc_reg_clear(lradc, reg & clr_irq, LRADC_CTRL1);
  1021. return IRQ_HANDLED;
  1022. }
  1023. /*
  1024. * Trigger handling
  1025. */
  1026. static irqreturn_t mxs_lradc_trigger_handler(int irq, void *p)
  1027. {
  1028. struct iio_poll_func *pf = p;
  1029. struct iio_dev *iio = pf->indio_dev;
  1030. struct mxs_lradc *lradc = iio_priv(iio);
  1031. const u32 chan_value = LRADC_CH_ACCUMULATE |
  1032. ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
  1033. unsigned int i, j = 0;
  1034. for_each_set_bit(i, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
  1035. lradc->buffer[j] = readl(lradc->base + LRADC_CH(j));
  1036. mxs_lradc_reg_wrt(lradc, chan_value, LRADC_CH(j));
  1037. lradc->buffer[j] &= LRADC_CH_VALUE_MASK;
  1038. lradc->buffer[j] /= LRADC_DELAY_TIMER_LOOP;
  1039. j++;
  1040. }
  1041. iio_push_to_buffers_with_timestamp(iio, lradc->buffer, pf->timestamp);
  1042. iio_trigger_notify_done(iio->trig);
  1043. return IRQ_HANDLED;
  1044. }
  1045. static int mxs_lradc_configure_trigger(struct iio_trigger *trig, bool state)
  1046. {
  1047. struct iio_dev *iio = iio_trigger_get_drvdata(trig);
  1048. struct mxs_lradc *lradc = iio_priv(iio);
  1049. const u32 st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
  1050. mxs_lradc_reg_wrt(lradc, LRADC_DELAY_KICK, LRADC_DELAY(0) + st);
  1051. return 0;
  1052. }
  1053. static const struct iio_trigger_ops mxs_lradc_trigger_ops = {
  1054. .owner = THIS_MODULE,
  1055. .set_trigger_state = &mxs_lradc_configure_trigger,
  1056. };
  1057. static int mxs_lradc_trigger_init(struct iio_dev *iio)
  1058. {
  1059. int ret;
  1060. struct iio_trigger *trig;
  1061. struct mxs_lradc *lradc = iio_priv(iio);
  1062. trig = iio_trigger_alloc("%s-dev%i", iio->name, iio->id);
  1063. if (!trig)
  1064. return -ENOMEM;
  1065. trig->dev.parent = lradc->dev;
  1066. iio_trigger_set_drvdata(trig, iio);
  1067. trig->ops = &mxs_lradc_trigger_ops;
  1068. ret = iio_trigger_register(trig);
  1069. if (ret) {
  1070. iio_trigger_free(trig);
  1071. return ret;
  1072. }
  1073. lradc->trig = trig;
  1074. return 0;
  1075. }
  1076. static void mxs_lradc_trigger_remove(struct iio_dev *iio)
  1077. {
  1078. struct mxs_lradc *lradc = iio_priv(iio);
  1079. iio_trigger_unregister(lradc->trig);
  1080. iio_trigger_free(lradc->trig);
  1081. }
  1082. static int mxs_lradc_buffer_preenable(struct iio_dev *iio)
  1083. {
  1084. struct mxs_lradc *lradc = iio_priv(iio);
  1085. int ret = 0, chan, ofs = 0;
  1086. unsigned long enable = 0;
  1087. u32 ctrl4_set = 0;
  1088. u32 ctrl4_clr = 0;
  1089. u32 ctrl1_irq = 0;
  1090. const u32 chan_value = LRADC_CH_ACCUMULATE |
  1091. ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
  1092. const int len = bitmap_weight(iio->active_scan_mask,
  1093. LRADC_MAX_TOTAL_CHANS);
  1094. if (!len)
  1095. return -EINVAL;
  1096. /*
  1097. * Lock the driver so raw access can not be done during buffered
  1098. * operation. This simplifies the code a lot.
  1099. */
  1100. ret = mutex_trylock(&lradc->lock);
  1101. if (!ret)
  1102. return -EBUSY;
  1103. lradc->buffer = kmalloc_array(len, sizeof(*lradc->buffer), GFP_KERNEL);
  1104. if (!lradc->buffer) {
  1105. ret = -ENOMEM;
  1106. goto err_mem;
  1107. }
  1108. if (lradc->soc == IMX28_LRADC)
  1109. mxs_lradc_reg_clear(
  1110. lradc,
  1111. lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
  1112. LRADC_CTRL1);
  1113. mxs_lradc_reg_clear(lradc, lradc->buffer_vchans, LRADC_CTRL0);
  1114. for_each_set_bit(chan, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
  1115. ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
  1116. ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs);
  1117. ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
  1118. mxs_lradc_reg_wrt(lradc, chan_value, LRADC_CH(ofs));
  1119. bitmap_set(&enable, ofs, 1);
  1120. ofs++;
  1121. }
  1122. mxs_lradc_reg_clear(lradc, LRADC_DELAY_TRIGGER_LRADCS_MASK |
  1123. LRADC_DELAY_KICK, LRADC_DELAY(0));
  1124. mxs_lradc_reg_clear(lradc, ctrl4_clr, LRADC_CTRL4);
  1125. mxs_lradc_reg_set(lradc, ctrl4_set, LRADC_CTRL4);
  1126. mxs_lradc_reg_set(lradc, ctrl1_irq, LRADC_CTRL1);
  1127. mxs_lradc_reg_set(lradc, enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
  1128. LRADC_DELAY(0));
  1129. return 0;
  1130. err_mem:
  1131. mutex_unlock(&lradc->lock);
  1132. return ret;
  1133. }
  1134. static int mxs_lradc_buffer_postdisable(struct iio_dev *iio)
  1135. {
  1136. struct mxs_lradc *lradc = iio_priv(iio);
  1137. mxs_lradc_reg_clear(lradc, LRADC_DELAY_TRIGGER_LRADCS_MASK |
  1138. LRADC_DELAY_KICK, LRADC_DELAY(0));
  1139. mxs_lradc_reg_clear(lradc, lradc->buffer_vchans, LRADC_CTRL0);
  1140. if (lradc->soc == IMX28_LRADC)
  1141. mxs_lradc_reg_clear(
  1142. lradc,
  1143. lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
  1144. LRADC_CTRL1);
  1145. kfree(lradc->buffer);
  1146. mutex_unlock(&lradc->lock);
  1147. return 0;
  1148. }
  1149. static bool mxs_lradc_validate_scan_mask(struct iio_dev *iio,
  1150. const unsigned long *mask)
  1151. {
  1152. struct mxs_lradc *lradc = iio_priv(iio);
  1153. const int map_chans = bitmap_weight(mask, LRADC_MAX_TOTAL_CHANS);
  1154. int rsvd_chans = 0;
  1155. unsigned long rsvd_mask = 0;
  1156. if (lradc->use_touchbutton)
  1157. rsvd_mask |= CHAN_MASK_TOUCHBUTTON;
  1158. if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_4WIRE)
  1159. rsvd_mask |= CHAN_MASK_TOUCHSCREEN_4WIRE;
  1160. if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE)
  1161. rsvd_mask |= CHAN_MASK_TOUCHSCREEN_5WIRE;
  1162. if (lradc->use_touchbutton)
  1163. rsvd_chans++;
  1164. if (lradc->use_touchscreen)
  1165. rsvd_chans += 2;
  1166. /* Test for attempts to map channels with special mode of operation. */
  1167. if (bitmap_intersects(mask, &rsvd_mask, LRADC_MAX_TOTAL_CHANS))
  1168. return false;
  1169. /* Test for attempts to map more channels then available slots. */
  1170. if (map_chans + rsvd_chans > LRADC_MAX_MAPPED_CHANS)
  1171. return false;
  1172. return true;
  1173. }
  1174. static const struct iio_buffer_setup_ops mxs_lradc_buffer_ops = {
  1175. .preenable = &mxs_lradc_buffer_preenable,
  1176. .postenable = &iio_triggered_buffer_postenable,
  1177. .predisable = &iio_triggered_buffer_predisable,
  1178. .postdisable = &mxs_lradc_buffer_postdisable,
  1179. .validate_scan_mask = &mxs_lradc_validate_scan_mask,
  1180. };
  1181. /*
  1182. * Driver initialization
  1183. */
  1184. #define MXS_ADC_CHAN(idx, chan_type, name) { \
  1185. .type = (chan_type), \
  1186. .indexed = 1, \
  1187. .scan_index = (idx), \
  1188. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  1189. BIT(IIO_CHAN_INFO_SCALE), \
  1190. .channel = (idx), \
  1191. .address = (idx), \
  1192. .scan_type = { \
  1193. .sign = 'u', \
  1194. .realbits = LRADC_RESOLUTION, \
  1195. .storagebits = 32, \
  1196. }, \
  1197. .datasheet_name = (name), \
  1198. }
  1199. static const struct iio_chan_spec mx23_lradc_chan_spec[] = {
  1200. MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"),
  1201. MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"),
  1202. MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"),
  1203. MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"),
  1204. MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"),
  1205. MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"),
  1206. MXS_ADC_CHAN(6, IIO_VOLTAGE, "VDDIO"),
  1207. MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"),
  1208. /* Combined Temperature sensors */
  1209. {
  1210. .type = IIO_TEMP,
  1211. .indexed = 1,
  1212. .scan_index = 8,
  1213. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
  1214. BIT(IIO_CHAN_INFO_OFFSET) |
  1215. BIT(IIO_CHAN_INFO_SCALE),
  1216. .channel = 8,
  1217. .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
  1218. .datasheet_name = "TEMP_DIE",
  1219. },
  1220. /* Hidden channel to keep indexes */
  1221. {
  1222. .type = IIO_TEMP,
  1223. .indexed = 1,
  1224. .scan_index = -1,
  1225. .channel = 9,
  1226. },
  1227. MXS_ADC_CHAN(10, IIO_VOLTAGE, NULL),
  1228. MXS_ADC_CHAN(11, IIO_VOLTAGE, NULL),
  1229. MXS_ADC_CHAN(12, IIO_VOLTAGE, "USB_DP"),
  1230. MXS_ADC_CHAN(13, IIO_VOLTAGE, "USB_DN"),
  1231. MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"),
  1232. MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"),
  1233. };
  1234. static const struct iio_chan_spec mx28_lradc_chan_spec[] = {
  1235. MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"),
  1236. MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"),
  1237. MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"),
  1238. MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"),
  1239. MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"),
  1240. MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"),
  1241. MXS_ADC_CHAN(6, IIO_VOLTAGE, "LRADC6"),
  1242. MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"),
  1243. /* Combined Temperature sensors */
  1244. {
  1245. .type = IIO_TEMP,
  1246. .indexed = 1,
  1247. .scan_index = 8,
  1248. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
  1249. BIT(IIO_CHAN_INFO_OFFSET) |
  1250. BIT(IIO_CHAN_INFO_SCALE),
  1251. .channel = 8,
  1252. .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
  1253. .datasheet_name = "TEMP_DIE",
  1254. },
  1255. /* Hidden channel to keep indexes */
  1256. {
  1257. .type = IIO_TEMP,
  1258. .indexed = 1,
  1259. .scan_index = -1,
  1260. .channel = 9,
  1261. },
  1262. MXS_ADC_CHAN(10, IIO_VOLTAGE, "VDDIO"),
  1263. MXS_ADC_CHAN(11, IIO_VOLTAGE, "VTH"),
  1264. MXS_ADC_CHAN(12, IIO_VOLTAGE, "VDDA"),
  1265. MXS_ADC_CHAN(13, IIO_VOLTAGE, "VDDD"),
  1266. MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"),
  1267. MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"),
  1268. };
  1269. static int mxs_lradc_hw_init(struct mxs_lradc *lradc)
  1270. {
  1271. /* The ADC always uses DELAY CHANNEL 0. */
  1272. const u32 adc_cfg =
  1273. (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + 0)) |
  1274. (LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET);
  1275. int ret = stmp_reset_block(lradc->base);
  1276. if (ret)
  1277. return ret;
  1278. /* Configure DELAY CHANNEL 0 for generic ADC sampling. */
  1279. mxs_lradc_reg_wrt(lradc, adc_cfg, LRADC_DELAY(0));
  1280. /* Disable remaining DELAY CHANNELs */
  1281. mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(1));
  1282. mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(2));
  1283. mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(3));
  1284. /* Configure the touchscreen type */
  1285. if (lradc->soc == IMX28_LRADC) {
  1286. mxs_lradc_reg_clear(lradc, LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE,
  1287. LRADC_CTRL0);
  1288. if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE)
  1289. mxs_lradc_reg_set(lradc, LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE,
  1290. LRADC_CTRL0);
  1291. }
  1292. /* Start internal temperature sensing. */
  1293. mxs_lradc_reg_wrt(lradc, 0, LRADC_CTRL2);
  1294. return 0;
  1295. }
  1296. static void mxs_lradc_hw_stop(struct mxs_lradc *lradc)
  1297. {
  1298. int i;
  1299. mxs_lradc_reg_clear(lradc, mxs_lradc_irq_en_mask(lradc), LRADC_CTRL1);
  1300. for (i = 0; i < LRADC_MAX_DELAY_CHANS; i++)
  1301. mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(i));
  1302. }
  1303. static const struct of_device_id mxs_lradc_dt_ids[] = {
  1304. { .compatible = "fsl,imx23-lradc", .data = (void *)IMX23_LRADC, },
  1305. { .compatible = "fsl,imx28-lradc", .data = (void *)IMX28_LRADC, },
  1306. { /* sentinel */ }
  1307. };
  1308. MODULE_DEVICE_TABLE(of, mxs_lradc_dt_ids);
  1309. static int mxs_lradc_probe_touchscreen(struct mxs_lradc *lradc,
  1310. struct device_node *lradc_node)
  1311. {
  1312. int ret;
  1313. u32 ts_wires = 0, adapt;
  1314. ret = of_property_read_u32(lradc_node, "fsl,lradc-touchscreen-wires",
  1315. &ts_wires);
  1316. if (ret)
  1317. return -ENODEV; /* touchscreen feature disabled */
  1318. switch (ts_wires) {
  1319. case 4:
  1320. lradc->use_touchscreen = MXS_LRADC_TOUCHSCREEN_4WIRE;
  1321. break;
  1322. case 5:
  1323. if (lradc->soc == IMX28_LRADC) {
  1324. lradc->use_touchscreen = MXS_LRADC_TOUCHSCREEN_5WIRE;
  1325. break;
  1326. }
  1327. /* fall through an error message for i.MX23 */
  1328. default:
  1329. dev_err(lradc->dev,
  1330. "Unsupported number of touchscreen wires (%d)\n",
  1331. ts_wires);
  1332. return -EINVAL;
  1333. }
  1334. if (of_property_read_u32(lradc_node, "fsl,ave-ctrl", &adapt)) {
  1335. lradc->over_sample_cnt = 4;
  1336. } else {
  1337. if (adapt < 1 || adapt > 32) {
  1338. dev_err(lradc->dev, "Invalid sample count (%u)\n",
  1339. adapt);
  1340. return -EINVAL;
  1341. }
  1342. lradc->over_sample_cnt = adapt;
  1343. }
  1344. if (of_property_read_u32(lradc_node, "fsl,ave-delay", &adapt)) {
  1345. lradc->over_sample_delay = 2;
  1346. } else {
  1347. if (adapt < 2 || adapt > LRADC_DELAY_DELAY_MASK + 1) {
  1348. dev_err(lradc->dev, "Invalid sample delay (%u)\n",
  1349. adapt);
  1350. return -EINVAL;
  1351. }
  1352. lradc->over_sample_delay = adapt;
  1353. }
  1354. if (of_property_read_u32(lradc_node, "fsl,settling", &adapt)) {
  1355. lradc->settling_delay = 10;
  1356. } else {
  1357. if (adapt < 1 || adapt > LRADC_DELAY_DELAY_MASK) {
  1358. dev_err(lradc->dev, "Invalid settling delay (%u)\n",
  1359. adapt);
  1360. return -EINVAL;
  1361. }
  1362. lradc->settling_delay = adapt;
  1363. }
  1364. return 0;
  1365. }
  1366. static int mxs_lradc_probe(struct platform_device *pdev)
  1367. {
  1368. const struct of_device_id *of_id =
  1369. of_match_device(mxs_lradc_dt_ids, &pdev->dev);
  1370. const struct mxs_lradc_of_config *of_cfg =
  1371. &mxs_lradc_of_config[(enum mxs_lradc_id)of_id->data];
  1372. struct device *dev = &pdev->dev;
  1373. struct device_node *node = dev->of_node;
  1374. struct mxs_lradc *lradc;
  1375. struct iio_dev *iio;
  1376. struct resource *iores;
  1377. int ret = 0, touch_ret;
  1378. int i, s;
  1379. u64 scale_uv;
  1380. /* Allocate the IIO device. */
  1381. iio = devm_iio_device_alloc(dev, sizeof(*lradc));
  1382. if (!iio) {
  1383. dev_err(dev, "Failed to allocate IIO device\n");
  1384. return -ENOMEM;
  1385. }
  1386. lradc = iio_priv(iio);
  1387. lradc->soc = (enum mxs_lradc_id)of_id->data;
  1388. /* Grab the memory area */
  1389. iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1390. lradc->dev = &pdev->dev;
  1391. lradc->base = devm_ioremap_resource(dev, iores);
  1392. if (IS_ERR(lradc->base))
  1393. return PTR_ERR(lradc->base);
  1394. lradc->clk = devm_clk_get(&pdev->dev, NULL);
  1395. if (IS_ERR(lradc->clk)) {
  1396. dev_err(dev, "Failed to get the delay unit clock\n");
  1397. return PTR_ERR(lradc->clk);
  1398. }
  1399. ret = clk_prepare_enable(lradc->clk);
  1400. if (ret != 0) {
  1401. dev_err(dev, "Failed to enable the delay unit clock\n");
  1402. return ret;
  1403. }
  1404. touch_ret = mxs_lradc_probe_touchscreen(lradc, node);
  1405. if (touch_ret == 0)
  1406. lradc->buffer_vchans = BUFFER_VCHANS_LIMITED;
  1407. else
  1408. lradc->buffer_vchans = BUFFER_VCHANS_ALL;
  1409. /* Grab all IRQ sources */
  1410. for (i = 0; i < of_cfg->irq_count; i++) {
  1411. lradc->irq[i] = platform_get_irq(pdev, i);
  1412. if (lradc->irq[i] < 0) {
  1413. ret = lradc->irq[i];
  1414. goto err_clk;
  1415. }
  1416. ret = devm_request_irq(dev, lradc->irq[i],
  1417. mxs_lradc_handle_irq, 0,
  1418. of_cfg->irq_name[i], iio);
  1419. if (ret)
  1420. goto err_clk;
  1421. }
  1422. lradc->vref_mv = of_cfg->vref_mv;
  1423. platform_set_drvdata(pdev, iio);
  1424. init_completion(&lradc->completion);
  1425. mutex_init(&lradc->lock);
  1426. iio->name = pdev->name;
  1427. iio->dev.parent = &pdev->dev;
  1428. iio->info = &mxs_lradc_iio_info;
  1429. iio->modes = INDIO_DIRECT_MODE;
  1430. iio->masklength = LRADC_MAX_TOTAL_CHANS;
  1431. if (lradc->soc == IMX23_LRADC) {
  1432. iio->channels = mx23_lradc_chan_spec;
  1433. iio->num_channels = ARRAY_SIZE(mx23_lradc_chan_spec);
  1434. } else {
  1435. iio->channels = mx28_lradc_chan_spec;
  1436. iio->num_channels = ARRAY_SIZE(mx28_lradc_chan_spec);
  1437. }
  1438. ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time,
  1439. &mxs_lradc_trigger_handler,
  1440. &mxs_lradc_buffer_ops);
  1441. if (ret)
  1442. goto err_clk;
  1443. ret = mxs_lradc_trigger_init(iio);
  1444. if (ret)
  1445. goto err_trig;
  1446. /* Populate available ADC input ranges */
  1447. for (i = 0; i < LRADC_MAX_TOTAL_CHANS; i++) {
  1448. for (s = 0; s < ARRAY_SIZE(lradc->scale_avail[i]); s++) {
  1449. /*
  1450. * [s=0] = optional divider by two disabled (default)
  1451. * [s=1] = optional divider by two enabled
  1452. *
  1453. * The scale is calculated by doing:
  1454. * Vref >> (realbits - s)
  1455. * which multiplies by two on the second component
  1456. * of the array.
  1457. */
  1458. scale_uv = ((u64)lradc->vref_mv[i] * 100000000) >>
  1459. (LRADC_RESOLUTION - s);
  1460. lradc->scale_avail[i][s].nano =
  1461. do_div(scale_uv, 100000000) * 10;
  1462. lradc->scale_avail[i][s].integer = scale_uv;
  1463. }
  1464. }
  1465. /* Configure the hardware. */
  1466. ret = mxs_lradc_hw_init(lradc);
  1467. if (ret)
  1468. goto err_dev;
  1469. /* Register the touchscreen input device. */
  1470. if (touch_ret == 0) {
  1471. ret = mxs_lradc_ts_register(lradc);
  1472. if (ret)
  1473. goto err_ts_register;
  1474. }
  1475. /* Register IIO device. */
  1476. ret = iio_device_register(iio);
  1477. if (ret) {
  1478. dev_err(dev, "Failed to register IIO device\n");
  1479. goto err_ts;
  1480. }
  1481. return 0;
  1482. err_ts:
  1483. mxs_lradc_ts_unregister(lradc);
  1484. err_ts_register:
  1485. mxs_lradc_hw_stop(lradc);
  1486. err_dev:
  1487. mxs_lradc_trigger_remove(iio);
  1488. err_trig:
  1489. iio_triggered_buffer_cleanup(iio);
  1490. err_clk:
  1491. clk_disable_unprepare(lradc->clk);
  1492. return ret;
  1493. }
  1494. static int mxs_lradc_remove(struct platform_device *pdev)
  1495. {
  1496. struct iio_dev *iio = platform_get_drvdata(pdev);
  1497. struct mxs_lradc *lradc = iio_priv(iio);
  1498. iio_device_unregister(iio);
  1499. mxs_lradc_ts_unregister(lradc);
  1500. mxs_lradc_hw_stop(lradc);
  1501. mxs_lradc_trigger_remove(iio);
  1502. iio_triggered_buffer_cleanup(iio);
  1503. clk_disable_unprepare(lradc->clk);
  1504. return 0;
  1505. }
  1506. static struct platform_driver mxs_lradc_driver = {
  1507. .driver = {
  1508. .name = DRIVER_NAME,
  1509. .of_match_table = mxs_lradc_dt_ids,
  1510. },
  1511. .probe = mxs_lradc_probe,
  1512. .remove = mxs_lradc_remove,
  1513. };
  1514. module_platform_driver(mxs_lradc_driver);
  1515. MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
  1516. MODULE_DESCRIPTION("Freescale MXS LRADC driver");
  1517. MODULE_LICENSE("GPL v2");
  1518. MODULE_ALIAS("platform:" DRIVER_NAME);