ina2xx-adc.c 18 KB

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  1. /*
  2. * INA2XX Current and Power Monitors
  3. *
  4. * Copyright 2015 Baylibre SAS.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * Based on linux/drivers/iio/adc/ad7291.c
  11. * Copyright 2010-2011 Analog Devices Inc.
  12. *
  13. * Based on linux/drivers/hwmon/ina2xx.c
  14. * Copyright 2012 Lothar Felten <l-felten@ti.com>
  15. *
  16. * Licensed under the GPL-2 or later.
  17. *
  18. * IIO driver for INA219-220-226-230-231
  19. *
  20. * Configurable 7-bit I2C slave address from 0x40 to 0x4F
  21. */
  22. #include <linux/delay.h>
  23. #include <linux/i2c.h>
  24. #include <linux/iio/kfifo_buf.h>
  25. #include <linux/iio/sysfs.h>
  26. #include <linux/kthread.h>
  27. #include <linux/module.h>
  28. #include <linux/regmap.h>
  29. #include <linux/util_macros.h>
  30. #include <linux/platform_data/ina2xx.h>
  31. /* INA2XX registers definition */
  32. #define INA2XX_CONFIG 0x00
  33. #define INA2XX_SHUNT_VOLTAGE 0x01 /* readonly */
  34. #define INA2XX_BUS_VOLTAGE 0x02 /* readonly */
  35. #define INA2XX_POWER 0x03 /* readonly */
  36. #define INA2XX_CURRENT 0x04 /* readonly */
  37. #define INA2XX_CALIBRATION 0x05
  38. #define INA226_ALERT_MASK GENMASK(2, 1)
  39. #define INA266_CVRF BIT(3)
  40. #define INA2XX_MAX_REGISTERS 8
  41. /* settings - depend on use case */
  42. #define INA219_CONFIG_DEFAULT 0x399F /* PGA=8 */
  43. #define INA226_CONFIG_DEFAULT 0x4327
  44. #define INA226_DEFAULT_AVG 4
  45. #define INA226_DEFAULT_IT 1110
  46. #define INA2XX_RSHUNT_DEFAULT 10000
  47. /*
  48. * bit mask for reading the averaging setting in the configuration register
  49. * FIXME: use regmap_fields.
  50. */
  51. #define INA2XX_MODE_MASK GENMASK(3, 0)
  52. #define INA226_AVG_MASK GENMASK(11, 9)
  53. #define INA226_SHIFT_AVG(val) ((val) << 9)
  54. /* Integration time for VBus */
  55. #define INA226_ITB_MASK GENMASK(8, 6)
  56. #define INA226_SHIFT_ITB(val) ((val) << 6)
  57. /* Integration time for VShunt */
  58. #define INA226_ITS_MASK GENMASK(5, 3)
  59. #define INA226_SHIFT_ITS(val) ((val) << 3)
  60. /* Cosmetic macro giving the sampling period for a full P=UxI cycle */
  61. #define SAMPLING_PERIOD(c) ((c->int_time_vbus + c->int_time_vshunt) \
  62. * c->avg)
  63. static bool ina2xx_is_writeable_reg(struct device *dev, unsigned int reg)
  64. {
  65. return (reg == INA2XX_CONFIG) || (reg > INA2XX_CURRENT);
  66. }
  67. static bool ina2xx_is_volatile_reg(struct device *dev, unsigned int reg)
  68. {
  69. return (reg != INA2XX_CONFIG);
  70. }
  71. static inline bool is_signed_reg(unsigned int reg)
  72. {
  73. return (reg == INA2XX_SHUNT_VOLTAGE) || (reg == INA2XX_CURRENT);
  74. }
  75. static const struct regmap_config ina2xx_regmap_config = {
  76. .reg_bits = 8,
  77. .val_bits = 16,
  78. .max_register = INA2XX_MAX_REGISTERS,
  79. .writeable_reg = ina2xx_is_writeable_reg,
  80. .volatile_reg = ina2xx_is_volatile_reg,
  81. };
  82. enum ina2xx_ids { ina219, ina226 };
  83. struct ina2xx_config {
  84. u16 config_default;
  85. int calibration_factor;
  86. int shunt_div;
  87. int bus_voltage_shift;
  88. int bus_voltage_lsb; /* uV */
  89. int power_lsb; /* uW */
  90. };
  91. struct ina2xx_chip_info {
  92. struct regmap *regmap;
  93. struct task_struct *task;
  94. const struct ina2xx_config *config;
  95. struct mutex state_lock;
  96. unsigned int shunt_resistor;
  97. int avg;
  98. s64 prev_ns; /* track buffer capture time, check for underruns */
  99. int int_time_vbus; /* Bus voltage integration time uS */
  100. int int_time_vshunt; /* Shunt voltage integration time uS */
  101. bool allow_async_readout;
  102. };
  103. static const struct ina2xx_config ina2xx_config[] = {
  104. [ina219] = {
  105. .config_default = INA219_CONFIG_DEFAULT,
  106. .calibration_factor = 40960000,
  107. .shunt_div = 100,
  108. .bus_voltage_shift = 3,
  109. .bus_voltage_lsb = 4000,
  110. .power_lsb = 20000,
  111. },
  112. [ina226] = {
  113. .config_default = INA226_CONFIG_DEFAULT,
  114. .calibration_factor = 5120000,
  115. .shunt_div = 400,
  116. .bus_voltage_shift = 0,
  117. .bus_voltage_lsb = 1250,
  118. .power_lsb = 25000,
  119. },
  120. };
  121. static int ina2xx_read_raw(struct iio_dev *indio_dev,
  122. struct iio_chan_spec const *chan,
  123. int *val, int *val2, long mask)
  124. {
  125. int ret;
  126. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  127. unsigned int regval;
  128. switch (mask) {
  129. case IIO_CHAN_INFO_RAW:
  130. ret = regmap_read(chip->regmap, chan->address, &regval);
  131. if (ret)
  132. return ret;
  133. if (is_signed_reg(chan->address))
  134. *val = (s16) regval;
  135. else
  136. *val = regval;
  137. return IIO_VAL_INT;
  138. case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
  139. *val = chip->avg;
  140. return IIO_VAL_INT;
  141. case IIO_CHAN_INFO_INT_TIME:
  142. *val = 0;
  143. if (chan->address == INA2XX_SHUNT_VOLTAGE)
  144. *val2 = chip->int_time_vshunt;
  145. else
  146. *val2 = chip->int_time_vbus;
  147. return IIO_VAL_INT_PLUS_MICRO;
  148. case IIO_CHAN_INFO_SAMP_FREQ:
  149. /*
  150. * Sample freq is read only, it is a consequence of
  151. * 1/AVG*(CT_bus+CT_shunt).
  152. */
  153. *val = DIV_ROUND_CLOSEST(1000000, SAMPLING_PERIOD(chip));
  154. return IIO_VAL_INT;
  155. case IIO_CHAN_INFO_SCALE:
  156. switch (chan->address) {
  157. case INA2XX_SHUNT_VOLTAGE:
  158. /* processed (mV) = raw/shunt_div */
  159. *val2 = chip->config->shunt_div;
  160. *val = 1;
  161. return IIO_VAL_FRACTIONAL;
  162. case INA2XX_BUS_VOLTAGE:
  163. /* processed (mV) = raw*lsb (uV) / (1000 << shift) */
  164. *val = chip->config->bus_voltage_lsb;
  165. *val2 = 1000 << chip->config->bus_voltage_shift;
  166. return IIO_VAL_FRACTIONAL;
  167. case INA2XX_POWER:
  168. /* processed (mW) = raw*lsb (uW) / 1000 */
  169. *val = chip->config->power_lsb;
  170. *val2 = 1000;
  171. return IIO_VAL_FRACTIONAL;
  172. case INA2XX_CURRENT:
  173. /* processed (mA) = raw (mA) */
  174. *val = 1;
  175. return IIO_VAL_INT;
  176. }
  177. }
  178. return -EINVAL;
  179. }
  180. /*
  181. * Available averaging rates for ina226. The indices correspond with
  182. * the bit values expected by the chip (according to the ina226 datasheet,
  183. * table 3 AVG bit settings, found at
  184. * http://www.ti.com/lit/ds/symlink/ina226.pdf.
  185. */
  186. static const int ina226_avg_tab[] = { 1, 4, 16, 64, 128, 256, 512, 1024 };
  187. static int ina226_set_average(struct ina2xx_chip_info *chip, unsigned int val,
  188. unsigned int *config)
  189. {
  190. int bits;
  191. if (val > 1024 || val < 1)
  192. return -EINVAL;
  193. bits = find_closest(val, ina226_avg_tab,
  194. ARRAY_SIZE(ina226_avg_tab));
  195. chip->avg = ina226_avg_tab[bits];
  196. *config &= ~INA226_AVG_MASK;
  197. *config |= INA226_SHIFT_AVG(bits) & INA226_AVG_MASK;
  198. return 0;
  199. }
  200. /* Conversion times in uS */
  201. static const int ina226_conv_time_tab[] = { 140, 204, 332, 588, 1100,
  202. 2116, 4156, 8244 };
  203. static int ina226_set_int_time_vbus(struct ina2xx_chip_info *chip,
  204. unsigned int val_us, unsigned int *config)
  205. {
  206. int bits;
  207. if (val_us > 8244 || val_us < 140)
  208. return -EINVAL;
  209. bits = find_closest(val_us, ina226_conv_time_tab,
  210. ARRAY_SIZE(ina226_conv_time_tab));
  211. chip->int_time_vbus = ina226_conv_time_tab[bits];
  212. *config &= ~INA226_ITB_MASK;
  213. *config |= INA226_SHIFT_ITB(bits) & INA226_ITB_MASK;
  214. return 0;
  215. }
  216. static int ina226_set_int_time_vshunt(struct ina2xx_chip_info *chip,
  217. unsigned int val_us, unsigned int *config)
  218. {
  219. int bits;
  220. if (val_us > 8244 || val_us < 140)
  221. return -EINVAL;
  222. bits = find_closest(val_us, ina226_conv_time_tab,
  223. ARRAY_SIZE(ina226_conv_time_tab));
  224. chip->int_time_vshunt = ina226_conv_time_tab[bits];
  225. *config &= ~INA226_ITS_MASK;
  226. *config |= INA226_SHIFT_ITS(bits) & INA226_ITS_MASK;
  227. return 0;
  228. }
  229. static int ina2xx_write_raw(struct iio_dev *indio_dev,
  230. struct iio_chan_spec const *chan,
  231. int val, int val2, long mask)
  232. {
  233. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  234. unsigned int config, tmp;
  235. int ret;
  236. if (iio_buffer_enabled(indio_dev))
  237. return -EBUSY;
  238. mutex_lock(&chip->state_lock);
  239. ret = regmap_read(chip->regmap, INA2XX_CONFIG, &config);
  240. if (ret)
  241. goto err;
  242. tmp = config;
  243. switch (mask) {
  244. case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
  245. ret = ina226_set_average(chip, val, &tmp);
  246. break;
  247. case IIO_CHAN_INFO_INT_TIME:
  248. if (chan->address == INA2XX_SHUNT_VOLTAGE)
  249. ret = ina226_set_int_time_vshunt(chip, val2, &tmp);
  250. else
  251. ret = ina226_set_int_time_vbus(chip, val2, &tmp);
  252. break;
  253. default:
  254. ret = -EINVAL;
  255. }
  256. if (!ret && (tmp != config))
  257. ret = regmap_write(chip->regmap, INA2XX_CONFIG, tmp);
  258. err:
  259. mutex_unlock(&chip->state_lock);
  260. return ret;
  261. }
  262. static ssize_t ina2xx_allow_async_readout_show(struct device *dev,
  263. struct device_attribute *attr,
  264. char *buf)
  265. {
  266. struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev));
  267. return sprintf(buf, "%d\n", chip->allow_async_readout);
  268. }
  269. static ssize_t ina2xx_allow_async_readout_store(struct device *dev,
  270. struct device_attribute *attr,
  271. const char *buf, size_t len)
  272. {
  273. struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev));
  274. bool val;
  275. int ret;
  276. ret = strtobool((const char *) buf, &val);
  277. if (ret)
  278. return ret;
  279. chip->allow_async_readout = val;
  280. return len;
  281. }
  282. /*
  283. * Set current LSB to 1mA, shunt is in uOhms
  284. * (equation 13 in datasheet). We hardcode a Current_LSB
  285. * of 1.0 x10-6. The only remaining parameter is RShunt.
  286. * There is no need to expose the CALIBRATION register
  287. * to the user for now. But we need to reset this register
  288. * if the user updates RShunt after driver init, e.g upon
  289. * reading an EEPROM/Probe-type value.
  290. */
  291. static int ina2xx_set_calibration(struct ina2xx_chip_info *chip)
  292. {
  293. u16 regval = DIV_ROUND_CLOSEST(chip->config->calibration_factor,
  294. chip->shunt_resistor);
  295. return regmap_write(chip->regmap, INA2XX_CALIBRATION, regval);
  296. }
  297. static int set_shunt_resistor(struct ina2xx_chip_info *chip, unsigned int val)
  298. {
  299. if (val <= 0 || val > chip->config->calibration_factor)
  300. return -EINVAL;
  301. chip->shunt_resistor = val;
  302. return 0;
  303. }
  304. static ssize_t ina2xx_shunt_resistor_show(struct device *dev,
  305. struct device_attribute *attr,
  306. char *buf)
  307. {
  308. struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev));
  309. return sprintf(buf, "%d\n", chip->shunt_resistor);
  310. }
  311. static ssize_t ina2xx_shunt_resistor_store(struct device *dev,
  312. struct device_attribute *attr,
  313. const char *buf, size_t len)
  314. {
  315. struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev));
  316. unsigned long val;
  317. int ret;
  318. ret = kstrtoul((const char *) buf, 10, &val);
  319. if (ret)
  320. return ret;
  321. ret = set_shunt_resistor(chip, val);
  322. if (ret)
  323. return ret;
  324. /* Update the Calibration register */
  325. ret = ina2xx_set_calibration(chip);
  326. if (ret)
  327. return ret;
  328. return len;
  329. }
  330. #define INA2XX_CHAN(_type, _index, _address) { \
  331. .type = (_type), \
  332. .address = (_address), \
  333. .indexed = 1, \
  334. .channel = (_index), \
  335. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \
  336. | BIT(IIO_CHAN_INFO_SCALE), \
  337. .info_mask_shared_by_dir = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
  338. BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
  339. .scan_index = (_index), \
  340. .scan_type = { \
  341. .sign = 'u', \
  342. .realbits = 16, \
  343. .storagebits = 16, \
  344. .endianness = IIO_CPU, \
  345. } \
  346. }
  347. /*
  348. * Sampling Freq is a consequence of the integration times of
  349. * the Voltage channels.
  350. */
  351. #define INA2XX_CHAN_VOLTAGE(_index, _address) { \
  352. .type = IIO_VOLTAGE, \
  353. .address = (_address), \
  354. .indexed = 1, \
  355. .channel = (_index), \
  356. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  357. BIT(IIO_CHAN_INFO_SCALE) | \
  358. BIT(IIO_CHAN_INFO_INT_TIME), \
  359. .scan_index = (_index), \
  360. .scan_type = { \
  361. .sign = 'u', \
  362. .realbits = 16, \
  363. .storagebits = 16, \
  364. .endianness = IIO_LE, \
  365. } \
  366. }
  367. static const struct iio_chan_spec ina2xx_channels[] = {
  368. INA2XX_CHAN_VOLTAGE(0, INA2XX_SHUNT_VOLTAGE),
  369. INA2XX_CHAN_VOLTAGE(1, INA2XX_BUS_VOLTAGE),
  370. INA2XX_CHAN(IIO_POWER, 2, INA2XX_POWER),
  371. INA2XX_CHAN(IIO_CURRENT, 3, INA2XX_CURRENT),
  372. IIO_CHAN_SOFT_TIMESTAMP(4),
  373. };
  374. static int ina2xx_work_buffer(struct iio_dev *indio_dev)
  375. {
  376. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  377. unsigned short data[8];
  378. int bit, ret, i = 0;
  379. s64 time_a, time_b;
  380. unsigned int alert;
  381. time_a = iio_get_time_ns();
  382. /*
  383. * Because the timer thread and the chip conversion clock
  384. * are asynchronous, the period difference will eventually
  385. * result in reading V[k-1] again, or skip V[k] at time Tk.
  386. * In order to resync the timer with the conversion process
  387. * we check the ConVersionReadyFlag.
  388. * On hardware that supports using the ALERT pin to toggle a
  389. * GPIO a triggered buffer could be used instead.
  390. * For now, we pay for that extra read of the ALERT register
  391. */
  392. if (!chip->allow_async_readout)
  393. do {
  394. ret = regmap_read(chip->regmap, INA226_ALERT_MASK,
  395. &alert);
  396. if (ret < 0)
  397. return ret;
  398. alert &= INA266_CVRF;
  399. } while (!alert);
  400. /*
  401. * Single register reads: bulk_read will not work with ina226
  402. * as there is no auto-increment of the address register for
  403. * data length longer than 16bits.
  404. */
  405. for_each_set_bit(bit, indio_dev->active_scan_mask,
  406. indio_dev->masklength) {
  407. unsigned int val;
  408. ret = regmap_read(chip->regmap,
  409. INA2XX_SHUNT_VOLTAGE + bit, &val);
  410. if (ret < 0)
  411. return ret;
  412. data[i++] = val;
  413. }
  414. time_b = iio_get_time_ns();
  415. iio_push_to_buffers_with_timestamp(indio_dev,
  416. (unsigned int *)data, time_a);
  417. chip->prev_ns = time_a;
  418. return (unsigned long)(time_b - time_a) / 1000;
  419. };
  420. static int ina2xx_capture_thread(void *data)
  421. {
  422. struct iio_dev *indio_dev = data;
  423. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  424. unsigned int sampling_us = SAMPLING_PERIOD(chip);
  425. int buffer_us;
  426. /*
  427. * Poll a bit faster than the chip internal Fs, in case
  428. * we wish to sync with the conversion ready flag.
  429. */
  430. if (!chip->allow_async_readout)
  431. sampling_us -= 200;
  432. do {
  433. buffer_us = ina2xx_work_buffer(indio_dev);
  434. if (buffer_us < 0)
  435. return buffer_us;
  436. if (sampling_us > buffer_us)
  437. udelay(sampling_us - buffer_us);
  438. } while (!kthread_should_stop());
  439. return 0;
  440. }
  441. static int ina2xx_buffer_enable(struct iio_dev *indio_dev)
  442. {
  443. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  444. unsigned int sampling_us = SAMPLING_PERIOD(chip);
  445. dev_dbg(&indio_dev->dev, "Enabling buffer w/ scan_mask %02x, freq = %d, avg =%u\n",
  446. (unsigned int)(*indio_dev->active_scan_mask),
  447. 1000000 / sampling_us, chip->avg);
  448. dev_dbg(&indio_dev->dev, "Expected work period: %u us\n", sampling_us);
  449. dev_dbg(&indio_dev->dev, "Async readout mode: %d\n",
  450. chip->allow_async_readout);
  451. chip->prev_ns = iio_get_time_ns();
  452. chip->task = kthread_run(ina2xx_capture_thread, (void *)indio_dev,
  453. "%s:%d-%uus", indio_dev->name, indio_dev->id,
  454. sampling_us);
  455. return PTR_ERR_OR_ZERO(chip->task);
  456. }
  457. static int ina2xx_buffer_disable(struct iio_dev *indio_dev)
  458. {
  459. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  460. if (chip->task) {
  461. kthread_stop(chip->task);
  462. chip->task = NULL;
  463. }
  464. return 0;
  465. }
  466. static const struct iio_buffer_setup_ops ina2xx_setup_ops = {
  467. .postenable = &ina2xx_buffer_enable,
  468. .predisable = &ina2xx_buffer_disable,
  469. };
  470. static int ina2xx_debug_reg(struct iio_dev *indio_dev,
  471. unsigned reg, unsigned writeval, unsigned *readval)
  472. {
  473. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  474. if (!readval)
  475. return regmap_write(chip->regmap, reg, writeval);
  476. return regmap_read(chip->regmap, reg, readval);
  477. }
  478. /* Possible integration times for vshunt and vbus */
  479. static IIO_CONST_ATTR_INT_TIME_AVAIL("0.000140 0.000204 0.000332 0.000588 0.001100 0.002116 0.004156 0.008244");
  480. static IIO_DEVICE_ATTR(in_allow_async_readout, S_IRUGO | S_IWUSR,
  481. ina2xx_allow_async_readout_show,
  482. ina2xx_allow_async_readout_store, 0);
  483. static IIO_DEVICE_ATTR(in_shunt_resistor, S_IRUGO | S_IWUSR,
  484. ina2xx_shunt_resistor_show,
  485. ina2xx_shunt_resistor_store, 0);
  486. static struct attribute *ina2xx_attributes[] = {
  487. &iio_dev_attr_in_allow_async_readout.dev_attr.attr,
  488. &iio_const_attr_integration_time_available.dev_attr.attr,
  489. &iio_dev_attr_in_shunt_resistor.dev_attr.attr,
  490. NULL,
  491. };
  492. static const struct attribute_group ina2xx_attribute_group = {
  493. .attrs = ina2xx_attributes,
  494. };
  495. static const struct iio_info ina2xx_info = {
  496. .driver_module = THIS_MODULE,
  497. .attrs = &ina2xx_attribute_group,
  498. .read_raw = ina2xx_read_raw,
  499. .write_raw = ina2xx_write_raw,
  500. .debugfs_reg_access = ina2xx_debug_reg,
  501. };
  502. /* Initialize the configuration and calibration registers. */
  503. static int ina2xx_init(struct ina2xx_chip_info *chip, unsigned int config)
  504. {
  505. int ret = regmap_write(chip->regmap, INA2XX_CONFIG, config);
  506. if (ret)
  507. return ret;
  508. return ina2xx_set_calibration(chip);
  509. }
  510. static int ina2xx_probe(struct i2c_client *client,
  511. const struct i2c_device_id *id)
  512. {
  513. struct ina2xx_chip_info *chip;
  514. struct iio_dev *indio_dev;
  515. struct iio_buffer *buffer;
  516. unsigned int val;
  517. int ret;
  518. indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip));
  519. if (!indio_dev)
  520. return -ENOMEM;
  521. chip = iio_priv(indio_dev);
  522. /* This is only used for device removal purposes. */
  523. i2c_set_clientdata(client, indio_dev);
  524. chip->regmap = devm_regmap_init_i2c(client, &ina2xx_regmap_config);
  525. if (IS_ERR(chip->regmap)) {
  526. dev_err(&client->dev, "failed to allocate register map\n");
  527. return PTR_ERR(chip->regmap);
  528. }
  529. chip->config = &ina2xx_config[id->driver_data];
  530. mutex_init(&chip->state_lock);
  531. if (of_property_read_u32(client->dev.of_node,
  532. "shunt-resistor", &val) < 0) {
  533. struct ina2xx_platform_data *pdata =
  534. dev_get_platdata(&client->dev);
  535. if (pdata)
  536. val = pdata->shunt_uohms;
  537. else
  538. val = INA2XX_RSHUNT_DEFAULT;
  539. }
  540. ret = set_shunt_resistor(chip, val);
  541. if (ret)
  542. return ret;
  543. /* Patch the current config register with default. */
  544. val = chip->config->config_default;
  545. if (id->driver_data == ina226) {
  546. ina226_set_average(chip, INA226_DEFAULT_AVG, &val);
  547. ina226_set_int_time_vbus(chip, INA226_DEFAULT_IT, &val);
  548. ina226_set_int_time_vshunt(chip, INA226_DEFAULT_IT, &val);
  549. }
  550. ret = ina2xx_init(chip, val);
  551. if (ret) {
  552. dev_err(&client->dev, "error configuring the device\n");
  553. return ret;
  554. }
  555. indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
  556. indio_dev->dev.parent = &client->dev;
  557. indio_dev->channels = ina2xx_channels;
  558. indio_dev->num_channels = ARRAY_SIZE(ina2xx_channels);
  559. indio_dev->name = id->name;
  560. indio_dev->info = &ina2xx_info;
  561. indio_dev->setup_ops = &ina2xx_setup_ops;
  562. buffer = devm_iio_kfifo_allocate(&indio_dev->dev);
  563. if (!buffer)
  564. return -ENOMEM;
  565. iio_device_attach_buffer(indio_dev, buffer);
  566. return iio_device_register(indio_dev);
  567. }
  568. static int ina2xx_remove(struct i2c_client *client)
  569. {
  570. struct iio_dev *indio_dev = i2c_get_clientdata(client);
  571. struct ina2xx_chip_info *chip = iio_priv(indio_dev);
  572. iio_device_unregister(indio_dev);
  573. /* Powerdown */
  574. return regmap_update_bits(chip->regmap, INA2XX_CONFIG,
  575. INA2XX_MODE_MASK, 0);
  576. }
  577. static const struct i2c_device_id ina2xx_id[] = {
  578. {"ina219", ina219},
  579. {"ina220", ina219},
  580. {"ina226", ina226},
  581. {"ina230", ina226},
  582. {"ina231", ina226},
  583. {}
  584. };
  585. MODULE_DEVICE_TABLE(i2c, ina2xx_id);
  586. static struct i2c_driver ina2xx_driver = {
  587. .driver = {
  588. .name = KBUILD_MODNAME,
  589. },
  590. .probe = ina2xx_probe,
  591. .remove = ina2xx_remove,
  592. .id_table = ina2xx_id,
  593. };
  594. module_i2c_driver(ina2xx_driver);
  595. MODULE_AUTHOR("Marc Titinger <marc.titinger@baylibre.com>");
  596. MODULE_DESCRIPTION("Texas Instruments INA2XX ADC driver");
  597. MODULE_LICENSE("GPL v2");