ixgbe_common.c 120 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* Copyright(c) 1999 - 2018 Intel Corporation. */
  3. #include <linux/pci.h>
  4. #include <linux/delay.h>
  5. #include <linux/sched.h>
  6. #include <linux/netdevice.h>
  7. #include "ixgbe.h"
  8. #include "ixgbe_common.h"
  9. #include "ixgbe_phy.h"
  10. static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
  11. static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
  12. static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
  13. static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
  14. static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
  15. static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
  16. u16 count);
  17. static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
  18. static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
  19. static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
  20. static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
  21. static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
  22. static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
  23. static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
  24. u16 words, u16 *data);
  25. static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
  26. u16 words, u16 *data);
  27. static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
  28. u16 offset);
  29. static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
  30. /* Base table for registers values that change by MAC */
  31. const u32 ixgbe_mvals_8259X[IXGBE_MVALS_IDX_LIMIT] = {
  32. IXGBE_MVALS_INIT(8259X)
  33. };
  34. /**
  35. * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
  36. * control
  37. * @hw: pointer to hardware structure
  38. *
  39. * There are several phys that do not support autoneg flow control. This
  40. * function check the device id to see if the associated phy supports
  41. * autoneg flow control.
  42. **/
  43. bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
  44. {
  45. bool supported = false;
  46. ixgbe_link_speed speed;
  47. bool link_up;
  48. switch (hw->phy.media_type) {
  49. case ixgbe_media_type_fiber:
  50. /* flow control autoneg black list */
  51. switch (hw->device_id) {
  52. case IXGBE_DEV_ID_X550EM_A_SFP:
  53. case IXGBE_DEV_ID_X550EM_A_SFP_N:
  54. supported = false;
  55. break;
  56. default:
  57. hw->mac.ops.check_link(hw, &speed, &link_up, false);
  58. /* if link is down, assume supported */
  59. if (link_up)
  60. supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
  61. true : false;
  62. else
  63. supported = true;
  64. }
  65. break;
  66. case ixgbe_media_type_backplane:
  67. if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI)
  68. supported = false;
  69. else
  70. supported = true;
  71. break;
  72. case ixgbe_media_type_copper:
  73. /* only some copper devices support flow control autoneg */
  74. switch (hw->device_id) {
  75. case IXGBE_DEV_ID_82599_T3_LOM:
  76. case IXGBE_DEV_ID_X540T:
  77. case IXGBE_DEV_ID_X540T1:
  78. case IXGBE_DEV_ID_X550T:
  79. case IXGBE_DEV_ID_X550T1:
  80. case IXGBE_DEV_ID_X550EM_X_10G_T:
  81. case IXGBE_DEV_ID_X550EM_A_10G_T:
  82. case IXGBE_DEV_ID_X550EM_A_1G_T:
  83. case IXGBE_DEV_ID_X550EM_A_1G_T_L:
  84. supported = true;
  85. break;
  86. default:
  87. break;
  88. }
  89. default:
  90. break;
  91. }
  92. if (!supported)
  93. hw_dbg(hw, "Device %x does not support flow control autoneg\n",
  94. hw->device_id);
  95. return supported;
  96. }
  97. /**
  98. * ixgbe_setup_fc_generic - Set up flow control
  99. * @hw: pointer to hardware structure
  100. *
  101. * Called at init time to set up flow control.
  102. **/
  103. s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
  104. {
  105. s32 ret_val = 0;
  106. u32 reg = 0, reg_bp = 0;
  107. u16 reg_cu = 0;
  108. bool locked = false;
  109. /*
  110. * Validate the requested mode. Strict IEEE mode does not allow
  111. * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
  112. */
  113. if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
  114. hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
  115. return IXGBE_ERR_INVALID_LINK_SETTINGS;
  116. }
  117. /*
  118. * 10gig parts do not have a word in the EEPROM to determine the
  119. * default flow control setting, so we explicitly set it to full.
  120. */
  121. if (hw->fc.requested_mode == ixgbe_fc_default)
  122. hw->fc.requested_mode = ixgbe_fc_full;
  123. /*
  124. * Set up the 1G and 10G flow control advertisement registers so the
  125. * HW will be able to do fc autoneg once the cable is plugged in. If
  126. * we link at 10G, the 1G advertisement is harmless and vice versa.
  127. */
  128. switch (hw->phy.media_type) {
  129. case ixgbe_media_type_backplane:
  130. /* some MAC's need RMW protection on AUTOC */
  131. ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &reg_bp);
  132. if (ret_val)
  133. return ret_val;
  134. /* fall through - only backplane uses autoc */
  135. case ixgbe_media_type_fiber:
  136. reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
  137. break;
  138. case ixgbe_media_type_copper:
  139. hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
  140. MDIO_MMD_AN, &reg_cu);
  141. break;
  142. default:
  143. break;
  144. }
  145. /*
  146. * The possible values of fc.requested_mode are:
  147. * 0: Flow control is completely disabled
  148. * 1: Rx flow control is enabled (we can receive pause frames,
  149. * but not send pause frames).
  150. * 2: Tx flow control is enabled (we can send pause frames but
  151. * we do not support receiving pause frames).
  152. * 3: Both Rx and Tx flow control (symmetric) are enabled.
  153. * other: Invalid.
  154. */
  155. switch (hw->fc.requested_mode) {
  156. case ixgbe_fc_none:
  157. /* Flow control completely disabled by software override. */
  158. reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
  159. if (hw->phy.media_type == ixgbe_media_type_backplane)
  160. reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
  161. IXGBE_AUTOC_ASM_PAUSE);
  162. else if (hw->phy.media_type == ixgbe_media_type_copper)
  163. reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
  164. break;
  165. case ixgbe_fc_tx_pause:
  166. /*
  167. * Tx Flow control is enabled, and Rx Flow control is
  168. * disabled by software override.
  169. */
  170. reg |= IXGBE_PCS1GANA_ASM_PAUSE;
  171. reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
  172. if (hw->phy.media_type == ixgbe_media_type_backplane) {
  173. reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
  174. reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
  175. } else if (hw->phy.media_type == ixgbe_media_type_copper) {
  176. reg_cu |= IXGBE_TAF_ASM_PAUSE;
  177. reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
  178. }
  179. break;
  180. case ixgbe_fc_rx_pause:
  181. /*
  182. * Rx Flow control is enabled and Tx Flow control is
  183. * disabled by software override. Since there really
  184. * isn't a way to advertise that we are capable of RX
  185. * Pause ONLY, we will advertise that we support both
  186. * symmetric and asymmetric Rx PAUSE, as such we fall
  187. * through to the fc_full statement. Later, we will
  188. * disable the adapter's ability to send PAUSE frames.
  189. */
  190. case ixgbe_fc_full:
  191. /* Flow control (both Rx and Tx) is enabled by SW override. */
  192. reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
  193. if (hw->phy.media_type == ixgbe_media_type_backplane)
  194. reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
  195. IXGBE_AUTOC_ASM_PAUSE;
  196. else if (hw->phy.media_type == ixgbe_media_type_copper)
  197. reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
  198. break;
  199. default:
  200. hw_dbg(hw, "Flow control param set incorrectly\n");
  201. return IXGBE_ERR_CONFIG;
  202. }
  203. if (hw->mac.type != ixgbe_mac_X540) {
  204. /*
  205. * Enable auto-negotiation between the MAC & PHY;
  206. * the MAC will advertise clause 37 flow control.
  207. */
  208. IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
  209. reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
  210. /* Disable AN timeout */
  211. if (hw->fc.strict_ieee)
  212. reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
  213. IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
  214. hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
  215. }
  216. /*
  217. * AUTOC restart handles negotiation of 1G and 10G on backplane
  218. * and copper. There is no need to set the PCS1GCTL register.
  219. *
  220. */
  221. if (hw->phy.media_type == ixgbe_media_type_backplane) {
  222. /* Need the SW/FW semaphore around AUTOC writes if 82599 and
  223. * LESM is on, likewise reset_pipeline requries the lock as
  224. * it also writes AUTOC.
  225. */
  226. ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
  227. if (ret_val)
  228. return ret_val;
  229. } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
  230. ixgbe_device_supports_autoneg_fc(hw)) {
  231. hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
  232. MDIO_MMD_AN, reg_cu);
  233. }
  234. hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
  235. return ret_val;
  236. }
  237. /**
  238. * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
  239. * @hw: pointer to hardware structure
  240. *
  241. * Starts the hardware by filling the bus info structure and media type, clears
  242. * all on chip counters, initializes receive address registers, multicast
  243. * table, VLAN filter table, calls routine to set up link and flow control
  244. * settings, and leaves transmit and receive units disabled and uninitialized
  245. **/
  246. s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
  247. {
  248. s32 ret_val;
  249. u32 ctrl_ext;
  250. u16 device_caps;
  251. /* Set the media type */
  252. hw->phy.media_type = hw->mac.ops.get_media_type(hw);
  253. /* Identify the PHY */
  254. hw->phy.ops.identify(hw);
  255. /* Clear the VLAN filter table */
  256. hw->mac.ops.clear_vfta(hw);
  257. /* Clear statistics registers */
  258. hw->mac.ops.clear_hw_cntrs(hw);
  259. /* Set No Snoop Disable */
  260. ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
  261. ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
  262. IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
  263. IXGBE_WRITE_FLUSH(hw);
  264. /* Setup flow control if method for doing so */
  265. if (hw->mac.ops.setup_fc) {
  266. ret_val = hw->mac.ops.setup_fc(hw);
  267. if (ret_val)
  268. return ret_val;
  269. }
  270. /* Cashe bit indicating need for crosstalk fix */
  271. switch (hw->mac.type) {
  272. case ixgbe_mac_82599EB:
  273. case ixgbe_mac_X550EM_x:
  274. case ixgbe_mac_x550em_a:
  275. hw->mac.ops.get_device_caps(hw, &device_caps);
  276. if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
  277. hw->need_crosstalk_fix = false;
  278. else
  279. hw->need_crosstalk_fix = true;
  280. break;
  281. default:
  282. hw->need_crosstalk_fix = false;
  283. break;
  284. }
  285. /* Clear adapter stopped flag */
  286. hw->adapter_stopped = false;
  287. return 0;
  288. }
  289. /**
  290. * ixgbe_start_hw_gen2 - Init sequence for common device family
  291. * @hw: pointer to hw structure
  292. *
  293. * Performs the init sequence common to the second generation
  294. * of 10 GbE devices.
  295. * Devices in the second generation:
  296. * 82599
  297. * X540
  298. **/
  299. s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
  300. {
  301. u32 i;
  302. /* Clear the rate limiters */
  303. for (i = 0; i < hw->mac.max_tx_queues; i++) {
  304. IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
  305. IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
  306. }
  307. IXGBE_WRITE_FLUSH(hw);
  308. return 0;
  309. }
  310. /**
  311. * ixgbe_init_hw_generic - Generic hardware initialization
  312. * @hw: pointer to hardware structure
  313. *
  314. * Initialize the hardware by resetting the hardware, filling the bus info
  315. * structure and media type, clears all on chip counters, initializes receive
  316. * address registers, multicast table, VLAN filter table, calls routine to set
  317. * up link and flow control settings, and leaves transmit and receive units
  318. * disabled and uninitialized
  319. **/
  320. s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
  321. {
  322. s32 status;
  323. /* Reset the hardware */
  324. status = hw->mac.ops.reset_hw(hw);
  325. if (status == 0) {
  326. /* Start the HW */
  327. status = hw->mac.ops.start_hw(hw);
  328. }
  329. /* Initialize the LED link active for LED blink support */
  330. if (hw->mac.ops.init_led_link_act)
  331. hw->mac.ops.init_led_link_act(hw);
  332. return status;
  333. }
  334. /**
  335. * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
  336. * @hw: pointer to hardware structure
  337. *
  338. * Clears all hardware statistics counters by reading them from the hardware
  339. * Statistics counters are clear on read.
  340. **/
  341. s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
  342. {
  343. u16 i = 0;
  344. IXGBE_READ_REG(hw, IXGBE_CRCERRS);
  345. IXGBE_READ_REG(hw, IXGBE_ILLERRC);
  346. IXGBE_READ_REG(hw, IXGBE_ERRBC);
  347. IXGBE_READ_REG(hw, IXGBE_MSPDC);
  348. for (i = 0; i < 8; i++)
  349. IXGBE_READ_REG(hw, IXGBE_MPC(i));
  350. IXGBE_READ_REG(hw, IXGBE_MLFC);
  351. IXGBE_READ_REG(hw, IXGBE_MRFC);
  352. IXGBE_READ_REG(hw, IXGBE_RLEC);
  353. IXGBE_READ_REG(hw, IXGBE_LXONTXC);
  354. IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
  355. if (hw->mac.type >= ixgbe_mac_82599EB) {
  356. IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
  357. IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
  358. } else {
  359. IXGBE_READ_REG(hw, IXGBE_LXONRXC);
  360. IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
  361. }
  362. for (i = 0; i < 8; i++) {
  363. IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
  364. IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
  365. if (hw->mac.type >= ixgbe_mac_82599EB) {
  366. IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
  367. IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
  368. } else {
  369. IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
  370. IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
  371. }
  372. }
  373. if (hw->mac.type >= ixgbe_mac_82599EB)
  374. for (i = 0; i < 8; i++)
  375. IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
  376. IXGBE_READ_REG(hw, IXGBE_PRC64);
  377. IXGBE_READ_REG(hw, IXGBE_PRC127);
  378. IXGBE_READ_REG(hw, IXGBE_PRC255);
  379. IXGBE_READ_REG(hw, IXGBE_PRC511);
  380. IXGBE_READ_REG(hw, IXGBE_PRC1023);
  381. IXGBE_READ_REG(hw, IXGBE_PRC1522);
  382. IXGBE_READ_REG(hw, IXGBE_GPRC);
  383. IXGBE_READ_REG(hw, IXGBE_BPRC);
  384. IXGBE_READ_REG(hw, IXGBE_MPRC);
  385. IXGBE_READ_REG(hw, IXGBE_GPTC);
  386. IXGBE_READ_REG(hw, IXGBE_GORCL);
  387. IXGBE_READ_REG(hw, IXGBE_GORCH);
  388. IXGBE_READ_REG(hw, IXGBE_GOTCL);
  389. IXGBE_READ_REG(hw, IXGBE_GOTCH);
  390. if (hw->mac.type == ixgbe_mac_82598EB)
  391. for (i = 0; i < 8; i++)
  392. IXGBE_READ_REG(hw, IXGBE_RNBC(i));
  393. IXGBE_READ_REG(hw, IXGBE_RUC);
  394. IXGBE_READ_REG(hw, IXGBE_RFC);
  395. IXGBE_READ_REG(hw, IXGBE_ROC);
  396. IXGBE_READ_REG(hw, IXGBE_RJC);
  397. IXGBE_READ_REG(hw, IXGBE_MNGPRC);
  398. IXGBE_READ_REG(hw, IXGBE_MNGPDC);
  399. IXGBE_READ_REG(hw, IXGBE_MNGPTC);
  400. IXGBE_READ_REG(hw, IXGBE_TORL);
  401. IXGBE_READ_REG(hw, IXGBE_TORH);
  402. IXGBE_READ_REG(hw, IXGBE_TPR);
  403. IXGBE_READ_REG(hw, IXGBE_TPT);
  404. IXGBE_READ_REG(hw, IXGBE_PTC64);
  405. IXGBE_READ_REG(hw, IXGBE_PTC127);
  406. IXGBE_READ_REG(hw, IXGBE_PTC255);
  407. IXGBE_READ_REG(hw, IXGBE_PTC511);
  408. IXGBE_READ_REG(hw, IXGBE_PTC1023);
  409. IXGBE_READ_REG(hw, IXGBE_PTC1522);
  410. IXGBE_READ_REG(hw, IXGBE_MPTC);
  411. IXGBE_READ_REG(hw, IXGBE_BPTC);
  412. for (i = 0; i < 16; i++) {
  413. IXGBE_READ_REG(hw, IXGBE_QPRC(i));
  414. IXGBE_READ_REG(hw, IXGBE_QPTC(i));
  415. if (hw->mac.type >= ixgbe_mac_82599EB) {
  416. IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
  417. IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
  418. IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
  419. IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
  420. IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
  421. } else {
  422. IXGBE_READ_REG(hw, IXGBE_QBRC(i));
  423. IXGBE_READ_REG(hw, IXGBE_QBTC(i));
  424. }
  425. }
  426. if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
  427. if (hw->phy.id == 0)
  428. hw->phy.ops.identify(hw);
  429. hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i);
  430. hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i);
  431. hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i);
  432. hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i);
  433. }
  434. return 0;
  435. }
  436. /**
  437. * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
  438. * @hw: pointer to hardware structure
  439. * @pba_num: stores the part number string from the EEPROM
  440. * @pba_num_size: part number string buffer length
  441. *
  442. * Reads the part number string from the EEPROM.
  443. **/
  444. s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
  445. u32 pba_num_size)
  446. {
  447. s32 ret_val;
  448. u16 data;
  449. u16 pba_ptr;
  450. u16 offset;
  451. u16 length;
  452. if (pba_num == NULL) {
  453. hw_dbg(hw, "PBA string buffer was null\n");
  454. return IXGBE_ERR_INVALID_ARGUMENT;
  455. }
  456. ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
  457. if (ret_val) {
  458. hw_dbg(hw, "NVM Read Error\n");
  459. return ret_val;
  460. }
  461. ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
  462. if (ret_val) {
  463. hw_dbg(hw, "NVM Read Error\n");
  464. return ret_val;
  465. }
  466. /*
  467. * if data is not ptr guard the PBA must be in legacy format which
  468. * means pba_ptr is actually our second data word for the PBA number
  469. * and we can decode it into an ascii string
  470. */
  471. if (data != IXGBE_PBANUM_PTR_GUARD) {
  472. hw_dbg(hw, "NVM PBA number is not stored as string\n");
  473. /* we will need 11 characters to store the PBA */
  474. if (pba_num_size < 11) {
  475. hw_dbg(hw, "PBA string buffer too small\n");
  476. return IXGBE_ERR_NO_SPACE;
  477. }
  478. /* extract hex string from data and pba_ptr */
  479. pba_num[0] = (data >> 12) & 0xF;
  480. pba_num[1] = (data >> 8) & 0xF;
  481. pba_num[2] = (data >> 4) & 0xF;
  482. pba_num[3] = data & 0xF;
  483. pba_num[4] = (pba_ptr >> 12) & 0xF;
  484. pba_num[5] = (pba_ptr >> 8) & 0xF;
  485. pba_num[6] = '-';
  486. pba_num[7] = 0;
  487. pba_num[8] = (pba_ptr >> 4) & 0xF;
  488. pba_num[9] = pba_ptr & 0xF;
  489. /* put a null character on the end of our string */
  490. pba_num[10] = '\0';
  491. /* switch all the data but the '-' to hex char */
  492. for (offset = 0; offset < 10; offset++) {
  493. if (pba_num[offset] < 0xA)
  494. pba_num[offset] += '0';
  495. else if (pba_num[offset] < 0x10)
  496. pba_num[offset] += 'A' - 0xA;
  497. }
  498. return 0;
  499. }
  500. ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
  501. if (ret_val) {
  502. hw_dbg(hw, "NVM Read Error\n");
  503. return ret_val;
  504. }
  505. if (length == 0xFFFF || length == 0) {
  506. hw_dbg(hw, "NVM PBA number section invalid length\n");
  507. return IXGBE_ERR_PBA_SECTION;
  508. }
  509. /* check if pba_num buffer is big enough */
  510. if (pba_num_size < (((u32)length * 2) - 1)) {
  511. hw_dbg(hw, "PBA string buffer too small\n");
  512. return IXGBE_ERR_NO_SPACE;
  513. }
  514. /* trim pba length from start of string */
  515. pba_ptr++;
  516. length--;
  517. for (offset = 0; offset < length; offset++) {
  518. ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
  519. if (ret_val) {
  520. hw_dbg(hw, "NVM Read Error\n");
  521. return ret_val;
  522. }
  523. pba_num[offset * 2] = (u8)(data >> 8);
  524. pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
  525. }
  526. pba_num[offset * 2] = '\0';
  527. return 0;
  528. }
  529. /**
  530. * ixgbe_get_mac_addr_generic - Generic get MAC address
  531. * @hw: pointer to hardware structure
  532. * @mac_addr: Adapter MAC address
  533. *
  534. * Reads the adapter's MAC address from first Receive Address Register (RAR0)
  535. * A reset of the adapter must be performed prior to calling this function
  536. * in order for the MAC address to have been loaded from the EEPROM into RAR0
  537. **/
  538. s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
  539. {
  540. u32 rar_high;
  541. u32 rar_low;
  542. u16 i;
  543. rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
  544. rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
  545. for (i = 0; i < 4; i++)
  546. mac_addr[i] = (u8)(rar_low >> (i*8));
  547. for (i = 0; i < 2; i++)
  548. mac_addr[i+4] = (u8)(rar_high >> (i*8));
  549. return 0;
  550. }
  551. enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status)
  552. {
  553. switch (link_status & IXGBE_PCI_LINK_WIDTH) {
  554. case IXGBE_PCI_LINK_WIDTH_1:
  555. return ixgbe_bus_width_pcie_x1;
  556. case IXGBE_PCI_LINK_WIDTH_2:
  557. return ixgbe_bus_width_pcie_x2;
  558. case IXGBE_PCI_LINK_WIDTH_4:
  559. return ixgbe_bus_width_pcie_x4;
  560. case IXGBE_PCI_LINK_WIDTH_8:
  561. return ixgbe_bus_width_pcie_x8;
  562. default:
  563. return ixgbe_bus_width_unknown;
  564. }
  565. }
  566. enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status)
  567. {
  568. switch (link_status & IXGBE_PCI_LINK_SPEED) {
  569. case IXGBE_PCI_LINK_SPEED_2500:
  570. return ixgbe_bus_speed_2500;
  571. case IXGBE_PCI_LINK_SPEED_5000:
  572. return ixgbe_bus_speed_5000;
  573. case IXGBE_PCI_LINK_SPEED_8000:
  574. return ixgbe_bus_speed_8000;
  575. default:
  576. return ixgbe_bus_speed_unknown;
  577. }
  578. }
  579. /**
  580. * ixgbe_get_bus_info_generic - Generic set PCI bus info
  581. * @hw: pointer to hardware structure
  582. *
  583. * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
  584. **/
  585. s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
  586. {
  587. u16 link_status;
  588. hw->bus.type = ixgbe_bus_type_pci_express;
  589. /* Get the negotiated link width and speed from PCI config space */
  590. link_status = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_LINK_STATUS);
  591. hw->bus.width = ixgbe_convert_bus_width(link_status);
  592. hw->bus.speed = ixgbe_convert_bus_speed(link_status);
  593. hw->mac.ops.set_lan_id(hw);
  594. return 0;
  595. }
  596. /**
  597. * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
  598. * @hw: pointer to the HW structure
  599. *
  600. * Determines the LAN function id by reading memory-mapped registers
  601. * and swaps the port value if requested.
  602. **/
  603. void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
  604. {
  605. struct ixgbe_bus_info *bus = &hw->bus;
  606. u16 ee_ctrl_4;
  607. u32 reg;
  608. reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
  609. bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
  610. bus->lan_id = bus->func;
  611. /* check for a port swap */
  612. reg = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw));
  613. if (reg & IXGBE_FACTPS_LFS)
  614. bus->func ^= 0x1;
  615. /* Get MAC instance from EEPROM for configuring CS4227 */
  616. if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) {
  617. hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4);
  618. bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >>
  619. IXGBE_EE_CTRL_4_INST_ID_SHIFT;
  620. }
  621. }
  622. /**
  623. * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
  624. * @hw: pointer to hardware structure
  625. *
  626. * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
  627. * disables transmit and receive units. The adapter_stopped flag is used by
  628. * the shared code and drivers to determine if the adapter is in a stopped
  629. * state and should not touch the hardware.
  630. **/
  631. s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
  632. {
  633. u32 reg_val;
  634. u16 i;
  635. /*
  636. * Set the adapter_stopped flag so other driver functions stop touching
  637. * the hardware
  638. */
  639. hw->adapter_stopped = true;
  640. /* Disable the receive unit */
  641. hw->mac.ops.disable_rx(hw);
  642. /* Clear interrupt mask to stop interrupts from being generated */
  643. IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
  644. /* Clear any pending interrupts, flush previous writes */
  645. IXGBE_READ_REG(hw, IXGBE_EICR);
  646. /* Disable the transmit unit. Each queue must be disabled. */
  647. for (i = 0; i < hw->mac.max_tx_queues; i++)
  648. IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
  649. /* Disable the receive unit by stopping each queue */
  650. for (i = 0; i < hw->mac.max_rx_queues; i++) {
  651. reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
  652. reg_val &= ~IXGBE_RXDCTL_ENABLE;
  653. reg_val |= IXGBE_RXDCTL_SWFLSH;
  654. IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
  655. }
  656. /* flush all queues disables */
  657. IXGBE_WRITE_FLUSH(hw);
  658. usleep_range(1000, 2000);
  659. /*
  660. * Prevent the PCI-E bus from from hanging by disabling PCI-E master
  661. * access and verify no pending requests
  662. */
  663. return ixgbe_disable_pcie_master(hw);
  664. }
  665. /**
  666. * ixgbe_init_led_link_act_generic - Store the LED index link/activity.
  667. * @hw: pointer to hardware structure
  668. *
  669. * Store the index for the link active LED. This will be used to support
  670. * blinking the LED.
  671. **/
  672. s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw)
  673. {
  674. struct ixgbe_mac_info *mac = &hw->mac;
  675. u32 led_reg, led_mode;
  676. u16 i;
  677. led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
  678. /* Get LED link active from the LEDCTL register */
  679. for (i = 0; i < 4; i++) {
  680. led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i);
  681. if ((led_mode & IXGBE_LED_MODE_MASK_BASE) ==
  682. IXGBE_LED_LINK_ACTIVE) {
  683. mac->led_link_act = i;
  684. return 0;
  685. }
  686. }
  687. /* If LEDCTL register does not have the LED link active set, then use
  688. * known MAC defaults.
  689. */
  690. switch (hw->mac.type) {
  691. case ixgbe_mac_x550em_a:
  692. mac->led_link_act = 0;
  693. break;
  694. case ixgbe_mac_X550EM_x:
  695. mac->led_link_act = 1;
  696. break;
  697. default:
  698. mac->led_link_act = 2;
  699. }
  700. return 0;
  701. }
  702. /**
  703. * ixgbe_led_on_generic - Turns on the software controllable LEDs.
  704. * @hw: pointer to hardware structure
  705. * @index: led number to turn on
  706. **/
  707. s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
  708. {
  709. u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
  710. if (index > 3)
  711. return IXGBE_ERR_PARAM;
  712. /* To turn on the LED, set mode to ON. */
  713. led_reg &= ~IXGBE_LED_MODE_MASK(index);
  714. led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
  715. IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
  716. IXGBE_WRITE_FLUSH(hw);
  717. return 0;
  718. }
  719. /**
  720. * ixgbe_led_off_generic - Turns off the software controllable LEDs.
  721. * @hw: pointer to hardware structure
  722. * @index: led number to turn off
  723. **/
  724. s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
  725. {
  726. u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
  727. if (index > 3)
  728. return IXGBE_ERR_PARAM;
  729. /* To turn off the LED, set mode to OFF. */
  730. led_reg &= ~IXGBE_LED_MODE_MASK(index);
  731. led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
  732. IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
  733. IXGBE_WRITE_FLUSH(hw);
  734. return 0;
  735. }
  736. /**
  737. * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
  738. * @hw: pointer to hardware structure
  739. *
  740. * Initializes the EEPROM parameters ixgbe_eeprom_info within the
  741. * ixgbe_hw struct in order to set up EEPROM access.
  742. **/
  743. s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
  744. {
  745. struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  746. u32 eec;
  747. u16 eeprom_size;
  748. if (eeprom->type == ixgbe_eeprom_uninitialized) {
  749. eeprom->type = ixgbe_eeprom_none;
  750. /* Set default semaphore delay to 10ms which is a well
  751. * tested value */
  752. eeprom->semaphore_delay = 10;
  753. /* Clear EEPROM page size, it will be initialized as needed */
  754. eeprom->word_page_size = 0;
  755. /*
  756. * Check for EEPROM present first.
  757. * If not present leave as none
  758. */
  759. eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
  760. if (eec & IXGBE_EEC_PRES) {
  761. eeprom->type = ixgbe_eeprom_spi;
  762. /*
  763. * SPI EEPROM is assumed here. This code would need to
  764. * change if a future EEPROM is not SPI.
  765. */
  766. eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
  767. IXGBE_EEC_SIZE_SHIFT);
  768. eeprom->word_size = BIT(eeprom_size +
  769. IXGBE_EEPROM_WORD_SIZE_SHIFT);
  770. }
  771. if (eec & IXGBE_EEC_ADDR_SIZE)
  772. eeprom->address_bits = 16;
  773. else
  774. eeprom->address_bits = 8;
  775. hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: %d\n",
  776. eeprom->type, eeprom->word_size, eeprom->address_bits);
  777. }
  778. return 0;
  779. }
  780. /**
  781. * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
  782. * @hw: pointer to hardware structure
  783. * @offset: offset within the EEPROM to write
  784. * @words: number of words
  785. * @data: 16 bit word(s) to write to EEPROM
  786. *
  787. * Reads 16 bit word(s) from EEPROM through bit-bang method
  788. **/
  789. s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
  790. u16 words, u16 *data)
  791. {
  792. s32 status;
  793. u16 i, count;
  794. hw->eeprom.ops.init_params(hw);
  795. if (words == 0)
  796. return IXGBE_ERR_INVALID_ARGUMENT;
  797. if (offset + words > hw->eeprom.word_size)
  798. return IXGBE_ERR_EEPROM;
  799. /*
  800. * The EEPROM page size cannot be queried from the chip. We do lazy
  801. * initialization. It is worth to do that when we write large buffer.
  802. */
  803. if ((hw->eeprom.word_page_size == 0) &&
  804. (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
  805. ixgbe_detect_eeprom_page_size_generic(hw, offset);
  806. /*
  807. * We cannot hold synchronization semaphores for too long
  808. * to avoid other entity starvation. However it is more efficient
  809. * to read in bursts than synchronizing access for each word.
  810. */
  811. for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
  812. count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
  813. IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
  814. status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
  815. count, &data[i]);
  816. if (status != 0)
  817. break;
  818. }
  819. return status;
  820. }
  821. /**
  822. * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
  823. * @hw: pointer to hardware structure
  824. * @offset: offset within the EEPROM to be written to
  825. * @words: number of word(s)
  826. * @data: 16 bit word(s) to be written to the EEPROM
  827. *
  828. * If ixgbe_eeprom_update_checksum is not called after this function, the
  829. * EEPROM will most likely contain an invalid checksum.
  830. **/
  831. static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
  832. u16 words, u16 *data)
  833. {
  834. s32 status;
  835. u16 word;
  836. u16 page_size;
  837. u16 i;
  838. u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
  839. /* Prepare the EEPROM for writing */
  840. status = ixgbe_acquire_eeprom(hw);
  841. if (status)
  842. return status;
  843. if (ixgbe_ready_eeprom(hw) != 0) {
  844. ixgbe_release_eeprom(hw);
  845. return IXGBE_ERR_EEPROM;
  846. }
  847. for (i = 0; i < words; i++) {
  848. ixgbe_standby_eeprom(hw);
  849. /* Send the WRITE ENABLE command (8 bit opcode) */
  850. ixgbe_shift_out_eeprom_bits(hw,
  851. IXGBE_EEPROM_WREN_OPCODE_SPI,
  852. IXGBE_EEPROM_OPCODE_BITS);
  853. ixgbe_standby_eeprom(hw);
  854. /* Some SPI eeproms use the 8th address bit embedded
  855. * in the opcode
  856. */
  857. if ((hw->eeprom.address_bits == 8) &&
  858. ((offset + i) >= 128))
  859. write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
  860. /* Send the Write command (8-bit opcode + addr) */
  861. ixgbe_shift_out_eeprom_bits(hw, write_opcode,
  862. IXGBE_EEPROM_OPCODE_BITS);
  863. ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
  864. hw->eeprom.address_bits);
  865. page_size = hw->eeprom.word_page_size;
  866. /* Send the data in burst via SPI */
  867. do {
  868. word = data[i];
  869. word = (word >> 8) | (word << 8);
  870. ixgbe_shift_out_eeprom_bits(hw, word, 16);
  871. if (page_size == 0)
  872. break;
  873. /* do not wrap around page */
  874. if (((offset + i) & (page_size - 1)) ==
  875. (page_size - 1))
  876. break;
  877. } while (++i < words);
  878. ixgbe_standby_eeprom(hw);
  879. usleep_range(10000, 20000);
  880. }
  881. /* Done with writing - release the EEPROM */
  882. ixgbe_release_eeprom(hw);
  883. return 0;
  884. }
  885. /**
  886. * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
  887. * @hw: pointer to hardware structure
  888. * @offset: offset within the EEPROM to be written to
  889. * @data: 16 bit word to be written to the EEPROM
  890. *
  891. * If ixgbe_eeprom_update_checksum is not called after this function, the
  892. * EEPROM will most likely contain an invalid checksum.
  893. **/
  894. s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
  895. {
  896. hw->eeprom.ops.init_params(hw);
  897. if (offset >= hw->eeprom.word_size)
  898. return IXGBE_ERR_EEPROM;
  899. return ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
  900. }
  901. /**
  902. * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
  903. * @hw: pointer to hardware structure
  904. * @offset: offset within the EEPROM to be read
  905. * @words: number of word(s)
  906. * @data: read 16 bit words(s) from EEPROM
  907. *
  908. * Reads 16 bit word(s) from EEPROM through bit-bang method
  909. **/
  910. s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
  911. u16 words, u16 *data)
  912. {
  913. s32 status;
  914. u16 i, count;
  915. hw->eeprom.ops.init_params(hw);
  916. if (words == 0)
  917. return IXGBE_ERR_INVALID_ARGUMENT;
  918. if (offset + words > hw->eeprom.word_size)
  919. return IXGBE_ERR_EEPROM;
  920. /*
  921. * We cannot hold synchronization semaphores for too long
  922. * to avoid other entity starvation. However it is more efficient
  923. * to read in bursts than synchronizing access for each word.
  924. */
  925. for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
  926. count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
  927. IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
  928. status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
  929. count, &data[i]);
  930. if (status)
  931. return status;
  932. }
  933. return 0;
  934. }
  935. /**
  936. * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
  937. * @hw: pointer to hardware structure
  938. * @offset: offset within the EEPROM to be read
  939. * @words: number of word(s)
  940. * @data: read 16 bit word(s) from EEPROM
  941. *
  942. * Reads 16 bit word(s) from EEPROM through bit-bang method
  943. **/
  944. static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
  945. u16 words, u16 *data)
  946. {
  947. s32 status;
  948. u16 word_in;
  949. u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
  950. u16 i;
  951. /* Prepare the EEPROM for reading */
  952. status = ixgbe_acquire_eeprom(hw);
  953. if (status)
  954. return status;
  955. if (ixgbe_ready_eeprom(hw) != 0) {
  956. ixgbe_release_eeprom(hw);
  957. return IXGBE_ERR_EEPROM;
  958. }
  959. for (i = 0; i < words; i++) {
  960. ixgbe_standby_eeprom(hw);
  961. /* Some SPI eeproms use the 8th address bit embedded
  962. * in the opcode
  963. */
  964. if ((hw->eeprom.address_bits == 8) &&
  965. ((offset + i) >= 128))
  966. read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
  967. /* Send the READ command (opcode + addr) */
  968. ixgbe_shift_out_eeprom_bits(hw, read_opcode,
  969. IXGBE_EEPROM_OPCODE_BITS);
  970. ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
  971. hw->eeprom.address_bits);
  972. /* Read the data. */
  973. word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
  974. data[i] = (word_in >> 8) | (word_in << 8);
  975. }
  976. /* End this read operation */
  977. ixgbe_release_eeprom(hw);
  978. return 0;
  979. }
  980. /**
  981. * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
  982. * @hw: pointer to hardware structure
  983. * @offset: offset within the EEPROM to be read
  984. * @data: read 16 bit value from EEPROM
  985. *
  986. * Reads 16 bit value from EEPROM through bit-bang method
  987. **/
  988. s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
  989. u16 *data)
  990. {
  991. hw->eeprom.ops.init_params(hw);
  992. if (offset >= hw->eeprom.word_size)
  993. return IXGBE_ERR_EEPROM;
  994. return ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
  995. }
  996. /**
  997. * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
  998. * @hw: pointer to hardware structure
  999. * @offset: offset of word in the EEPROM to read
  1000. * @words: number of word(s)
  1001. * @data: 16 bit word(s) from the EEPROM
  1002. *
  1003. * Reads a 16 bit word(s) from the EEPROM using the EERD register.
  1004. **/
  1005. s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
  1006. u16 words, u16 *data)
  1007. {
  1008. u32 eerd;
  1009. s32 status;
  1010. u32 i;
  1011. hw->eeprom.ops.init_params(hw);
  1012. if (words == 0)
  1013. return IXGBE_ERR_INVALID_ARGUMENT;
  1014. if (offset >= hw->eeprom.word_size)
  1015. return IXGBE_ERR_EEPROM;
  1016. for (i = 0; i < words; i++) {
  1017. eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
  1018. IXGBE_EEPROM_RW_REG_START;
  1019. IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
  1020. status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
  1021. if (status == 0) {
  1022. data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
  1023. IXGBE_EEPROM_RW_REG_DATA);
  1024. } else {
  1025. hw_dbg(hw, "Eeprom read timed out\n");
  1026. return status;
  1027. }
  1028. }
  1029. return 0;
  1030. }
  1031. /**
  1032. * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
  1033. * @hw: pointer to hardware structure
  1034. * @offset: offset within the EEPROM to be used as a scratch pad
  1035. *
  1036. * Discover EEPROM page size by writing marching data at given offset.
  1037. * This function is called only when we are writing a new large buffer
  1038. * at given offset so the data would be overwritten anyway.
  1039. **/
  1040. static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
  1041. u16 offset)
  1042. {
  1043. u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
  1044. s32 status;
  1045. u16 i;
  1046. for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
  1047. data[i] = i;
  1048. hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
  1049. status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
  1050. IXGBE_EEPROM_PAGE_SIZE_MAX, data);
  1051. hw->eeprom.word_page_size = 0;
  1052. if (status)
  1053. return status;
  1054. status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
  1055. if (status)
  1056. return status;
  1057. /*
  1058. * When writing in burst more than the actual page size
  1059. * EEPROM address wraps around current page.
  1060. */
  1061. hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
  1062. hw_dbg(hw, "Detected EEPROM page size = %d words.\n",
  1063. hw->eeprom.word_page_size);
  1064. return 0;
  1065. }
  1066. /**
  1067. * ixgbe_read_eerd_generic - Read EEPROM word using EERD
  1068. * @hw: pointer to hardware structure
  1069. * @offset: offset of word in the EEPROM to read
  1070. * @data: word read from the EEPROM
  1071. *
  1072. * Reads a 16 bit word from the EEPROM using the EERD register.
  1073. **/
  1074. s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
  1075. {
  1076. return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
  1077. }
  1078. /**
  1079. * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
  1080. * @hw: pointer to hardware structure
  1081. * @offset: offset of word in the EEPROM to write
  1082. * @words: number of words
  1083. * @data: word(s) write to the EEPROM
  1084. *
  1085. * Write a 16 bit word(s) to the EEPROM using the EEWR register.
  1086. **/
  1087. s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
  1088. u16 words, u16 *data)
  1089. {
  1090. u32 eewr;
  1091. s32 status;
  1092. u16 i;
  1093. hw->eeprom.ops.init_params(hw);
  1094. if (words == 0)
  1095. return IXGBE_ERR_INVALID_ARGUMENT;
  1096. if (offset >= hw->eeprom.word_size)
  1097. return IXGBE_ERR_EEPROM;
  1098. for (i = 0; i < words; i++) {
  1099. eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
  1100. (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
  1101. IXGBE_EEPROM_RW_REG_START;
  1102. status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
  1103. if (status) {
  1104. hw_dbg(hw, "Eeprom write EEWR timed out\n");
  1105. return status;
  1106. }
  1107. IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
  1108. status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
  1109. if (status) {
  1110. hw_dbg(hw, "Eeprom write EEWR timed out\n");
  1111. return status;
  1112. }
  1113. }
  1114. return 0;
  1115. }
  1116. /**
  1117. * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
  1118. * @hw: pointer to hardware structure
  1119. * @offset: offset of word in the EEPROM to write
  1120. * @data: word write to the EEPROM
  1121. *
  1122. * Write a 16 bit word to the EEPROM using the EEWR register.
  1123. **/
  1124. s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
  1125. {
  1126. return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
  1127. }
  1128. /**
  1129. * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
  1130. * @hw: pointer to hardware structure
  1131. * @ee_reg: EEPROM flag for polling
  1132. *
  1133. * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
  1134. * read or write is done respectively.
  1135. **/
  1136. static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
  1137. {
  1138. u32 i;
  1139. u32 reg;
  1140. for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
  1141. if (ee_reg == IXGBE_NVM_POLL_READ)
  1142. reg = IXGBE_READ_REG(hw, IXGBE_EERD);
  1143. else
  1144. reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
  1145. if (reg & IXGBE_EEPROM_RW_REG_DONE) {
  1146. return 0;
  1147. }
  1148. udelay(5);
  1149. }
  1150. return IXGBE_ERR_EEPROM;
  1151. }
  1152. /**
  1153. * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
  1154. * @hw: pointer to hardware structure
  1155. *
  1156. * Prepares EEPROM for access using bit-bang method. This function should
  1157. * be called before issuing a command to the EEPROM.
  1158. **/
  1159. static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
  1160. {
  1161. u32 eec;
  1162. u32 i;
  1163. if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
  1164. return IXGBE_ERR_SWFW_SYNC;
  1165. eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
  1166. /* Request EEPROM Access */
  1167. eec |= IXGBE_EEC_REQ;
  1168. IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
  1169. for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
  1170. eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
  1171. if (eec & IXGBE_EEC_GNT)
  1172. break;
  1173. udelay(5);
  1174. }
  1175. /* Release if grant not acquired */
  1176. if (!(eec & IXGBE_EEC_GNT)) {
  1177. eec &= ~IXGBE_EEC_REQ;
  1178. IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
  1179. hw_dbg(hw, "Could not acquire EEPROM grant\n");
  1180. hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
  1181. return IXGBE_ERR_EEPROM;
  1182. }
  1183. /* Setup EEPROM for Read/Write */
  1184. /* Clear CS and SK */
  1185. eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
  1186. IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
  1187. IXGBE_WRITE_FLUSH(hw);
  1188. udelay(1);
  1189. return 0;
  1190. }
  1191. /**
  1192. * ixgbe_get_eeprom_semaphore - Get hardware semaphore
  1193. * @hw: pointer to hardware structure
  1194. *
  1195. * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
  1196. **/
  1197. static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
  1198. {
  1199. u32 timeout = 2000;
  1200. u32 i;
  1201. u32 swsm;
  1202. /* Get SMBI software semaphore between device drivers first */
  1203. for (i = 0; i < timeout; i++) {
  1204. /*
  1205. * If the SMBI bit is 0 when we read it, then the bit will be
  1206. * set and we have the semaphore
  1207. */
  1208. swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
  1209. if (!(swsm & IXGBE_SWSM_SMBI))
  1210. break;
  1211. usleep_range(50, 100);
  1212. }
  1213. if (i == timeout) {
  1214. hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore not granted.\n");
  1215. /* this release is particularly important because our attempts
  1216. * above to get the semaphore may have succeeded, and if there
  1217. * was a timeout, we should unconditionally clear the semaphore
  1218. * bits to free the driver to make progress
  1219. */
  1220. ixgbe_release_eeprom_semaphore(hw);
  1221. usleep_range(50, 100);
  1222. /* one last try
  1223. * If the SMBI bit is 0 when we read it, then the bit will be
  1224. * set and we have the semaphore
  1225. */
  1226. swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
  1227. if (swsm & IXGBE_SWSM_SMBI) {
  1228. hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n");
  1229. return IXGBE_ERR_EEPROM;
  1230. }
  1231. }
  1232. /* Now get the semaphore between SW/FW through the SWESMBI bit */
  1233. for (i = 0; i < timeout; i++) {
  1234. swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
  1235. /* Set the SW EEPROM semaphore bit to request access */
  1236. swsm |= IXGBE_SWSM_SWESMBI;
  1237. IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);
  1238. /* If we set the bit successfully then we got the
  1239. * semaphore.
  1240. */
  1241. swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
  1242. if (swsm & IXGBE_SWSM_SWESMBI)
  1243. break;
  1244. usleep_range(50, 100);
  1245. }
  1246. /* Release semaphores and return error if SW EEPROM semaphore
  1247. * was not granted because we don't have access to the EEPROM
  1248. */
  1249. if (i >= timeout) {
  1250. hw_dbg(hw, "SWESMBI Software EEPROM semaphore not granted.\n");
  1251. ixgbe_release_eeprom_semaphore(hw);
  1252. return IXGBE_ERR_EEPROM;
  1253. }
  1254. return 0;
  1255. }
  1256. /**
  1257. * ixgbe_release_eeprom_semaphore - Release hardware semaphore
  1258. * @hw: pointer to hardware structure
  1259. *
  1260. * This function clears hardware semaphore bits.
  1261. **/
  1262. static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
  1263. {
  1264. u32 swsm;
  1265. swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
  1266. /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
  1267. swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
  1268. IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);
  1269. IXGBE_WRITE_FLUSH(hw);
  1270. }
  1271. /**
  1272. * ixgbe_ready_eeprom - Polls for EEPROM ready
  1273. * @hw: pointer to hardware structure
  1274. **/
  1275. static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
  1276. {
  1277. u16 i;
  1278. u8 spi_stat_reg;
  1279. /*
  1280. * Read "Status Register" repeatedly until the LSB is cleared. The
  1281. * EEPROM will signal that the command has been completed by clearing
  1282. * bit 0 of the internal status register. If it's not cleared within
  1283. * 5 milliseconds, then error out.
  1284. */
  1285. for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
  1286. ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
  1287. IXGBE_EEPROM_OPCODE_BITS);
  1288. spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
  1289. if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
  1290. break;
  1291. udelay(5);
  1292. ixgbe_standby_eeprom(hw);
  1293. }
  1294. /*
  1295. * On some parts, SPI write time could vary from 0-20mSec on 3.3V
  1296. * devices (and only 0-5mSec on 5V devices)
  1297. */
  1298. if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
  1299. hw_dbg(hw, "SPI EEPROM Status error\n");
  1300. return IXGBE_ERR_EEPROM;
  1301. }
  1302. return 0;
  1303. }
  1304. /**
  1305. * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
  1306. * @hw: pointer to hardware structure
  1307. **/
  1308. static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
  1309. {
  1310. u32 eec;
  1311. eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
  1312. /* Toggle CS to flush commands */
  1313. eec |= IXGBE_EEC_CS;
  1314. IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
  1315. IXGBE_WRITE_FLUSH(hw);
  1316. udelay(1);
  1317. eec &= ~IXGBE_EEC_CS;
  1318. IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
  1319. IXGBE_WRITE_FLUSH(hw);
  1320. udelay(1);
  1321. }
  1322. /**
  1323. * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
  1324. * @hw: pointer to hardware structure
  1325. * @data: data to send to the EEPROM
  1326. * @count: number of bits to shift out
  1327. **/
  1328. static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
  1329. u16 count)
  1330. {
  1331. u32 eec;
  1332. u32 mask;
  1333. u32 i;
  1334. eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
  1335. /*
  1336. * Mask is used to shift "count" bits of "data" out to the EEPROM
  1337. * one bit at a time. Determine the starting bit based on count
  1338. */
  1339. mask = BIT(count - 1);
  1340. for (i = 0; i < count; i++) {
  1341. /*
  1342. * A "1" is shifted out to the EEPROM by setting bit "DI" to a
  1343. * "1", and then raising and then lowering the clock (the SK
  1344. * bit controls the clock input to the EEPROM). A "0" is
  1345. * shifted out to the EEPROM by setting "DI" to "0" and then
  1346. * raising and then lowering the clock.
  1347. */
  1348. if (data & mask)
  1349. eec |= IXGBE_EEC_DI;
  1350. else
  1351. eec &= ~IXGBE_EEC_DI;
  1352. IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
  1353. IXGBE_WRITE_FLUSH(hw);
  1354. udelay(1);
  1355. ixgbe_raise_eeprom_clk(hw, &eec);
  1356. ixgbe_lower_eeprom_clk(hw, &eec);
  1357. /*
  1358. * Shift mask to signify next bit of data to shift in to the
  1359. * EEPROM
  1360. */
  1361. mask = mask >> 1;
  1362. }
  1363. /* We leave the "DI" bit set to "0" when we leave this routine. */
  1364. eec &= ~IXGBE_EEC_DI;
  1365. IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
  1366. IXGBE_WRITE_FLUSH(hw);
  1367. }
  1368. /**
  1369. * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
  1370. * @hw: pointer to hardware structure
  1371. * @count: number of bits to shift
  1372. **/
  1373. static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
  1374. {
  1375. u32 eec;
  1376. u32 i;
  1377. u16 data = 0;
  1378. /*
  1379. * In order to read a register from the EEPROM, we need to shift
  1380. * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
  1381. * the clock input to the EEPROM (setting the SK bit), and then reading
  1382. * the value of the "DO" bit. During this "shifting in" process the
  1383. * "DI" bit should always be clear.
  1384. */
  1385. eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
  1386. eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
  1387. for (i = 0; i < count; i++) {
  1388. data = data << 1;
  1389. ixgbe_raise_eeprom_clk(hw, &eec);
  1390. eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
  1391. eec &= ~(IXGBE_EEC_DI);
  1392. if (eec & IXGBE_EEC_DO)
  1393. data |= 1;
  1394. ixgbe_lower_eeprom_clk(hw, &eec);
  1395. }
  1396. return data;
  1397. }
  1398. /**
  1399. * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
  1400. * @hw: pointer to hardware structure
  1401. * @eec: EEC register's current value
  1402. **/
  1403. static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
  1404. {
  1405. /*
  1406. * Raise the clock input to the EEPROM
  1407. * (setting the SK bit), then delay
  1408. */
  1409. *eec = *eec | IXGBE_EEC_SK;
  1410. IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec);
  1411. IXGBE_WRITE_FLUSH(hw);
  1412. udelay(1);
  1413. }
  1414. /**
  1415. * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
  1416. * @hw: pointer to hardware structure
  1417. * @eec: EEC's current value
  1418. **/
  1419. static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
  1420. {
  1421. /*
  1422. * Lower the clock input to the EEPROM (clearing the SK bit), then
  1423. * delay
  1424. */
  1425. *eec = *eec & ~IXGBE_EEC_SK;
  1426. IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec);
  1427. IXGBE_WRITE_FLUSH(hw);
  1428. udelay(1);
  1429. }
  1430. /**
  1431. * ixgbe_release_eeprom - Release EEPROM, release semaphores
  1432. * @hw: pointer to hardware structure
  1433. **/
  1434. static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
  1435. {
  1436. u32 eec;
  1437. eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
  1438. eec |= IXGBE_EEC_CS; /* Pull CS high */
  1439. eec &= ~IXGBE_EEC_SK; /* Lower SCK */
  1440. IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
  1441. IXGBE_WRITE_FLUSH(hw);
  1442. udelay(1);
  1443. /* Stop requesting EEPROM access */
  1444. eec &= ~IXGBE_EEC_REQ;
  1445. IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
  1446. hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
  1447. /*
  1448. * Delay before attempt to obtain semaphore again to allow FW
  1449. * access. semaphore_delay is in ms we need us for usleep_range
  1450. */
  1451. usleep_range(hw->eeprom.semaphore_delay * 1000,
  1452. hw->eeprom.semaphore_delay * 2000);
  1453. }
  1454. /**
  1455. * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
  1456. * @hw: pointer to hardware structure
  1457. **/
  1458. s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
  1459. {
  1460. u16 i;
  1461. u16 j;
  1462. u16 checksum = 0;
  1463. u16 length = 0;
  1464. u16 pointer = 0;
  1465. u16 word = 0;
  1466. /* Include 0x0-0x3F in the checksum */
  1467. for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
  1468. if (hw->eeprom.ops.read(hw, i, &word)) {
  1469. hw_dbg(hw, "EEPROM read failed\n");
  1470. break;
  1471. }
  1472. checksum += word;
  1473. }
  1474. /* Include all data from pointers except for the fw pointer */
  1475. for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
  1476. if (hw->eeprom.ops.read(hw, i, &pointer)) {
  1477. hw_dbg(hw, "EEPROM read failed\n");
  1478. return IXGBE_ERR_EEPROM;
  1479. }
  1480. /* If the pointer seems invalid */
  1481. if (pointer == 0xFFFF || pointer == 0)
  1482. continue;
  1483. if (hw->eeprom.ops.read(hw, pointer, &length)) {
  1484. hw_dbg(hw, "EEPROM read failed\n");
  1485. return IXGBE_ERR_EEPROM;
  1486. }
  1487. if (length == 0xFFFF || length == 0)
  1488. continue;
  1489. for (j = pointer + 1; j <= pointer + length; j++) {
  1490. if (hw->eeprom.ops.read(hw, j, &word)) {
  1491. hw_dbg(hw, "EEPROM read failed\n");
  1492. return IXGBE_ERR_EEPROM;
  1493. }
  1494. checksum += word;
  1495. }
  1496. }
  1497. checksum = (u16)IXGBE_EEPROM_SUM - checksum;
  1498. return (s32)checksum;
  1499. }
  1500. /**
  1501. * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
  1502. * @hw: pointer to hardware structure
  1503. * @checksum_val: calculated checksum
  1504. *
  1505. * Performs checksum calculation and validates the EEPROM checksum. If the
  1506. * caller does not need checksum_val, the value can be NULL.
  1507. **/
  1508. s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
  1509. u16 *checksum_val)
  1510. {
  1511. s32 status;
  1512. u16 checksum;
  1513. u16 read_checksum = 0;
  1514. /*
  1515. * Read the first word from the EEPROM. If this times out or fails, do
  1516. * not continue or we could be in for a very long wait while every
  1517. * EEPROM read fails
  1518. */
  1519. status = hw->eeprom.ops.read(hw, 0, &checksum);
  1520. if (status) {
  1521. hw_dbg(hw, "EEPROM read failed\n");
  1522. return status;
  1523. }
  1524. status = hw->eeprom.ops.calc_checksum(hw);
  1525. if (status < 0)
  1526. return status;
  1527. checksum = (u16)(status & 0xffff);
  1528. status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
  1529. if (status) {
  1530. hw_dbg(hw, "EEPROM read failed\n");
  1531. return status;
  1532. }
  1533. /* Verify read checksum from EEPROM is the same as
  1534. * calculated checksum
  1535. */
  1536. if (read_checksum != checksum)
  1537. status = IXGBE_ERR_EEPROM_CHECKSUM;
  1538. /* If the user cares, return the calculated checksum */
  1539. if (checksum_val)
  1540. *checksum_val = checksum;
  1541. return status;
  1542. }
  1543. /**
  1544. * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
  1545. * @hw: pointer to hardware structure
  1546. **/
  1547. s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
  1548. {
  1549. s32 status;
  1550. u16 checksum;
  1551. /*
  1552. * Read the first word from the EEPROM. If this times out or fails, do
  1553. * not continue or we could be in for a very long wait while every
  1554. * EEPROM read fails
  1555. */
  1556. status = hw->eeprom.ops.read(hw, 0, &checksum);
  1557. if (status) {
  1558. hw_dbg(hw, "EEPROM read failed\n");
  1559. return status;
  1560. }
  1561. status = hw->eeprom.ops.calc_checksum(hw);
  1562. if (status < 0)
  1563. return status;
  1564. checksum = (u16)(status & 0xffff);
  1565. status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
  1566. return status;
  1567. }
  1568. /**
  1569. * ixgbe_set_rar_generic - Set Rx address register
  1570. * @hw: pointer to hardware structure
  1571. * @index: Receive address register to write
  1572. * @addr: Address to put into receive address register
  1573. * @vmdq: VMDq "set" or "pool" index
  1574. * @enable_addr: set flag that address is active
  1575. *
  1576. * Puts an ethernet address into a receive address register.
  1577. **/
  1578. s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
  1579. u32 enable_addr)
  1580. {
  1581. u32 rar_low, rar_high;
  1582. u32 rar_entries = hw->mac.num_rar_entries;
  1583. /* Make sure we are using a valid rar index range */
  1584. if (index >= rar_entries) {
  1585. hw_dbg(hw, "RAR index %d is out of range.\n", index);
  1586. return IXGBE_ERR_INVALID_ARGUMENT;
  1587. }
  1588. /* setup VMDq pool selection before this RAR gets enabled */
  1589. hw->mac.ops.set_vmdq(hw, index, vmdq);
  1590. /*
  1591. * HW expects these in little endian so we reverse the byte
  1592. * order from network order (big endian) to little endian
  1593. */
  1594. rar_low = ((u32)addr[0] |
  1595. ((u32)addr[1] << 8) |
  1596. ((u32)addr[2] << 16) |
  1597. ((u32)addr[3] << 24));
  1598. /*
  1599. * Some parts put the VMDq setting in the extra RAH bits,
  1600. * so save everything except the lower 16 bits that hold part
  1601. * of the address and the address valid bit.
  1602. */
  1603. rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
  1604. rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
  1605. rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
  1606. if (enable_addr != 0)
  1607. rar_high |= IXGBE_RAH_AV;
  1608. /* Record lower 32 bits of MAC address and then make
  1609. * sure that write is flushed to hardware before writing
  1610. * the upper 16 bits and setting the valid bit.
  1611. */
  1612. IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
  1613. IXGBE_WRITE_FLUSH(hw);
  1614. IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
  1615. return 0;
  1616. }
  1617. /**
  1618. * ixgbe_clear_rar_generic - Remove Rx address register
  1619. * @hw: pointer to hardware structure
  1620. * @index: Receive address register to write
  1621. *
  1622. * Clears an ethernet address from a receive address register.
  1623. **/
  1624. s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
  1625. {
  1626. u32 rar_high;
  1627. u32 rar_entries = hw->mac.num_rar_entries;
  1628. /* Make sure we are using a valid rar index range */
  1629. if (index >= rar_entries) {
  1630. hw_dbg(hw, "RAR index %d is out of range.\n", index);
  1631. return IXGBE_ERR_INVALID_ARGUMENT;
  1632. }
  1633. /*
  1634. * Some parts put the VMDq setting in the extra RAH bits,
  1635. * so save everything except the lower 16 bits that hold part
  1636. * of the address and the address valid bit.
  1637. */
  1638. rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
  1639. rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
  1640. /* Clear the address valid bit and upper 16 bits of the address
  1641. * before clearing the lower bits. This way we aren't updating
  1642. * a live filter.
  1643. */
  1644. IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
  1645. IXGBE_WRITE_FLUSH(hw);
  1646. IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
  1647. /* clear VMDq pool/queue selection for this RAR */
  1648. hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
  1649. return 0;
  1650. }
  1651. /**
  1652. * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
  1653. * @hw: pointer to hardware structure
  1654. *
  1655. * Places the MAC address in receive address register 0 and clears the rest
  1656. * of the receive address registers. Clears the multicast table. Assumes
  1657. * the receiver is in reset when the routine is called.
  1658. **/
  1659. s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
  1660. {
  1661. u32 i;
  1662. u32 rar_entries = hw->mac.num_rar_entries;
  1663. /*
  1664. * If the current mac address is valid, assume it is a software override
  1665. * to the permanent address.
  1666. * Otherwise, use the permanent address from the eeprom.
  1667. */
  1668. if (!is_valid_ether_addr(hw->mac.addr)) {
  1669. /* Get the MAC address from the RAR0 for later reference */
  1670. hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
  1671. hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
  1672. } else {
  1673. /* Setup the receive address. */
  1674. hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
  1675. hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
  1676. hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
  1677. }
  1678. /* clear VMDq pool/queue selection for RAR 0 */
  1679. hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
  1680. hw->addr_ctrl.overflow_promisc = 0;
  1681. hw->addr_ctrl.rar_used_count = 1;
  1682. /* Zero out the other receive addresses. */
  1683. hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
  1684. for (i = 1; i < rar_entries; i++) {
  1685. IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
  1686. IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
  1687. }
  1688. /* Clear the MTA */
  1689. hw->addr_ctrl.mta_in_use = 0;
  1690. IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
  1691. hw_dbg(hw, " Clearing MTA\n");
  1692. for (i = 0; i < hw->mac.mcft_size; i++)
  1693. IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
  1694. if (hw->mac.ops.init_uta_tables)
  1695. hw->mac.ops.init_uta_tables(hw);
  1696. return 0;
  1697. }
  1698. /**
  1699. * ixgbe_mta_vector - Determines bit-vector in multicast table to set
  1700. * @hw: pointer to hardware structure
  1701. * @mc_addr: the multicast address
  1702. *
  1703. * Extracts the 12 bits, from a multicast address, to determine which
  1704. * bit-vector to set in the multicast table. The hardware uses 12 bits, from
  1705. * incoming rx multicast addresses, to determine the bit-vector to check in
  1706. * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
  1707. * by the MO field of the MCSTCTRL. The MO field is set during initialization
  1708. * to mc_filter_type.
  1709. **/
  1710. static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
  1711. {
  1712. u32 vector = 0;
  1713. switch (hw->mac.mc_filter_type) {
  1714. case 0: /* use bits [47:36] of the address */
  1715. vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
  1716. break;
  1717. case 1: /* use bits [46:35] of the address */
  1718. vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
  1719. break;
  1720. case 2: /* use bits [45:34] of the address */
  1721. vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
  1722. break;
  1723. case 3: /* use bits [43:32] of the address */
  1724. vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
  1725. break;
  1726. default: /* Invalid mc_filter_type */
  1727. hw_dbg(hw, "MC filter type param set incorrectly\n");
  1728. break;
  1729. }
  1730. /* vector can only be 12-bits or boundary will be exceeded */
  1731. vector &= 0xFFF;
  1732. return vector;
  1733. }
  1734. /**
  1735. * ixgbe_set_mta - Set bit-vector in multicast table
  1736. * @hw: pointer to hardware structure
  1737. * @mc_addr: Multicast address
  1738. *
  1739. * Sets the bit-vector in the multicast table.
  1740. **/
  1741. static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
  1742. {
  1743. u32 vector;
  1744. u32 vector_bit;
  1745. u32 vector_reg;
  1746. hw->addr_ctrl.mta_in_use++;
  1747. vector = ixgbe_mta_vector(hw, mc_addr);
  1748. hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
  1749. /*
  1750. * The MTA is a register array of 128 32-bit registers. It is treated
  1751. * like an array of 4096 bits. We want to set bit
  1752. * BitArray[vector_value]. So we figure out what register the bit is
  1753. * in, read it, OR in the new bit, then write back the new value. The
  1754. * register is determined by the upper 7 bits of the vector value and
  1755. * the bit within that register are determined by the lower 5 bits of
  1756. * the value.
  1757. */
  1758. vector_reg = (vector >> 5) & 0x7F;
  1759. vector_bit = vector & 0x1F;
  1760. hw->mac.mta_shadow[vector_reg] |= BIT(vector_bit);
  1761. }
  1762. /**
  1763. * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
  1764. * @hw: pointer to hardware structure
  1765. * @netdev: pointer to net device structure
  1766. *
  1767. * The given list replaces any existing list. Clears the MC addrs from receive
  1768. * address registers and the multicast table. Uses unused receive address
  1769. * registers for the first multicast addresses, and hashes the rest into the
  1770. * multicast table.
  1771. **/
  1772. s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
  1773. struct net_device *netdev)
  1774. {
  1775. struct netdev_hw_addr *ha;
  1776. u32 i;
  1777. /*
  1778. * Set the new number of MC addresses that we are being requested to
  1779. * use.
  1780. */
  1781. hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
  1782. hw->addr_ctrl.mta_in_use = 0;
  1783. /* Clear mta_shadow */
  1784. hw_dbg(hw, " Clearing MTA\n");
  1785. memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
  1786. /* Update mta shadow */
  1787. netdev_for_each_mc_addr(ha, netdev) {
  1788. hw_dbg(hw, " Adding the multicast addresses:\n");
  1789. ixgbe_set_mta(hw, ha->addr);
  1790. }
  1791. /* Enable mta */
  1792. for (i = 0; i < hw->mac.mcft_size; i++)
  1793. IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
  1794. hw->mac.mta_shadow[i]);
  1795. if (hw->addr_ctrl.mta_in_use > 0)
  1796. IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
  1797. IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
  1798. hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
  1799. return 0;
  1800. }
  1801. /**
  1802. * ixgbe_enable_mc_generic - Enable multicast address in RAR
  1803. * @hw: pointer to hardware structure
  1804. *
  1805. * Enables multicast address in RAR and the use of the multicast hash table.
  1806. **/
  1807. s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
  1808. {
  1809. struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
  1810. if (a->mta_in_use > 0)
  1811. IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
  1812. hw->mac.mc_filter_type);
  1813. return 0;
  1814. }
  1815. /**
  1816. * ixgbe_disable_mc_generic - Disable multicast address in RAR
  1817. * @hw: pointer to hardware structure
  1818. *
  1819. * Disables multicast address in RAR and the use of the multicast hash table.
  1820. **/
  1821. s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
  1822. {
  1823. struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
  1824. if (a->mta_in_use > 0)
  1825. IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
  1826. return 0;
  1827. }
  1828. /**
  1829. * ixgbe_fc_enable_generic - Enable flow control
  1830. * @hw: pointer to hardware structure
  1831. *
  1832. * Enable flow control according to the current settings.
  1833. **/
  1834. s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
  1835. {
  1836. u32 mflcn_reg, fccfg_reg;
  1837. u32 reg;
  1838. u32 fcrtl, fcrth;
  1839. int i;
  1840. /* Validate the water mark configuration. */
  1841. if (!hw->fc.pause_time)
  1842. return IXGBE_ERR_INVALID_LINK_SETTINGS;
  1843. /* Low water mark of zero causes XOFF floods */
  1844. for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
  1845. if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
  1846. hw->fc.high_water[i]) {
  1847. if (!hw->fc.low_water[i] ||
  1848. hw->fc.low_water[i] >= hw->fc.high_water[i]) {
  1849. hw_dbg(hw, "Invalid water mark configuration\n");
  1850. return IXGBE_ERR_INVALID_LINK_SETTINGS;
  1851. }
  1852. }
  1853. }
  1854. /* Negotiate the fc mode to use */
  1855. hw->mac.ops.fc_autoneg(hw);
  1856. /* Disable any previous flow control settings */
  1857. mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
  1858. mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
  1859. fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
  1860. fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
  1861. /*
  1862. * The possible values of fc.current_mode are:
  1863. * 0: Flow control is completely disabled
  1864. * 1: Rx flow control is enabled (we can receive pause frames,
  1865. * but not send pause frames).
  1866. * 2: Tx flow control is enabled (we can send pause frames but
  1867. * we do not support receiving pause frames).
  1868. * 3: Both Rx and Tx flow control (symmetric) are enabled.
  1869. * other: Invalid.
  1870. */
  1871. switch (hw->fc.current_mode) {
  1872. case ixgbe_fc_none:
  1873. /*
  1874. * Flow control is disabled by software override or autoneg.
  1875. * The code below will actually disable it in the HW.
  1876. */
  1877. break;
  1878. case ixgbe_fc_rx_pause:
  1879. /*
  1880. * Rx Flow control is enabled and Tx Flow control is
  1881. * disabled by software override. Since there really
  1882. * isn't a way to advertise that we are capable of RX
  1883. * Pause ONLY, we will advertise that we support both
  1884. * symmetric and asymmetric Rx PAUSE. Later, we will
  1885. * disable the adapter's ability to send PAUSE frames.
  1886. */
  1887. mflcn_reg |= IXGBE_MFLCN_RFCE;
  1888. break;
  1889. case ixgbe_fc_tx_pause:
  1890. /*
  1891. * Tx Flow control is enabled, and Rx Flow control is
  1892. * disabled by software override.
  1893. */
  1894. fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
  1895. break;
  1896. case ixgbe_fc_full:
  1897. /* Flow control (both Rx and Tx) is enabled by SW override. */
  1898. mflcn_reg |= IXGBE_MFLCN_RFCE;
  1899. fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
  1900. break;
  1901. default:
  1902. hw_dbg(hw, "Flow control param set incorrectly\n");
  1903. return IXGBE_ERR_CONFIG;
  1904. }
  1905. /* Set 802.3x based flow control settings. */
  1906. mflcn_reg |= IXGBE_MFLCN_DPF;
  1907. IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
  1908. IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
  1909. /* Set up and enable Rx high/low water mark thresholds, enable XON. */
  1910. for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
  1911. if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
  1912. hw->fc.high_water[i]) {
  1913. fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
  1914. IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
  1915. fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
  1916. } else {
  1917. IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
  1918. /*
  1919. * In order to prevent Tx hangs when the internal Tx
  1920. * switch is enabled we must set the high water mark
  1921. * to the Rx packet buffer size - 24KB. This allows
  1922. * the Tx switch to function even under heavy Rx
  1923. * workloads.
  1924. */
  1925. fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
  1926. }
  1927. IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
  1928. }
  1929. /* Configure pause time (2 TCs per register) */
  1930. reg = hw->fc.pause_time * 0x00010001;
  1931. for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
  1932. IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
  1933. IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
  1934. return 0;
  1935. }
  1936. /**
  1937. * ixgbe_negotiate_fc - Negotiate flow control
  1938. * @hw: pointer to hardware structure
  1939. * @adv_reg: flow control advertised settings
  1940. * @lp_reg: link partner's flow control settings
  1941. * @adv_sym: symmetric pause bit in advertisement
  1942. * @adv_asm: asymmetric pause bit in advertisement
  1943. * @lp_sym: symmetric pause bit in link partner advertisement
  1944. * @lp_asm: asymmetric pause bit in link partner advertisement
  1945. *
  1946. * Find the intersection between advertised settings and link partner's
  1947. * advertised settings
  1948. **/
  1949. s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
  1950. u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
  1951. {
  1952. if ((!(adv_reg)) || (!(lp_reg)))
  1953. return IXGBE_ERR_FC_NOT_NEGOTIATED;
  1954. if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
  1955. /*
  1956. * Now we need to check if the user selected Rx ONLY
  1957. * of pause frames. In this case, we had to advertise
  1958. * FULL flow control because we could not advertise RX
  1959. * ONLY. Hence, we must now check to see if we need to
  1960. * turn OFF the TRANSMISSION of PAUSE frames.
  1961. */
  1962. if (hw->fc.requested_mode == ixgbe_fc_full) {
  1963. hw->fc.current_mode = ixgbe_fc_full;
  1964. hw_dbg(hw, "Flow Control = FULL.\n");
  1965. } else {
  1966. hw->fc.current_mode = ixgbe_fc_rx_pause;
  1967. hw_dbg(hw, "Flow Control=RX PAUSE frames only\n");
  1968. }
  1969. } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
  1970. (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
  1971. hw->fc.current_mode = ixgbe_fc_tx_pause;
  1972. hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
  1973. } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
  1974. !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
  1975. hw->fc.current_mode = ixgbe_fc_rx_pause;
  1976. hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
  1977. } else {
  1978. hw->fc.current_mode = ixgbe_fc_none;
  1979. hw_dbg(hw, "Flow Control = NONE.\n");
  1980. }
  1981. return 0;
  1982. }
  1983. /**
  1984. * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
  1985. * @hw: pointer to hardware structure
  1986. *
  1987. * Enable flow control according on 1 gig fiber.
  1988. **/
  1989. static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
  1990. {
  1991. u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
  1992. s32 ret_val;
  1993. /*
  1994. * On multispeed fiber at 1g, bail out if
  1995. * - link is up but AN did not complete, or if
  1996. * - link is up and AN completed but timed out
  1997. */
  1998. linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
  1999. if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
  2000. (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
  2001. return IXGBE_ERR_FC_NOT_NEGOTIATED;
  2002. pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
  2003. pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
  2004. ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
  2005. pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
  2006. IXGBE_PCS1GANA_ASM_PAUSE,
  2007. IXGBE_PCS1GANA_SYM_PAUSE,
  2008. IXGBE_PCS1GANA_ASM_PAUSE);
  2009. return ret_val;
  2010. }
  2011. /**
  2012. * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
  2013. * @hw: pointer to hardware structure
  2014. *
  2015. * Enable flow control according to IEEE clause 37.
  2016. **/
  2017. static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
  2018. {
  2019. u32 links2, anlp1_reg, autoc_reg, links;
  2020. s32 ret_val;
  2021. /*
  2022. * On backplane, bail out if
  2023. * - backplane autoneg was not completed, or if
  2024. * - we are 82599 and link partner is not AN enabled
  2025. */
  2026. links = IXGBE_READ_REG(hw, IXGBE_LINKS);
  2027. if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
  2028. return IXGBE_ERR_FC_NOT_NEGOTIATED;
  2029. if (hw->mac.type == ixgbe_mac_82599EB) {
  2030. links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
  2031. if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
  2032. return IXGBE_ERR_FC_NOT_NEGOTIATED;
  2033. }
  2034. /*
  2035. * Read the 10g AN autoc and LP ability registers and resolve
  2036. * local flow control settings accordingly
  2037. */
  2038. autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
  2039. anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
  2040. ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
  2041. anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
  2042. IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
  2043. return ret_val;
  2044. }
  2045. /**
  2046. * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
  2047. * @hw: pointer to hardware structure
  2048. *
  2049. * Enable flow control according to IEEE clause 37.
  2050. **/
  2051. static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
  2052. {
  2053. u16 technology_ability_reg = 0;
  2054. u16 lp_technology_ability_reg = 0;
  2055. hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
  2056. MDIO_MMD_AN,
  2057. &technology_ability_reg);
  2058. hw->phy.ops.read_reg(hw, MDIO_AN_LPA,
  2059. MDIO_MMD_AN,
  2060. &lp_technology_ability_reg);
  2061. return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
  2062. (u32)lp_technology_ability_reg,
  2063. IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
  2064. IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
  2065. }
  2066. /**
  2067. * ixgbe_fc_autoneg - Configure flow control
  2068. * @hw: pointer to hardware structure
  2069. *
  2070. * Compares our advertised flow control capabilities to those advertised by
  2071. * our link partner, and determines the proper flow control mode to use.
  2072. **/
  2073. void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
  2074. {
  2075. s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
  2076. ixgbe_link_speed speed;
  2077. bool link_up;
  2078. /*
  2079. * AN should have completed when the cable was plugged in.
  2080. * Look for reasons to bail out. Bail out if:
  2081. * - FC autoneg is disabled, or if
  2082. * - link is not up.
  2083. *
  2084. * Since we're being called from an LSC, link is already known to be up.
  2085. * So use link_up_wait_to_complete=false.
  2086. */
  2087. if (hw->fc.disable_fc_autoneg)
  2088. goto out;
  2089. hw->mac.ops.check_link(hw, &speed, &link_up, false);
  2090. if (!link_up)
  2091. goto out;
  2092. switch (hw->phy.media_type) {
  2093. /* Autoneg flow control on fiber adapters */
  2094. case ixgbe_media_type_fiber:
  2095. if (speed == IXGBE_LINK_SPEED_1GB_FULL)
  2096. ret_val = ixgbe_fc_autoneg_fiber(hw);
  2097. break;
  2098. /* Autoneg flow control on backplane adapters */
  2099. case ixgbe_media_type_backplane:
  2100. ret_val = ixgbe_fc_autoneg_backplane(hw);
  2101. break;
  2102. /* Autoneg flow control on copper adapters */
  2103. case ixgbe_media_type_copper:
  2104. if (ixgbe_device_supports_autoneg_fc(hw))
  2105. ret_val = ixgbe_fc_autoneg_copper(hw);
  2106. break;
  2107. default:
  2108. break;
  2109. }
  2110. out:
  2111. if (ret_val == 0) {
  2112. hw->fc.fc_was_autonegged = true;
  2113. } else {
  2114. hw->fc.fc_was_autonegged = false;
  2115. hw->fc.current_mode = hw->fc.requested_mode;
  2116. }
  2117. }
  2118. /**
  2119. * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
  2120. * @hw: pointer to hardware structure
  2121. *
  2122. * System-wide timeout range is encoded in PCIe Device Control2 register.
  2123. *
  2124. * Add 10% to specified maximum and return the number of times to poll for
  2125. * completion timeout, in units of 100 microsec. Never return less than
  2126. * 800 = 80 millisec.
  2127. **/
  2128. static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
  2129. {
  2130. s16 devctl2;
  2131. u32 pollcnt;
  2132. devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2);
  2133. devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
  2134. switch (devctl2) {
  2135. case IXGBE_PCIDEVCTRL2_65_130ms:
  2136. pollcnt = 1300; /* 130 millisec */
  2137. break;
  2138. case IXGBE_PCIDEVCTRL2_260_520ms:
  2139. pollcnt = 5200; /* 520 millisec */
  2140. break;
  2141. case IXGBE_PCIDEVCTRL2_1_2s:
  2142. pollcnt = 20000; /* 2 sec */
  2143. break;
  2144. case IXGBE_PCIDEVCTRL2_4_8s:
  2145. pollcnt = 80000; /* 8 sec */
  2146. break;
  2147. case IXGBE_PCIDEVCTRL2_17_34s:
  2148. pollcnt = 34000; /* 34 sec */
  2149. break;
  2150. case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
  2151. case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
  2152. case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
  2153. case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
  2154. default:
  2155. pollcnt = 800; /* 80 millisec minimum */
  2156. break;
  2157. }
  2158. /* add 10% to spec maximum */
  2159. return (pollcnt * 11) / 10;
  2160. }
  2161. /**
  2162. * ixgbe_disable_pcie_master - Disable PCI-express master access
  2163. * @hw: pointer to hardware structure
  2164. *
  2165. * Disables PCI-Express master access and verifies there are no pending
  2166. * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
  2167. * bit hasn't caused the master requests to be disabled, else 0
  2168. * is returned signifying master requests disabled.
  2169. **/
  2170. static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
  2171. {
  2172. u32 i, poll;
  2173. u16 value;
  2174. /* Always set this bit to ensure any future transactions are blocked */
  2175. IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
  2176. /* Poll for bit to read as set */
  2177. for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
  2178. if (IXGBE_READ_REG(hw, IXGBE_CTRL) & IXGBE_CTRL_GIO_DIS)
  2179. break;
  2180. usleep_range(100, 120);
  2181. }
  2182. if (i >= IXGBE_PCI_MASTER_DISABLE_TIMEOUT) {
  2183. hw_dbg(hw, "GIO disable did not set - requesting resets\n");
  2184. goto gio_disable_fail;
  2185. }
  2186. /* Exit if master requests are blocked */
  2187. if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
  2188. ixgbe_removed(hw->hw_addr))
  2189. return 0;
  2190. /* Poll for master request bit to clear */
  2191. for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
  2192. udelay(100);
  2193. if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
  2194. return 0;
  2195. }
  2196. /*
  2197. * Two consecutive resets are required via CTRL.RST per datasheet
  2198. * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
  2199. * of this need. The first reset prevents new master requests from
  2200. * being issued by our device. We then must wait 1usec or more for any
  2201. * remaining completions from the PCIe bus to trickle in, and then reset
  2202. * again to clear out any effects they may have had on our device.
  2203. */
  2204. hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
  2205. gio_disable_fail:
  2206. hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
  2207. if (hw->mac.type >= ixgbe_mac_X550)
  2208. return 0;
  2209. /*
  2210. * Before proceeding, make sure that the PCIe block does not have
  2211. * transactions pending.
  2212. */
  2213. poll = ixgbe_pcie_timeout_poll(hw);
  2214. for (i = 0; i < poll; i++) {
  2215. udelay(100);
  2216. value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS);
  2217. if (ixgbe_removed(hw->hw_addr))
  2218. return 0;
  2219. if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
  2220. return 0;
  2221. }
  2222. hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
  2223. return IXGBE_ERR_MASTER_REQUESTS_PENDING;
  2224. }
  2225. /**
  2226. * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
  2227. * @hw: pointer to hardware structure
  2228. * @mask: Mask to specify which semaphore to acquire
  2229. *
  2230. * Acquires the SWFW semaphore through the GSSR register for the specified
  2231. * function (CSR, PHY0, PHY1, EEPROM, Flash)
  2232. **/
  2233. s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
  2234. {
  2235. u32 gssr = 0;
  2236. u32 swmask = mask;
  2237. u32 fwmask = mask << 5;
  2238. u32 timeout = 200;
  2239. u32 i;
  2240. for (i = 0; i < timeout; i++) {
  2241. /*
  2242. * SW NVM semaphore bit is used for access to all
  2243. * SW_FW_SYNC bits (not just NVM)
  2244. */
  2245. if (ixgbe_get_eeprom_semaphore(hw))
  2246. return IXGBE_ERR_SWFW_SYNC;
  2247. gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
  2248. if (!(gssr & (fwmask | swmask))) {
  2249. gssr |= swmask;
  2250. IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
  2251. ixgbe_release_eeprom_semaphore(hw);
  2252. return 0;
  2253. } else {
  2254. /* Resource is currently in use by FW or SW */
  2255. ixgbe_release_eeprom_semaphore(hw);
  2256. usleep_range(5000, 10000);
  2257. }
  2258. }
  2259. /* If time expired clear the bits holding the lock and retry */
  2260. if (gssr & (fwmask | swmask))
  2261. ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
  2262. usleep_range(5000, 10000);
  2263. return IXGBE_ERR_SWFW_SYNC;
  2264. }
  2265. /**
  2266. * ixgbe_release_swfw_sync - Release SWFW semaphore
  2267. * @hw: pointer to hardware structure
  2268. * @mask: Mask to specify which semaphore to release
  2269. *
  2270. * Releases the SWFW semaphore through the GSSR register for the specified
  2271. * function (CSR, PHY0, PHY1, EEPROM, Flash)
  2272. **/
  2273. void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
  2274. {
  2275. u32 gssr;
  2276. u32 swmask = mask;
  2277. ixgbe_get_eeprom_semaphore(hw);
  2278. gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
  2279. gssr &= ~swmask;
  2280. IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
  2281. ixgbe_release_eeprom_semaphore(hw);
  2282. }
  2283. /**
  2284. * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
  2285. * @hw: pointer to hardware structure
  2286. * @reg_val: Value we read from AUTOC
  2287. * @locked: bool to indicate whether the SW/FW lock should be taken. Never
  2288. * true in this the generic case.
  2289. *
  2290. * The default case requires no protection so just to the register read.
  2291. **/
  2292. s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
  2293. {
  2294. *locked = false;
  2295. *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
  2296. return 0;
  2297. }
  2298. /**
  2299. * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
  2300. * @hw: pointer to hardware structure
  2301. * @reg_val: value to write to AUTOC
  2302. * @locked: bool to indicate whether the SW/FW lock was already taken by
  2303. * previous read.
  2304. **/
  2305. s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
  2306. {
  2307. IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
  2308. return 0;
  2309. }
  2310. /**
  2311. * ixgbe_disable_rx_buff_generic - Stops the receive data path
  2312. * @hw: pointer to hardware structure
  2313. *
  2314. * Stops the receive data path and waits for the HW to internally
  2315. * empty the Rx security block.
  2316. **/
  2317. s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw)
  2318. {
  2319. #define IXGBE_MAX_SECRX_POLL 40
  2320. int i;
  2321. int secrxreg;
  2322. secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
  2323. secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
  2324. IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
  2325. for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
  2326. secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
  2327. if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
  2328. break;
  2329. else
  2330. /* Use interrupt-safe sleep just in case */
  2331. udelay(1000);
  2332. }
  2333. /* For informational purposes only */
  2334. if (i >= IXGBE_MAX_SECRX_POLL)
  2335. hw_dbg(hw, "Rx unit being enabled before security path fully disabled. Continuing with init.\n");
  2336. return 0;
  2337. }
  2338. /**
  2339. * ixgbe_enable_rx_buff - Enables the receive data path
  2340. * @hw: pointer to hardware structure
  2341. *
  2342. * Enables the receive data path
  2343. **/
  2344. s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw)
  2345. {
  2346. u32 secrxreg;
  2347. secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
  2348. secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
  2349. IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
  2350. IXGBE_WRITE_FLUSH(hw);
  2351. return 0;
  2352. }
  2353. /**
  2354. * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
  2355. * @hw: pointer to hardware structure
  2356. * @regval: register value to write to RXCTRL
  2357. *
  2358. * Enables the Rx DMA unit
  2359. **/
  2360. s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
  2361. {
  2362. if (regval & IXGBE_RXCTRL_RXEN)
  2363. hw->mac.ops.enable_rx(hw);
  2364. else
  2365. hw->mac.ops.disable_rx(hw);
  2366. return 0;
  2367. }
  2368. /**
  2369. * ixgbe_blink_led_start_generic - Blink LED based on index.
  2370. * @hw: pointer to hardware structure
  2371. * @index: led number to blink
  2372. **/
  2373. s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
  2374. {
  2375. ixgbe_link_speed speed = 0;
  2376. bool link_up = false;
  2377. u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
  2378. u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
  2379. bool locked = false;
  2380. s32 ret_val;
  2381. if (index > 3)
  2382. return IXGBE_ERR_PARAM;
  2383. /*
  2384. * Link must be up to auto-blink the LEDs;
  2385. * Force it if link is down.
  2386. */
  2387. hw->mac.ops.check_link(hw, &speed, &link_up, false);
  2388. if (!link_up) {
  2389. ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
  2390. if (ret_val)
  2391. return ret_val;
  2392. autoc_reg |= IXGBE_AUTOC_AN_RESTART;
  2393. autoc_reg |= IXGBE_AUTOC_FLU;
  2394. ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
  2395. if (ret_val)
  2396. return ret_val;
  2397. IXGBE_WRITE_FLUSH(hw);
  2398. usleep_range(10000, 20000);
  2399. }
  2400. led_reg &= ~IXGBE_LED_MODE_MASK(index);
  2401. led_reg |= IXGBE_LED_BLINK(index);
  2402. IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
  2403. IXGBE_WRITE_FLUSH(hw);
  2404. return 0;
  2405. }
  2406. /**
  2407. * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
  2408. * @hw: pointer to hardware structure
  2409. * @index: led number to stop blinking
  2410. **/
  2411. s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
  2412. {
  2413. u32 autoc_reg = 0;
  2414. u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
  2415. bool locked = false;
  2416. s32 ret_val;
  2417. if (index > 3)
  2418. return IXGBE_ERR_PARAM;
  2419. ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
  2420. if (ret_val)
  2421. return ret_val;
  2422. autoc_reg &= ~IXGBE_AUTOC_FLU;
  2423. autoc_reg |= IXGBE_AUTOC_AN_RESTART;
  2424. ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
  2425. if (ret_val)
  2426. return ret_val;
  2427. led_reg &= ~IXGBE_LED_MODE_MASK(index);
  2428. led_reg &= ~IXGBE_LED_BLINK(index);
  2429. led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
  2430. IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
  2431. IXGBE_WRITE_FLUSH(hw);
  2432. return 0;
  2433. }
  2434. /**
  2435. * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
  2436. * @hw: pointer to hardware structure
  2437. * @san_mac_offset: SAN MAC address offset
  2438. *
  2439. * This function will read the EEPROM location for the SAN MAC address
  2440. * pointer, and returns the value at that location. This is used in both
  2441. * get and set mac_addr routines.
  2442. **/
  2443. static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
  2444. u16 *san_mac_offset)
  2445. {
  2446. s32 ret_val;
  2447. /*
  2448. * First read the EEPROM pointer to see if the MAC addresses are
  2449. * available.
  2450. */
  2451. ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
  2452. san_mac_offset);
  2453. if (ret_val)
  2454. hw_err(hw, "eeprom read at offset %d failed\n",
  2455. IXGBE_SAN_MAC_ADDR_PTR);
  2456. return ret_val;
  2457. }
  2458. /**
  2459. * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
  2460. * @hw: pointer to hardware structure
  2461. * @san_mac_addr: SAN MAC address
  2462. *
  2463. * Reads the SAN MAC address from the EEPROM, if it's available. This is
  2464. * per-port, so set_lan_id() must be called before reading the addresses.
  2465. * set_lan_id() is called by identify_sfp(), but this cannot be relied
  2466. * upon for non-SFP connections, so we must call it here.
  2467. **/
  2468. s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
  2469. {
  2470. u16 san_mac_data, san_mac_offset;
  2471. u8 i;
  2472. s32 ret_val;
  2473. /*
  2474. * First read the EEPROM pointer to see if the MAC addresses are
  2475. * available. If they're not, no point in calling set_lan_id() here.
  2476. */
  2477. ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
  2478. if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
  2479. goto san_mac_addr_clr;
  2480. /* make sure we know which port we need to program */
  2481. hw->mac.ops.set_lan_id(hw);
  2482. /* apply the port offset to the address offset */
  2483. (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
  2484. (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
  2485. for (i = 0; i < 3; i++) {
  2486. ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
  2487. &san_mac_data);
  2488. if (ret_val) {
  2489. hw_err(hw, "eeprom read at offset %d failed\n",
  2490. san_mac_offset);
  2491. goto san_mac_addr_clr;
  2492. }
  2493. san_mac_addr[i * 2] = (u8)(san_mac_data);
  2494. san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
  2495. san_mac_offset++;
  2496. }
  2497. return 0;
  2498. san_mac_addr_clr:
  2499. /* No addresses available in this EEPROM. It's not necessarily an
  2500. * error though, so just wipe the local address and return.
  2501. */
  2502. for (i = 0; i < 6; i++)
  2503. san_mac_addr[i] = 0xFF;
  2504. return ret_val;
  2505. }
  2506. /**
  2507. * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
  2508. * @hw: pointer to hardware structure
  2509. *
  2510. * Read PCIe configuration space, and get the MSI-X vector count from
  2511. * the capabilities table.
  2512. **/
  2513. u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
  2514. {
  2515. u16 msix_count;
  2516. u16 max_msix_count;
  2517. u16 pcie_offset;
  2518. switch (hw->mac.type) {
  2519. case ixgbe_mac_82598EB:
  2520. pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
  2521. max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
  2522. break;
  2523. case ixgbe_mac_82599EB:
  2524. case ixgbe_mac_X540:
  2525. case ixgbe_mac_X550:
  2526. case ixgbe_mac_X550EM_x:
  2527. case ixgbe_mac_x550em_a:
  2528. pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
  2529. max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
  2530. break;
  2531. default:
  2532. return 1;
  2533. }
  2534. msix_count = ixgbe_read_pci_cfg_word(hw, pcie_offset);
  2535. if (ixgbe_removed(hw->hw_addr))
  2536. msix_count = 0;
  2537. msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
  2538. /* MSI-X count is zero-based in HW */
  2539. msix_count++;
  2540. if (msix_count > max_msix_count)
  2541. msix_count = max_msix_count;
  2542. return msix_count;
  2543. }
  2544. /**
  2545. * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
  2546. * @hw: pointer to hardware struct
  2547. * @rar: receive address register index to disassociate
  2548. * @vmdq: VMDq pool index to remove from the rar
  2549. **/
  2550. s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
  2551. {
  2552. u32 mpsar_lo, mpsar_hi;
  2553. u32 rar_entries = hw->mac.num_rar_entries;
  2554. /* Make sure we are using a valid rar index range */
  2555. if (rar >= rar_entries) {
  2556. hw_dbg(hw, "RAR index %d is out of range.\n", rar);
  2557. return IXGBE_ERR_INVALID_ARGUMENT;
  2558. }
  2559. mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
  2560. mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
  2561. if (ixgbe_removed(hw->hw_addr))
  2562. return 0;
  2563. if (!mpsar_lo && !mpsar_hi)
  2564. return 0;
  2565. if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
  2566. if (mpsar_lo) {
  2567. IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
  2568. mpsar_lo = 0;
  2569. }
  2570. if (mpsar_hi) {
  2571. IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
  2572. mpsar_hi = 0;
  2573. }
  2574. } else if (vmdq < 32) {
  2575. mpsar_lo &= ~BIT(vmdq);
  2576. IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
  2577. } else {
  2578. mpsar_hi &= ~BIT(vmdq - 32);
  2579. IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
  2580. }
  2581. /* was that the last pool using this rar? */
  2582. if (mpsar_lo == 0 && mpsar_hi == 0 &&
  2583. rar != 0 && rar != hw->mac.san_mac_rar_index)
  2584. hw->mac.ops.clear_rar(hw, rar);
  2585. return 0;
  2586. }
  2587. /**
  2588. * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
  2589. * @hw: pointer to hardware struct
  2590. * @rar: receive address register index to associate with a VMDq index
  2591. * @vmdq: VMDq pool index
  2592. **/
  2593. s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
  2594. {
  2595. u32 mpsar;
  2596. u32 rar_entries = hw->mac.num_rar_entries;
  2597. /* Make sure we are using a valid rar index range */
  2598. if (rar >= rar_entries) {
  2599. hw_dbg(hw, "RAR index %d is out of range.\n", rar);
  2600. return IXGBE_ERR_INVALID_ARGUMENT;
  2601. }
  2602. if (vmdq < 32) {
  2603. mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
  2604. mpsar |= BIT(vmdq);
  2605. IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
  2606. } else {
  2607. mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
  2608. mpsar |= BIT(vmdq - 32);
  2609. IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
  2610. }
  2611. return 0;
  2612. }
  2613. /**
  2614. * This function should only be involved in the IOV mode.
  2615. * In IOV mode, Default pool is next pool after the number of
  2616. * VFs advertized and not 0.
  2617. * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
  2618. *
  2619. * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
  2620. * @hw: pointer to hardware struct
  2621. * @vmdq: VMDq pool index
  2622. **/
  2623. s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
  2624. {
  2625. u32 rar = hw->mac.san_mac_rar_index;
  2626. if (vmdq < 32) {
  2627. IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), BIT(vmdq));
  2628. IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
  2629. } else {
  2630. IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
  2631. IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), BIT(vmdq - 32));
  2632. }
  2633. return 0;
  2634. }
  2635. /**
  2636. * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
  2637. * @hw: pointer to hardware structure
  2638. **/
  2639. s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
  2640. {
  2641. int i;
  2642. for (i = 0; i < 128; i++)
  2643. IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
  2644. return 0;
  2645. }
  2646. /**
  2647. * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
  2648. * @hw: pointer to hardware structure
  2649. * @vlan: VLAN id to write to VLAN filter
  2650. * @vlvf_bypass: true to find vlanid only, false returns first empty slot if
  2651. * vlanid not found
  2652. *
  2653. * return the VLVF index where this VLAN id should be placed
  2654. *
  2655. **/
  2656. static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)
  2657. {
  2658. s32 regindex, first_empty_slot;
  2659. u32 bits;
  2660. /* short cut the special case */
  2661. if (vlan == 0)
  2662. return 0;
  2663. /* if vlvf_bypass is set we don't want to use an empty slot, we
  2664. * will simply bypass the VLVF if there are no entries present in the
  2665. * VLVF that contain our VLAN
  2666. */
  2667. first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0;
  2668. /* add VLAN enable bit for comparison */
  2669. vlan |= IXGBE_VLVF_VIEN;
  2670. /* Search for the vlan id in the VLVF entries. Save off the first empty
  2671. * slot found along the way.
  2672. *
  2673. * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1
  2674. */
  2675. for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) {
  2676. bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
  2677. if (bits == vlan)
  2678. return regindex;
  2679. if (!first_empty_slot && !bits)
  2680. first_empty_slot = regindex;
  2681. }
  2682. /* If we are here then we didn't find the VLAN. Return first empty
  2683. * slot we found during our search, else error.
  2684. */
  2685. if (!first_empty_slot)
  2686. hw_dbg(hw, "No space in VLVF.\n");
  2687. return first_empty_slot ? : IXGBE_ERR_NO_SPACE;
  2688. }
  2689. /**
  2690. * ixgbe_set_vfta_generic - Set VLAN filter table
  2691. * @hw: pointer to hardware structure
  2692. * @vlan: VLAN id to write to VLAN filter
  2693. * @vind: VMDq output index that maps queue to VLAN id in VFVFB
  2694. * @vlan_on: boolean flag to turn on/off VLAN in VFVF
  2695. * @vlvf_bypass: boolean flag indicating updating default pool is okay
  2696. *
  2697. * Turn on/off specified VLAN in the VLAN filter table.
  2698. **/
  2699. s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
  2700. bool vlan_on, bool vlvf_bypass)
  2701. {
  2702. u32 regidx, vfta_delta, vfta, bits;
  2703. s32 vlvf_index;
  2704. if ((vlan > 4095) || (vind > 63))
  2705. return IXGBE_ERR_PARAM;
  2706. /*
  2707. * this is a 2 part operation - first the VFTA, then the
  2708. * VLVF and VLVFB if VT Mode is set
  2709. * We don't write the VFTA until we know the VLVF part succeeded.
  2710. */
  2711. /* Part 1
  2712. * The VFTA is a bitstring made up of 128 32-bit registers
  2713. * that enable the particular VLAN id, much like the MTA:
  2714. * bits[11-5]: which register
  2715. * bits[4-0]: which bit in the register
  2716. */
  2717. regidx = vlan / 32;
  2718. vfta_delta = BIT(vlan % 32);
  2719. vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx));
  2720. /* vfta_delta represents the difference between the current value
  2721. * of vfta and the value we want in the register. Since the diff
  2722. * is an XOR mask we can just update vfta using an XOR.
  2723. */
  2724. vfta_delta &= vlan_on ? ~vfta : vfta;
  2725. vfta ^= vfta_delta;
  2726. /* Part 2
  2727. * If VT Mode is set
  2728. * Either vlan_on
  2729. * make sure the vlan is in VLVF
  2730. * set the vind bit in the matching VLVFB
  2731. * Or !vlan_on
  2732. * clear the pool bit and possibly the vind
  2733. */
  2734. if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE))
  2735. goto vfta_update;
  2736. vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
  2737. if (vlvf_index < 0) {
  2738. if (vlvf_bypass)
  2739. goto vfta_update;
  2740. return vlvf_index;
  2741. }
  2742. bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32));
  2743. /* set the pool bit */
  2744. bits |= BIT(vind % 32);
  2745. if (vlan_on)
  2746. goto vlvf_update;
  2747. /* clear the pool bit */
  2748. bits ^= BIT(vind % 32);
  2749. if (!bits &&
  2750. !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) {
  2751. /* Clear VFTA first, then disable VLVF. Otherwise
  2752. * we run the risk of stray packets leaking into
  2753. * the PF via the default pool
  2754. */
  2755. if (vfta_delta)
  2756. IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta);
  2757. /* disable VLVF and clear remaining bit from pool */
  2758. IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
  2759. IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0);
  2760. return 0;
  2761. }
  2762. /* If there are still bits set in the VLVFB registers
  2763. * for the VLAN ID indicated we need to see if the
  2764. * caller is requesting that we clear the VFTA entry bit.
  2765. * If the caller has requested that we clear the VFTA
  2766. * entry bit but there are still pools/VFs using this VLAN
  2767. * ID entry then ignore the request. We're not worried
  2768. * about the case where we're turning the VFTA VLAN ID
  2769. * entry bit on, only when requested to turn it off as
  2770. * there may be multiple pools and/or VFs using the
  2771. * VLAN ID entry. In that case we cannot clear the
  2772. * VFTA bit until all pools/VFs using that VLAN ID have also
  2773. * been cleared. This will be indicated by "bits" being
  2774. * zero.
  2775. */
  2776. vfta_delta = 0;
  2777. vlvf_update:
  2778. /* record pool change and enable VLAN ID if not already enabled */
  2779. IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits);
  2780. IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan);
  2781. vfta_update:
  2782. /* Update VFTA now that we are ready for traffic */
  2783. if (vfta_delta)
  2784. IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta);
  2785. return 0;
  2786. }
  2787. /**
  2788. * ixgbe_clear_vfta_generic - Clear VLAN filter table
  2789. * @hw: pointer to hardware structure
  2790. *
  2791. * Clears the VLAN filer table, and the VMDq index associated with the filter
  2792. **/
  2793. s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
  2794. {
  2795. u32 offset;
  2796. for (offset = 0; offset < hw->mac.vft_size; offset++)
  2797. IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
  2798. for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
  2799. IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
  2800. IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
  2801. IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0);
  2802. }
  2803. return 0;
  2804. }
  2805. /**
  2806. * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
  2807. * @hw: pointer to hardware structure
  2808. *
  2809. * Contains the logic to identify if we need to verify link for the
  2810. * crosstalk fix
  2811. **/
  2812. static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw)
  2813. {
  2814. /* Does FW say we need the fix */
  2815. if (!hw->need_crosstalk_fix)
  2816. return false;
  2817. /* Only consider SFP+ PHYs i.e. media type fiber */
  2818. switch (hw->mac.ops.get_media_type(hw)) {
  2819. case ixgbe_media_type_fiber:
  2820. case ixgbe_media_type_fiber_qsfp:
  2821. break;
  2822. default:
  2823. return false;
  2824. }
  2825. return true;
  2826. }
  2827. /**
  2828. * ixgbe_check_mac_link_generic - Determine link and speed status
  2829. * @hw: pointer to hardware structure
  2830. * @speed: pointer to link speed
  2831. * @link_up: true when link is up
  2832. * @link_up_wait_to_complete: bool used to wait for link up or not
  2833. *
  2834. * Reads the links register to determine if link is up and the current speed
  2835. **/
  2836. s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
  2837. bool *link_up, bool link_up_wait_to_complete)
  2838. {
  2839. u32 links_reg, links_orig;
  2840. u32 i;
  2841. /* If Crosstalk fix enabled do the sanity check of making sure
  2842. * the SFP+ cage is full.
  2843. */
  2844. if (ixgbe_need_crosstalk_fix(hw)) {
  2845. u32 sfp_cage_full;
  2846. switch (hw->mac.type) {
  2847. case ixgbe_mac_82599EB:
  2848. sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
  2849. IXGBE_ESDP_SDP2;
  2850. break;
  2851. case ixgbe_mac_X550EM_x:
  2852. case ixgbe_mac_x550em_a:
  2853. sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
  2854. IXGBE_ESDP_SDP0;
  2855. break;
  2856. default:
  2857. /* sanity check - No SFP+ devices here */
  2858. sfp_cage_full = false;
  2859. break;
  2860. }
  2861. if (!sfp_cage_full) {
  2862. *link_up = false;
  2863. *speed = IXGBE_LINK_SPEED_UNKNOWN;
  2864. return 0;
  2865. }
  2866. }
  2867. /* clear the old state */
  2868. links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
  2869. links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
  2870. if (links_orig != links_reg) {
  2871. hw_dbg(hw, "LINKS changed from %08X to %08X\n",
  2872. links_orig, links_reg);
  2873. }
  2874. if (link_up_wait_to_complete) {
  2875. for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
  2876. if (links_reg & IXGBE_LINKS_UP) {
  2877. *link_up = true;
  2878. break;
  2879. } else {
  2880. *link_up = false;
  2881. }
  2882. msleep(100);
  2883. links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
  2884. }
  2885. } else {
  2886. if (links_reg & IXGBE_LINKS_UP)
  2887. *link_up = true;
  2888. else
  2889. *link_up = false;
  2890. }
  2891. switch (links_reg & IXGBE_LINKS_SPEED_82599) {
  2892. case IXGBE_LINKS_SPEED_10G_82599:
  2893. if ((hw->mac.type >= ixgbe_mac_X550) &&
  2894. (links_reg & IXGBE_LINKS_SPEED_NON_STD))
  2895. *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
  2896. else
  2897. *speed = IXGBE_LINK_SPEED_10GB_FULL;
  2898. break;
  2899. case IXGBE_LINKS_SPEED_1G_82599:
  2900. *speed = IXGBE_LINK_SPEED_1GB_FULL;
  2901. break;
  2902. case IXGBE_LINKS_SPEED_100_82599:
  2903. if ((hw->mac.type >= ixgbe_mac_X550) &&
  2904. (links_reg & IXGBE_LINKS_SPEED_NON_STD))
  2905. *speed = IXGBE_LINK_SPEED_5GB_FULL;
  2906. else
  2907. *speed = IXGBE_LINK_SPEED_100_FULL;
  2908. break;
  2909. case IXGBE_LINKS_SPEED_10_X550EM_A:
  2910. *speed = IXGBE_LINK_SPEED_UNKNOWN;
  2911. if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
  2912. hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {
  2913. *speed = IXGBE_LINK_SPEED_10_FULL;
  2914. }
  2915. break;
  2916. default:
  2917. *speed = IXGBE_LINK_SPEED_UNKNOWN;
  2918. }
  2919. return 0;
  2920. }
  2921. /**
  2922. * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
  2923. * the EEPROM
  2924. * @hw: pointer to hardware structure
  2925. * @wwnn_prefix: the alternative WWNN prefix
  2926. * @wwpn_prefix: the alternative WWPN prefix
  2927. *
  2928. * This function will read the EEPROM from the alternative SAN MAC address
  2929. * block to check the support for the alternative WWNN/WWPN prefix support.
  2930. **/
  2931. s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
  2932. u16 *wwpn_prefix)
  2933. {
  2934. u16 offset, caps;
  2935. u16 alt_san_mac_blk_offset;
  2936. /* clear output first */
  2937. *wwnn_prefix = 0xFFFF;
  2938. *wwpn_prefix = 0xFFFF;
  2939. /* check if alternative SAN MAC is supported */
  2940. offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
  2941. if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
  2942. goto wwn_prefix_err;
  2943. if ((alt_san_mac_blk_offset == 0) ||
  2944. (alt_san_mac_blk_offset == 0xFFFF))
  2945. return 0;
  2946. /* check capability in alternative san mac address block */
  2947. offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
  2948. if (hw->eeprom.ops.read(hw, offset, &caps))
  2949. goto wwn_prefix_err;
  2950. if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
  2951. return 0;
  2952. /* get the corresponding prefix for WWNN/WWPN */
  2953. offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
  2954. if (hw->eeprom.ops.read(hw, offset, wwnn_prefix))
  2955. hw_err(hw, "eeprom read at offset %d failed\n", offset);
  2956. offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
  2957. if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
  2958. goto wwn_prefix_err;
  2959. return 0;
  2960. wwn_prefix_err:
  2961. hw_err(hw, "eeprom read at offset %d failed\n", offset);
  2962. return 0;
  2963. }
  2964. /**
  2965. * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
  2966. * @hw: pointer to hardware structure
  2967. * @enable: enable or disable switch for MAC anti-spoofing
  2968. * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
  2969. *
  2970. **/
  2971. void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
  2972. {
  2973. int vf_target_reg = vf >> 3;
  2974. int vf_target_shift = vf % 8;
  2975. u32 pfvfspoof;
  2976. if (hw->mac.type == ixgbe_mac_82598EB)
  2977. return;
  2978. pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
  2979. if (enable)
  2980. pfvfspoof |= BIT(vf_target_shift);
  2981. else
  2982. pfvfspoof &= ~BIT(vf_target_shift);
  2983. IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
  2984. }
  2985. /**
  2986. * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
  2987. * @hw: pointer to hardware structure
  2988. * @enable: enable or disable switch for VLAN anti-spoofing
  2989. * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
  2990. *
  2991. **/
  2992. void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
  2993. {
  2994. int vf_target_reg = vf >> 3;
  2995. int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
  2996. u32 pfvfspoof;
  2997. if (hw->mac.type == ixgbe_mac_82598EB)
  2998. return;
  2999. pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
  3000. if (enable)
  3001. pfvfspoof |= BIT(vf_target_shift);
  3002. else
  3003. pfvfspoof &= ~BIT(vf_target_shift);
  3004. IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
  3005. }
  3006. /**
  3007. * ixgbe_fw_recovery_mode - Check if in FW NVM recovery mode
  3008. * @hw: pointer to hardware structure
  3009. */
  3010. bool ixgbe_fw_recovery_mode(struct ixgbe_hw *hw)
  3011. {
  3012. if (hw->mac.ops.fw_recovery_mode)
  3013. return hw->mac.ops.fw_recovery_mode(hw);
  3014. return false;
  3015. }
  3016. /**
  3017. * ixgbe_get_device_caps_generic - Get additional device capabilities
  3018. * @hw: pointer to hardware structure
  3019. * @device_caps: the EEPROM word with the extra device capabilities
  3020. *
  3021. * This function will read the EEPROM location for the device capabilities,
  3022. * and return the word through device_caps.
  3023. **/
  3024. s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
  3025. {
  3026. hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
  3027. return 0;
  3028. }
  3029. /**
  3030. * ixgbe_set_rxpba_generic - Initialize RX packet buffer
  3031. * @hw: pointer to hardware structure
  3032. * @num_pb: number of packet buffers to allocate
  3033. * @headroom: reserve n KB of headroom
  3034. * @strategy: packet buffer allocation strategy
  3035. **/
  3036. void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw,
  3037. int num_pb,
  3038. u32 headroom,
  3039. int strategy)
  3040. {
  3041. u32 pbsize = hw->mac.rx_pb_size;
  3042. int i = 0;
  3043. u32 rxpktsize, txpktsize, txpbthresh;
  3044. /* Reserve headroom */
  3045. pbsize -= headroom;
  3046. if (!num_pb)
  3047. num_pb = 1;
  3048. /* Divide remaining packet buffer space amongst the number
  3049. * of packet buffers requested using supplied strategy.
  3050. */
  3051. switch (strategy) {
  3052. case (PBA_STRATEGY_WEIGHTED):
  3053. /* pba_80_48 strategy weight first half of packet buffer with
  3054. * 5/8 of the packet buffer space.
  3055. */
  3056. rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8));
  3057. pbsize -= rxpktsize * (num_pb / 2);
  3058. rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
  3059. for (; i < (num_pb / 2); i++)
  3060. IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
  3061. /* fall through - configure remaining packet buffers */
  3062. case (PBA_STRATEGY_EQUAL):
  3063. /* Divide the remaining Rx packet buffer evenly among the TCs */
  3064. rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
  3065. for (; i < num_pb; i++)
  3066. IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
  3067. break;
  3068. default:
  3069. break;
  3070. }
  3071. /*
  3072. * Setup Tx packet buffer and threshold equally for all TCs
  3073. * TXPBTHRESH register is set in K so divide by 1024 and subtract
  3074. * 10 since the largest packet we support is just over 9K.
  3075. */
  3076. txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
  3077. txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
  3078. for (i = 0; i < num_pb; i++) {
  3079. IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
  3080. IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
  3081. }
  3082. /* Clear unused TCs, if any, to zero buffer size*/
  3083. for (; i < IXGBE_MAX_PB; i++) {
  3084. IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
  3085. IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
  3086. IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
  3087. }
  3088. }
  3089. /**
  3090. * ixgbe_calculate_checksum - Calculate checksum for buffer
  3091. * @buffer: pointer to EEPROM
  3092. * @length: size of EEPROM to calculate a checksum for
  3093. *
  3094. * Calculates the checksum for some buffer on a specified length. The
  3095. * checksum calculated is returned.
  3096. **/
  3097. u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
  3098. {
  3099. u32 i;
  3100. u8 sum = 0;
  3101. if (!buffer)
  3102. return 0;
  3103. for (i = 0; i < length; i++)
  3104. sum += buffer[i];
  3105. return (u8) (0 - sum);
  3106. }
  3107. /**
  3108. * ixgbe_hic_unlocked - Issue command to manageability block unlocked
  3109. * @hw: pointer to the HW structure
  3110. * @buffer: command to write and where the return status will be placed
  3111. * @length: length of buffer, must be multiple of 4 bytes
  3112. * @timeout: time in ms to wait for command completion
  3113. *
  3114. * Communicates with the manageability block. On success return 0
  3115. * else returns semaphore error when encountering an error acquiring
  3116. * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
  3117. *
  3118. * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held
  3119. * by the caller.
  3120. **/
  3121. s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length,
  3122. u32 timeout)
  3123. {
  3124. u32 hicr, i, fwsts;
  3125. u16 dword_len;
  3126. if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
  3127. hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length);
  3128. return IXGBE_ERR_HOST_INTERFACE_COMMAND;
  3129. }
  3130. /* Set bit 9 of FWSTS clearing FW reset indication */
  3131. fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
  3132. IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
  3133. /* Check that the host interface is enabled. */
  3134. hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
  3135. if (!(hicr & IXGBE_HICR_EN)) {
  3136. hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n");
  3137. return IXGBE_ERR_HOST_INTERFACE_COMMAND;
  3138. }
  3139. /* Calculate length in DWORDs. We must be DWORD aligned */
  3140. if (length % sizeof(u32)) {
  3141. hw_dbg(hw, "Buffer length failure, not aligned to dword");
  3142. return IXGBE_ERR_INVALID_ARGUMENT;
  3143. }
  3144. dword_len = length >> 2;
  3145. /* The device driver writes the relevant command block
  3146. * into the ram area.
  3147. */
  3148. for (i = 0; i < dword_len; i++)
  3149. IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
  3150. i, (__force u32)cpu_to_le32(buffer[i]));
  3151. /* Setting this bit tells the ARC that a new command is pending. */
  3152. IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
  3153. for (i = 0; i < timeout; i++) {
  3154. hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
  3155. if (!(hicr & IXGBE_HICR_C))
  3156. break;
  3157. usleep_range(1000, 2000);
  3158. }
  3159. /* Check command successful completion. */
  3160. if ((timeout && i == timeout) ||
  3161. !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))
  3162. return IXGBE_ERR_HOST_INTERFACE_COMMAND;
  3163. return 0;
  3164. }
  3165. /**
  3166. * ixgbe_host_interface_command - Issue command to manageability block
  3167. * @hw: pointer to the HW structure
  3168. * @buffer: contains the command to write and where the return status will
  3169. * be placed
  3170. * @length: length of buffer, must be multiple of 4 bytes
  3171. * @timeout: time in ms to wait for command completion
  3172. * @return_data: read and return data from the buffer (true) or not (false)
  3173. * Needed because FW structures are big endian and decoding of
  3174. * these fields can be 8 bit or 16 bit based on command. Decoding
  3175. * is not easily understood without making a table of commands.
  3176. * So we will leave this up to the caller to read back the data
  3177. * in these cases.
  3178. *
  3179. * Communicates with the manageability block. On success return 0
  3180. * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
  3181. **/
  3182. s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, void *buffer,
  3183. u32 length, u32 timeout,
  3184. bool return_data)
  3185. {
  3186. u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
  3187. union {
  3188. struct ixgbe_hic_hdr hdr;
  3189. u32 u32arr[1];
  3190. } *bp = buffer;
  3191. u16 buf_len, dword_len;
  3192. s32 status;
  3193. u32 bi;
  3194. if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
  3195. hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length);
  3196. return IXGBE_ERR_HOST_INTERFACE_COMMAND;
  3197. }
  3198. /* Take management host interface semaphore */
  3199. status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
  3200. if (status)
  3201. return status;
  3202. status = ixgbe_hic_unlocked(hw, buffer, length, timeout);
  3203. if (status)
  3204. goto rel_out;
  3205. if (!return_data)
  3206. goto rel_out;
  3207. /* Calculate length in DWORDs */
  3208. dword_len = hdr_size >> 2;
  3209. /* first pull in the header so we know the buffer length */
  3210. for (bi = 0; bi < dword_len; bi++) {
  3211. bp->u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
  3212. le32_to_cpus(&bp->u32arr[bi]);
  3213. }
  3214. /* If there is any thing in data position pull it in */
  3215. buf_len = bp->hdr.buf_len;
  3216. if (!buf_len)
  3217. goto rel_out;
  3218. if (length < round_up(buf_len, 4) + hdr_size) {
  3219. hw_dbg(hw, "Buffer not large enough for reply message.\n");
  3220. status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
  3221. goto rel_out;
  3222. }
  3223. /* Calculate length in DWORDs, add 3 for odd lengths */
  3224. dword_len = (buf_len + 3) >> 2;
  3225. /* Pull in the rest of the buffer (bi is where we left off) */
  3226. for (; bi <= dword_len; bi++) {
  3227. bp->u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
  3228. le32_to_cpus(&bp->u32arr[bi]);
  3229. }
  3230. rel_out:
  3231. hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
  3232. return status;
  3233. }
  3234. /**
  3235. * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
  3236. * @hw: pointer to the HW structure
  3237. * @maj: driver version major number
  3238. * @min: driver version minor number
  3239. * @build: driver version build number
  3240. * @sub: driver version sub build number
  3241. * @len: length of driver_ver string
  3242. * @driver_ver: driver string
  3243. *
  3244. * Sends driver version number to firmware through the manageability
  3245. * block. On success return 0
  3246. * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
  3247. * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
  3248. **/
  3249. s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
  3250. u8 build, u8 sub, __always_unused u16 len,
  3251. __always_unused const char *driver_ver)
  3252. {
  3253. struct ixgbe_hic_drv_info fw_cmd;
  3254. int i;
  3255. s32 ret_val;
  3256. fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
  3257. fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
  3258. fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
  3259. fw_cmd.port_num = hw->bus.func;
  3260. fw_cmd.ver_maj = maj;
  3261. fw_cmd.ver_min = min;
  3262. fw_cmd.ver_build = build;
  3263. fw_cmd.ver_sub = sub;
  3264. fw_cmd.hdr.checksum = 0;
  3265. fw_cmd.pad = 0;
  3266. fw_cmd.pad2 = 0;
  3267. fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
  3268. (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
  3269. for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
  3270. ret_val = ixgbe_host_interface_command(hw, &fw_cmd,
  3271. sizeof(fw_cmd),
  3272. IXGBE_HI_COMMAND_TIMEOUT,
  3273. true);
  3274. if (ret_val != 0)
  3275. continue;
  3276. if (fw_cmd.hdr.cmd_or_resp.ret_status ==
  3277. FW_CEM_RESP_STATUS_SUCCESS)
  3278. ret_val = 0;
  3279. else
  3280. ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
  3281. break;
  3282. }
  3283. return ret_val;
  3284. }
  3285. /**
  3286. * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
  3287. * @hw: pointer to the hardware structure
  3288. *
  3289. * The 82599 and x540 MACs can experience issues if TX work is still pending
  3290. * when a reset occurs. This function prevents this by flushing the PCIe
  3291. * buffers on the system.
  3292. **/
  3293. void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
  3294. {
  3295. u32 gcr_ext, hlreg0, i, poll;
  3296. u16 value;
  3297. /*
  3298. * If double reset is not requested then all transactions should
  3299. * already be clear and as such there is no work to do
  3300. */
  3301. if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
  3302. return;
  3303. /*
  3304. * Set loopback enable to prevent any transmits from being sent
  3305. * should the link come up. This assumes that the RXCTRL.RXEN bit
  3306. * has already been cleared.
  3307. */
  3308. hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
  3309. IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
  3310. /* wait for a last completion before clearing buffers */
  3311. IXGBE_WRITE_FLUSH(hw);
  3312. usleep_range(3000, 6000);
  3313. /* Before proceeding, make sure that the PCIe block does not have
  3314. * transactions pending.
  3315. */
  3316. poll = ixgbe_pcie_timeout_poll(hw);
  3317. for (i = 0; i < poll; i++) {
  3318. usleep_range(100, 200);
  3319. value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS);
  3320. if (ixgbe_removed(hw->hw_addr))
  3321. break;
  3322. if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
  3323. break;
  3324. }
  3325. /* initiate cleaning flow for buffers in the PCIe transaction layer */
  3326. gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
  3327. IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
  3328. gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
  3329. /* Flush all writes and allow 20usec for all transactions to clear */
  3330. IXGBE_WRITE_FLUSH(hw);
  3331. udelay(20);
  3332. /* restore previous register values */
  3333. IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
  3334. IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
  3335. }
  3336. static const u8 ixgbe_emc_temp_data[4] = {
  3337. IXGBE_EMC_INTERNAL_DATA,
  3338. IXGBE_EMC_DIODE1_DATA,
  3339. IXGBE_EMC_DIODE2_DATA,
  3340. IXGBE_EMC_DIODE3_DATA
  3341. };
  3342. static const u8 ixgbe_emc_therm_limit[4] = {
  3343. IXGBE_EMC_INTERNAL_THERM_LIMIT,
  3344. IXGBE_EMC_DIODE1_THERM_LIMIT,
  3345. IXGBE_EMC_DIODE2_THERM_LIMIT,
  3346. IXGBE_EMC_DIODE3_THERM_LIMIT
  3347. };
  3348. /**
  3349. * ixgbe_get_ets_data - Extracts the ETS bit data
  3350. * @hw: pointer to hardware structure
  3351. * @ets_cfg: extected ETS data
  3352. * @ets_offset: offset of ETS data
  3353. *
  3354. * Returns error code.
  3355. **/
  3356. static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg,
  3357. u16 *ets_offset)
  3358. {
  3359. s32 status;
  3360. status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset);
  3361. if (status)
  3362. return status;
  3363. if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF))
  3364. return IXGBE_NOT_IMPLEMENTED;
  3365. status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg);
  3366. if (status)
  3367. return status;
  3368. if ((*ets_cfg & IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED)
  3369. return IXGBE_NOT_IMPLEMENTED;
  3370. return 0;
  3371. }
  3372. /**
  3373. * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
  3374. * @hw: pointer to hardware structure
  3375. *
  3376. * Returns the thermal sensor data structure
  3377. **/
  3378. s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
  3379. {
  3380. s32 status;
  3381. u16 ets_offset;
  3382. u16 ets_cfg;
  3383. u16 ets_sensor;
  3384. u8 num_sensors;
  3385. u8 i;
  3386. struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
  3387. /* Only support thermal sensors attached to physical port 0 */
  3388. if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
  3389. return IXGBE_NOT_IMPLEMENTED;
  3390. status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
  3391. if (status)
  3392. return status;
  3393. num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
  3394. if (num_sensors > IXGBE_MAX_SENSORS)
  3395. num_sensors = IXGBE_MAX_SENSORS;
  3396. for (i = 0; i < num_sensors; i++) {
  3397. u8 sensor_index;
  3398. u8 sensor_location;
  3399. status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
  3400. &ets_sensor);
  3401. if (status)
  3402. return status;
  3403. sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
  3404. IXGBE_ETS_DATA_INDEX_SHIFT);
  3405. sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
  3406. IXGBE_ETS_DATA_LOC_SHIFT);
  3407. if (sensor_location != 0) {
  3408. status = hw->phy.ops.read_i2c_byte(hw,
  3409. ixgbe_emc_temp_data[sensor_index],
  3410. IXGBE_I2C_THERMAL_SENSOR_ADDR,
  3411. &data->sensor[i].temp);
  3412. if (status)
  3413. return status;
  3414. }
  3415. }
  3416. return 0;
  3417. }
  3418. /**
  3419. * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
  3420. * @hw: pointer to hardware structure
  3421. *
  3422. * Inits the thermal sensor thresholds according to the NVM map
  3423. * and save off the threshold and location values into mac.thermal_sensor_data
  3424. **/
  3425. s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
  3426. {
  3427. s32 status;
  3428. u16 ets_offset;
  3429. u16 ets_cfg;
  3430. u16 ets_sensor;
  3431. u8 low_thresh_delta;
  3432. u8 num_sensors;
  3433. u8 therm_limit;
  3434. u8 i;
  3435. struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
  3436. memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
  3437. /* Only support thermal sensors attached to physical port 0 */
  3438. if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
  3439. return IXGBE_NOT_IMPLEMENTED;
  3440. status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
  3441. if (status)
  3442. return status;
  3443. low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
  3444. IXGBE_ETS_LTHRES_DELTA_SHIFT);
  3445. num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
  3446. if (num_sensors > IXGBE_MAX_SENSORS)
  3447. num_sensors = IXGBE_MAX_SENSORS;
  3448. for (i = 0; i < num_sensors; i++) {
  3449. u8 sensor_index;
  3450. u8 sensor_location;
  3451. if (hw->eeprom.ops.read(hw, ets_offset + 1 + i, &ets_sensor)) {
  3452. hw_err(hw, "eeprom read at offset %d failed\n",
  3453. ets_offset + 1 + i);
  3454. continue;
  3455. }
  3456. sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
  3457. IXGBE_ETS_DATA_INDEX_SHIFT);
  3458. sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
  3459. IXGBE_ETS_DATA_LOC_SHIFT);
  3460. therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
  3461. hw->phy.ops.write_i2c_byte(hw,
  3462. ixgbe_emc_therm_limit[sensor_index],
  3463. IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
  3464. if (sensor_location == 0)
  3465. continue;
  3466. data->sensor[i].location = sensor_location;
  3467. data->sensor[i].caution_thresh = therm_limit;
  3468. data->sensor[i].max_op_thresh = therm_limit - low_thresh_delta;
  3469. }
  3470. return 0;
  3471. }
  3472. /**
  3473. * ixgbe_get_orom_version - Return option ROM from EEPROM
  3474. *
  3475. * @hw: pointer to hardware structure
  3476. * @nvm_ver: pointer to output structure
  3477. *
  3478. * if valid option ROM version, nvm_ver->or_valid set to true
  3479. * else nvm_ver->or_valid is false.
  3480. **/
  3481. void ixgbe_get_orom_version(struct ixgbe_hw *hw,
  3482. struct ixgbe_nvm_version *nvm_ver)
  3483. {
  3484. u16 offset, eeprom_cfg_blkh, eeprom_cfg_blkl;
  3485. nvm_ver->or_valid = false;
  3486. /* Option Rom may or may not be present. Start with pointer */
  3487. hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset);
  3488. /* make sure offset is valid */
  3489. if (offset == 0x0 || offset == NVM_INVALID_PTR)
  3490. return;
  3491. hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh);
  3492. hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl);
  3493. /* option rom exists and is valid */
  3494. if ((eeprom_cfg_blkl | eeprom_cfg_blkh) == 0x0 ||
  3495. eeprom_cfg_blkl == NVM_VER_INVALID ||
  3496. eeprom_cfg_blkh == NVM_VER_INVALID)
  3497. return;
  3498. nvm_ver->or_valid = true;
  3499. nvm_ver->or_major = eeprom_cfg_blkl >> NVM_OROM_SHIFT;
  3500. nvm_ver->or_build = (eeprom_cfg_blkl << NVM_OROM_SHIFT) |
  3501. (eeprom_cfg_blkh >> NVM_OROM_SHIFT);
  3502. nvm_ver->or_patch = eeprom_cfg_blkh & NVM_OROM_PATCH_MASK;
  3503. }
  3504. /**
  3505. * ixgbe_get_oem_prod_version Etrack ID from EEPROM
  3506. *
  3507. * @hw: pointer to hardware structure
  3508. * @nvm_ver: pointer to output structure
  3509. *
  3510. * if valid OEM product version, nvm_ver->oem_valid set to true
  3511. * else nvm_ver->oem_valid is false.
  3512. **/
  3513. void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw,
  3514. struct ixgbe_nvm_version *nvm_ver)
  3515. {
  3516. u16 rel_num, prod_ver, mod_len, cap, offset;
  3517. nvm_ver->oem_valid = false;
  3518. hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset);
  3519. /* Return is offset to OEM Product Version block is invalid */
  3520. if (offset == 0x0 || offset == NVM_INVALID_PTR)
  3521. return;
  3522. /* Read product version block */
  3523. hw->eeprom.ops.read(hw, offset, &mod_len);
  3524. hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap);
  3525. /* Return if OEM product version block is invalid */
  3526. if (mod_len != NVM_OEM_PROD_VER_MOD_LEN ||
  3527. (cap & NVM_OEM_PROD_VER_CAP_MASK) != 0x0)
  3528. return;
  3529. hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver);
  3530. hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num);
  3531. /* Return if version is invalid */
  3532. if ((rel_num | prod_ver) == 0x0 ||
  3533. rel_num == NVM_VER_INVALID || prod_ver == NVM_VER_INVALID)
  3534. return;
  3535. nvm_ver->oem_major = prod_ver >> NVM_VER_SHIFT;
  3536. nvm_ver->oem_minor = prod_ver & NVM_VER_MASK;
  3537. nvm_ver->oem_release = rel_num;
  3538. nvm_ver->oem_valid = true;
  3539. }
  3540. /**
  3541. * ixgbe_get_etk_id - Return Etrack ID from EEPROM
  3542. *
  3543. * @hw: pointer to hardware structure
  3544. * @nvm_ver: pointer to output structure
  3545. *
  3546. * word read errors will return 0xFFFF
  3547. **/
  3548. void ixgbe_get_etk_id(struct ixgbe_hw *hw,
  3549. struct ixgbe_nvm_version *nvm_ver)
  3550. {
  3551. u16 etk_id_l, etk_id_h;
  3552. if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l))
  3553. etk_id_l = NVM_VER_INVALID;
  3554. if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h))
  3555. etk_id_h = NVM_VER_INVALID;
  3556. /* The word order for the version format is determined by high order
  3557. * word bit 15.
  3558. */
  3559. if ((etk_id_h & NVM_ETK_VALID) == 0) {
  3560. nvm_ver->etk_id = etk_id_h;
  3561. nvm_ver->etk_id |= (etk_id_l << NVM_ETK_SHIFT);
  3562. } else {
  3563. nvm_ver->etk_id = etk_id_l;
  3564. nvm_ver->etk_id |= (etk_id_h << NVM_ETK_SHIFT);
  3565. }
  3566. }
  3567. void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
  3568. {
  3569. u32 rxctrl;
  3570. rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
  3571. if (rxctrl & IXGBE_RXCTRL_RXEN) {
  3572. if (hw->mac.type != ixgbe_mac_82598EB) {
  3573. u32 pfdtxgswc;
  3574. pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
  3575. if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
  3576. pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
  3577. IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
  3578. hw->mac.set_lben = true;
  3579. } else {
  3580. hw->mac.set_lben = false;
  3581. }
  3582. }
  3583. rxctrl &= ~IXGBE_RXCTRL_RXEN;
  3584. IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
  3585. }
  3586. }
  3587. void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
  3588. {
  3589. u32 rxctrl;
  3590. rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
  3591. IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
  3592. if (hw->mac.type != ixgbe_mac_82598EB) {
  3593. if (hw->mac.set_lben) {
  3594. u32 pfdtxgswc;
  3595. pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
  3596. pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
  3597. IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
  3598. hw->mac.set_lben = false;
  3599. }
  3600. }
  3601. }
  3602. /** ixgbe_mng_present - returns true when management capability is present
  3603. * @hw: pointer to hardware structure
  3604. **/
  3605. bool ixgbe_mng_present(struct ixgbe_hw *hw)
  3606. {
  3607. u32 fwsm;
  3608. if (hw->mac.type < ixgbe_mac_82599EB)
  3609. return false;
  3610. fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
  3611. return !!(fwsm & IXGBE_FWSM_FW_MODE_PT);
  3612. }
  3613. /**
  3614. * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
  3615. * @hw: pointer to hardware structure
  3616. * @speed: new link speed
  3617. * @autoneg_wait_to_complete: true when waiting for completion is needed
  3618. *
  3619. * Set the link speed in the MAC and/or PHY register and restarts link.
  3620. */
  3621. s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
  3622. ixgbe_link_speed speed,
  3623. bool autoneg_wait_to_complete)
  3624. {
  3625. ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
  3626. ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
  3627. s32 status = 0;
  3628. u32 speedcnt = 0;
  3629. u32 i = 0;
  3630. bool autoneg, link_up = false;
  3631. /* Mask off requested but non-supported speeds */
  3632. status = hw->mac.ops.get_link_capabilities(hw, &link_speed, &autoneg);
  3633. if (status)
  3634. return status;
  3635. speed &= link_speed;
  3636. /* Try each speed one by one, highest priority first. We do this in
  3637. * software because 10Gb fiber doesn't support speed autonegotiation.
  3638. */
  3639. if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
  3640. speedcnt++;
  3641. highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
  3642. /* Set the module link speed */
  3643. switch (hw->phy.media_type) {
  3644. case ixgbe_media_type_fiber:
  3645. hw->mac.ops.set_rate_select_speed(hw,
  3646. IXGBE_LINK_SPEED_10GB_FULL);
  3647. break;
  3648. case ixgbe_media_type_fiber_qsfp:
  3649. /* QSFP module automatically detects MAC link speed */
  3650. break;
  3651. default:
  3652. hw_dbg(hw, "Unexpected media type\n");
  3653. break;
  3654. }
  3655. /* Allow module to change analog characteristics (1G->10G) */
  3656. msleep(40);
  3657. status = hw->mac.ops.setup_mac_link(hw,
  3658. IXGBE_LINK_SPEED_10GB_FULL,
  3659. autoneg_wait_to_complete);
  3660. if (status)
  3661. return status;
  3662. /* Flap the Tx laser if it has not already been done */
  3663. if (hw->mac.ops.flap_tx_laser)
  3664. hw->mac.ops.flap_tx_laser(hw);
  3665. /* Wait for the controller to acquire link. Per IEEE 802.3ap,
  3666. * Section 73.10.2, we may have to wait up to 500ms if KR is
  3667. * attempted. 82599 uses the same timing for 10g SFI.
  3668. */
  3669. for (i = 0; i < 5; i++) {
  3670. /* Wait for the link partner to also set speed */
  3671. msleep(100);
  3672. /* If we have link, just jump out */
  3673. status = hw->mac.ops.check_link(hw, &link_speed,
  3674. &link_up, false);
  3675. if (status)
  3676. return status;
  3677. if (link_up)
  3678. goto out;
  3679. }
  3680. }
  3681. if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
  3682. speedcnt++;
  3683. if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
  3684. highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
  3685. /* Set the module link speed */
  3686. switch (hw->phy.media_type) {
  3687. case ixgbe_media_type_fiber:
  3688. hw->mac.ops.set_rate_select_speed(hw,
  3689. IXGBE_LINK_SPEED_1GB_FULL);
  3690. break;
  3691. case ixgbe_media_type_fiber_qsfp:
  3692. /* QSFP module automatically detects link speed */
  3693. break;
  3694. default:
  3695. hw_dbg(hw, "Unexpected media type\n");
  3696. break;
  3697. }
  3698. /* Allow module to change analog characteristics (10G->1G) */
  3699. msleep(40);
  3700. status = hw->mac.ops.setup_mac_link(hw,
  3701. IXGBE_LINK_SPEED_1GB_FULL,
  3702. autoneg_wait_to_complete);
  3703. if (status)
  3704. return status;
  3705. /* Flap the Tx laser if it has not already been done */
  3706. if (hw->mac.ops.flap_tx_laser)
  3707. hw->mac.ops.flap_tx_laser(hw);
  3708. /* Wait for the link partner to also set speed */
  3709. msleep(100);
  3710. /* If we have link, just jump out */
  3711. status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
  3712. false);
  3713. if (status)
  3714. return status;
  3715. if (link_up)
  3716. goto out;
  3717. }
  3718. /* We didn't get link. Configure back to the highest speed we tried,
  3719. * (if there was more than one). We call ourselves back with just the
  3720. * single highest speed that the user requested.
  3721. */
  3722. if (speedcnt > 1)
  3723. status = ixgbe_setup_mac_link_multispeed_fiber(hw,
  3724. highest_link_speed,
  3725. autoneg_wait_to_complete);
  3726. out:
  3727. /* Set autoneg_advertised value based on input link speed */
  3728. hw->phy.autoneg_advertised = 0;
  3729. if (speed & IXGBE_LINK_SPEED_10GB_FULL)
  3730. hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
  3731. if (speed & IXGBE_LINK_SPEED_1GB_FULL)
  3732. hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
  3733. return status;
  3734. }
  3735. /**
  3736. * ixgbe_set_soft_rate_select_speed - Set module link speed
  3737. * @hw: pointer to hardware structure
  3738. * @speed: link speed to set
  3739. *
  3740. * Set module link speed via the soft rate select.
  3741. */
  3742. void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
  3743. ixgbe_link_speed speed)
  3744. {
  3745. s32 status;
  3746. u8 rs, eeprom_data;
  3747. switch (speed) {
  3748. case IXGBE_LINK_SPEED_10GB_FULL:
  3749. /* one bit mask same as setting on */
  3750. rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
  3751. break;
  3752. case IXGBE_LINK_SPEED_1GB_FULL:
  3753. rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
  3754. break;
  3755. default:
  3756. hw_dbg(hw, "Invalid fixed module speed\n");
  3757. return;
  3758. }
  3759. /* Set RS0 */
  3760. status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
  3761. IXGBE_I2C_EEPROM_DEV_ADDR2,
  3762. &eeprom_data);
  3763. if (status) {
  3764. hw_dbg(hw, "Failed to read Rx Rate Select RS0\n");
  3765. return;
  3766. }
  3767. eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
  3768. status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
  3769. IXGBE_I2C_EEPROM_DEV_ADDR2,
  3770. eeprom_data);
  3771. if (status) {
  3772. hw_dbg(hw, "Failed to write Rx Rate Select RS0\n");
  3773. return;
  3774. }
  3775. /* Set RS1 */
  3776. status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
  3777. IXGBE_I2C_EEPROM_DEV_ADDR2,
  3778. &eeprom_data);
  3779. if (status) {
  3780. hw_dbg(hw, "Failed to read Rx Rate Select RS1\n");
  3781. return;
  3782. }
  3783. eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
  3784. status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
  3785. IXGBE_I2C_EEPROM_DEV_ADDR2,
  3786. eeprom_data);
  3787. if (status) {
  3788. hw_dbg(hw, "Failed to write Rx Rate Select RS1\n");
  3789. return;
  3790. }
  3791. }