phy-qcom-8x16-usb.c 9.3 KB

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  1. /*
  2. * Copyright (c) 2015, Linaro Limited
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 and
  6. * only version 2 as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/delay.h>
  15. #include <linux/device.h>
  16. #include <linux/err.h>
  17. #include <linux/extcon.h>
  18. #include <linux/gpio/consumer.h>
  19. #include <linux/io.h>
  20. #include <linux/module.h>
  21. #include <linux/of.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/reboot.h>
  24. #include <linux/regulator/consumer.h>
  25. #include <linux/reset.h>
  26. #include <linux/slab.h>
  27. #include <linux/usb.h>
  28. #include <linux/usb/ulpi.h>
  29. #define HSPHY_AHBBURST 0x0090
  30. #define HSPHY_AHBMODE 0x0098
  31. #define HSPHY_GENCONFIG 0x009c
  32. #define HSPHY_GENCONFIG_2 0x00a0
  33. #define HSPHY_USBCMD 0x0140
  34. #define HSPHY_ULPI_VIEWPORT 0x0170
  35. #define HSPHY_CTRL 0x0240
  36. #define HSPHY_TXFIFO_IDLE_FORCE_DIS BIT(4)
  37. #define HSPHY_SESS_VLD_CTRL_EN BIT(7)
  38. #define HSPHY_POR_ASSERT BIT(0)
  39. #define HSPHY_RETEN BIT(1)
  40. #define HSPHY_SESS_VLD_CTRL BIT(25)
  41. #define ULPI_PWR_CLK_MNG_REG 0x88
  42. #define ULPI_PWR_OTG_COMP_DISABLE BIT(0)
  43. #define ULPI_MISC_A 0x96
  44. #define ULPI_MISC_A_VBUSVLDEXTSEL BIT(1)
  45. #define ULPI_MISC_A_VBUSVLDEXT BIT(0)
  46. #define HSPHY_3P3_MIN 3050000 /* uV */
  47. #define HSPHY_3P3_MAX 3300000 /* uV */
  48. #define HSPHY_1P8_MIN 1800000 /* uV */
  49. #define HSPHY_1P8_MAX 1800000 /* uV */
  50. #define HSPHY_VDD_MIN 5
  51. #define HSPHY_VDD_MAX 7
  52. struct phy_8x16 {
  53. struct usb_phy phy;
  54. void __iomem *regs;
  55. struct clk *core_clk;
  56. struct clk *iface_clk;
  57. struct regulator_bulk_data regulator[3];
  58. struct reset_control *phy_reset;
  59. struct gpio_desc *switch_gpio;
  60. struct notifier_block reboot_notify;
  61. };
  62. static int phy_8x16_notify_connect(struct usb_phy *phy,
  63. enum usb_device_speed speed)
  64. {
  65. struct phy_8x16 *qphy = container_of(phy, struct phy_8x16, phy);
  66. u32 val;
  67. val = ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT;
  68. usb_phy_io_write(&qphy->phy, val, ULPI_SET(ULPI_MISC_A));
  69. val = readl(qphy->regs + HSPHY_USBCMD);
  70. val |= HSPHY_SESS_VLD_CTRL;
  71. writel(val, qphy->regs + HSPHY_USBCMD);
  72. return 0;
  73. }
  74. static int phy_8x16_notify_disconnect(struct usb_phy *phy,
  75. enum usb_device_speed speed)
  76. {
  77. struct phy_8x16 *qphy = container_of(phy, struct phy_8x16, phy);
  78. u32 val;
  79. val = ULPI_MISC_A_VBUSVLDEXT | ULPI_MISC_A_VBUSVLDEXTSEL;
  80. usb_phy_io_write(&qphy->phy, val, ULPI_CLR(ULPI_MISC_A));
  81. val = readl(qphy->regs + HSPHY_USBCMD);
  82. val &= ~HSPHY_SESS_VLD_CTRL;
  83. writel(val, qphy->regs + HSPHY_USBCMD);
  84. return 0;
  85. }
  86. static int phy_8x16_vbus_on(struct phy_8x16 *qphy)
  87. {
  88. phy_8x16_notify_connect(&qphy->phy, USB_SPEED_UNKNOWN);
  89. /* Switch D+/D- lines to Device connector */
  90. gpiod_set_value_cansleep(qphy->switch_gpio, 0);
  91. return 0;
  92. }
  93. static int phy_8x16_vbus_off(struct phy_8x16 *qphy)
  94. {
  95. phy_8x16_notify_disconnect(&qphy->phy, USB_SPEED_UNKNOWN);
  96. /* Switch D+/D- lines to USB HUB */
  97. gpiod_set_value_cansleep(qphy->switch_gpio, 1);
  98. return 0;
  99. }
  100. static int phy_8x16_vbus_notify(struct notifier_block *nb, unsigned long event,
  101. void *ptr)
  102. {
  103. struct usb_phy *usb_phy = container_of(nb, struct usb_phy, vbus_nb);
  104. struct phy_8x16 *qphy = container_of(usb_phy, struct phy_8x16, phy);
  105. if (event)
  106. phy_8x16_vbus_on(qphy);
  107. else
  108. phy_8x16_vbus_off(qphy);
  109. return NOTIFY_DONE;
  110. }
  111. static int phy_8x16_init(struct usb_phy *phy)
  112. {
  113. struct phy_8x16 *qphy = container_of(phy, struct phy_8x16, phy);
  114. u32 val, init[] = {0x44, 0x6B, 0x24, 0x13};
  115. u32 addr = ULPI_EXT_VENDOR_SPECIFIC;
  116. int idx, state;
  117. for (idx = 0; idx < ARRAY_SIZE(init); idx++)
  118. usb_phy_io_write(phy, init[idx], addr + idx);
  119. reset_control_reset(qphy->phy_reset);
  120. /* Assert USB HSPHY_POR */
  121. val = readl(qphy->regs + HSPHY_CTRL);
  122. val |= HSPHY_POR_ASSERT;
  123. writel(val, qphy->regs + HSPHY_CTRL);
  124. /*
  125. * wait for minimum 10 microseconds as suggested in HPG.
  126. * Use a slightly larger value since the exact value didn't
  127. * work 100% of the time.
  128. */
  129. usleep_range(12, 15);
  130. /* Deassert USB HSPHY_POR */
  131. val = readl(qphy->regs + HSPHY_CTRL);
  132. val &= ~HSPHY_POR_ASSERT;
  133. writel(val, qphy->regs + HSPHY_CTRL);
  134. usleep_range(10, 15);
  135. writel(0x00, qphy->regs + HSPHY_AHBBURST);
  136. writel(0x08, qphy->regs + HSPHY_AHBMODE);
  137. /* workaround for rx buffer collision issue */
  138. val = readl(qphy->regs + HSPHY_GENCONFIG);
  139. val &= ~HSPHY_TXFIFO_IDLE_FORCE_DIS;
  140. writel(val, qphy->regs + HSPHY_GENCONFIG);
  141. val = readl(qphy->regs + HSPHY_GENCONFIG_2);
  142. val |= HSPHY_SESS_VLD_CTRL_EN;
  143. writel(val, qphy->regs + HSPHY_GENCONFIG_2);
  144. val = ULPI_PWR_OTG_COMP_DISABLE;
  145. usb_phy_io_write(phy, val, ULPI_SET(ULPI_PWR_CLK_MNG_REG));
  146. state = extcon_get_state(qphy->phy.edev, EXTCON_USB);
  147. if (state)
  148. phy_8x16_vbus_on(qphy);
  149. else
  150. phy_8x16_vbus_off(qphy);
  151. val = usb_phy_io_read(&qphy->phy, ULPI_FUNC_CTRL);
  152. val &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
  153. val |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
  154. usb_phy_io_write(&qphy->phy, val, ULPI_FUNC_CTRL);
  155. return 0;
  156. }
  157. static void phy_8x16_shutdown(struct usb_phy *phy)
  158. {
  159. u32 val;
  160. /* Put the controller in non-driving mode */
  161. val = usb_phy_io_read(phy, ULPI_FUNC_CTRL);
  162. val &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
  163. val |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
  164. usb_phy_io_write(phy, val, ULPI_FUNC_CTRL);
  165. }
  166. static int phy_8x16_read_devicetree(struct phy_8x16 *qphy)
  167. {
  168. struct device *dev = qphy->phy.dev;
  169. int ret;
  170. qphy->core_clk = devm_clk_get(dev, "core");
  171. if (IS_ERR(qphy->core_clk))
  172. return PTR_ERR(qphy->core_clk);
  173. qphy->iface_clk = devm_clk_get(dev, "iface");
  174. if (IS_ERR(qphy->iface_clk))
  175. return PTR_ERR(qphy->iface_clk);
  176. qphy->regulator[0].supply = "v3p3";
  177. qphy->regulator[1].supply = "v1p8";
  178. qphy->regulator[2].supply = "vddcx";
  179. ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(qphy->regulator),
  180. qphy->regulator);
  181. if (ret)
  182. return ret;
  183. qphy->phy_reset = devm_reset_control_get(dev, "phy");
  184. if (IS_ERR(qphy->phy_reset))
  185. return PTR_ERR(qphy->phy_reset);
  186. qphy->switch_gpio = devm_gpiod_get_optional(dev, "switch",
  187. GPIOD_OUT_LOW);
  188. return PTR_ERR_OR_ZERO(qphy->switch_gpio);
  189. }
  190. static int phy_8x16_reboot_notify(struct notifier_block *this,
  191. unsigned long code, void *unused)
  192. {
  193. struct phy_8x16 *qphy;
  194. qphy = container_of(this, struct phy_8x16, reboot_notify);
  195. /*
  196. * Ensure that D+/D- lines are routed to uB connector, so
  197. * we could load bootloader/kernel at next reboot_notify
  198. */
  199. gpiod_set_value_cansleep(qphy->switch_gpio, 0);
  200. return NOTIFY_DONE;
  201. }
  202. static int phy_8x16_probe(struct platform_device *pdev)
  203. {
  204. struct phy_8x16 *qphy;
  205. struct resource *res;
  206. struct usb_phy *phy;
  207. int ret;
  208. qphy = devm_kzalloc(&pdev->dev, sizeof(*qphy), GFP_KERNEL);
  209. if (!qphy)
  210. return -ENOMEM;
  211. platform_set_drvdata(pdev, qphy);
  212. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  213. qphy->regs = devm_ioremap_resource(&pdev->dev, res);
  214. if (IS_ERR(qphy->regs))
  215. return PTR_ERR(qphy->regs);
  216. phy = &qphy->phy;
  217. phy->dev = &pdev->dev;
  218. phy->label = dev_name(&pdev->dev);
  219. phy->init = phy_8x16_init;
  220. phy->shutdown = phy_8x16_shutdown;
  221. phy->notify_connect = phy_8x16_notify_connect;
  222. phy->notify_disconnect = phy_8x16_notify_disconnect;
  223. phy->io_priv = qphy->regs + HSPHY_ULPI_VIEWPORT;
  224. phy->io_ops = &ulpi_viewport_access_ops;
  225. phy->type = USB_PHY_TYPE_USB2;
  226. phy->vbus_nb.notifier_call = phy_8x16_vbus_notify;
  227. phy->id_nb.notifier_call = NULL;
  228. ret = phy_8x16_read_devicetree(qphy);
  229. if (ret < 0)
  230. return ret;
  231. ret = clk_set_rate(qphy->core_clk, INT_MAX);
  232. if (ret < 0)
  233. dev_dbg(phy->dev, "Can't boost core clock\n");
  234. ret = clk_prepare_enable(qphy->core_clk);
  235. if (ret < 0)
  236. return ret;
  237. ret = clk_prepare_enable(qphy->iface_clk);
  238. if (ret < 0)
  239. goto off_core;
  240. ret = regulator_bulk_enable(ARRAY_SIZE(qphy->regulator),
  241. qphy->regulator);
  242. if (WARN_ON(ret))
  243. goto off_clks;
  244. ret = usb_add_phy_dev(&qphy->phy);
  245. if (ret)
  246. goto off_power;
  247. qphy->reboot_notify.notifier_call = phy_8x16_reboot_notify;
  248. register_reboot_notifier(&qphy->reboot_notify);
  249. return 0;
  250. off_power:
  251. regulator_bulk_disable(ARRAY_SIZE(qphy->regulator), qphy->regulator);
  252. off_clks:
  253. clk_disable_unprepare(qphy->iface_clk);
  254. off_core:
  255. clk_disable_unprepare(qphy->core_clk);
  256. return ret;
  257. }
  258. static int phy_8x16_remove(struct platform_device *pdev)
  259. {
  260. struct phy_8x16 *qphy = platform_get_drvdata(pdev);
  261. unregister_reboot_notifier(&qphy->reboot_notify);
  262. /*
  263. * Ensure that D+/D- lines are routed to uB connector, so
  264. * we could load bootloader/kernel at next reboot_notify
  265. */
  266. gpiod_set_value_cansleep(qphy->switch_gpio, 0);
  267. usb_remove_phy(&qphy->phy);
  268. clk_disable_unprepare(qphy->iface_clk);
  269. clk_disable_unprepare(qphy->core_clk);
  270. regulator_bulk_disable(ARRAY_SIZE(qphy->regulator), qphy->regulator);
  271. return 0;
  272. }
  273. static const struct of_device_id phy_8x16_dt_match[] = {
  274. { .compatible = "qcom,usb-8x16-phy" },
  275. { }
  276. };
  277. MODULE_DEVICE_TABLE(of, phy_8x16_dt_match);
  278. static struct platform_driver phy_8x16_driver = {
  279. .probe = phy_8x16_probe,
  280. .remove = phy_8x16_remove,
  281. .driver = {
  282. .name = "phy-qcom-8x16-usb",
  283. .of_match_table = phy_8x16_dt_match,
  284. },
  285. };
  286. module_platform_driver(phy_8x16_driver);
  287. MODULE_LICENSE("GPL v2");
  288. MODULE_DESCRIPTION("Qualcomm APQ8016/MSM8916 chipsets USB transceiver driver");