xhci-rcar.c 6.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247
  1. /*
  2. * xHCI host controller driver for R-Car SoCs
  3. *
  4. * Copyright (C) 2014 Renesas Electronics Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. */
  10. #include <linux/firmware.h>
  11. #include <linux/module.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/of.h>
  14. #include <linux/usb/phy.h>
  15. #include <linux/sys_soc.h>
  16. #include "xhci.h"
  17. #include "xhci-plat.h"
  18. #include "xhci-rcar.h"
  19. /*
  20. * - The V3 firmware is for r8a7796 (with good performance) and r8a7795 es2.0
  21. * or later.
  22. * - The V2 firmware can be used on both r8a7795 (es1.x) and r8a7796.
  23. * - The V2 firmware is possible to use on R-Car Gen2. However, the V2 causes
  24. * performance degradation. So, this driver continues to use the V1 if R-Car
  25. * Gen2.
  26. * - The V1 firmware is impossible to use on R-Car Gen3.
  27. */
  28. MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V1);
  29. MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V2);
  30. MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V3);
  31. /*** Register Offset ***/
  32. #define RCAR_USB3_INT_ENA 0x224 /* Interrupt Enable */
  33. #define RCAR_USB3_DL_CTRL 0x250 /* FW Download Control & Status */
  34. #define RCAR_USB3_FW_DATA0 0x258 /* FW Data0 */
  35. #define RCAR_USB3_LCLK 0xa44 /* LCLK Select */
  36. #define RCAR_USB3_CONF1 0xa48 /* USB3.0 Configuration1 */
  37. #define RCAR_USB3_CONF2 0xa5c /* USB3.0 Configuration2 */
  38. #define RCAR_USB3_CONF3 0xaa8 /* USB3.0 Configuration3 */
  39. #define RCAR_USB3_RX_POL 0xab0 /* USB3.0 RX Polarity */
  40. #define RCAR_USB3_TX_POL 0xab8 /* USB3.0 TX Polarity */
  41. /*** Register Settings ***/
  42. /* Interrupt Enable */
  43. #define RCAR_USB3_INT_XHC_ENA 0x00000001
  44. #define RCAR_USB3_INT_PME_ENA 0x00000002
  45. #define RCAR_USB3_INT_HSE_ENA 0x00000004
  46. #define RCAR_USB3_INT_ENA_VAL (RCAR_USB3_INT_XHC_ENA | \
  47. RCAR_USB3_INT_PME_ENA | RCAR_USB3_INT_HSE_ENA)
  48. /* FW Download Control & Status */
  49. #define RCAR_USB3_DL_CTRL_ENABLE 0x00000001
  50. #define RCAR_USB3_DL_CTRL_FW_SUCCESS 0x00000010
  51. #define RCAR_USB3_DL_CTRL_FW_SET_DATA0 0x00000100
  52. /* LCLK Select */
  53. #define RCAR_USB3_LCLK_ENA_VAL 0x01030001
  54. /* USB3.0 Configuration */
  55. #define RCAR_USB3_CONF1_VAL 0x00030204
  56. #define RCAR_USB3_CONF2_VAL 0x00030300
  57. #define RCAR_USB3_CONF3_VAL 0x13802007
  58. /* USB3.0 Polarity */
  59. #define RCAR_USB3_RX_POL_VAL BIT(21)
  60. #define RCAR_USB3_TX_POL_VAL BIT(4)
  61. /* For soc_device_attribute */
  62. #define RCAR_XHCI_FIRMWARE_V2 BIT(0) /* FIRMWARE V2 */
  63. #define RCAR_XHCI_FIRMWARE_V3 BIT(1) /* FIRMWARE V3 */
  64. static const struct soc_device_attribute rcar_quirks_match[] = {
  65. {
  66. .soc_id = "r8a7795", .revision = "ES1.*",
  67. .data = (void *)RCAR_XHCI_FIRMWARE_V2,
  68. },
  69. {
  70. .soc_id = "r8a7795",
  71. .data = (void *)RCAR_XHCI_FIRMWARE_V3,
  72. },
  73. {
  74. .soc_id = "r8a7796",
  75. .data = (void *)RCAR_XHCI_FIRMWARE_V3,
  76. },
  77. { /* sentinel */ },
  78. };
  79. static void xhci_rcar_start_gen2(struct usb_hcd *hcd)
  80. {
  81. /* LCLK Select */
  82. writel(RCAR_USB3_LCLK_ENA_VAL, hcd->regs + RCAR_USB3_LCLK);
  83. /* USB3.0 Configuration */
  84. writel(RCAR_USB3_CONF1_VAL, hcd->regs + RCAR_USB3_CONF1);
  85. writel(RCAR_USB3_CONF2_VAL, hcd->regs + RCAR_USB3_CONF2);
  86. writel(RCAR_USB3_CONF3_VAL, hcd->regs + RCAR_USB3_CONF3);
  87. /* USB3.0 Polarity */
  88. writel(RCAR_USB3_RX_POL_VAL, hcd->regs + RCAR_USB3_RX_POL);
  89. writel(RCAR_USB3_TX_POL_VAL, hcd->regs + RCAR_USB3_TX_POL);
  90. }
  91. static int xhci_rcar_is_gen2(struct device *dev)
  92. {
  93. struct device_node *node = dev->of_node;
  94. return of_device_is_compatible(node, "renesas,xhci-r8a7790") ||
  95. of_device_is_compatible(node, "renesas,xhci-r8a7791") ||
  96. of_device_is_compatible(node, "renesas,xhci-r8a7793") ||
  97. of_device_is_compatible(node, "renensas,rcar-gen2-xhci");
  98. }
  99. static int xhci_rcar_is_gen3(struct device *dev)
  100. {
  101. struct device_node *node = dev->of_node;
  102. return of_device_is_compatible(node, "renesas,xhci-r8a7795") ||
  103. of_device_is_compatible(node, "renesas,xhci-r8a7796") ||
  104. of_device_is_compatible(node, "renesas,rcar-gen3-xhci");
  105. }
  106. void xhci_rcar_start(struct usb_hcd *hcd)
  107. {
  108. u32 temp;
  109. if (hcd->regs != NULL) {
  110. /* Interrupt Enable */
  111. temp = readl(hcd->regs + RCAR_USB3_INT_ENA);
  112. temp |= RCAR_USB3_INT_ENA_VAL;
  113. writel(temp, hcd->regs + RCAR_USB3_INT_ENA);
  114. if (xhci_rcar_is_gen2(hcd->self.controller))
  115. xhci_rcar_start_gen2(hcd);
  116. }
  117. }
  118. static int xhci_rcar_download_firmware(struct usb_hcd *hcd)
  119. {
  120. struct device *dev = hcd->self.controller;
  121. void __iomem *regs = hcd->regs;
  122. struct xhci_plat_priv *priv = hcd_to_xhci_priv(hcd);
  123. const struct firmware *fw;
  124. int retval, index, j, time;
  125. int timeout = 10000;
  126. u32 data, val, temp;
  127. u32 quirks = 0;
  128. const struct soc_device_attribute *attr;
  129. const char *firmware_name;
  130. attr = soc_device_match(rcar_quirks_match);
  131. if (attr)
  132. quirks = (uintptr_t)attr->data;
  133. if (quirks & RCAR_XHCI_FIRMWARE_V2)
  134. firmware_name = XHCI_RCAR_FIRMWARE_NAME_V2;
  135. else if (quirks & RCAR_XHCI_FIRMWARE_V3)
  136. firmware_name = XHCI_RCAR_FIRMWARE_NAME_V3;
  137. else
  138. firmware_name = priv->firmware_name;
  139. /* request R-Car USB3.0 firmware */
  140. retval = request_firmware(&fw, firmware_name, dev);
  141. if (retval)
  142. return retval;
  143. /* download R-Car USB3.0 firmware */
  144. temp = readl(regs + RCAR_USB3_DL_CTRL);
  145. temp |= RCAR_USB3_DL_CTRL_ENABLE;
  146. writel(temp, regs + RCAR_USB3_DL_CTRL);
  147. for (index = 0; index < fw->size; index += 4) {
  148. /* to avoid reading beyond the end of the buffer */
  149. for (data = 0, j = 3; j >= 0; j--) {
  150. if ((j + index) < fw->size)
  151. data |= fw->data[index + j] << (8 * j);
  152. }
  153. writel(data, regs + RCAR_USB3_FW_DATA0);
  154. temp = readl(regs + RCAR_USB3_DL_CTRL);
  155. temp |= RCAR_USB3_DL_CTRL_FW_SET_DATA0;
  156. writel(temp, regs + RCAR_USB3_DL_CTRL);
  157. for (time = 0; time < timeout; time++) {
  158. val = readl(regs + RCAR_USB3_DL_CTRL);
  159. if ((val & RCAR_USB3_DL_CTRL_FW_SET_DATA0) == 0)
  160. break;
  161. udelay(1);
  162. }
  163. if (time == timeout) {
  164. retval = -ETIMEDOUT;
  165. break;
  166. }
  167. }
  168. temp = readl(regs + RCAR_USB3_DL_CTRL);
  169. temp &= ~RCAR_USB3_DL_CTRL_ENABLE;
  170. writel(temp, regs + RCAR_USB3_DL_CTRL);
  171. for (time = 0; time < timeout; time++) {
  172. val = readl(regs + RCAR_USB3_DL_CTRL);
  173. if (val & RCAR_USB3_DL_CTRL_FW_SUCCESS) {
  174. retval = 0;
  175. break;
  176. }
  177. udelay(1);
  178. }
  179. if (time == timeout)
  180. retval = -ETIMEDOUT;
  181. release_firmware(fw);
  182. return retval;
  183. }
  184. /* This function needs to initialize a "phy" of usb before */
  185. int xhci_rcar_init_quirk(struct usb_hcd *hcd)
  186. {
  187. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  188. /* If hcd->regs is NULL, we don't just call the following function */
  189. if (!hcd->regs)
  190. return 0;
  191. /*
  192. * On R-Car Gen2 and Gen3, the AC64 bit (bit 0) of HCCPARAMS1 is set
  193. * to 1. However, these SoCs don't support 64-bit address memory
  194. * pointers. So, this driver clears the AC64 bit of xhci->hcc_params
  195. * to call dma_set_coherent_mask(dev, DMA_BIT_MASK(32)) in
  196. * xhci_gen_setup().
  197. */
  198. if (xhci_rcar_is_gen2(hcd->self.controller) ||
  199. xhci_rcar_is_gen3(hcd->self.controller))
  200. xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
  201. return xhci_rcar_download_firmware(hcd);
  202. }
  203. int xhci_rcar_resume_quirk(struct usb_hcd *hcd)
  204. {
  205. int ret;
  206. ret = xhci_rcar_download_firmware(hcd);
  207. if (!ret)
  208. xhci_rcar_start(hcd);
  209. return ret;
  210. }