dwc3-pci.c 10 KB

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  1. /**
  2. * dwc3-pci.c - PCI Specific glue layer
  3. *
  4. * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
  5. *
  6. * Authors: Felipe Balbi <balbi@ti.com>,
  7. * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  8. *
  9. * This program is free software: you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 of
  11. * the License as published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. */
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/slab.h>
  21. #include <linux/pci.h>
  22. #include <linux/pm_runtime.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/gpio/consumer.h>
  25. #include <linux/acpi.h>
  26. #include <linux/delay.h>
  27. #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 0xabcd
  28. #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI 0xabce
  29. #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31 0xabcf
  30. #define PCI_DEVICE_ID_INTEL_BYT 0x0f37
  31. #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e
  32. #define PCI_DEVICE_ID_INTEL_BSW 0x22b7
  33. #define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30
  34. #define PCI_DEVICE_ID_INTEL_SPTH 0xa130
  35. #define PCI_DEVICE_ID_INTEL_BXT 0x0aaa
  36. #define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa
  37. #define PCI_DEVICE_ID_INTEL_APL 0x5aaa
  38. #define PCI_DEVICE_ID_INTEL_KBP 0xa2b0
  39. #define PCI_DEVICE_ID_INTEL_GLK 0x31aa
  40. #define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee
  41. #define PCI_DEVICE_ID_INTEL_CNPH 0xa36e
  42. #define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
  43. #define PCI_INTEL_BXT_FUNC_PMU_PWR 4
  44. #define PCI_INTEL_BXT_STATE_D0 0
  45. #define PCI_INTEL_BXT_STATE_D3 3
  46. /**
  47. * struct dwc3_pci - Driver private structure
  48. * @dwc3: child dwc3 platform_device
  49. * @pci: our link to PCI bus
  50. * @guid: _DSM GUID
  51. * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
  52. */
  53. struct dwc3_pci {
  54. struct platform_device *dwc3;
  55. struct pci_dev *pci;
  56. guid_t guid;
  57. unsigned int has_dsm_for_pm:1;
  58. };
  59. static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
  60. static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
  61. static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
  62. { "reset-gpios", &reset_gpios, 1 },
  63. { "cs-gpios", &cs_gpios, 1 },
  64. { },
  65. };
  66. static int dwc3_pci_quirks(struct dwc3_pci *dwc)
  67. {
  68. struct platform_device *dwc3 = dwc->dwc3;
  69. struct pci_dev *pdev = dwc->pci;
  70. if (pdev->vendor == PCI_VENDOR_ID_AMD &&
  71. pdev->device == PCI_DEVICE_ID_AMD_NL_USB) {
  72. struct property_entry properties[] = {
  73. PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
  74. PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
  75. PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
  76. PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
  77. PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
  78. PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
  79. PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
  80. PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
  81. PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
  82. PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
  83. PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
  84. /*
  85. * FIXME these quirks should be removed when AMD NL
  86. * tapes out
  87. */
  88. PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
  89. PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
  90. PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
  91. PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
  92. { },
  93. };
  94. return platform_device_add_properties(dwc3, properties);
  95. }
  96. if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
  97. int ret;
  98. struct property_entry properties[] = {
  99. PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
  100. PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
  101. { }
  102. };
  103. ret = platform_device_add_properties(dwc3, properties);
  104. if (ret < 0)
  105. return ret;
  106. if (pdev->device == PCI_DEVICE_ID_INTEL_BXT ||
  107. pdev->device == PCI_DEVICE_ID_INTEL_BXT_M) {
  108. guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid);
  109. dwc->has_dsm_for_pm = true;
  110. }
  111. if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
  112. struct gpio_desc *gpio;
  113. ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
  114. acpi_dwc3_byt_gpios);
  115. if (ret)
  116. dev_dbg(&pdev->dev, "failed to add mapping table\n");
  117. /*
  118. * These GPIOs will turn on the USB2 PHY. Note that we have to
  119. * put the gpio descriptors again here because the phy driver
  120. * might want to grab them, too.
  121. */
  122. gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
  123. if (IS_ERR(gpio))
  124. return PTR_ERR(gpio);
  125. gpiod_set_value_cansleep(gpio, 1);
  126. gpiod_put(gpio);
  127. gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
  128. if (IS_ERR(gpio))
  129. return PTR_ERR(gpio);
  130. if (gpio) {
  131. gpiod_set_value_cansleep(gpio, 1);
  132. gpiod_put(gpio);
  133. usleep_range(10000, 11000);
  134. }
  135. }
  136. }
  137. if (pdev->vendor == PCI_VENDOR_ID_SYNOPSYS &&
  138. (pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 ||
  139. pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI ||
  140. pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31)) {
  141. struct property_entry properties[] = {
  142. PROPERTY_ENTRY_BOOL("snps,usb3_lpm_capable"),
  143. PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
  144. PROPERTY_ENTRY_BOOL("snps,dis_enblslpm_quirk"),
  145. PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
  146. { },
  147. };
  148. return platform_device_add_properties(dwc3, properties);
  149. }
  150. return 0;
  151. }
  152. static int dwc3_pci_probe(struct pci_dev *pci,
  153. const struct pci_device_id *id)
  154. {
  155. struct dwc3_pci *dwc;
  156. struct resource res[2];
  157. int ret;
  158. struct device *dev = &pci->dev;
  159. ret = pcim_enable_device(pci);
  160. if (ret) {
  161. dev_err(dev, "failed to enable pci device\n");
  162. return -ENODEV;
  163. }
  164. pci_set_master(pci);
  165. dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
  166. if (!dwc)
  167. return -ENOMEM;
  168. dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
  169. if (!dwc->dwc3)
  170. return -ENOMEM;
  171. memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
  172. res[0].start = pci_resource_start(pci, 0);
  173. res[0].end = pci_resource_end(pci, 0);
  174. res[0].name = "dwc_usb3";
  175. res[0].flags = IORESOURCE_MEM;
  176. res[1].start = pci->irq;
  177. res[1].name = "dwc_usb3";
  178. res[1].flags = IORESOURCE_IRQ;
  179. ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
  180. if (ret) {
  181. dev_err(dev, "couldn't add resources to dwc3 device\n");
  182. return ret;
  183. }
  184. dwc->pci = pci;
  185. dwc->dwc3->dev.parent = dev;
  186. ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));
  187. ret = dwc3_pci_quirks(dwc);
  188. if (ret)
  189. goto err;
  190. ret = platform_device_add(dwc->dwc3);
  191. if (ret) {
  192. dev_err(dev, "failed to register dwc3 device\n");
  193. goto err;
  194. }
  195. device_init_wakeup(dev, true);
  196. pci_set_drvdata(pci, dwc);
  197. pm_runtime_put(dev);
  198. return 0;
  199. err:
  200. platform_device_put(dwc->dwc3);
  201. return ret;
  202. }
  203. static void dwc3_pci_remove(struct pci_dev *pci)
  204. {
  205. struct dwc3_pci *dwc = pci_get_drvdata(pci);
  206. device_init_wakeup(&pci->dev, false);
  207. pm_runtime_get(&pci->dev);
  208. platform_device_unregister(dwc->dwc3);
  209. }
  210. static const struct pci_device_id dwc3_pci_id_table[] = {
  211. {
  212. PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
  213. PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3),
  214. },
  215. {
  216. PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
  217. PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI),
  218. },
  219. {
  220. PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
  221. PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31),
  222. },
  223. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW), },
  224. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT), },
  225. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MRFLD), },
  226. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SPTLP), },
  227. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SPTH), },
  228. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BXT), },
  229. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BXT_M), },
  230. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL), },
  231. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBP), },
  232. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GLK), },
  233. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CNPLP), },
  234. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CNPH), },
  235. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB), },
  236. { } /* Terminating Entry */
  237. };
  238. MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
  239. #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP)
  240. static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
  241. {
  242. union acpi_object *obj;
  243. union acpi_object tmp;
  244. union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
  245. if (!dwc->has_dsm_for_pm)
  246. return 0;
  247. tmp.type = ACPI_TYPE_INTEGER;
  248. tmp.integer.value = param;
  249. obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid,
  250. 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
  251. if (!obj) {
  252. dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
  253. return -EIO;
  254. }
  255. ACPI_FREE(obj);
  256. return 0;
  257. }
  258. #endif /* CONFIG_PM || CONFIG_PM_SLEEP */
  259. #ifdef CONFIG_PM
  260. static int dwc3_pci_runtime_suspend(struct device *dev)
  261. {
  262. struct dwc3_pci *dwc = dev_get_drvdata(dev);
  263. if (device_can_wakeup(dev))
  264. return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
  265. return -EBUSY;
  266. }
  267. static int dwc3_pci_runtime_resume(struct device *dev)
  268. {
  269. struct dwc3_pci *dwc = dev_get_drvdata(dev);
  270. struct platform_device *dwc3 = dwc->dwc3;
  271. int ret;
  272. ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
  273. if (ret)
  274. return ret;
  275. return pm_runtime_get(&dwc3->dev);
  276. }
  277. #endif /* CONFIG_PM */
  278. #ifdef CONFIG_PM_SLEEP
  279. static int dwc3_pci_suspend(struct device *dev)
  280. {
  281. struct dwc3_pci *dwc = dev_get_drvdata(dev);
  282. return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
  283. }
  284. static int dwc3_pci_resume(struct device *dev)
  285. {
  286. struct dwc3_pci *dwc = dev_get_drvdata(dev);
  287. return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
  288. }
  289. #endif /* CONFIG_PM_SLEEP */
  290. static const struct dev_pm_ops dwc3_pci_dev_pm_ops = {
  291. SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
  292. SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
  293. NULL)
  294. };
  295. static struct pci_driver dwc3_pci_driver = {
  296. .name = "dwc3-pci",
  297. .id_table = dwc3_pci_id_table,
  298. .probe = dwc3_pci_probe,
  299. .remove = dwc3_pci_remove,
  300. .driver = {
  301. .pm = &dwc3_pci_dev_pm_ops,
  302. }
  303. };
  304. MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
  305. MODULE_LICENSE("GPL v2");
  306. MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
  307. module_pci_driver(dwc3_pci_driver);