Kconfig 3.1 KB

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  1. config USB_DWC3
  2. tristate "DesignWare USB3 DRD Core Support"
  3. depends on (USB || USB_GADGET) && HAS_DMA
  4. select USB_XHCI_PLATFORM if USB_XHCI_HCD
  5. help
  6. Say Y or M here if your system has a Dual Role SuperSpeed
  7. USB controller based on the DesignWare USB3 IP Core.
  8. If you choose to build this driver is a dynamically linked
  9. module, the module will be called dwc3.ko.
  10. if USB_DWC3
  11. config USB_DWC3_ULPI
  12. bool "Register ULPI PHY Interface"
  13. depends on USB_ULPI_BUS=y || USB_ULPI_BUS=USB_DWC3
  14. help
  15. Select this if you have ULPI type PHY attached to your DWC3
  16. controller.
  17. choice
  18. bool "DWC3 Mode Selection"
  19. default USB_DWC3_DUAL_ROLE if (USB && USB_GADGET)
  20. default USB_DWC3_HOST if (USB && !USB_GADGET)
  21. default USB_DWC3_GADGET if (!USB && USB_GADGET)
  22. config USB_DWC3_HOST
  23. bool "Host only mode"
  24. depends on USB=y || USB=USB_DWC3
  25. help
  26. Select this when you want to use DWC3 in host mode only,
  27. thereby the gadget feature will be regressed.
  28. config USB_DWC3_GADGET
  29. bool "Gadget only mode"
  30. depends on USB_GADGET=y || USB_GADGET=USB_DWC3
  31. help
  32. Select this when you want to use DWC3 in gadget mode only,
  33. thereby the host feature will be regressed.
  34. config USB_DWC3_DUAL_ROLE
  35. bool "Dual Role mode"
  36. depends on ((USB=y || USB=USB_DWC3) && (USB_GADGET=y || USB_GADGET=USB_DWC3))
  37. depends on (EXTCON=y || EXTCON=USB_DWC3)
  38. help
  39. This is the default mode of working of DWC3 controller where
  40. both host and gadget features are enabled.
  41. endchoice
  42. comment "Platform Glue Driver Support"
  43. config USB_DWC3_OMAP
  44. tristate "Texas Instruments OMAP5 and similar Platforms"
  45. depends on EXTCON && (ARCH_OMAP2PLUS || COMPILE_TEST)
  46. depends on OF
  47. default USB_DWC3
  48. help
  49. Some platforms from Texas Instruments like OMAP5, DRA7xxx and
  50. AM437x use this IP for USB2/3 functionality.
  51. Say 'Y' or 'M' here if you have one such device
  52. config USB_DWC3_EXYNOS
  53. tristate "Samsung Exynos Platform"
  54. depends on (ARCH_EXYNOS || COMPILE_TEST) && OF
  55. default USB_DWC3
  56. help
  57. Recent Exynos5 SoCs ship with one DesignWare Core USB3 IP inside,
  58. say 'Y' or 'M' if you have one such device.
  59. config USB_DWC3_PCI
  60. tristate "PCIe-based Platforms"
  61. depends on USB_PCI && ACPI
  62. default USB_DWC3
  63. help
  64. If you're using the DesignWare Core IP with a PCIe, please say
  65. 'Y' or 'M' here.
  66. One such PCIe-based platform is Synopsys' PCIe HAPS model of
  67. this IP.
  68. config USB_DWC3_KEYSTONE
  69. tristate "Texas Instruments Keystone2 Platforms"
  70. depends on ARCH_KEYSTONE || COMPILE_TEST
  71. default USB_DWC3
  72. help
  73. Support of USB2/3 functionality in TI Keystone2 platforms.
  74. Say 'Y' or 'M' here if you have one such device
  75. config USB_DWC3_OF_SIMPLE
  76. tristate "Generic OF Simple Glue Layer"
  77. depends on OF && COMMON_CLK
  78. default USB_DWC3
  79. help
  80. Support USB2/3 functionality in simple SoC integrations.
  81. Currently supports Xilinx and Qualcomm DWC USB3 IP.
  82. Say 'Y' or 'M' if you have one such device.
  83. config USB_DWC3_ST
  84. tristate "STMicroelectronics Platforms"
  85. depends on (ARCH_STI || COMPILE_TEST) && OF
  86. default USB_DWC3
  87. help
  88. STMicroelectronics SoCs with one DesignWare Core USB3 IP
  89. inside (i.e. STiH407).
  90. Say 'Y' or 'M' if you have one such device.
  91. endif