reset-socfpga.c 4.0 KB

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  1. /*
  2. * Socfpga Reset Controller Driver
  3. *
  4. * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
  5. *
  6. * based on
  7. * Allwinner SoCs Reset Controller driver
  8. *
  9. * Copyright 2013 Maxime Ripard
  10. *
  11. * Maxime Ripard <maxime.ripard@free-electrons.com>
  12. *
  13. * This program is free software; you can redistribute it and/or modify
  14. * it under the terms of the GNU General Public License as published by
  15. * the Free Software Foundation; either version 2 of the License, or
  16. * (at your option) any later version.
  17. */
  18. #include <linux/err.h>
  19. #include <linux/io.h>
  20. #include <linux/init.h>
  21. #include <linux/of.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/reset-controller.h>
  24. #include <linux/spinlock.h>
  25. #include <linux/types.h>
  26. #define BANK_INCREMENT 4
  27. #define NR_BANKS 8
  28. struct socfpga_reset_data {
  29. spinlock_t lock;
  30. void __iomem *membase;
  31. struct reset_controller_dev rcdev;
  32. };
  33. static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
  34. unsigned long id)
  35. {
  36. struct socfpga_reset_data *data = container_of(rcdev,
  37. struct socfpga_reset_data,
  38. rcdev);
  39. int bank = id / BITS_PER_LONG;
  40. int offset = id % BITS_PER_LONG;
  41. unsigned long flags;
  42. u32 reg;
  43. spin_lock_irqsave(&data->lock, flags);
  44. reg = readl(data->membase + (bank * BANK_INCREMENT));
  45. writel(reg | BIT(offset), data->membase + (bank * BANK_INCREMENT));
  46. spin_unlock_irqrestore(&data->lock, flags);
  47. return 0;
  48. }
  49. static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
  50. unsigned long id)
  51. {
  52. struct socfpga_reset_data *data = container_of(rcdev,
  53. struct socfpga_reset_data,
  54. rcdev);
  55. int bank = id / BITS_PER_LONG;
  56. int offset = id % BITS_PER_LONG;
  57. unsigned long flags;
  58. u32 reg;
  59. spin_lock_irqsave(&data->lock, flags);
  60. reg = readl(data->membase + (bank * BANK_INCREMENT));
  61. writel(reg & ~BIT(offset), data->membase + (bank * BANK_INCREMENT));
  62. spin_unlock_irqrestore(&data->lock, flags);
  63. return 0;
  64. }
  65. static int socfpga_reset_status(struct reset_controller_dev *rcdev,
  66. unsigned long id)
  67. {
  68. struct socfpga_reset_data *data = container_of(rcdev,
  69. struct socfpga_reset_data, rcdev);
  70. int bank = id / BITS_PER_LONG;
  71. int offset = id % BITS_PER_LONG;
  72. u32 reg;
  73. reg = readl(data->membase + (bank * BANK_INCREMENT));
  74. return !(reg & BIT(offset));
  75. }
  76. static const struct reset_control_ops socfpga_reset_ops = {
  77. .assert = socfpga_reset_assert,
  78. .deassert = socfpga_reset_deassert,
  79. .status = socfpga_reset_status,
  80. };
  81. static int socfpga_reset_probe(struct platform_device *pdev)
  82. {
  83. struct socfpga_reset_data *data;
  84. struct resource *res;
  85. struct device *dev = &pdev->dev;
  86. struct device_node *np = dev->of_node;
  87. u32 modrst_offset;
  88. /*
  89. * The binding was mainlined without the required property.
  90. * Do not continue, when we encounter an old DT.
  91. */
  92. if (!of_find_property(pdev->dev.of_node, "#reset-cells", NULL)) {
  93. dev_err(&pdev->dev, "%pOF missing #reset-cells property\n",
  94. pdev->dev.of_node);
  95. return -EINVAL;
  96. }
  97. data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
  98. if (!data)
  99. return -ENOMEM;
  100. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  101. data->membase = devm_ioremap_resource(&pdev->dev, res);
  102. if (IS_ERR(data->membase))
  103. return PTR_ERR(data->membase);
  104. if (of_property_read_u32(np, "altr,modrst-offset", &modrst_offset)) {
  105. dev_warn(dev, "missing altr,modrst-offset property, assuming 0x10!\n");
  106. modrst_offset = 0x10;
  107. }
  108. data->membase += modrst_offset;
  109. spin_lock_init(&data->lock);
  110. data->rcdev.owner = THIS_MODULE;
  111. data->rcdev.nr_resets = NR_BANKS * BITS_PER_LONG;
  112. data->rcdev.ops = &socfpga_reset_ops;
  113. data->rcdev.of_node = pdev->dev.of_node;
  114. return devm_reset_controller_register(dev, &data->rcdev);
  115. }
  116. static const struct of_device_id socfpga_reset_dt_ids[] = {
  117. { .compatible = "altr,rst-mgr", },
  118. { /* sentinel */ },
  119. };
  120. static struct platform_driver socfpga_reset_driver = {
  121. .probe = socfpga_reset_probe,
  122. .driver = {
  123. .name = "socfpga-reset",
  124. .of_match_table = socfpga_reset_dt_ids,
  125. },
  126. };
  127. builtin_platform_driver(socfpga_reset_driver);