iwl-nvm-parse.c 31 KB

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  1. /******************************************************************************
  2. *
  3. * This file is provided under a dual BSD/GPLv2 license. When using or
  4. * redistributing this file, you may do so under either license.
  5. *
  6. * GPL LICENSE SUMMARY
  7. *
  8. * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
  9. * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10. * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of version 2 of the GNU General Public License as
  14. * published by the Free Software Foundation.
  15. *
  16. * This program is distributed in the hope that it will be useful, but
  17. * WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19. * General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  24. * USA
  25. *
  26. * The full GNU General Public License is included in this distribution
  27. * in the file called COPYING.
  28. *
  29. * Contact Information:
  30. * Intel Linux Wireless <linuxwifi@intel.com>
  31. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  32. *
  33. * BSD LICENSE
  34. *
  35. * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
  36. * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  37. * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  38. * All rights reserved.
  39. *
  40. * Redistribution and use in source and binary forms, with or without
  41. * modification, are permitted provided that the following conditions
  42. * are met:
  43. *
  44. * * Redistributions of source code must retain the above copyright
  45. * notice, this list of conditions and the following disclaimer.
  46. * * Redistributions in binary form must reproduce the above copyright
  47. * notice, this list of conditions and the following disclaimer in
  48. * the documentation and/or other materials provided with the
  49. * distribution.
  50. * * Neither the name Intel Corporation nor the names of its
  51. * contributors may be used to endorse or promote products derived
  52. * from this software without specific prior written permission.
  53. *
  54. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  55. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  56. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  57. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  58. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  59. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  60. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  61. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  62. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  63. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  64. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  65. *****************************************************************************/
  66. #include <linux/types.h>
  67. #include <linux/slab.h>
  68. #include <linux/export.h>
  69. #include <linux/etherdevice.h>
  70. #include <linux/pci.h>
  71. #include <linux/acpi.h>
  72. #include "iwl-drv.h"
  73. #include "iwl-modparams.h"
  74. #include "iwl-nvm-parse.h"
  75. #include "iwl-prph.h"
  76. #include "iwl-io.h"
  77. #include "iwl-csr.h"
  78. /* NVM offsets (in words) definitions */
  79. enum wkp_nvm_offsets {
  80. /* NVM HW-Section offset (in words) definitions */
  81. SUBSYSTEM_ID = 0x0A,
  82. HW_ADDR = 0x15,
  83. /* NVM SW-Section offset (in words) definitions */
  84. NVM_SW_SECTION = 0x1C0,
  85. NVM_VERSION = 0,
  86. RADIO_CFG = 1,
  87. SKU = 2,
  88. N_HW_ADDRS = 3,
  89. NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION,
  90. /* NVM calibration section offset (in words) definitions */
  91. NVM_CALIB_SECTION = 0x2B8,
  92. XTAL_CALIB = 0x316 - NVM_CALIB_SECTION
  93. };
  94. enum ext_nvm_offsets {
  95. /* NVM HW-Section offset (in words) definitions */
  96. MAC_ADDRESS_OVERRIDE_EXT_NVM = 1,
  97. /* NVM SW-Section offset (in words) definitions */
  98. NVM_VERSION_EXT_NVM = 0,
  99. RADIO_CFG_FAMILY_EXT_NVM = 0,
  100. SKU_FAMILY_8000 = 2,
  101. N_HW_ADDRS_FAMILY_8000 = 3,
  102. /* NVM REGULATORY -Section offset (in words) definitions */
  103. NVM_CHANNELS_EXTENDED = 0,
  104. NVM_LAR_OFFSET_OLD = 0x4C7,
  105. NVM_LAR_OFFSET = 0x507,
  106. NVM_LAR_ENABLED = 0x7,
  107. };
  108. /* SKU Capabilities (actual values from NVM definition) */
  109. enum nvm_sku_bits {
  110. NVM_SKU_CAP_BAND_24GHZ = BIT(0),
  111. NVM_SKU_CAP_BAND_52GHZ = BIT(1),
  112. NVM_SKU_CAP_11N_ENABLE = BIT(2),
  113. NVM_SKU_CAP_11AC_ENABLE = BIT(3),
  114. NVM_SKU_CAP_MIMO_DISABLE = BIT(5),
  115. };
  116. /*
  117. * These are the channel numbers in the order that they are stored in the NVM
  118. */
  119. static const u8 iwl_nvm_channels[] = {
  120. /* 2.4 GHz */
  121. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
  122. /* 5 GHz */
  123. 36, 40, 44 , 48, 52, 56, 60, 64,
  124. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
  125. 149, 153, 157, 161, 165
  126. };
  127. static const u8 iwl_ext_nvm_channels[] = {
  128. /* 2.4 GHz */
  129. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
  130. /* 5 GHz */
  131. 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
  132. 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
  133. 149, 153, 157, 161, 165, 169, 173, 177, 181
  134. };
  135. #define IWL_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels)
  136. #define IWL_NUM_CHANNELS_EXT ARRAY_SIZE(iwl_ext_nvm_channels)
  137. #define NUM_2GHZ_CHANNELS 14
  138. #define NUM_2GHZ_CHANNELS_EXT 14
  139. #define FIRST_2GHZ_HT_MINUS 5
  140. #define LAST_2GHZ_HT_PLUS 9
  141. #define LAST_5GHZ_HT 165
  142. #define LAST_5GHZ_HT_FAMILY_8000 181
  143. #define N_HW_ADDR_MASK 0xF
  144. /* rate data (static) */
  145. static struct ieee80211_rate iwl_cfg80211_rates[] = {
  146. { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, },
  147. { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1,
  148. .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
  149. { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2,
  150. .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
  151. { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3,
  152. .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
  153. { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, },
  154. { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, },
  155. { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, },
  156. { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, },
  157. { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, },
  158. { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, },
  159. { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, },
  160. { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, },
  161. };
  162. #define RATES_24_OFFS 0
  163. #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates)
  164. #define RATES_52_OFFS 4
  165. #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS)
  166. /**
  167. * enum iwl_nvm_channel_flags - channel flags in NVM
  168. * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo
  169. * @NVM_CHANNEL_IBSS: usable as an IBSS channel
  170. * @NVM_CHANNEL_ACTIVE: active scanning allowed
  171. * @NVM_CHANNEL_RADAR: radar detection required
  172. * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed
  173. * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS
  174. * on same channel on 2.4 or same UNII band on 5.2
  175. * @NVM_CHANNEL_UNIFORM: uniform spreading required
  176. * @NVM_CHANNEL_20MHZ: 20 MHz channel okay
  177. * @NVM_CHANNEL_40MHZ: 40 MHz channel okay
  178. * @NVM_CHANNEL_80MHZ: 80 MHz channel okay
  179. * @NVM_CHANNEL_160MHZ: 160 MHz channel okay
  180. * @NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?)
  181. */
  182. enum iwl_nvm_channel_flags {
  183. NVM_CHANNEL_VALID = BIT(0),
  184. NVM_CHANNEL_IBSS = BIT(1),
  185. NVM_CHANNEL_ACTIVE = BIT(3),
  186. NVM_CHANNEL_RADAR = BIT(4),
  187. NVM_CHANNEL_INDOOR_ONLY = BIT(5),
  188. NVM_CHANNEL_GO_CONCURRENT = BIT(6),
  189. NVM_CHANNEL_UNIFORM = BIT(7),
  190. NVM_CHANNEL_20MHZ = BIT(8),
  191. NVM_CHANNEL_40MHZ = BIT(9),
  192. NVM_CHANNEL_80MHZ = BIT(10),
  193. NVM_CHANNEL_160MHZ = BIT(11),
  194. NVM_CHANNEL_DC_HIGH = BIT(12),
  195. };
  196. #define CHECK_AND_PRINT_I(x) \
  197. ((ch_flags & NVM_CHANNEL_##x) ? # x " " : "")
  198. static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, bool is_5ghz,
  199. u16 nvm_flags, const struct iwl_cfg *cfg)
  200. {
  201. u32 flags = IEEE80211_CHAN_NO_HT40;
  202. u32 last_5ghz_ht = LAST_5GHZ_HT;
  203. if (cfg->ext_nvm)
  204. last_5ghz_ht = LAST_5GHZ_HT_FAMILY_8000;
  205. if (!is_5ghz && (nvm_flags & NVM_CHANNEL_40MHZ)) {
  206. if (ch_num <= LAST_2GHZ_HT_PLUS)
  207. flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
  208. if (ch_num >= FIRST_2GHZ_HT_MINUS)
  209. flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
  210. } else if (ch_num <= last_5ghz_ht && (nvm_flags & NVM_CHANNEL_40MHZ)) {
  211. if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
  212. flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
  213. else
  214. flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
  215. }
  216. if (!(nvm_flags & NVM_CHANNEL_80MHZ))
  217. flags |= IEEE80211_CHAN_NO_80MHZ;
  218. if (!(nvm_flags & NVM_CHANNEL_160MHZ))
  219. flags |= IEEE80211_CHAN_NO_160MHZ;
  220. if (!(nvm_flags & NVM_CHANNEL_IBSS))
  221. flags |= IEEE80211_CHAN_NO_IR;
  222. if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
  223. flags |= IEEE80211_CHAN_NO_IR;
  224. if (nvm_flags & NVM_CHANNEL_RADAR)
  225. flags |= IEEE80211_CHAN_RADAR;
  226. if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
  227. flags |= IEEE80211_CHAN_INDOOR_ONLY;
  228. /* Set the GO concurrent flag only in case that NO_IR is set.
  229. * Otherwise it is meaningless
  230. */
  231. if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
  232. (flags & IEEE80211_CHAN_NO_IR))
  233. flags |= IEEE80211_CHAN_IR_CONCURRENT;
  234. return flags;
  235. }
  236. static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg,
  237. struct iwl_nvm_data *data,
  238. const __le16 * const nvm_ch_flags,
  239. bool lar_supported, bool no_wide_in_5ghz)
  240. {
  241. int ch_idx;
  242. int n_channels = 0;
  243. struct ieee80211_channel *channel;
  244. u16 ch_flags;
  245. int num_of_ch, num_2ghz_channels;
  246. const u8 *nvm_chan;
  247. if (!cfg->ext_nvm) {
  248. num_of_ch = IWL_NUM_CHANNELS;
  249. nvm_chan = &iwl_nvm_channels[0];
  250. num_2ghz_channels = NUM_2GHZ_CHANNELS;
  251. } else {
  252. num_of_ch = IWL_NUM_CHANNELS_EXT;
  253. nvm_chan = &iwl_ext_nvm_channels[0];
  254. num_2ghz_channels = NUM_2GHZ_CHANNELS_EXT;
  255. }
  256. for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
  257. bool is_5ghz = (ch_idx >= num_2ghz_channels);
  258. ch_flags = __le16_to_cpup(nvm_ch_flags + ch_idx);
  259. if (is_5ghz && !data->sku_cap_band_52GHz_enable)
  260. continue;
  261. /* workaround to disable wide channels in 5GHz */
  262. if (no_wide_in_5ghz && is_5ghz) {
  263. ch_flags &= ~(NVM_CHANNEL_40MHZ |
  264. NVM_CHANNEL_80MHZ |
  265. NVM_CHANNEL_160MHZ);
  266. }
  267. if (ch_flags & NVM_CHANNEL_160MHZ)
  268. data->vht160_supported = true;
  269. if (!lar_supported && !(ch_flags & NVM_CHANNEL_VALID)) {
  270. /*
  271. * Channels might become valid later if lar is
  272. * supported, hence we still want to add them to
  273. * the list of supported channels to cfg80211.
  274. */
  275. IWL_DEBUG_EEPROM(dev,
  276. "Ch. %d Flags %x [%sGHz] - No traffic\n",
  277. nvm_chan[ch_idx],
  278. ch_flags,
  279. (ch_idx >= num_2ghz_channels) ?
  280. "5.2" : "2.4");
  281. continue;
  282. }
  283. channel = &data->channels[n_channels];
  284. n_channels++;
  285. channel->hw_value = nvm_chan[ch_idx];
  286. channel->band = is_5ghz ?
  287. NL80211_BAND_5GHZ : NL80211_BAND_2GHZ;
  288. channel->center_freq =
  289. ieee80211_channel_to_frequency(
  290. channel->hw_value, channel->band);
  291. /* Initialize regulatory-based run-time data */
  292. /*
  293. * Default value - highest tx power value. max_power
  294. * is not used in mvm, and is used for backwards compatibility
  295. */
  296. channel->max_power = IWL_DEFAULT_MAX_TX_POWER;
  297. /* don't put limitations in case we're using LAR */
  298. if (!lar_supported)
  299. channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx],
  300. ch_idx, is_5ghz,
  301. ch_flags, cfg);
  302. else
  303. channel->flags = 0;
  304. IWL_DEBUG_EEPROM(dev,
  305. "Ch. %d [%sGHz] flags 0x%x %s%s%s%s%s%s%s%s%s%s%s%s(%ddBm): Ad-Hoc %ssupported\n",
  306. channel->hw_value,
  307. is_5ghz ? "5.2" : "2.4",
  308. ch_flags,
  309. CHECK_AND_PRINT_I(VALID),
  310. CHECK_AND_PRINT_I(IBSS),
  311. CHECK_AND_PRINT_I(ACTIVE),
  312. CHECK_AND_PRINT_I(RADAR),
  313. CHECK_AND_PRINT_I(INDOOR_ONLY),
  314. CHECK_AND_PRINT_I(GO_CONCURRENT),
  315. CHECK_AND_PRINT_I(UNIFORM),
  316. CHECK_AND_PRINT_I(20MHZ),
  317. CHECK_AND_PRINT_I(40MHZ),
  318. CHECK_AND_PRINT_I(80MHZ),
  319. CHECK_AND_PRINT_I(160MHZ),
  320. CHECK_AND_PRINT_I(DC_HIGH),
  321. channel->max_power,
  322. ((ch_flags & NVM_CHANNEL_IBSS) &&
  323. !(ch_flags & NVM_CHANNEL_RADAR))
  324. ? "" : "not ");
  325. }
  326. return n_channels;
  327. }
  328. static void iwl_init_vht_hw_capab(const struct iwl_cfg *cfg,
  329. struct iwl_nvm_data *data,
  330. struct ieee80211_sta_vht_cap *vht_cap,
  331. u8 tx_chains, u8 rx_chains)
  332. {
  333. int num_rx_ants = num_of_ant(rx_chains);
  334. int num_tx_ants = num_of_ant(tx_chains);
  335. unsigned int max_ampdu_exponent = (cfg->max_vht_ampdu_exponent ?:
  336. IEEE80211_VHT_MAX_AMPDU_1024K);
  337. vht_cap->vht_supported = true;
  338. vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 |
  339. IEEE80211_VHT_CAP_RXSTBC_1 |
  340. IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
  341. 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT |
  342. max_ampdu_exponent <<
  343. IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT;
  344. if (data->vht160_supported)
  345. vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ |
  346. IEEE80211_VHT_CAP_SHORT_GI_160;
  347. if (cfg->vht_mu_mimo_supported)
  348. vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE;
  349. if (cfg->ht_params->ldpc)
  350. vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
  351. if (data->sku_cap_mimo_disabled) {
  352. num_rx_ants = 1;
  353. num_tx_ants = 1;
  354. }
  355. if (num_tx_ants > 1)
  356. vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
  357. else
  358. vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN;
  359. switch (iwlwifi_mod_params.amsdu_size) {
  360. case IWL_AMSDU_DEF:
  361. if (cfg->mq_rx_supported)
  362. vht_cap->cap |=
  363. IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
  364. else
  365. vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
  366. break;
  367. case IWL_AMSDU_4K:
  368. vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
  369. break;
  370. case IWL_AMSDU_8K:
  371. vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991;
  372. break;
  373. case IWL_AMSDU_12K:
  374. vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
  375. break;
  376. default:
  377. break;
  378. }
  379. vht_cap->vht_mcs.rx_mcs_map =
  380. cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
  381. IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 |
  382. IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
  383. IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
  384. IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
  385. IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
  386. IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
  387. IEEE80211_VHT_MCS_NOT_SUPPORTED << 14);
  388. if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) {
  389. vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN;
  390. /* this works because NOT_SUPPORTED == 3 */
  391. vht_cap->vht_mcs.rx_mcs_map |=
  392. cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2);
  393. }
  394. vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map;
  395. }
  396. void iwl_init_sbands(struct device *dev, const struct iwl_cfg *cfg,
  397. struct iwl_nvm_data *data, const __le16 *nvm_ch_flags,
  398. u8 tx_chains, u8 rx_chains, bool lar_supported,
  399. bool no_wide_in_5ghz)
  400. {
  401. int n_channels;
  402. int n_used = 0;
  403. struct ieee80211_supported_band *sband;
  404. n_channels = iwl_init_channel_map(dev, cfg, data, nvm_ch_flags,
  405. lar_supported, no_wide_in_5ghz);
  406. sband = &data->bands[NL80211_BAND_2GHZ];
  407. sband->band = NL80211_BAND_2GHZ;
  408. sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS];
  409. sband->n_bitrates = N_RATES_24;
  410. n_used += iwl_init_sband_channels(data, sband, n_channels,
  411. NL80211_BAND_2GHZ);
  412. iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, NL80211_BAND_2GHZ,
  413. tx_chains, rx_chains);
  414. sband = &data->bands[NL80211_BAND_5GHZ];
  415. sband->band = NL80211_BAND_5GHZ;
  416. sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
  417. sband->n_bitrates = N_RATES_52;
  418. n_used += iwl_init_sband_channels(data, sband, n_channels,
  419. NL80211_BAND_5GHZ);
  420. iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, NL80211_BAND_5GHZ,
  421. tx_chains, rx_chains);
  422. if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac)
  423. iwl_init_vht_hw_capab(cfg, data, &sband->vht_cap,
  424. tx_chains, rx_chains);
  425. if (n_channels != n_used)
  426. IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n",
  427. n_used, n_channels);
  428. }
  429. IWL_EXPORT_SYMBOL(iwl_init_sbands);
  430. static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
  431. const __le16 *phy_sku)
  432. {
  433. if (!cfg->ext_nvm)
  434. return le16_to_cpup(nvm_sw + SKU);
  435. return le32_to_cpup((__le32 *)(phy_sku + SKU_FAMILY_8000));
  436. }
  437. static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
  438. {
  439. if (!cfg->ext_nvm)
  440. return le16_to_cpup(nvm_sw + NVM_VERSION);
  441. else
  442. return le32_to_cpup((__le32 *)(nvm_sw +
  443. NVM_VERSION_EXT_NVM));
  444. }
  445. static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
  446. const __le16 *phy_sku)
  447. {
  448. if (!cfg->ext_nvm)
  449. return le16_to_cpup(nvm_sw + RADIO_CFG);
  450. return le32_to_cpup((__le32 *)(phy_sku + RADIO_CFG_FAMILY_EXT_NVM));
  451. }
  452. static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
  453. {
  454. int n_hw_addr;
  455. if (!cfg->ext_nvm)
  456. return le16_to_cpup(nvm_sw + N_HW_ADDRS);
  457. n_hw_addr = le32_to_cpup((__le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000));
  458. return n_hw_addr & N_HW_ADDR_MASK;
  459. }
  460. static void iwl_set_radio_cfg(const struct iwl_cfg *cfg,
  461. struct iwl_nvm_data *data,
  462. u32 radio_cfg)
  463. {
  464. if (!cfg->ext_nvm) {
  465. data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg);
  466. data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg);
  467. data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg);
  468. data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg);
  469. return;
  470. }
  471. /* set the radio configuration for family 8000 */
  472. data->radio_cfg_type = EXT_NVM_RF_CFG_TYPE_MSK(radio_cfg);
  473. data->radio_cfg_step = EXT_NVM_RF_CFG_STEP_MSK(radio_cfg);
  474. data->radio_cfg_dash = EXT_NVM_RF_CFG_DASH_MSK(radio_cfg);
  475. data->radio_cfg_pnum = EXT_NVM_RF_CFG_FLAVOR_MSK(radio_cfg);
  476. data->valid_tx_ant = EXT_NVM_RF_CFG_TX_ANT_MSK(radio_cfg);
  477. data->valid_rx_ant = EXT_NVM_RF_CFG_RX_ANT_MSK(radio_cfg);
  478. }
  479. static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest)
  480. {
  481. const u8 *hw_addr;
  482. hw_addr = (const u8 *)&mac_addr0;
  483. dest[0] = hw_addr[3];
  484. dest[1] = hw_addr[2];
  485. dest[2] = hw_addr[1];
  486. dest[3] = hw_addr[0];
  487. hw_addr = (const u8 *)&mac_addr1;
  488. dest[4] = hw_addr[1];
  489. dest[5] = hw_addr[0];
  490. }
  491. void iwl_set_hw_address_from_csr(struct iwl_trans *trans,
  492. struct iwl_nvm_data *data)
  493. {
  494. __le32 mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_STRAP));
  495. __le32 mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_STRAP));
  496. iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
  497. /*
  498. * If the OEM fused a valid address, use it instead of the one in the
  499. * OTP
  500. */
  501. if (is_valid_ether_addr(data->hw_addr))
  502. return;
  503. mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_OTP));
  504. mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_OTP));
  505. iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
  506. }
  507. IWL_EXPORT_SYMBOL(iwl_set_hw_address_from_csr);
  508. static void iwl_set_hw_address_family_8000(struct iwl_trans *trans,
  509. const struct iwl_cfg *cfg,
  510. struct iwl_nvm_data *data,
  511. const __le16 *mac_override,
  512. const __be16 *nvm_hw)
  513. {
  514. const u8 *hw_addr;
  515. if (mac_override) {
  516. static const u8 reserved_mac[] = {
  517. 0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00
  518. };
  519. hw_addr = (const u8 *)(mac_override +
  520. MAC_ADDRESS_OVERRIDE_EXT_NVM);
  521. /*
  522. * Store the MAC address from MAO section.
  523. * No byte swapping is required in MAO section
  524. */
  525. memcpy(data->hw_addr, hw_addr, ETH_ALEN);
  526. /*
  527. * Force the use of the OTP MAC address in case of reserved MAC
  528. * address in the NVM, or if address is given but invalid.
  529. */
  530. if (is_valid_ether_addr(data->hw_addr) &&
  531. memcmp(reserved_mac, hw_addr, ETH_ALEN) != 0)
  532. return;
  533. IWL_ERR(trans,
  534. "mac address from nvm override section is not valid\n");
  535. }
  536. if (nvm_hw) {
  537. /* read the mac address from WFMP registers */
  538. __le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans,
  539. WFMP_MAC_ADDR_0));
  540. __le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans,
  541. WFMP_MAC_ADDR_1));
  542. iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
  543. return;
  544. }
  545. IWL_ERR(trans, "mac address is not found\n");
  546. }
  547. static int iwl_set_hw_address(struct iwl_trans *trans,
  548. const struct iwl_cfg *cfg,
  549. struct iwl_nvm_data *data, const __be16 *nvm_hw,
  550. const __le16 *mac_override)
  551. {
  552. if (cfg->mac_addr_from_csr) {
  553. iwl_set_hw_address_from_csr(trans, data);
  554. } else if (!cfg->ext_nvm) {
  555. const u8 *hw_addr = (const u8 *)(nvm_hw + HW_ADDR);
  556. /* The byte order is little endian 16 bit, meaning 214365 */
  557. data->hw_addr[0] = hw_addr[1];
  558. data->hw_addr[1] = hw_addr[0];
  559. data->hw_addr[2] = hw_addr[3];
  560. data->hw_addr[3] = hw_addr[2];
  561. data->hw_addr[4] = hw_addr[5];
  562. data->hw_addr[5] = hw_addr[4];
  563. } else {
  564. iwl_set_hw_address_family_8000(trans, cfg, data,
  565. mac_override, nvm_hw);
  566. }
  567. if (!is_valid_ether_addr(data->hw_addr)) {
  568. IWL_ERR(trans, "no valid mac address was found\n");
  569. return -EINVAL;
  570. }
  571. IWL_INFO(trans, "base HW address: %pM\n", data->hw_addr);
  572. return 0;
  573. }
  574. static bool
  575. iwl_nvm_no_wide_in_5ghz(struct device *dev, const struct iwl_cfg *cfg,
  576. const __be16 *nvm_hw)
  577. {
  578. /*
  579. * Workaround a bug in Indonesia SKUs where the regulatory in
  580. * some 7000-family OTPs erroneously allow wide channels in
  581. * 5GHz. To check for Indonesia, we take the SKU value from
  582. * bits 1-4 in the subsystem ID and check if it is either 5 or
  583. * 9. In those cases, we need to force-disable wide channels
  584. * in 5GHz otherwise the FW will throw a sysassert when we try
  585. * to use them.
  586. */
  587. if (cfg->device_family == IWL_DEVICE_FAMILY_7000) {
  588. /*
  589. * Unlike the other sections in the NVM, the hw
  590. * section uses big-endian.
  591. */
  592. u16 subsystem_id = be16_to_cpup(nvm_hw + SUBSYSTEM_ID);
  593. u8 sku = (subsystem_id & 0x1e) >> 1;
  594. if (sku == 5 || sku == 9) {
  595. IWL_DEBUG_EEPROM(dev,
  596. "disabling wide channels in 5GHz (0x%0x %d)\n",
  597. subsystem_id, sku);
  598. return true;
  599. }
  600. }
  601. return false;
  602. }
  603. struct iwl_nvm_data *
  604. iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg,
  605. const __be16 *nvm_hw, const __le16 *nvm_sw,
  606. const __le16 *nvm_calib, const __le16 *regulatory,
  607. const __le16 *mac_override, const __le16 *phy_sku,
  608. u8 tx_chains, u8 rx_chains, bool lar_fw_supported)
  609. {
  610. struct device *dev = trans->dev;
  611. struct iwl_nvm_data *data;
  612. bool lar_enabled;
  613. bool no_wide_in_5ghz = iwl_nvm_no_wide_in_5ghz(dev, cfg, nvm_hw);
  614. u32 sku, radio_cfg;
  615. u16 lar_config;
  616. const __le16 *ch_section;
  617. if (!cfg->ext_nvm)
  618. data = kzalloc(sizeof(*data) +
  619. sizeof(struct ieee80211_channel) *
  620. IWL_NUM_CHANNELS,
  621. GFP_KERNEL);
  622. else
  623. data = kzalloc(sizeof(*data) +
  624. sizeof(struct ieee80211_channel) *
  625. IWL_NUM_CHANNELS_EXT,
  626. GFP_KERNEL);
  627. if (!data)
  628. return NULL;
  629. data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw);
  630. radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku);
  631. iwl_set_radio_cfg(cfg, data, radio_cfg);
  632. if (data->valid_tx_ant)
  633. tx_chains &= data->valid_tx_ant;
  634. if (data->valid_rx_ant)
  635. rx_chains &= data->valid_rx_ant;
  636. sku = iwl_get_sku(cfg, nvm_sw, phy_sku);
  637. data->sku_cap_band_24GHz_enable = sku & NVM_SKU_CAP_BAND_24GHZ;
  638. data->sku_cap_band_52GHz_enable = sku & NVM_SKU_CAP_BAND_52GHZ;
  639. data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE;
  640. if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
  641. data->sku_cap_11n_enable = false;
  642. data->sku_cap_11ac_enable = data->sku_cap_11n_enable &&
  643. (sku & NVM_SKU_CAP_11AC_ENABLE);
  644. data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE;
  645. data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw);
  646. if (!cfg->ext_nvm) {
  647. /* Checking for required sections */
  648. if (!nvm_calib) {
  649. IWL_ERR(trans,
  650. "Can't parse empty Calib NVM sections\n");
  651. kfree(data);
  652. return NULL;
  653. }
  654. /* in family 8000 Xtal calibration values moved to OTP */
  655. data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB);
  656. data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1);
  657. lar_enabled = true;
  658. ch_section = &nvm_sw[NVM_CHANNELS];
  659. } else {
  660. u16 lar_offset = data->nvm_version < 0xE39 ?
  661. NVM_LAR_OFFSET_OLD :
  662. NVM_LAR_OFFSET;
  663. lar_config = le16_to_cpup(regulatory + lar_offset);
  664. data->lar_enabled = !!(lar_config &
  665. NVM_LAR_ENABLED);
  666. lar_enabled = data->lar_enabled;
  667. ch_section = &regulatory[NVM_CHANNELS_EXTENDED];
  668. }
  669. /* If no valid mac address was found - bail out */
  670. if (iwl_set_hw_address(trans, cfg, data, nvm_hw, mac_override)) {
  671. kfree(data);
  672. return NULL;
  673. }
  674. iwl_init_sbands(dev, cfg, data, ch_section, tx_chains, rx_chains,
  675. lar_fw_supported && lar_enabled, no_wide_in_5ghz);
  676. data->calib_version = 255;
  677. return data;
  678. }
  679. IWL_EXPORT_SYMBOL(iwl_parse_nvm_data);
  680. static u32 iwl_nvm_get_regdom_bw_flags(const u8 *nvm_chan,
  681. int ch_idx, u16 nvm_flags,
  682. const struct iwl_cfg *cfg)
  683. {
  684. u32 flags = NL80211_RRF_NO_HT40;
  685. u32 last_5ghz_ht = LAST_5GHZ_HT;
  686. if (cfg->ext_nvm)
  687. last_5ghz_ht = LAST_5GHZ_HT_FAMILY_8000;
  688. if (ch_idx < NUM_2GHZ_CHANNELS &&
  689. (nvm_flags & NVM_CHANNEL_40MHZ)) {
  690. if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS)
  691. flags &= ~NL80211_RRF_NO_HT40PLUS;
  692. if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS)
  693. flags &= ~NL80211_RRF_NO_HT40MINUS;
  694. } else if (nvm_chan[ch_idx] <= last_5ghz_ht &&
  695. (nvm_flags & NVM_CHANNEL_40MHZ)) {
  696. if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
  697. flags &= ~NL80211_RRF_NO_HT40PLUS;
  698. else
  699. flags &= ~NL80211_RRF_NO_HT40MINUS;
  700. }
  701. if (!(nvm_flags & NVM_CHANNEL_80MHZ))
  702. flags |= NL80211_RRF_NO_80MHZ;
  703. if (!(nvm_flags & NVM_CHANNEL_160MHZ))
  704. flags |= NL80211_RRF_NO_160MHZ;
  705. if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
  706. flags |= NL80211_RRF_NO_IR;
  707. if (nvm_flags & NVM_CHANNEL_RADAR)
  708. flags |= NL80211_RRF_DFS;
  709. if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
  710. flags |= NL80211_RRF_NO_OUTDOOR;
  711. /* Set the GO concurrent flag only in case that NO_IR is set.
  712. * Otherwise it is meaningless
  713. */
  714. if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
  715. (flags & NL80211_RRF_NO_IR))
  716. flags |= NL80211_RRF_GO_CONCURRENT;
  717. return flags;
  718. }
  719. struct ieee80211_regdomain *
  720. iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg,
  721. int num_of_ch, __le32 *channels, u16 fw_mcc)
  722. {
  723. int ch_idx;
  724. u16 ch_flags;
  725. u32 reg_rule_flags, prev_reg_rule_flags = 0;
  726. const u8 *nvm_chan = cfg->ext_nvm ?
  727. iwl_ext_nvm_channels : iwl_nvm_channels;
  728. struct ieee80211_regdomain *regd;
  729. int size_of_regd;
  730. struct ieee80211_reg_rule *rule;
  731. enum nl80211_band band;
  732. int center_freq, prev_center_freq = 0;
  733. int valid_rules = 0;
  734. bool new_rule;
  735. int max_num_ch = cfg->ext_nvm ?
  736. IWL_NUM_CHANNELS_EXT : IWL_NUM_CHANNELS;
  737. if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES))
  738. return ERR_PTR(-EINVAL);
  739. if (WARN_ON(num_of_ch > max_num_ch))
  740. num_of_ch = max_num_ch;
  741. IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n",
  742. num_of_ch);
  743. /* build a regdomain rule for every valid channel */
  744. size_of_regd =
  745. sizeof(struct ieee80211_regdomain) +
  746. num_of_ch * sizeof(struct ieee80211_reg_rule);
  747. regd = kzalloc(size_of_regd, GFP_KERNEL);
  748. if (!regd)
  749. return ERR_PTR(-ENOMEM);
  750. for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
  751. ch_flags = (u16)__le32_to_cpup(channels + ch_idx);
  752. band = (ch_idx < NUM_2GHZ_CHANNELS) ?
  753. NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
  754. center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx],
  755. band);
  756. new_rule = false;
  757. if (!(ch_flags & NVM_CHANNEL_VALID)) {
  758. IWL_DEBUG_DEV(dev, IWL_DL_LAR,
  759. "Ch. %d Flags %x [%sGHz] - No traffic\n",
  760. nvm_chan[ch_idx],
  761. ch_flags,
  762. (ch_idx >= NUM_2GHZ_CHANNELS) ?
  763. "5.2" : "2.4");
  764. continue;
  765. }
  766. reg_rule_flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx,
  767. ch_flags, cfg);
  768. /* we can't continue the same rule */
  769. if (ch_idx == 0 || prev_reg_rule_flags != reg_rule_flags ||
  770. center_freq - prev_center_freq > 20) {
  771. valid_rules++;
  772. new_rule = true;
  773. }
  774. rule = &regd->reg_rules[valid_rules - 1];
  775. if (new_rule)
  776. rule->freq_range.start_freq_khz =
  777. MHZ_TO_KHZ(center_freq - 10);
  778. rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10);
  779. /* this doesn't matter - not used by FW */
  780. rule->power_rule.max_antenna_gain = DBI_TO_MBI(6);
  781. rule->power_rule.max_eirp =
  782. DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER);
  783. rule->flags = reg_rule_flags;
  784. /* rely on auto-calculation to merge BW of contiguous chans */
  785. rule->flags |= NL80211_RRF_AUTO_BW;
  786. rule->freq_range.max_bandwidth_khz = 0;
  787. prev_center_freq = center_freq;
  788. prev_reg_rule_flags = reg_rule_flags;
  789. IWL_DEBUG_DEV(dev, IWL_DL_LAR,
  790. "Ch. %d [%sGHz] %s%s%s%s%s%s%s%s%s%s%s%s(0x%02x)\n",
  791. center_freq,
  792. band == NL80211_BAND_5GHZ ? "5.2" : "2.4",
  793. CHECK_AND_PRINT_I(VALID),
  794. CHECK_AND_PRINT_I(IBSS),
  795. CHECK_AND_PRINT_I(ACTIVE),
  796. CHECK_AND_PRINT_I(RADAR),
  797. CHECK_AND_PRINT_I(INDOOR_ONLY),
  798. CHECK_AND_PRINT_I(GO_CONCURRENT),
  799. CHECK_AND_PRINT_I(UNIFORM),
  800. CHECK_AND_PRINT_I(20MHZ),
  801. CHECK_AND_PRINT_I(40MHZ),
  802. CHECK_AND_PRINT_I(80MHZ),
  803. CHECK_AND_PRINT_I(160MHZ),
  804. CHECK_AND_PRINT_I(DC_HIGH),
  805. ch_flags);
  806. IWL_DEBUG_DEV(dev, IWL_DL_LAR,
  807. "Ch. %d [%sGHz] reg_flags 0x%x: %s\n",
  808. center_freq,
  809. band == NL80211_BAND_5GHZ ? "5.2" : "2.4",
  810. reg_rule_flags,
  811. ((ch_flags & NVM_CHANNEL_ACTIVE) &&
  812. !(ch_flags & NVM_CHANNEL_RADAR))
  813. ? "Ad-Hoc" : "");
  814. }
  815. regd->n_reg_rules = valid_rules;
  816. /* set alpha2 from FW. */
  817. regd->alpha2[0] = fw_mcc >> 8;
  818. regd->alpha2[1] = fw_mcc & 0xff;
  819. return regd;
  820. }
  821. IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info);
  822. #ifdef CONFIG_ACPI
  823. #define WRDD_METHOD "WRDD"
  824. #define WRDD_WIFI (0x07)
  825. #define WRDD_WIGIG (0x10)
  826. static u32 iwl_wrdd_get_mcc(struct device *dev, union acpi_object *wrdd)
  827. {
  828. union acpi_object *mcc_pkg, *domain_type, *mcc_value;
  829. u32 i;
  830. if (wrdd->type != ACPI_TYPE_PACKAGE ||
  831. wrdd->package.count < 2 ||
  832. wrdd->package.elements[0].type != ACPI_TYPE_INTEGER ||
  833. wrdd->package.elements[0].integer.value != 0) {
  834. IWL_DEBUG_EEPROM(dev, "Unsupported wrdd structure\n");
  835. return 0;
  836. }
  837. for (i = 1 ; i < wrdd->package.count ; ++i) {
  838. mcc_pkg = &wrdd->package.elements[i];
  839. if (mcc_pkg->type != ACPI_TYPE_PACKAGE ||
  840. mcc_pkg->package.count < 2 ||
  841. mcc_pkg->package.elements[0].type != ACPI_TYPE_INTEGER ||
  842. mcc_pkg->package.elements[1].type != ACPI_TYPE_INTEGER) {
  843. mcc_pkg = NULL;
  844. continue;
  845. }
  846. domain_type = &mcc_pkg->package.elements[0];
  847. if (domain_type->integer.value == WRDD_WIFI)
  848. break;
  849. mcc_pkg = NULL;
  850. }
  851. if (mcc_pkg) {
  852. mcc_value = &mcc_pkg->package.elements[1];
  853. return mcc_value->integer.value;
  854. }
  855. return 0;
  856. }
  857. int iwl_get_bios_mcc(struct device *dev, char *mcc)
  858. {
  859. acpi_handle root_handle;
  860. acpi_handle handle;
  861. struct acpi_buffer wrdd = {ACPI_ALLOCATE_BUFFER, NULL};
  862. acpi_status status;
  863. u32 mcc_val;
  864. root_handle = ACPI_HANDLE(dev);
  865. if (!root_handle) {
  866. IWL_DEBUG_EEPROM(dev,
  867. "Could not retrieve root port ACPI handle\n");
  868. return -ENOENT;
  869. }
  870. /* Get the method's handle */
  871. status = acpi_get_handle(root_handle, (acpi_string)WRDD_METHOD,
  872. &handle);
  873. if (ACPI_FAILURE(status)) {
  874. IWL_DEBUG_EEPROM(dev, "WRD method not found\n");
  875. return -ENOENT;
  876. }
  877. /* Call WRDD with no arguments */
  878. status = acpi_evaluate_object(handle, NULL, NULL, &wrdd);
  879. if (ACPI_FAILURE(status)) {
  880. IWL_DEBUG_EEPROM(dev, "WRDC invocation failed (0x%x)\n",
  881. status);
  882. return -ENOENT;
  883. }
  884. mcc_val = iwl_wrdd_get_mcc(dev, wrdd.pointer);
  885. kfree(wrdd.pointer);
  886. if (!mcc_val)
  887. return -ENOENT;
  888. mcc[0] = (mcc_val >> 8) & 0xff;
  889. mcc[1] = mcc_val & 0xff;
  890. mcc[2] = '\0';
  891. return 0;
  892. }
  893. IWL_EXPORT_SYMBOL(iwl_get_bios_mcc);
  894. #endif