main.c 65 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/delay.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. u8 ath9k_parse_mpdudensity(u8 mpdudensity)
  21. {
  22. /*
  23. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  24. * 0 for no restriction
  25. * 1 for 1/4 us
  26. * 2 for 1/2 us
  27. * 3 for 1 us
  28. * 4 for 2 us
  29. * 5 for 4 us
  30. * 6 for 8 us
  31. * 7 for 16 us
  32. */
  33. switch (mpdudensity) {
  34. case 0:
  35. return 0;
  36. case 1:
  37. case 2:
  38. case 3:
  39. /* Our lower layer calculations limit our precision to
  40. 1 microsecond */
  41. return 1;
  42. case 4:
  43. return 2;
  44. case 5:
  45. return 4;
  46. case 6:
  47. return 8;
  48. case 7:
  49. return 16;
  50. default:
  51. return 0;
  52. }
  53. }
  54. static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq,
  55. bool sw_pending)
  56. {
  57. bool pending = false;
  58. spin_lock_bh(&txq->axq_lock);
  59. if (txq->axq_depth) {
  60. pending = true;
  61. goto out;
  62. }
  63. if (!sw_pending)
  64. goto out;
  65. if (txq->mac80211_qnum >= 0) {
  66. struct ath_acq *acq;
  67. acq = &sc->cur_chan->acq[txq->mac80211_qnum];
  68. if (!list_empty(&acq->acq_new) || !list_empty(&acq->acq_old))
  69. pending = true;
  70. }
  71. out:
  72. spin_unlock_bh(&txq->axq_lock);
  73. return pending;
  74. }
  75. static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  76. {
  77. unsigned long flags;
  78. bool ret;
  79. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  80. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  81. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  82. return ret;
  83. }
  84. void ath_ps_full_sleep(unsigned long data)
  85. {
  86. struct ath_softc *sc = (struct ath_softc *) data;
  87. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  88. bool reset;
  89. spin_lock(&common->cc_lock);
  90. ath_hw_cycle_counters_update(common);
  91. spin_unlock(&common->cc_lock);
  92. ath9k_hw_setrxabort(sc->sc_ah, 1);
  93. ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
  94. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
  95. }
  96. void ath9k_ps_wakeup(struct ath_softc *sc)
  97. {
  98. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  99. unsigned long flags;
  100. enum ath9k_power_mode power_mode;
  101. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  102. if (++sc->ps_usecount != 1)
  103. goto unlock;
  104. del_timer_sync(&sc->sleep_timer);
  105. power_mode = sc->sc_ah->power_mode;
  106. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  107. /*
  108. * While the hardware is asleep, the cycle counters contain no
  109. * useful data. Better clear them now so that they don't mess up
  110. * survey data results.
  111. */
  112. if (power_mode != ATH9K_PM_AWAKE) {
  113. spin_lock(&common->cc_lock);
  114. ath_hw_cycle_counters_update(common);
  115. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  116. memset(&common->cc_ani, 0, sizeof(common->cc_ani));
  117. spin_unlock(&common->cc_lock);
  118. }
  119. unlock:
  120. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  121. }
  122. void ath9k_ps_restore(struct ath_softc *sc)
  123. {
  124. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  125. enum ath9k_power_mode mode;
  126. unsigned long flags;
  127. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  128. if (--sc->ps_usecount != 0)
  129. goto unlock;
  130. if (sc->ps_idle) {
  131. mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
  132. goto unlock;
  133. }
  134. if (sc->ps_enabled &&
  135. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  136. PS_WAIT_FOR_CAB |
  137. PS_WAIT_FOR_PSPOLL_DATA |
  138. PS_WAIT_FOR_TX_ACK |
  139. PS_WAIT_FOR_ANI))) {
  140. mode = ATH9K_PM_NETWORK_SLEEP;
  141. if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
  142. ath9k_btcoex_stop_gen_timer(sc);
  143. } else {
  144. goto unlock;
  145. }
  146. spin_lock(&common->cc_lock);
  147. ath_hw_cycle_counters_update(common);
  148. spin_unlock(&common->cc_lock);
  149. ath9k_hw_setpower(sc->sc_ah, mode);
  150. unlock:
  151. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  152. }
  153. static void __ath_cancel_work(struct ath_softc *sc)
  154. {
  155. cancel_work_sync(&sc->paprd_work);
  156. cancel_delayed_work_sync(&sc->hw_check_work);
  157. cancel_delayed_work_sync(&sc->hw_pll_work);
  158. #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
  159. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  160. cancel_work_sync(&sc->mci_work);
  161. #endif
  162. }
  163. void ath_cancel_work(struct ath_softc *sc)
  164. {
  165. __ath_cancel_work(sc);
  166. cancel_work_sync(&sc->hw_reset_work);
  167. }
  168. void ath_restart_work(struct ath_softc *sc)
  169. {
  170. ieee80211_queue_delayed_work(sc->hw, &sc->hw_check_work,
  171. ATH_HW_CHECK_POLL_INT);
  172. if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
  173. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
  174. msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
  175. ath_start_ani(sc);
  176. }
  177. static bool ath_prepare_reset(struct ath_softc *sc)
  178. {
  179. struct ath_hw *ah = sc->sc_ah;
  180. bool ret = true;
  181. ieee80211_stop_queues(sc->hw);
  182. ath_stop_ani(sc);
  183. ath9k_hw_disable_interrupts(ah);
  184. if (AR_SREV_9300_20_OR_LATER(ah)) {
  185. ret &= ath_stoprecv(sc);
  186. ret &= ath_drain_all_txq(sc);
  187. } else {
  188. ret &= ath_drain_all_txq(sc);
  189. ret &= ath_stoprecv(sc);
  190. }
  191. return ret;
  192. }
  193. static bool ath_complete_reset(struct ath_softc *sc, bool start)
  194. {
  195. struct ath_hw *ah = sc->sc_ah;
  196. struct ath_common *common = ath9k_hw_common(ah);
  197. unsigned long flags;
  198. ath9k_calculate_summary_state(sc, sc->cur_chan);
  199. ath_startrecv(sc);
  200. ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
  201. sc->cur_chan->txpower,
  202. &sc->cur_chan->cur_txpower);
  203. clear_bit(ATH_OP_HW_RESET, &common->op_flags);
  204. if (!sc->cur_chan->offchannel && start) {
  205. /* restore per chanctx TSF timer */
  206. if (sc->cur_chan->tsf_val) {
  207. u32 offset;
  208. offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts,
  209. NULL);
  210. ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset);
  211. }
  212. if (!test_bit(ATH_OP_BEACONS, &common->op_flags))
  213. goto work;
  214. if (ah->opmode == NL80211_IFTYPE_STATION &&
  215. test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
  216. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  217. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  218. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  219. } else {
  220. ath9k_set_beacon(sc);
  221. }
  222. work:
  223. ath_restart_work(sc);
  224. ath_txq_schedule_all(sc);
  225. }
  226. sc->gtt_cnt = 0;
  227. ath9k_hw_set_interrupts(ah);
  228. ath9k_hw_enable_interrupts(ah);
  229. ieee80211_wake_queues(sc->hw);
  230. ath9k_p2p_ps_timer(sc);
  231. return true;
  232. }
  233. static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
  234. {
  235. struct ath_hw *ah = sc->sc_ah;
  236. struct ath_common *common = ath9k_hw_common(ah);
  237. struct ath9k_hw_cal_data *caldata = NULL;
  238. bool fastcc = true;
  239. int r;
  240. __ath_cancel_work(sc);
  241. disable_irq(sc->irq);
  242. tasklet_disable(&sc->intr_tq);
  243. tasklet_disable(&sc->bcon_tasklet);
  244. spin_lock_bh(&sc->sc_pcu_lock);
  245. if (!sc->cur_chan->offchannel) {
  246. fastcc = false;
  247. caldata = &sc->cur_chan->caldata;
  248. }
  249. if (!hchan) {
  250. fastcc = false;
  251. hchan = ah->curchan;
  252. }
  253. if (!ath_prepare_reset(sc))
  254. fastcc = false;
  255. if (ath9k_is_chanctx_enabled())
  256. fastcc = false;
  257. spin_lock_bh(&sc->chan_lock);
  258. sc->cur_chandef = sc->cur_chan->chandef;
  259. spin_unlock_bh(&sc->chan_lock);
  260. ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
  261. hchan->channel, IS_CHAN_HT40(hchan), fastcc);
  262. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  263. if (r) {
  264. ath_err(common,
  265. "Unable to reset channel, reset status %d\n", r);
  266. ath9k_hw_enable_interrupts(ah);
  267. ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
  268. goto out;
  269. }
  270. if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
  271. sc->cur_chan->offchannel)
  272. ath9k_mci_set_txpower(sc, true, false);
  273. if (!ath_complete_reset(sc, true))
  274. r = -EIO;
  275. out:
  276. enable_irq(sc->irq);
  277. spin_unlock_bh(&sc->sc_pcu_lock);
  278. tasklet_enable(&sc->bcon_tasklet);
  279. tasklet_enable(&sc->intr_tq);
  280. return r;
  281. }
  282. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
  283. struct ieee80211_vif *vif)
  284. {
  285. struct ath_node *an;
  286. an = (struct ath_node *)sta->drv_priv;
  287. an->sc = sc;
  288. an->sta = sta;
  289. an->vif = vif;
  290. memset(&an->key_idx, 0, sizeof(an->key_idx));
  291. ath_tx_node_init(sc, an);
  292. ath_dynack_node_init(sc->sc_ah, an);
  293. }
  294. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  295. {
  296. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  297. ath_tx_node_cleanup(sc, an);
  298. ath_dynack_node_deinit(sc->sc_ah, an);
  299. }
  300. void ath9k_tasklet(unsigned long data)
  301. {
  302. struct ath_softc *sc = (struct ath_softc *)data;
  303. struct ath_hw *ah = sc->sc_ah;
  304. struct ath_common *common = ath9k_hw_common(ah);
  305. enum ath_reset_type type;
  306. unsigned long flags;
  307. u32 status;
  308. u32 rxmask;
  309. spin_lock_irqsave(&sc->intr_lock, flags);
  310. status = sc->intrstatus;
  311. sc->intrstatus = 0;
  312. spin_unlock_irqrestore(&sc->intr_lock, flags);
  313. ath9k_ps_wakeup(sc);
  314. spin_lock(&sc->sc_pcu_lock);
  315. if (status & ATH9K_INT_FATAL) {
  316. type = RESET_TYPE_FATAL_INT;
  317. ath9k_queue_reset(sc, type);
  318. ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
  319. goto out;
  320. }
  321. if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
  322. (status & ATH9K_INT_BB_WATCHDOG)) {
  323. spin_lock(&common->cc_lock);
  324. ath_hw_cycle_counters_update(common);
  325. ar9003_hw_bb_watchdog_dbg_info(ah);
  326. spin_unlock(&common->cc_lock);
  327. if (ar9003_hw_bb_watchdog_check(ah)) {
  328. type = RESET_TYPE_BB_WATCHDOG;
  329. ath9k_queue_reset(sc, type);
  330. ath_dbg(common, RESET,
  331. "BB_WATCHDOG: Skipping interrupts\n");
  332. goto out;
  333. }
  334. }
  335. if (status & ATH9K_INT_GTT) {
  336. sc->gtt_cnt++;
  337. if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
  338. type = RESET_TYPE_TX_GTT;
  339. ath9k_queue_reset(sc, type);
  340. ath_dbg(common, RESET,
  341. "GTT: Skipping interrupts\n");
  342. goto out;
  343. }
  344. }
  345. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  346. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  347. /*
  348. * TSF sync does not look correct; remain awake to sync with
  349. * the next Beacon.
  350. */
  351. ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
  352. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  353. }
  354. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  355. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  356. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  357. ATH9K_INT_RXORN);
  358. else
  359. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  360. if (status & rxmask) {
  361. /* Check for high priority Rx first */
  362. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  363. (status & ATH9K_INT_RXHP))
  364. ath_rx_tasklet(sc, 0, true);
  365. ath_rx_tasklet(sc, 0, false);
  366. }
  367. if (status & ATH9K_INT_TX) {
  368. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  369. /*
  370. * For EDMA chips, TX completion is enabled for the
  371. * beacon queue, so if a beacon has been transmitted
  372. * successfully after a GTT interrupt, the GTT counter
  373. * gets reset to zero here.
  374. */
  375. sc->gtt_cnt = 0;
  376. ath_tx_edma_tasklet(sc);
  377. } else {
  378. ath_tx_tasklet(sc);
  379. }
  380. wake_up(&sc->tx_wait);
  381. }
  382. if (status & ATH9K_INT_GENTIMER)
  383. ath_gen_timer_isr(sc->sc_ah);
  384. ath9k_btcoex_handle_interrupt(sc, status);
  385. /* re-enable hardware interrupt */
  386. ath9k_hw_resume_interrupts(ah);
  387. out:
  388. spin_unlock(&sc->sc_pcu_lock);
  389. ath9k_ps_restore(sc);
  390. }
  391. irqreturn_t ath_isr(int irq, void *dev)
  392. {
  393. #define SCHED_INTR ( \
  394. ATH9K_INT_FATAL | \
  395. ATH9K_INT_BB_WATCHDOG | \
  396. ATH9K_INT_RXORN | \
  397. ATH9K_INT_RXEOL | \
  398. ATH9K_INT_RX | \
  399. ATH9K_INT_RXLP | \
  400. ATH9K_INT_RXHP | \
  401. ATH9K_INT_TX | \
  402. ATH9K_INT_BMISS | \
  403. ATH9K_INT_CST | \
  404. ATH9K_INT_GTT | \
  405. ATH9K_INT_TSFOOR | \
  406. ATH9K_INT_GENTIMER | \
  407. ATH9K_INT_MCI)
  408. struct ath_softc *sc = dev;
  409. struct ath_hw *ah = sc->sc_ah;
  410. struct ath_common *common = ath9k_hw_common(ah);
  411. enum ath9k_int status;
  412. u32 sync_cause = 0;
  413. bool sched = false;
  414. /*
  415. * The hardware is not ready/present, don't
  416. * touch anything. Note this can happen early
  417. * on if the IRQ is shared.
  418. */
  419. if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags))
  420. return IRQ_NONE;
  421. /* shared irq, not for us */
  422. if (!ath9k_hw_intrpend(ah))
  423. return IRQ_NONE;
  424. /*
  425. * Figure out the reason(s) for the interrupt. Note
  426. * that the hal returns a pseudo-ISR that may include
  427. * bits we haven't explicitly enabled so we mask the
  428. * value to insure we only process bits we requested.
  429. */
  430. ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
  431. ath9k_debug_sync_cause(sc, sync_cause);
  432. status &= ah->imask; /* discard unasked-for bits */
  433. if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
  434. return IRQ_HANDLED;
  435. /*
  436. * If there are no status bits set, then this interrupt was not
  437. * for me (should have been caught above).
  438. */
  439. if (!status)
  440. return IRQ_NONE;
  441. /* Cache the status */
  442. spin_lock(&sc->intr_lock);
  443. sc->intrstatus |= status;
  444. spin_unlock(&sc->intr_lock);
  445. if (status & SCHED_INTR)
  446. sched = true;
  447. /*
  448. * If a FATAL interrupt is received, we have to reset the chip
  449. * immediately.
  450. */
  451. if (status & ATH9K_INT_FATAL)
  452. goto chip_reset;
  453. if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
  454. (status & ATH9K_INT_BB_WATCHDOG))
  455. goto chip_reset;
  456. if (status & ATH9K_INT_SWBA)
  457. tasklet_schedule(&sc->bcon_tasklet);
  458. if (status & ATH9K_INT_TXURN)
  459. ath9k_hw_updatetxtriglevel(ah, true);
  460. if (status & ATH9K_INT_RXEOL) {
  461. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  462. ath9k_hw_set_interrupts(ah);
  463. }
  464. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  465. if (status & ATH9K_INT_TIM_TIMER) {
  466. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  467. goto chip_reset;
  468. /* Clear RxAbort bit so that we can
  469. * receive frames */
  470. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  471. spin_lock(&sc->sc_pm_lock);
  472. ath9k_hw_setrxabort(sc->sc_ah, 0);
  473. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  474. spin_unlock(&sc->sc_pm_lock);
  475. }
  476. chip_reset:
  477. ath_debug_stat_interrupt(sc, status);
  478. if (sched) {
  479. /* turn off every interrupt */
  480. ath9k_hw_kill_interrupts(ah);
  481. tasklet_schedule(&sc->intr_tq);
  482. }
  483. return IRQ_HANDLED;
  484. #undef SCHED_INTR
  485. }
  486. /*
  487. * This function is called when a HW reset cannot be deferred
  488. * and has to be immediate.
  489. */
  490. int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan)
  491. {
  492. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  493. int r;
  494. ath9k_hw_kill_interrupts(sc->sc_ah);
  495. set_bit(ATH_OP_HW_RESET, &common->op_flags);
  496. ath9k_ps_wakeup(sc);
  497. r = ath_reset_internal(sc, hchan);
  498. ath9k_ps_restore(sc);
  499. return r;
  500. }
  501. /*
  502. * When a HW reset can be deferred, it is added to the
  503. * hw_reset_work workqueue, but we set ATH_OP_HW_RESET before
  504. * queueing.
  505. */
  506. void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
  507. {
  508. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  509. #ifdef CONFIG_ATH9K_DEBUGFS
  510. RESET_STAT_INC(sc, type);
  511. #endif
  512. ath9k_hw_kill_interrupts(sc->sc_ah);
  513. set_bit(ATH_OP_HW_RESET, &common->op_flags);
  514. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  515. }
  516. void ath_reset_work(struct work_struct *work)
  517. {
  518. struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
  519. ath9k_ps_wakeup(sc);
  520. ath_reset_internal(sc, NULL);
  521. ath9k_ps_restore(sc);
  522. }
  523. /**********************/
  524. /* mac80211 callbacks */
  525. /**********************/
  526. static int ath9k_start(struct ieee80211_hw *hw)
  527. {
  528. struct ath_softc *sc = hw->priv;
  529. struct ath_hw *ah = sc->sc_ah;
  530. struct ath_common *common = ath9k_hw_common(ah);
  531. struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;
  532. struct ath_chanctx *ctx = sc->cur_chan;
  533. struct ath9k_channel *init_channel;
  534. int r;
  535. ath_dbg(common, CONFIG,
  536. "Starting driver with initial channel: %d MHz\n",
  537. curchan->center_freq);
  538. ath9k_ps_wakeup(sc);
  539. mutex_lock(&sc->mutex);
  540. init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);
  541. sc->cur_chandef = hw->conf.chandef;
  542. /* Reset SERDES registers */
  543. ath9k_hw_configpcipowersave(ah, false);
  544. /*
  545. * The basic interface to setting the hardware in a good
  546. * state is ``reset''. On return the hardware is known to
  547. * be powered up and with interrupts disabled. This must
  548. * be followed by initialization of the appropriate bits
  549. * and then setup of the interrupt mask.
  550. */
  551. spin_lock_bh(&sc->sc_pcu_lock);
  552. atomic_set(&ah->intr_ref_cnt, -1);
  553. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  554. if (r) {
  555. ath_err(common,
  556. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  557. r, curchan->center_freq);
  558. ah->reset_power_on = false;
  559. }
  560. /* Setup our intr mask. */
  561. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  562. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  563. ATH9K_INT_GLOBAL;
  564. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  565. ah->imask |= ATH9K_INT_RXHP |
  566. ATH9K_INT_RXLP;
  567. else
  568. ah->imask |= ATH9K_INT_RX;
  569. if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
  570. ah->imask |= ATH9K_INT_BB_WATCHDOG;
  571. /*
  572. * Enable GTT interrupts only for AR9003/AR9004 chips
  573. * for now.
  574. */
  575. if (AR_SREV_9300_20_OR_LATER(ah))
  576. ah->imask |= ATH9K_INT_GTT;
  577. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  578. ah->imask |= ATH9K_INT_CST;
  579. ath_mci_enable(sc);
  580. clear_bit(ATH_OP_INVALID, &common->op_flags);
  581. sc->sc_ah->is_monitoring = false;
  582. if (!ath_complete_reset(sc, false))
  583. ah->reset_power_on = false;
  584. if (ah->led_pin >= 0) {
  585. ath9k_hw_set_gpio(ah, ah->led_pin,
  586. (ah->config.led_active_high) ? 1 : 0);
  587. ath9k_hw_gpio_request_out(ah, ah->led_pin, NULL,
  588. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  589. }
  590. /*
  591. * Reset key cache to sane defaults (all entries cleared) instead of
  592. * semi-random values after suspend/resume.
  593. */
  594. ath9k_cmn_init_crypto(sc->sc_ah);
  595. ath9k_hw_reset_tsf(ah);
  596. spin_unlock_bh(&sc->sc_pcu_lock);
  597. ath9k_rng_start(sc);
  598. mutex_unlock(&sc->mutex);
  599. ath9k_ps_restore(sc);
  600. return 0;
  601. }
  602. static void ath9k_tx(struct ieee80211_hw *hw,
  603. struct ieee80211_tx_control *control,
  604. struct sk_buff *skb)
  605. {
  606. struct ath_softc *sc = hw->priv;
  607. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  608. struct ath_tx_control txctl;
  609. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  610. unsigned long flags;
  611. if (sc->ps_enabled) {
  612. /*
  613. * mac80211 does not set PM field for normal data frames, so we
  614. * need to update that based on the current PS mode.
  615. */
  616. if (ieee80211_is_data(hdr->frame_control) &&
  617. !ieee80211_is_nullfunc(hdr->frame_control) &&
  618. !ieee80211_has_pm(hdr->frame_control)) {
  619. ath_dbg(common, PS,
  620. "Add PM=1 for a TX frame while in PS mode\n");
  621. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  622. }
  623. }
  624. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
  625. /*
  626. * We are using PS-Poll and mac80211 can request TX while in
  627. * power save mode. Need to wake up hardware for the TX to be
  628. * completed and if needed, also for RX of buffered frames.
  629. */
  630. ath9k_ps_wakeup(sc);
  631. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  632. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  633. ath9k_hw_setrxabort(sc->sc_ah, 0);
  634. if (ieee80211_is_pspoll(hdr->frame_control)) {
  635. ath_dbg(common, PS,
  636. "Sending PS-Poll to pick a buffered frame\n");
  637. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  638. } else {
  639. ath_dbg(common, PS, "Wake up to complete TX\n");
  640. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  641. }
  642. /*
  643. * The actual restore operation will happen only after
  644. * the ps_flags bit is cleared. We are just dropping
  645. * the ps_usecount here.
  646. */
  647. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  648. ath9k_ps_restore(sc);
  649. }
  650. /*
  651. * Cannot tx while the hardware is in full sleep, it first needs a full
  652. * chip reset to recover from that
  653. */
  654. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
  655. ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
  656. goto exit;
  657. }
  658. memset(&txctl, 0, sizeof(struct ath_tx_control));
  659. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  660. txctl.sta = control->sta;
  661. ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
  662. if (ath_tx_start(hw, skb, &txctl) != 0) {
  663. ath_dbg(common, XMIT, "TX failed\n");
  664. TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
  665. goto exit;
  666. }
  667. return;
  668. exit:
  669. ieee80211_free_txskb(hw, skb);
  670. }
  671. static void ath9k_stop(struct ieee80211_hw *hw)
  672. {
  673. struct ath_softc *sc = hw->priv;
  674. struct ath_hw *ah = sc->sc_ah;
  675. struct ath_common *common = ath9k_hw_common(ah);
  676. bool prev_idle;
  677. ath9k_deinit_channel_context(sc);
  678. mutex_lock(&sc->mutex);
  679. ath9k_rng_stop(sc);
  680. ath_cancel_work(sc);
  681. if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
  682. ath_dbg(common, ANY, "Device not present\n");
  683. mutex_unlock(&sc->mutex);
  684. return;
  685. }
  686. /* Ensure HW is awake when we try to shut it down. */
  687. ath9k_ps_wakeup(sc);
  688. spin_lock_bh(&sc->sc_pcu_lock);
  689. /* prevent tasklets to enable interrupts once we disable them */
  690. ah->imask &= ~ATH9K_INT_GLOBAL;
  691. /* make sure h/w will not generate any interrupt
  692. * before setting the invalid flag. */
  693. ath9k_hw_disable_interrupts(ah);
  694. spin_unlock_bh(&sc->sc_pcu_lock);
  695. /* we can now sync irq and kill any running tasklets, since we already
  696. * disabled interrupts and not holding a spin lock */
  697. synchronize_irq(sc->irq);
  698. tasklet_kill(&sc->intr_tq);
  699. tasklet_kill(&sc->bcon_tasklet);
  700. prev_idle = sc->ps_idle;
  701. sc->ps_idle = true;
  702. spin_lock_bh(&sc->sc_pcu_lock);
  703. if (ah->led_pin >= 0) {
  704. ath9k_hw_set_gpio(ah, ah->led_pin,
  705. (ah->config.led_active_high) ? 0 : 1);
  706. ath9k_hw_gpio_request_in(ah, ah->led_pin, NULL);
  707. }
  708. ath_prepare_reset(sc);
  709. if (sc->rx.frag) {
  710. dev_kfree_skb_any(sc->rx.frag);
  711. sc->rx.frag = NULL;
  712. }
  713. if (!ah->curchan)
  714. ah->curchan = ath9k_cmn_get_channel(hw, ah,
  715. &sc->cur_chan->chandef);
  716. ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  717. set_bit(ATH_OP_INVALID, &common->op_flags);
  718. ath9k_hw_phy_disable(ah);
  719. ath9k_hw_configpcipowersave(ah, true);
  720. spin_unlock_bh(&sc->sc_pcu_lock);
  721. ath9k_ps_restore(sc);
  722. sc->ps_idle = prev_idle;
  723. mutex_unlock(&sc->mutex);
  724. ath_dbg(common, CONFIG, "Driver halt\n");
  725. }
  726. static bool ath9k_uses_beacons(int type)
  727. {
  728. switch (type) {
  729. case NL80211_IFTYPE_AP:
  730. case NL80211_IFTYPE_ADHOC:
  731. case NL80211_IFTYPE_MESH_POINT:
  732. return true;
  733. default:
  734. return false;
  735. }
  736. }
  737. static void ath9k_vif_iter_set_beacon(struct ath9k_vif_iter_data *iter_data,
  738. struct ieee80211_vif *vif)
  739. {
  740. /* Use the first (configured) interface, but prefering AP interfaces. */
  741. if (!iter_data->primary_beacon_vif) {
  742. iter_data->primary_beacon_vif = vif;
  743. } else {
  744. if (iter_data->primary_beacon_vif->type != NL80211_IFTYPE_AP &&
  745. vif->type == NL80211_IFTYPE_AP)
  746. iter_data->primary_beacon_vif = vif;
  747. }
  748. iter_data->beacons = true;
  749. iter_data->nbcnvifs += 1;
  750. }
  751. static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data,
  752. u8 *mac, struct ieee80211_vif *vif)
  753. {
  754. struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
  755. int i;
  756. if (iter_data->has_hw_macaddr) {
  757. for (i = 0; i < ETH_ALEN; i++)
  758. iter_data->mask[i] &=
  759. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  760. } else {
  761. memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
  762. iter_data->has_hw_macaddr = true;
  763. }
  764. if (!vif->bss_conf.use_short_slot)
  765. iter_data->slottime = 20;
  766. switch (vif->type) {
  767. case NL80211_IFTYPE_AP:
  768. iter_data->naps++;
  769. if (vif->bss_conf.enable_beacon)
  770. ath9k_vif_iter_set_beacon(iter_data, vif);
  771. break;
  772. case NL80211_IFTYPE_STATION:
  773. iter_data->nstations++;
  774. if (avp->assoc && !iter_data->primary_sta)
  775. iter_data->primary_sta = vif;
  776. break;
  777. case NL80211_IFTYPE_OCB:
  778. iter_data->nocbs++;
  779. break;
  780. case NL80211_IFTYPE_ADHOC:
  781. iter_data->nadhocs++;
  782. if (vif->bss_conf.enable_beacon)
  783. ath9k_vif_iter_set_beacon(iter_data, vif);
  784. break;
  785. case NL80211_IFTYPE_MESH_POINT:
  786. iter_data->nmeshes++;
  787. if (vif->bss_conf.enable_beacon)
  788. ath9k_vif_iter_set_beacon(iter_data, vif);
  789. break;
  790. case NL80211_IFTYPE_WDS:
  791. iter_data->nwds++;
  792. break;
  793. default:
  794. break;
  795. }
  796. }
  797. static void ath9k_update_bssid_mask(struct ath_softc *sc,
  798. struct ath_chanctx *ctx,
  799. struct ath9k_vif_iter_data *iter_data)
  800. {
  801. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  802. struct ath_vif *avp;
  803. int i;
  804. if (!ath9k_is_chanctx_enabled())
  805. return;
  806. list_for_each_entry(avp, &ctx->vifs, list) {
  807. if (ctx->nvifs_assigned != 1)
  808. continue;
  809. if (!iter_data->has_hw_macaddr)
  810. continue;
  811. ether_addr_copy(common->curbssid, avp->bssid);
  812. /* perm_addr will be used as the p2p device address. */
  813. for (i = 0; i < ETH_ALEN; i++)
  814. iter_data->mask[i] &=
  815. ~(iter_data->hw_macaddr[i] ^
  816. sc->hw->wiphy->perm_addr[i]);
  817. }
  818. }
  819. /* Called with sc->mutex held. */
  820. void ath9k_calculate_iter_data(struct ath_softc *sc,
  821. struct ath_chanctx *ctx,
  822. struct ath9k_vif_iter_data *iter_data)
  823. {
  824. struct ath_vif *avp;
  825. /*
  826. * The hardware will use primary station addr together with the
  827. * BSSID mask when matching addresses.
  828. */
  829. memset(iter_data, 0, sizeof(*iter_data));
  830. eth_broadcast_addr(iter_data->mask);
  831. iter_data->slottime = 9;
  832. list_for_each_entry(avp, &ctx->vifs, list)
  833. ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);
  834. ath9k_update_bssid_mask(sc, ctx, iter_data);
  835. }
  836. static void ath9k_set_assoc_state(struct ath_softc *sc,
  837. struct ieee80211_vif *vif, bool changed)
  838. {
  839. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  840. struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
  841. unsigned long flags;
  842. set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
  843. ether_addr_copy(common->curbssid, avp->bssid);
  844. common->curaid = avp->aid;
  845. ath9k_hw_write_associd(sc->sc_ah);
  846. if (changed) {
  847. common->last_rssi = ATH_RSSI_DUMMY_MARKER;
  848. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  849. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  850. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  851. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  852. }
  853. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  854. ath9k_mci_update_wlan_channels(sc, false);
  855. ath_dbg(common, CONFIG,
  856. "Primary Station interface: %pM, BSSID: %pM\n",
  857. vif->addr, common->curbssid);
  858. }
  859. #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
  860. static void ath9k_set_offchannel_state(struct ath_softc *sc)
  861. {
  862. struct ath_hw *ah = sc->sc_ah;
  863. struct ath_common *common = ath9k_hw_common(ah);
  864. struct ieee80211_vif *vif = NULL;
  865. ath9k_ps_wakeup(sc);
  866. if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START)
  867. vif = sc->offchannel.scan_vif;
  868. else
  869. vif = sc->offchannel.roc_vif;
  870. if (WARN_ON(!vif))
  871. goto exit;
  872. eth_zero_addr(common->curbssid);
  873. eth_broadcast_addr(common->bssidmask);
  874. memcpy(common->macaddr, vif->addr, ETH_ALEN);
  875. common->curaid = 0;
  876. ah->opmode = vif->type;
  877. ah->imask &= ~ATH9K_INT_SWBA;
  878. ah->imask &= ~ATH9K_INT_TSFOOR;
  879. ah->slottime = 9;
  880. ath_hw_setbssidmask(common);
  881. ath9k_hw_setopmode(ah);
  882. ath9k_hw_write_associd(sc->sc_ah);
  883. ath9k_hw_set_interrupts(ah);
  884. ath9k_hw_init_global_settings(ah);
  885. exit:
  886. ath9k_ps_restore(sc);
  887. }
  888. #endif
  889. /* Called with sc->mutex held. */
  890. void ath9k_calculate_summary_state(struct ath_softc *sc,
  891. struct ath_chanctx *ctx)
  892. {
  893. struct ath_hw *ah = sc->sc_ah;
  894. struct ath_common *common = ath9k_hw_common(ah);
  895. struct ath9k_vif_iter_data iter_data;
  896. ath_chanctx_check_active(sc, ctx);
  897. if (ctx != sc->cur_chan)
  898. return;
  899. #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
  900. if (ctx == &sc->offchannel.chan)
  901. return ath9k_set_offchannel_state(sc);
  902. #endif
  903. ath9k_ps_wakeup(sc);
  904. ath9k_calculate_iter_data(sc, ctx, &iter_data);
  905. if (iter_data.has_hw_macaddr)
  906. memcpy(common->macaddr, iter_data.hw_macaddr, ETH_ALEN);
  907. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  908. ath_hw_setbssidmask(common);
  909. if (iter_data.naps > 0) {
  910. ath9k_hw_set_tsfadjust(ah, true);
  911. ah->opmode = NL80211_IFTYPE_AP;
  912. } else {
  913. ath9k_hw_set_tsfadjust(ah, false);
  914. if (iter_data.beacons)
  915. ath9k_beacon_ensure_primary_slot(sc);
  916. if (iter_data.nmeshes)
  917. ah->opmode = NL80211_IFTYPE_MESH_POINT;
  918. else if (iter_data.nocbs)
  919. ah->opmode = NL80211_IFTYPE_OCB;
  920. else if (iter_data.nwds)
  921. ah->opmode = NL80211_IFTYPE_AP;
  922. else if (iter_data.nadhocs)
  923. ah->opmode = NL80211_IFTYPE_ADHOC;
  924. else
  925. ah->opmode = NL80211_IFTYPE_STATION;
  926. }
  927. ath9k_hw_setopmode(ah);
  928. ctx->switch_after_beacon = false;
  929. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
  930. ah->imask |= ATH9K_INT_TSFOOR;
  931. else {
  932. ah->imask &= ~ATH9K_INT_TSFOOR;
  933. if (iter_data.naps == 1 && iter_data.beacons)
  934. ctx->switch_after_beacon = true;
  935. }
  936. if (ah->opmode == NL80211_IFTYPE_STATION) {
  937. bool changed = (iter_data.primary_sta != ctx->primary_sta);
  938. if (iter_data.primary_sta) {
  939. iter_data.primary_beacon_vif = iter_data.primary_sta;
  940. iter_data.beacons = true;
  941. ath9k_set_assoc_state(sc, iter_data.primary_sta,
  942. changed);
  943. ctx->primary_sta = iter_data.primary_sta;
  944. } else {
  945. ctx->primary_sta = NULL;
  946. eth_zero_addr(common->curbssid);
  947. common->curaid = 0;
  948. ath9k_hw_write_associd(sc->sc_ah);
  949. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  950. ath9k_mci_update_wlan_channels(sc, true);
  951. }
  952. }
  953. sc->nbcnvifs = iter_data.nbcnvifs;
  954. ath9k_beacon_config(sc, iter_data.primary_beacon_vif,
  955. iter_data.beacons);
  956. ath9k_hw_set_interrupts(ah);
  957. if (ah->slottime != iter_data.slottime) {
  958. ah->slottime = iter_data.slottime;
  959. ath9k_hw_init_global_settings(ah);
  960. }
  961. if (iter_data.primary_sta)
  962. set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
  963. else
  964. clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
  965. ath_dbg(common, CONFIG,
  966. "macaddr: %pM, bssid: %pM, bssidmask: %pM\n",
  967. common->macaddr, common->curbssid, common->bssidmask);
  968. ath9k_ps_restore(sc);
  969. }
  970. static void ath9k_tpc_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  971. {
  972. int *power = (int *)data;
  973. if (*power < vif->bss_conf.txpower)
  974. *power = vif->bss_conf.txpower;
  975. }
  976. /* Called with sc->mutex held. */
  977. void ath9k_set_txpower(struct ath_softc *sc, struct ieee80211_vif *vif)
  978. {
  979. int power;
  980. struct ath_hw *ah = sc->sc_ah;
  981. struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
  982. ath9k_ps_wakeup(sc);
  983. if (ah->tpc_enabled) {
  984. power = (vif) ? vif->bss_conf.txpower : -1;
  985. ieee80211_iterate_active_interfaces_atomic(
  986. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  987. ath9k_tpc_vif_iter, &power);
  988. if (power == -1)
  989. power = sc->hw->conf.power_level;
  990. } else {
  991. power = sc->hw->conf.power_level;
  992. }
  993. sc->cur_chan->txpower = 2 * power;
  994. ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
  995. sc->cur_chan->cur_txpower = reg->max_power_level;
  996. ath9k_ps_restore(sc);
  997. }
  998. static void ath9k_assign_hw_queues(struct ieee80211_hw *hw,
  999. struct ieee80211_vif *vif)
  1000. {
  1001. int i;
  1002. if (!ath9k_is_chanctx_enabled())
  1003. return;
  1004. for (i = 0; i < IEEE80211_NUM_ACS; i++)
  1005. vif->hw_queue[i] = i;
  1006. if (vif->type == NL80211_IFTYPE_AP ||
  1007. vif->type == NL80211_IFTYPE_MESH_POINT)
  1008. vif->cab_queue = hw->queues - 2;
  1009. else
  1010. vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
  1011. }
  1012. static int ath9k_add_interface(struct ieee80211_hw *hw,
  1013. struct ieee80211_vif *vif)
  1014. {
  1015. struct ath_softc *sc = hw->priv;
  1016. struct ath_hw *ah = sc->sc_ah;
  1017. struct ath_common *common = ath9k_hw_common(ah);
  1018. struct ath_vif *avp = (void *)vif->drv_priv;
  1019. struct ath_node *an = &avp->mcast_node;
  1020. mutex_lock(&sc->mutex);
  1021. if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
  1022. if (sc->cur_chan->nvifs >= 1) {
  1023. mutex_unlock(&sc->mutex);
  1024. return -EOPNOTSUPP;
  1025. }
  1026. sc->tx99_vif = vif;
  1027. }
  1028. ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
  1029. sc->cur_chan->nvifs++;
  1030. if (vif->type == NL80211_IFTYPE_STATION && ath9k_is_chanctx_enabled())
  1031. vif->driver_flags |= IEEE80211_VIF_GET_NOA_UPDATE;
  1032. if (ath9k_uses_beacons(vif->type))
  1033. ath9k_beacon_assign_slot(sc, vif);
  1034. avp->vif = vif;
  1035. if (!ath9k_is_chanctx_enabled()) {
  1036. avp->chanctx = sc->cur_chan;
  1037. list_add_tail(&avp->list, &avp->chanctx->vifs);
  1038. }
  1039. ath9k_calculate_summary_state(sc, avp->chanctx);
  1040. ath9k_assign_hw_queues(hw, vif);
  1041. ath9k_set_txpower(sc, vif);
  1042. an->sc = sc;
  1043. an->sta = NULL;
  1044. an->vif = vif;
  1045. an->no_ps_filter = true;
  1046. ath_tx_node_init(sc, an);
  1047. mutex_unlock(&sc->mutex);
  1048. return 0;
  1049. }
  1050. static int ath9k_change_interface(struct ieee80211_hw *hw,
  1051. struct ieee80211_vif *vif,
  1052. enum nl80211_iftype new_type,
  1053. bool p2p)
  1054. {
  1055. struct ath_softc *sc = hw->priv;
  1056. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1057. struct ath_vif *avp = (void *)vif->drv_priv;
  1058. mutex_lock(&sc->mutex);
  1059. if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
  1060. mutex_unlock(&sc->mutex);
  1061. return -EOPNOTSUPP;
  1062. }
  1063. ath_dbg(common, CONFIG, "Change Interface\n");
  1064. if (ath9k_uses_beacons(vif->type))
  1065. ath9k_beacon_remove_slot(sc, vif);
  1066. vif->type = new_type;
  1067. vif->p2p = p2p;
  1068. if (ath9k_uses_beacons(vif->type))
  1069. ath9k_beacon_assign_slot(sc, vif);
  1070. ath9k_assign_hw_queues(hw, vif);
  1071. ath9k_calculate_summary_state(sc, avp->chanctx);
  1072. ath9k_set_txpower(sc, vif);
  1073. mutex_unlock(&sc->mutex);
  1074. return 0;
  1075. }
  1076. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  1077. struct ieee80211_vif *vif)
  1078. {
  1079. struct ath_softc *sc = hw->priv;
  1080. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1081. struct ath_vif *avp = (void *)vif->drv_priv;
  1082. ath_dbg(common, CONFIG, "Detach Interface\n");
  1083. mutex_lock(&sc->mutex);
  1084. ath9k_p2p_remove_vif(sc, vif);
  1085. sc->cur_chan->nvifs--;
  1086. sc->tx99_vif = NULL;
  1087. if (!ath9k_is_chanctx_enabled())
  1088. list_del(&avp->list);
  1089. if (ath9k_uses_beacons(vif->type))
  1090. ath9k_beacon_remove_slot(sc, vif);
  1091. ath_tx_node_cleanup(sc, &avp->mcast_node);
  1092. ath9k_calculate_summary_state(sc, avp->chanctx);
  1093. ath9k_set_txpower(sc, NULL);
  1094. mutex_unlock(&sc->mutex);
  1095. }
  1096. static void ath9k_enable_ps(struct ath_softc *sc)
  1097. {
  1098. struct ath_hw *ah = sc->sc_ah;
  1099. struct ath_common *common = ath9k_hw_common(ah);
  1100. if (IS_ENABLED(CONFIG_ATH9K_TX99))
  1101. return;
  1102. sc->ps_enabled = true;
  1103. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1104. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  1105. ah->imask |= ATH9K_INT_TIM_TIMER;
  1106. ath9k_hw_set_interrupts(ah);
  1107. }
  1108. ath9k_hw_setrxabort(ah, 1);
  1109. }
  1110. ath_dbg(common, PS, "PowerSave enabled\n");
  1111. }
  1112. static void ath9k_disable_ps(struct ath_softc *sc)
  1113. {
  1114. struct ath_hw *ah = sc->sc_ah;
  1115. struct ath_common *common = ath9k_hw_common(ah);
  1116. if (IS_ENABLED(CONFIG_ATH9K_TX99))
  1117. return;
  1118. sc->ps_enabled = false;
  1119. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  1120. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1121. ath9k_hw_setrxabort(ah, 0);
  1122. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  1123. PS_WAIT_FOR_CAB |
  1124. PS_WAIT_FOR_PSPOLL_DATA |
  1125. PS_WAIT_FOR_TX_ACK);
  1126. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  1127. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  1128. ath9k_hw_set_interrupts(ah);
  1129. }
  1130. }
  1131. ath_dbg(common, PS, "PowerSave disabled\n");
  1132. }
  1133. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  1134. {
  1135. struct ath_softc *sc = hw->priv;
  1136. struct ath_hw *ah = sc->sc_ah;
  1137. struct ath_common *common = ath9k_hw_common(ah);
  1138. struct ieee80211_conf *conf = &hw->conf;
  1139. struct ath_chanctx *ctx = sc->cur_chan;
  1140. ath9k_ps_wakeup(sc);
  1141. mutex_lock(&sc->mutex);
  1142. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  1143. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  1144. if (sc->ps_idle) {
  1145. ath_cancel_work(sc);
  1146. ath9k_stop_btcoex(sc);
  1147. } else {
  1148. ath9k_start_btcoex(sc);
  1149. /*
  1150. * The chip needs a reset to properly wake up from
  1151. * full sleep
  1152. */
  1153. ath_chanctx_set_channel(sc, ctx, &ctx->chandef);
  1154. }
  1155. }
  1156. /*
  1157. * We just prepare to enable PS. We have to wait until our AP has
  1158. * ACK'd our null data frame to disable RX otherwise we'll ignore
  1159. * those ACKs and end up retransmitting the same null data frames.
  1160. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  1161. */
  1162. if (changed & IEEE80211_CONF_CHANGE_PS) {
  1163. unsigned long flags;
  1164. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1165. if (conf->flags & IEEE80211_CONF_PS)
  1166. ath9k_enable_ps(sc);
  1167. else
  1168. ath9k_disable_ps(sc);
  1169. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1170. }
  1171. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  1172. if (conf->flags & IEEE80211_CONF_MONITOR) {
  1173. ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
  1174. sc->sc_ah->is_monitoring = true;
  1175. } else {
  1176. ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
  1177. sc->sc_ah->is_monitoring = false;
  1178. }
  1179. }
  1180. if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
  1181. ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
  1182. ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
  1183. }
  1184. mutex_unlock(&sc->mutex);
  1185. ath9k_ps_restore(sc);
  1186. return 0;
  1187. }
  1188. #define SUPPORTED_FILTERS \
  1189. (FIF_ALLMULTI | \
  1190. FIF_CONTROL | \
  1191. FIF_PSPOLL | \
  1192. FIF_OTHER_BSS | \
  1193. FIF_BCN_PRBRESP_PROMISC | \
  1194. FIF_PROBE_REQ | \
  1195. FIF_FCSFAIL)
  1196. /* FIXME: sc->sc_full_reset ? */
  1197. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1198. unsigned int changed_flags,
  1199. unsigned int *total_flags,
  1200. u64 multicast)
  1201. {
  1202. struct ath_softc *sc = hw->priv;
  1203. struct ath_chanctx *ctx;
  1204. u32 rfilt;
  1205. changed_flags &= SUPPORTED_FILTERS;
  1206. *total_flags &= SUPPORTED_FILTERS;
  1207. spin_lock_bh(&sc->chan_lock);
  1208. ath_for_each_chanctx(sc, ctx)
  1209. ctx->rxfilter = *total_flags;
  1210. #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
  1211. sc->offchannel.chan.rxfilter = *total_flags;
  1212. #endif
  1213. spin_unlock_bh(&sc->chan_lock);
  1214. ath9k_ps_wakeup(sc);
  1215. rfilt = ath_calcrxfilter(sc);
  1216. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1217. ath9k_ps_restore(sc);
  1218. ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
  1219. rfilt);
  1220. }
  1221. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1222. struct ieee80211_vif *vif,
  1223. struct ieee80211_sta *sta)
  1224. {
  1225. struct ath_softc *sc = hw->priv;
  1226. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1227. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1228. struct ieee80211_key_conf ps_key = { };
  1229. int key;
  1230. ath_node_attach(sc, sta, vif);
  1231. if (vif->type != NL80211_IFTYPE_AP &&
  1232. vif->type != NL80211_IFTYPE_AP_VLAN)
  1233. return 0;
  1234. key = ath_key_config(common, vif, sta, &ps_key);
  1235. if (key > 0) {
  1236. an->ps_key = key;
  1237. an->key_idx[0] = key;
  1238. }
  1239. return 0;
  1240. }
  1241. static void ath9k_del_ps_key(struct ath_softc *sc,
  1242. struct ieee80211_vif *vif,
  1243. struct ieee80211_sta *sta)
  1244. {
  1245. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1246. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1247. struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
  1248. if (!an->ps_key)
  1249. return;
  1250. ath_key_delete(common, &ps_key);
  1251. an->ps_key = 0;
  1252. an->key_idx[0] = 0;
  1253. }
  1254. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1255. struct ieee80211_vif *vif,
  1256. struct ieee80211_sta *sta)
  1257. {
  1258. struct ath_softc *sc = hw->priv;
  1259. ath9k_del_ps_key(sc, vif, sta);
  1260. ath_node_detach(sc, sta);
  1261. return 0;
  1262. }
  1263. static int ath9k_sta_state(struct ieee80211_hw *hw,
  1264. struct ieee80211_vif *vif,
  1265. struct ieee80211_sta *sta,
  1266. enum ieee80211_sta_state old_state,
  1267. enum ieee80211_sta_state new_state)
  1268. {
  1269. struct ath_softc *sc = hw->priv;
  1270. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1271. int ret = 0;
  1272. if (old_state == IEEE80211_STA_NOTEXIST &&
  1273. new_state == IEEE80211_STA_NONE) {
  1274. ret = ath9k_sta_add(hw, vif, sta);
  1275. ath_dbg(common, CONFIG,
  1276. "Add station: %pM\n", sta->addr);
  1277. } else if (old_state == IEEE80211_STA_NONE &&
  1278. new_state == IEEE80211_STA_NOTEXIST) {
  1279. ret = ath9k_sta_remove(hw, vif, sta);
  1280. ath_dbg(common, CONFIG,
  1281. "Remove station: %pM\n", sta->addr);
  1282. }
  1283. if (ath9k_is_chanctx_enabled()) {
  1284. if (vif->type == NL80211_IFTYPE_STATION) {
  1285. if (old_state == IEEE80211_STA_ASSOC &&
  1286. new_state == IEEE80211_STA_AUTHORIZED)
  1287. ath_chanctx_event(sc, vif,
  1288. ATH_CHANCTX_EVENT_AUTHORIZED);
  1289. }
  1290. }
  1291. return ret;
  1292. }
  1293. static void ath9k_sta_set_tx_filter(struct ath_hw *ah,
  1294. struct ath_node *an,
  1295. bool set)
  1296. {
  1297. int i;
  1298. for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
  1299. if (!an->key_idx[i])
  1300. continue;
  1301. ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);
  1302. }
  1303. }
  1304. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1305. struct ieee80211_vif *vif,
  1306. enum sta_notify_cmd cmd,
  1307. struct ieee80211_sta *sta)
  1308. {
  1309. struct ath_softc *sc = hw->priv;
  1310. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1311. switch (cmd) {
  1312. case STA_NOTIFY_SLEEP:
  1313. an->sleeping = true;
  1314. ath_tx_aggr_sleep(sta, sc, an);
  1315. ath9k_sta_set_tx_filter(sc->sc_ah, an, true);
  1316. break;
  1317. case STA_NOTIFY_AWAKE:
  1318. ath9k_sta_set_tx_filter(sc->sc_ah, an, false);
  1319. an->sleeping = false;
  1320. ath_tx_aggr_wakeup(sc, an);
  1321. break;
  1322. }
  1323. }
  1324. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1325. struct ieee80211_vif *vif, u16 queue,
  1326. const struct ieee80211_tx_queue_params *params)
  1327. {
  1328. struct ath_softc *sc = hw->priv;
  1329. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1330. struct ath_txq *txq;
  1331. struct ath9k_tx_queue_info qi;
  1332. int ret = 0;
  1333. if (queue >= IEEE80211_NUM_ACS)
  1334. return 0;
  1335. txq = sc->tx.txq_map[queue];
  1336. ath9k_ps_wakeup(sc);
  1337. mutex_lock(&sc->mutex);
  1338. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1339. qi.tqi_aifs = params->aifs;
  1340. qi.tqi_cwmin = params->cw_min;
  1341. qi.tqi_cwmax = params->cw_max;
  1342. qi.tqi_burstTime = params->txop * 32;
  1343. ath_dbg(common, CONFIG,
  1344. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1345. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1346. params->cw_max, params->txop);
  1347. ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
  1348. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1349. if (ret)
  1350. ath_err(common, "TXQ Update failed\n");
  1351. mutex_unlock(&sc->mutex);
  1352. ath9k_ps_restore(sc);
  1353. return ret;
  1354. }
  1355. static int ath9k_set_key(struct ieee80211_hw *hw,
  1356. enum set_key_cmd cmd,
  1357. struct ieee80211_vif *vif,
  1358. struct ieee80211_sta *sta,
  1359. struct ieee80211_key_conf *key)
  1360. {
  1361. struct ath_softc *sc = hw->priv;
  1362. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1363. struct ath_node *an = NULL;
  1364. int ret = 0, i;
  1365. if (ath9k_modparam_nohwcrypt)
  1366. return -ENOSPC;
  1367. if ((vif->type == NL80211_IFTYPE_ADHOC ||
  1368. vif->type == NL80211_IFTYPE_MESH_POINT) &&
  1369. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  1370. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  1371. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  1372. /*
  1373. * For now, disable hw crypto for the RSN IBSS group keys. This
  1374. * could be optimized in the future to use a modified key cache
  1375. * design to support per-STA RX GTK, but until that gets
  1376. * implemented, use of software crypto for group addressed
  1377. * frames is a acceptable to allow RSN IBSS to be used.
  1378. */
  1379. return -EOPNOTSUPP;
  1380. }
  1381. mutex_lock(&sc->mutex);
  1382. ath9k_ps_wakeup(sc);
  1383. ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
  1384. if (sta)
  1385. an = (struct ath_node *)sta->drv_priv;
  1386. switch (cmd) {
  1387. case SET_KEY:
  1388. if (sta)
  1389. ath9k_del_ps_key(sc, vif, sta);
  1390. key->hw_key_idx = 0;
  1391. ret = ath_key_config(common, vif, sta, key);
  1392. if (ret >= 0) {
  1393. key->hw_key_idx = ret;
  1394. /* push IV and Michael MIC generation to stack */
  1395. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1396. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1397. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1398. if (sc->sc_ah->sw_mgmt_crypto_tx &&
  1399. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1400. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
  1401. ret = 0;
  1402. }
  1403. if (an && key->hw_key_idx) {
  1404. for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
  1405. if (an->key_idx[i])
  1406. continue;
  1407. an->key_idx[i] = key->hw_key_idx;
  1408. break;
  1409. }
  1410. WARN_ON(i == ARRAY_SIZE(an->key_idx));
  1411. }
  1412. break;
  1413. case DISABLE_KEY:
  1414. ath_key_delete(common, key);
  1415. if (an) {
  1416. for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
  1417. if (an->key_idx[i] != key->hw_key_idx)
  1418. continue;
  1419. an->key_idx[i] = 0;
  1420. break;
  1421. }
  1422. }
  1423. key->hw_key_idx = 0;
  1424. break;
  1425. default:
  1426. ret = -EINVAL;
  1427. }
  1428. ath9k_ps_restore(sc);
  1429. mutex_unlock(&sc->mutex);
  1430. return ret;
  1431. }
  1432. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1433. struct ieee80211_vif *vif,
  1434. struct ieee80211_bss_conf *bss_conf,
  1435. u32 changed)
  1436. {
  1437. #define CHECK_ANI \
  1438. (BSS_CHANGED_ASSOC | \
  1439. BSS_CHANGED_IBSS | \
  1440. BSS_CHANGED_BEACON_ENABLED)
  1441. struct ath_softc *sc = hw->priv;
  1442. struct ath_hw *ah = sc->sc_ah;
  1443. struct ath_common *common = ath9k_hw_common(ah);
  1444. struct ath_vif *avp = (void *)vif->drv_priv;
  1445. int slottime;
  1446. ath9k_ps_wakeup(sc);
  1447. mutex_lock(&sc->mutex);
  1448. if (changed & BSS_CHANGED_ASSOC) {
  1449. ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
  1450. bss_conf->bssid, bss_conf->assoc);
  1451. memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
  1452. avp->aid = bss_conf->aid;
  1453. avp->assoc = bss_conf->assoc;
  1454. ath9k_calculate_summary_state(sc, avp->chanctx);
  1455. }
  1456. if ((changed & BSS_CHANGED_IBSS) ||
  1457. (changed & BSS_CHANGED_OCB)) {
  1458. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1459. common->curaid = bss_conf->aid;
  1460. ath9k_hw_write_associd(sc->sc_ah);
  1461. }
  1462. if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
  1463. (changed & BSS_CHANGED_BEACON_INT) ||
  1464. (changed & BSS_CHANGED_BEACON_INFO)) {
  1465. ath9k_calculate_summary_state(sc, avp->chanctx);
  1466. }
  1467. if ((avp->chanctx == sc->cur_chan) &&
  1468. (changed & BSS_CHANGED_ERP_SLOT)) {
  1469. if (bss_conf->use_short_slot)
  1470. slottime = 9;
  1471. else
  1472. slottime = 20;
  1473. if (vif->type == NL80211_IFTYPE_AP) {
  1474. /*
  1475. * Defer update, so that connected stations can adjust
  1476. * their settings at the same time.
  1477. * See beacon.c for more details
  1478. */
  1479. sc->beacon.slottime = slottime;
  1480. sc->beacon.updateslot = UPDATE;
  1481. } else {
  1482. ah->slottime = slottime;
  1483. ath9k_hw_init_global_settings(ah);
  1484. }
  1485. }
  1486. if (changed & BSS_CHANGED_P2P_PS)
  1487. ath9k_p2p_bss_info_changed(sc, vif);
  1488. if (changed & CHECK_ANI)
  1489. ath_check_ani(sc);
  1490. if (changed & BSS_CHANGED_TXPOWER) {
  1491. ath_dbg(common, CONFIG, "vif %pM power %d dbm power_type %d\n",
  1492. vif->addr, bss_conf->txpower, bss_conf->txpower_type);
  1493. ath9k_set_txpower(sc, vif);
  1494. }
  1495. mutex_unlock(&sc->mutex);
  1496. ath9k_ps_restore(sc);
  1497. #undef CHECK_ANI
  1498. }
  1499. static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1500. {
  1501. struct ath_softc *sc = hw->priv;
  1502. struct ath_vif *avp = (void *)vif->drv_priv;
  1503. u64 tsf;
  1504. mutex_lock(&sc->mutex);
  1505. ath9k_ps_wakeup(sc);
  1506. /* Get current TSF either from HW or kernel time. */
  1507. if (sc->cur_chan == avp->chanctx) {
  1508. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1509. } else {
  1510. tsf = sc->cur_chan->tsf_val +
  1511. ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts, NULL);
  1512. }
  1513. tsf += le64_to_cpu(avp->tsf_adjust);
  1514. ath9k_ps_restore(sc);
  1515. mutex_unlock(&sc->mutex);
  1516. return tsf;
  1517. }
  1518. static void ath9k_set_tsf(struct ieee80211_hw *hw,
  1519. struct ieee80211_vif *vif,
  1520. u64 tsf)
  1521. {
  1522. struct ath_softc *sc = hw->priv;
  1523. struct ath_vif *avp = (void *)vif->drv_priv;
  1524. mutex_lock(&sc->mutex);
  1525. ath9k_ps_wakeup(sc);
  1526. tsf -= le64_to_cpu(avp->tsf_adjust);
  1527. getrawmonotonic(&avp->chanctx->tsf_ts);
  1528. if (sc->cur_chan == avp->chanctx)
  1529. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1530. avp->chanctx->tsf_val = tsf;
  1531. ath9k_ps_restore(sc);
  1532. mutex_unlock(&sc->mutex);
  1533. }
  1534. static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1535. {
  1536. struct ath_softc *sc = hw->priv;
  1537. struct ath_vif *avp = (void *)vif->drv_priv;
  1538. mutex_lock(&sc->mutex);
  1539. ath9k_ps_wakeup(sc);
  1540. getrawmonotonic(&avp->chanctx->tsf_ts);
  1541. if (sc->cur_chan == avp->chanctx)
  1542. ath9k_hw_reset_tsf(sc->sc_ah);
  1543. avp->chanctx->tsf_val = 0;
  1544. ath9k_ps_restore(sc);
  1545. mutex_unlock(&sc->mutex);
  1546. }
  1547. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1548. struct ieee80211_vif *vif,
  1549. struct ieee80211_ampdu_params *params)
  1550. {
  1551. struct ath_softc *sc = hw->priv;
  1552. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1553. bool flush = false;
  1554. int ret = 0;
  1555. struct ieee80211_sta *sta = params->sta;
  1556. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  1557. enum ieee80211_ampdu_mlme_action action = params->action;
  1558. u16 tid = params->tid;
  1559. u16 *ssn = &params->ssn;
  1560. struct ath_atx_tid *atid;
  1561. mutex_lock(&sc->mutex);
  1562. switch (action) {
  1563. case IEEE80211_AMPDU_RX_START:
  1564. break;
  1565. case IEEE80211_AMPDU_RX_STOP:
  1566. break;
  1567. case IEEE80211_AMPDU_TX_START:
  1568. if (ath9k_is_chanctx_enabled()) {
  1569. if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
  1570. ret = -EBUSY;
  1571. break;
  1572. }
  1573. }
  1574. ath9k_ps_wakeup(sc);
  1575. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1576. if (!ret)
  1577. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1578. ath9k_ps_restore(sc);
  1579. break;
  1580. case IEEE80211_AMPDU_TX_STOP_FLUSH:
  1581. case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
  1582. flush = true;
  1583. case IEEE80211_AMPDU_TX_STOP_CONT:
  1584. ath9k_ps_wakeup(sc);
  1585. ath_tx_aggr_stop(sc, sta, tid);
  1586. if (!flush)
  1587. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1588. ath9k_ps_restore(sc);
  1589. break;
  1590. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1591. atid = ath_node_to_tid(an, tid);
  1592. atid->baw_size = IEEE80211_MIN_AMPDU_BUF <<
  1593. sta->ht_cap.ampdu_factor;
  1594. break;
  1595. default:
  1596. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1597. }
  1598. mutex_unlock(&sc->mutex);
  1599. return ret;
  1600. }
  1601. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1602. struct survey_info *survey)
  1603. {
  1604. struct ath_softc *sc = hw->priv;
  1605. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1606. struct ieee80211_supported_band *sband;
  1607. struct ieee80211_channel *chan;
  1608. int pos;
  1609. if (IS_ENABLED(CONFIG_ATH9K_TX99))
  1610. return -EOPNOTSUPP;
  1611. spin_lock_bh(&common->cc_lock);
  1612. if (idx == 0)
  1613. ath_update_survey_stats(sc);
  1614. sband = hw->wiphy->bands[NL80211_BAND_2GHZ];
  1615. if (sband && idx >= sband->n_channels) {
  1616. idx -= sband->n_channels;
  1617. sband = NULL;
  1618. }
  1619. if (!sband)
  1620. sband = hw->wiphy->bands[NL80211_BAND_5GHZ];
  1621. if (!sband || idx >= sband->n_channels) {
  1622. spin_unlock_bh(&common->cc_lock);
  1623. return -ENOENT;
  1624. }
  1625. chan = &sband->channels[idx];
  1626. pos = chan->hw_value;
  1627. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1628. survey->channel = chan;
  1629. spin_unlock_bh(&common->cc_lock);
  1630. return 0;
  1631. }
  1632. static void ath9k_enable_dynack(struct ath_softc *sc)
  1633. {
  1634. #ifdef CONFIG_ATH9K_DYNACK
  1635. u32 rfilt;
  1636. struct ath_hw *ah = sc->sc_ah;
  1637. ath_dynack_reset(ah);
  1638. ah->dynack.enabled = true;
  1639. rfilt = ath_calcrxfilter(sc);
  1640. ath9k_hw_setrxfilter(ah, rfilt);
  1641. #endif
  1642. }
  1643. static void ath9k_set_coverage_class(struct ieee80211_hw *hw,
  1644. s16 coverage_class)
  1645. {
  1646. struct ath_softc *sc = hw->priv;
  1647. struct ath_hw *ah = sc->sc_ah;
  1648. if (IS_ENABLED(CONFIG_ATH9K_TX99))
  1649. return;
  1650. mutex_lock(&sc->mutex);
  1651. if (coverage_class >= 0) {
  1652. ah->coverage_class = coverage_class;
  1653. if (ah->dynack.enabled) {
  1654. u32 rfilt;
  1655. ah->dynack.enabled = false;
  1656. rfilt = ath_calcrxfilter(sc);
  1657. ath9k_hw_setrxfilter(ah, rfilt);
  1658. }
  1659. ath9k_ps_wakeup(sc);
  1660. ath9k_hw_init_global_settings(ah);
  1661. ath9k_ps_restore(sc);
  1662. } else if (!ah->dynack.enabled) {
  1663. ath9k_enable_dynack(sc);
  1664. }
  1665. mutex_unlock(&sc->mutex);
  1666. }
  1667. static bool ath9k_has_tx_pending(struct ath_softc *sc,
  1668. bool sw_pending)
  1669. {
  1670. int i, npend = 0;
  1671. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1672. if (!ATH_TXQ_SETUP(sc, i))
  1673. continue;
  1674. npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i],
  1675. sw_pending);
  1676. if (npend)
  1677. break;
  1678. }
  1679. return !!npend;
  1680. }
  1681. static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  1682. u32 queues, bool drop)
  1683. {
  1684. struct ath_softc *sc = hw->priv;
  1685. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1686. if (ath9k_is_chanctx_enabled()) {
  1687. if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
  1688. goto flush;
  1689. /*
  1690. * If MCC is active, extend the flush timeout
  1691. * and wait for the HW/SW queues to become
  1692. * empty. This needs to be done outside the
  1693. * sc->mutex lock to allow the channel scheduler
  1694. * to switch channel contexts.
  1695. *
  1696. * The vif queues have been stopped in mac80211,
  1697. * so there won't be any incoming frames.
  1698. */
  1699. __ath9k_flush(hw, queues, drop, true, true);
  1700. return;
  1701. }
  1702. flush:
  1703. mutex_lock(&sc->mutex);
  1704. __ath9k_flush(hw, queues, drop, true, false);
  1705. mutex_unlock(&sc->mutex);
  1706. }
  1707. void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop,
  1708. bool sw_pending, bool timeout_override)
  1709. {
  1710. struct ath_softc *sc = hw->priv;
  1711. struct ath_hw *ah = sc->sc_ah;
  1712. struct ath_common *common = ath9k_hw_common(ah);
  1713. int timeout;
  1714. bool drain_txq;
  1715. cancel_delayed_work_sync(&sc->hw_check_work);
  1716. if (ah->ah_flags & AH_UNPLUGGED) {
  1717. ath_dbg(common, ANY, "Device has been unplugged!\n");
  1718. return;
  1719. }
  1720. if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
  1721. ath_dbg(common, ANY, "Device not present\n");
  1722. return;
  1723. }
  1724. spin_lock_bh(&sc->chan_lock);
  1725. if (timeout_override)
  1726. timeout = HZ / 5;
  1727. else
  1728. timeout = sc->cur_chan->flush_timeout;
  1729. spin_unlock_bh(&sc->chan_lock);
  1730. ath_dbg(common, CHAN_CTX,
  1731. "Flush timeout: %d\n", jiffies_to_msecs(timeout));
  1732. if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc, sw_pending),
  1733. timeout) > 0)
  1734. drop = false;
  1735. if (drop) {
  1736. ath9k_ps_wakeup(sc);
  1737. spin_lock_bh(&sc->sc_pcu_lock);
  1738. drain_txq = ath_drain_all_txq(sc);
  1739. spin_unlock_bh(&sc->sc_pcu_lock);
  1740. if (!drain_txq)
  1741. ath_reset(sc, NULL);
  1742. ath9k_ps_restore(sc);
  1743. }
  1744. ieee80211_queue_delayed_work(hw, &sc->hw_check_work,
  1745. ATH_HW_CHECK_POLL_INT);
  1746. }
  1747. static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
  1748. {
  1749. struct ath_softc *sc = hw->priv;
  1750. return ath9k_has_tx_pending(sc, true);
  1751. }
  1752. static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
  1753. {
  1754. struct ath_softc *sc = hw->priv;
  1755. struct ath_hw *ah = sc->sc_ah;
  1756. struct ieee80211_vif *vif;
  1757. struct ath_vif *avp;
  1758. struct ath_buf *bf;
  1759. struct ath_tx_status ts;
  1760. bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1761. int status;
  1762. vif = sc->beacon.bslot[0];
  1763. if (!vif)
  1764. return 0;
  1765. if (!vif->bss_conf.enable_beacon)
  1766. return 0;
  1767. avp = (void *)vif->drv_priv;
  1768. if (!sc->beacon.tx_processed && !edma) {
  1769. tasklet_disable(&sc->bcon_tasklet);
  1770. bf = avp->av_bcbuf;
  1771. if (!bf || !bf->bf_mpdu)
  1772. goto skip;
  1773. status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
  1774. if (status == -EINPROGRESS)
  1775. goto skip;
  1776. sc->beacon.tx_processed = true;
  1777. sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
  1778. skip:
  1779. tasklet_enable(&sc->bcon_tasklet);
  1780. }
  1781. return sc->beacon.tx_last;
  1782. }
  1783. static int ath9k_get_stats(struct ieee80211_hw *hw,
  1784. struct ieee80211_low_level_stats *stats)
  1785. {
  1786. struct ath_softc *sc = hw->priv;
  1787. struct ath_hw *ah = sc->sc_ah;
  1788. struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
  1789. stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
  1790. stats->dot11RTSFailureCount = mib_stats->rts_bad;
  1791. stats->dot11FCSErrorCount = mib_stats->fcs_bad;
  1792. stats->dot11RTSSuccessCount = mib_stats->rts_good;
  1793. return 0;
  1794. }
  1795. static u32 fill_chainmask(u32 cap, u32 new)
  1796. {
  1797. u32 filled = 0;
  1798. int i;
  1799. for (i = 0; cap && new; i++, cap >>= 1) {
  1800. if (!(cap & BIT(0)))
  1801. continue;
  1802. if (new & BIT(0))
  1803. filled |= BIT(i);
  1804. new >>= 1;
  1805. }
  1806. return filled;
  1807. }
  1808. static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
  1809. {
  1810. if (AR_SREV_9300_20_OR_LATER(ah))
  1811. return true;
  1812. switch (val & 0x7) {
  1813. case 0x1:
  1814. case 0x3:
  1815. case 0x7:
  1816. return true;
  1817. case 0x2:
  1818. return (ah->caps.rx_chainmask == 1);
  1819. default:
  1820. return false;
  1821. }
  1822. }
  1823. static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
  1824. {
  1825. struct ath_softc *sc = hw->priv;
  1826. struct ath_hw *ah = sc->sc_ah;
  1827. if (ah->caps.rx_chainmask != 1)
  1828. rx_ant |= tx_ant;
  1829. if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
  1830. return -EINVAL;
  1831. sc->ant_rx = rx_ant;
  1832. sc->ant_tx = tx_ant;
  1833. if (ah->caps.rx_chainmask == 1)
  1834. return 0;
  1835. /* AR9100 runs into calibration issues if not all rx chains are enabled */
  1836. if (AR_SREV_9100(ah))
  1837. ah->rxchainmask = 0x7;
  1838. else
  1839. ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
  1840. ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
  1841. ath9k_cmn_reload_chainmask(ah);
  1842. return 0;
  1843. }
  1844. static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
  1845. {
  1846. struct ath_softc *sc = hw->priv;
  1847. *tx_ant = sc->ant_tx;
  1848. *rx_ant = sc->ant_rx;
  1849. return 0;
  1850. }
  1851. static void ath9k_sw_scan_start(struct ieee80211_hw *hw,
  1852. struct ieee80211_vif *vif,
  1853. const u8 *mac_addr)
  1854. {
  1855. struct ath_softc *sc = hw->priv;
  1856. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1857. set_bit(ATH_OP_SCANNING, &common->op_flags);
  1858. }
  1859. static void ath9k_sw_scan_complete(struct ieee80211_hw *hw,
  1860. struct ieee80211_vif *vif)
  1861. {
  1862. struct ath_softc *sc = hw->priv;
  1863. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1864. clear_bit(ATH_OP_SCANNING, &common->op_flags);
  1865. }
  1866. #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
  1867. static void ath9k_cancel_pending_offchannel(struct ath_softc *sc)
  1868. {
  1869. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1870. if (sc->offchannel.roc_vif) {
  1871. ath_dbg(common, CHAN_CTX,
  1872. "%s: Aborting RoC\n", __func__);
  1873. del_timer_sync(&sc->offchannel.timer);
  1874. if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
  1875. ath_roc_complete(sc, ATH_ROC_COMPLETE_ABORT);
  1876. }
  1877. if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
  1878. ath_dbg(common, CHAN_CTX,
  1879. "%s: Aborting HW scan\n", __func__);
  1880. del_timer_sync(&sc->offchannel.timer);
  1881. ath_scan_complete(sc, true);
  1882. }
  1883. }
  1884. static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  1885. struct ieee80211_scan_request *hw_req)
  1886. {
  1887. struct cfg80211_scan_request *req = &hw_req->req;
  1888. struct ath_softc *sc = hw->priv;
  1889. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1890. int ret = 0;
  1891. mutex_lock(&sc->mutex);
  1892. if (WARN_ON(sc->offchannel.scan_req)) {
  1893. ret = -EBUSY;
  1894. goto out;
  1895. }
  1896. ath9k_ps_wakeup(sc);
  1897. set_bit(ATH_OP_SCANNING, &common->op_flags);
  1898. sc->offchannel.scan_vif = vif;
  1899. sc->offchannel.scan_req = req;
  1900. sc->offchannel.scan_idx = 0;
  1901. ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",
  1902. vif->addr);
  1903. if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
  1904. ath_dbg(common, CHAN_CTX, "Starting HW scan\n");
  1905. ath_offchannel_next(sc);
  1906. }
  1907. out:
  1908. mutex_unlock(&sc->mutex);
  1909. return ret;
  1910. }
  1911. static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
  1912. struct ieee80211_vif *vif)
  1913. {
  1914. struct ath_softc *sc = hw->priv;
  1915. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1916. ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);
  1917. mutex_lock(&sc->mutex);
  1918. del_timer_sync(&sc->offchannel.timer);
  1919. ath_scan_complete(sc, true);
  1920. mutex_unlock(&sc->mutex);
  1921. }
  1922. static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
  1923. struct ieee80211_vif *vif,
  1924. struct ieee80211_channel *chan, int duration,
  1925. enum ieee80211_roc_type type)
  1926. {
  1927. struct ath_softc *sc = hw->priv;
  1928. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1929. int ret = 0;
  1930. mutex_lock(&sc->mutex);
  1931. if (WARN_ON(sc->offchannel.roc_vif)) {
  1932. ret = -EBUSY;
  1933. goto out;
  1934. }
  1935. ath9k_ps_wakeup(sc);
  1936. sc->offchannel.roc_vif = vif;
  1937. sc->offchannel.roc_chan = chan;
  1938. sc->offchannel.roc_duration = duration;
  1939. ath_dbg(common, CHAN_CTX,
  1940. "RoC request on vif: %pM, type: %d duration: %d\n",
  1941. vif->addr, type, duration);
  1942. if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
  1943. ath_dbg(common, CHAN_CTX, "Starting RoC period\n");
  1944. ath_offchannel_next(sc);
  1945. }
  1946. out:
  1947. mutex_unlock(&sc->mutex);
  1948. return ret;
  1949. }
  1950. static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw)
  1951. {
  1952. struct ath_softc *sc = hw->priv;
  1953. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1954. mutex_lock(&sc->mutex);
  1955. ath_dbg(common, CHAN_CTX, "Cancel RoC\n");
  1956. del_timer_sync(&sc->offchannel.timer);
  1957. if (sc->offchannel.roc_vif) {
  1958. if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
  1959. ath_roc_complete(sc, ATH_ROC_COMPLETE_CANCEL);
  1960. }
  1961. mutex_unlock(&sc->mutex);
  1962. return 0;
  1963. }
  1964. static int ath9k_add_chanctx(struct ieee80211_hw *hw,
  1965. struct ieee80211_chanctx_conf *conf)
  1966. {
  1967. struct ath_softc *sc = hw->priv;
  1968. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1969. struct ath_chanctx *ctx, **ptr;
  1970. int pos;
  1971. mutex_lock(&sc->mutex);
  1972. ath_for_each_chanctx(sc, ctx) {
  1973. if (ctx->assigned)
  1974. continue;
  1975. ptr = (void *) conf->drv_priv;
  1976. *ptr = ctx;
  1977. ctx->assigned = true;
  1978. pos = ctx - &sc->chanctx[0];
  1979. ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;
  1980. ath_dbg(common, CHAN_CTX,
  1981. "Add channel context: %d MHz\n",
  1982. conf->def.chan->center_freq);
  1983. ath_chanctx_set_channel(sc, ctx, &conf->def);
  1984. mutex_unlock(&sc->mutex);
  1985. return 0;
  1986. }
  1987. mutex_unlock(&sc->mutex);
  1988. return -ENOSPC;
  1989. }
  1990. static void ath9k_remove_chanctx(struct ieee80211_hw *hw,
  1991. struct ieee80211_chanctx_conf *conf)
  1992. {
  1993. struct ath_softc *sc = hw->priv;
  1994. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1995. struct ath_chanctx *ctx = ath_chanctx_get(conf);
  1996. mutex_lock(&sc->mutex);
  1997. ath_dbg(common, CHAN_CTX,
  1998. "Remove channel context: %d MHz\n",
  1999. conf->def.chan->center_freq);
  2000. ctx->assigned = false;
  2001. ctx->hw_queue_base = 0;
  2002. ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);
  2003. mutex_unlock(&sc->mutex);
  2004. }
  2005. static void ath9k_change_chanctx(struct ieee80211_hw *hw,
  2006. struct ieee80211_chanctx_conf *conf,
  2007. u32 changed)
  2008. {
  2009. struct ath_softc *sc = hw->priv;
  2010. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  2011. struct ath_chanctx *ctx = ath_chanctx_get(conf);
  2012. mutex_lock(&sc->mutex);
  2013. ath_dbg(common, CHAN_CTX,
  2014. "Change channel context: %d MHz\n",
  2015. conf->def.chan->center_freq);
  2016. ath_chanctx_set_channel(sc, ctx, &conf->def);
  2017. mutex_unlock(&sc->mutex);
  2018. }
  2019. static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,
  2020. struct ieee80211_vif *vif,
  2021. struct ieee80211_chanctx_conf *conf)
  2022. {
  2023. struct ath_softc *sc = hw->priv;
  2024. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  2025. struct ath_vif *avp = (void *)vif->drv_priv;
  2026. struct ath_chanctx *ctx = ath_chanctx_get(conf);
  2027. int i;
  2028. ath9k_cancel_pending_offchannel(sc);
  2029. mutex_lock(&sc->mutex);
  2030. ath_dbg(common, CHAN_CTX,
  2031. "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",
  2032. vif->addr, vif->type, vif->p2p,
  2033. conf->def.chan->center_freq);
  2034. avp->chanctx = ctx;
  2035. ctx->nvifs_assigned++;
  2036. list_add_tail(&avp->list, &ctx->vifs);
  2037. ath9k_calculate_summary_state(sc, ctx);
  2038. for (i = 0; i < IEEE80211_NUM_ACS; i++)
  2039. vif->hw_queue[i] = ctx->hw_queue_base + i;
  2040. mutex_unlock(&sc->mutex);
  2041. return 0;
  2042. }
  2043. static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,
  2044. struct ieee80211_vif *vif,
  2045. struct ieee80211_chanctx_conf *conf)
  2046. {
  2047. struct ath_softc *sc = hw->priv;
  2048. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  2049. struct ath_vif *avp = (void *)vif->drv_priv;
  2050. struct ath_chanctx *ctx = ath_chanctx_get(conf);
  2051. int ac;
  2052. ath9k_cancel_pending_offchannel(sc);
  2053. mutex_lock(&sc->mutex);
  2054. ath_dbg(common, CHAN_CTX,
  2055. "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",
  2056. vif->addr, vif->type, vif->p2p,
  2057. conf->def.chan->center_freq);
  2058. avp->chanctx = NULL;
  2059. ctx->nvifs_assigned--;
  2060. list_del(&avp->list);
  2061. ath9k_calculate_summary_state(sc, ctx);
  2062. for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
  2063. vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;
  2064. mutex_unlock(&sc->mutex);
  2065. }
  2066. static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw,
  2067. struct ieee80211_vif *vif)
  2068. {
  2069. struct ath_softc *sc = hw->priv;
  2070. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  2071. struct ath_vif *avp = (struct ath_vif *) vif->drv_priv;
  2072. struct ath_beacon_config *cur_conf;
  2073. struct ath_chanctx *go_ctx;
  2074. unsigned long timeout;
  2075. bool changed = false;
  2076. u32 beacon_int;
  2077. if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
  2078. return;
  2079. if (!avp->chanctx)
  2080. return;
  2081. mutex_lock(&sc->mutex);
  2082. spin_lock_bh(&sc->chan_lock);
  2083. if (sc->next_chan || (sc->cur_chan != avp->chanctx))
  2084. changed = true;
  2085. spin_unlock_bh(&sc->chan_lock);
  2086. if (!changed)
  2087. goto out;
  2088. ath9k_cancel_pending_offchannel(sc);
  2089. go_ctx = ath_is_go_chanctx_present(sc);
  2090. if (go_ctx) {
  2091. /*
  2092. * Wait till the GO interface gets a chance
  2093. * to send out an NoA.
  2094. */
  2095. spin_lock_bh(&sc->chan_lock);
  2096. sc->sched.mgd_prepare_tx = true;
  2097. cur_conf = &go_ctx->beacon;
  2098. beacon_int = TU_TO_USEC(cur_conf->beacon_interval);
  2099. spin_unlock_bh(&sc->chan_lock);
  2100. timeout = usecs_to_jiffies(beacon_int * 2);
  2101. init_completion(&sc->go_beacon);
  2102. mutex_unlock(&sc->mutex);
  2103. if (wait_for_completion_timeout(&sc->go_beacon,
  2104. timeout) == 0) {
  2105. ath_dbg(common, CHAN_CTX,
  2106. "Failed to send new NoA\n");
  2107. spin_lock_bh(&sc->chan_lock);
  2108. sc->sched.mgd_prepare_tx = false;
  2109. spin_unlock_bh(&sc->chan_lock);
  2110. }
  2111. mutex_lock(&sc->mutex);
  2112. }
  2113. ath_dbg(common, CHAN_CTX,
  2114. "%s: Set chanctx state to FORCE_ACTIVE for vif: %pM\n",
  2115. __func__, vif->addr);
  2116. spin_lock_bh(&sc->chan_lock);
  2117. sc->next_chan = avp->chanctx;
  2118. sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE;
  2119. spin_unlock_bh(&sc->chan_lock);
  2120. ath_chanctx_set_next(sc, true);
  2121. out:
  2122. mutex_unlock(&sc->mutex);
  2123. }
  2124. void ath9k_fill_chanctx_ops(void)
  2125. {
  2126. if (!ath9k_is_chanctx_enabled())
  2127. return;
  2128. ath9k_ops.hw_scan = ath9k_hw_scan;
  2129. ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan;
  2130. ath9k_ops.remain_on_channel = ath9k_remain_on_channel;
  2131. ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;
  2132. ath9k_ops.add_chanctx = ath9k_add_chanctx;
  2133. ath9k_ops.remove_chanctx = ath9k_remove_chanctx;
  2134. ath9k_ops.change_chanctx = ath9k_change_chanctx;
  2135. ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx;
  2136. ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx;
  2137. ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx;
  2138. }
  2139. #endif
  2140. static int ath9k_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  2141. int *dbm)
  2142. {
  2143. struct ath_softc *sc = hw->priv;
  2144. struct ath_vif *avp = (void *)vif->drv_priv;
  2145. mutex_lock(&sc->mutex);
  2146. if (avp->chanctx)
  2147. *dbm = avp->chanctx->cur_txpower;
  2148. else
  2149. *dbm = sc->cur_chan->cur_txpower;
  2150. mutex_unlock(&sc->mutex);
  2151. *dbm /= 2;
  2152. return 0;
  2153. }
  2154. struct ieee80211_ops ath9k_ops = {
  2155. .tx = ath9k_tx,
  2156. .start = ath9k_start,
  2157. .stop = ath9k_stop,
  2158. .add_interface = ath9k_add_interface,
  2159. .change_interface = ath9k_change_interface,
  2160. .remove_interface = ath9k_remove_interface,
  2161. .config = ath9k_config,
  2162. .configure_filter = ath9k_configure_filter,
  2163. .sta_state = ath9k_sta_state,
  2164. .sta_notify = ath9k_sta_notify,
  2165. .conf_tx = ath9k_conf_tx,
  2166. .bss_info_changed = ath9k_bss_info_changed,
  2167. .set_key = ath9k_set_key,
  2168. .get_tsf = ath9k_get_tsf,
  2169. .set_tsf = ath9k_set_tsf,
  2170. .reset_tsf = ath9k_reset_tsf,
  2171. .ampdu_action = ath9k_ampdu_action,
  2172. .get_survey = ath9k_get_survey,
  2173. .rfkill_poll = ath9k_rfkill_poll_state,
  2174. .set_coverage_class = ath9k_set_coverage_class,
  2175. .flush = ath9k_flush,
  2176. .tx_frames_pending = ath9k_tx_frames_pending,
  2177. .tx_last_beacon = ath9k_tx_last_beacon,
  2178. .release_buffered_frames = ath9k_release_buffered_frames,
  2179. .get_stats = ath9k_get_stats,
  2180. .set_antenna = ath9k_set_antenna,
  2181. .get_antenna = ath9k_get_antenna,
  2182. #ifdef CONFIG_ATH9K_WOW
  2183. .suspend = ath9k_suspend,
  2184. .resume = ath9k_resume,
  2185. .set_wakeup = ath9k_set_wakeup,
  2186. #endif
  2187. #ifdef CONFIG_ATH9K_DEBUGFS
  2188. .get_et_sset_count = ath9k_get_et_sset_count,
  2189. .get_et_stats = ath9k_get_et_stats,
  2190. .get_et_strings = ath9k_get_et_strings,
  2191. #endif
  2192. #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
  2193. .sta_add_debugfs = ath9k_sta_add_debugfs,
  2194. #endif
  2195. .sw_scan_start = ath9k_sw_scan_start,
  2196. .sw_scan_complete = ath9k_sw_scan_complete,
  2197. .get_txpower = ath9k_get_txpower,
  2198. .wake_tx_queue = ath9k_wake_tx_queue,
  2199. };