smsc95xx.c 55 KB

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  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2007-2008 SMSC
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, see <http://www.gnu.org/licenses/>.
  17. *
  18. *****************************************************************************/
  19. #include <linux/module.h>
  20. #include <linux/kmod.h>
  21. #include <linux/netdevice.h>
  22. #include <linux/etherdevice.h>
  23. #include <linux/ethtool.h>
  24. #include <linux/mii.h>
  25. #include <linux/usb.h>
  26. #include <linux/bitrev.h>
  27. #include <linux/crc16.h>
  28. #include <linux/crc32.h>
  29. #include <linux/usb/usbnet.h>
  30. #include <linux/slab.h>
  31. #include <linux/of_net.h>
  32. #include "smsc95xx.h"
  33. #define SMSC_CHIPNAME "smsc95xx"
  34. #define SMSC_DRIVER_VERSION "1.0.6"
  35. #define HS_USB_PKT_SIZE (512)
  36. #define FS_USB_PKT_SIZE (64)
  37. #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
  38. #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
  39. #define DEFAULT_BULK_IN_DELAY (0x00002000)
  40. #define MAX_SINGLE_PACKET_SIZE (2048)
  41. #define LAN95XX_EEPROM_MAGIC (0x9500)
  42. #define EEPROM_MAC_OFFSET (0x01)
  43. #define DEFAULT_TX_CSUM_ENABLE (true)
  44. #define DEFAULT_RX_CSUM_ENABLE (true)
  45. #define SMSC95XX_INTERNAL_PHY_ID (1)
  46. #define SMSC95XX_TX_OVERHEAD (8)
  47. #define SMSC95XX_TX_OVERHEAD_CSUM (12)
  48. #define SUPPORTED_WAKE (WAKE_PHY | WAKE_UCAST | WAKE_BCAST | \
  49. WAKE_MCAST | WAKE_ARP | WAKE_MAGIC)
  50. #define FEATURE_8_WAKEUP_FILTERS (0x01)
  51. #define FEATURE_PHY_NLP_CROSSOVER (0x02)
  52. #define FEATURE_REMOTE_WAKEUP (0x04)
  53. #define SUSPEND_SUSPEND0 (0x01)
  54. #define SUSPEND_SUSPEND1 (0x02)
  55. #define SUSPEND_SUSPEND2 (0x04)
  56. #define SUSPEND_SUSPEND3 (0x08)
  57. #define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
  58. SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
  59. #define CARRIER_CHECK_DELAY (2 * HZ)
  60. struct smsc95xx_priv {
  61. u32 chip_id;
  62. u32 mac_cr;
  63. u32 hash_hi;
  64. u32 hash_lo;
  65. u32 wolopts;
  66. spinlock_t mac_cr_lock;
  67. u8 features;
  68. u8 suspend_flags;
  69. u8 mdix_ctrl;
  70. bool link_ok;
  71. struct delayed_work carrier_check;
  72. struct usbnet *dev;
  73. };
  74. static bool turbo_mode = true;
  75. module_param(turbo_mode, bool, 0644);
  76. MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
  77. static int __must_check __smsc95xx_read_reg(struct usbnet *dev, u32 index,
  78. u32 *data, int in_pm)
  79. {
  80. u32 buf;
  81. int ret;
  82. int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
  83. BUG_ON(!dev);
  84. if (!in_pm)
  85. fn = usbnet_read_cmd;
  86. else
  87. fn = usbnet_read_cmd_nopm;
  88. ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
  89. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  90. 0, index, &buf, 4);
  91. if (unlikely(ret < 0)) {
  92. netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n",
  93. index, ret);
  94. return ret;
  95. }
  96. le32_to_cpus(&buf);
  97. *data = buf;
  98. return ret;
  99. }
  100. static int __must_check __smsc95xx_write_reg(struct usbnet *dev, u32 index,
  101. u32 data, int in_pm)
  102. {
  103. u32 buf;
  104. int ret;
  105. int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
  106. BUG_ON(!dev);
  107. if (!in_pm)
  108. fn = usbnet_write_cmd;
  109. else
  110. fn = usbnet_write_cmd_nopm;
  111. buf = data;
  112. cpu_to_le32s(&buf);
  113. ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT
  114. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  115. 0, index, &buf, 4);
  116. if (unlikely(ret < 0))
  117. netdev_warn(dev->net, "Failed to write reg index 0x%08x: %d\n",
  118. index, ret);
  119. return ret;
  120. }
  121. static int __must_check smsc95xx_read_reg_nopm(struct usbnet *dev, u32 index,
  122. u32 *data)
  123. {
  124. return __smsc95xx_read_reg(dev, index, data, 1);
  125. }
  126. static int __must_check smsc95xx_write_reg_nopm(struct usbnet *dev, u32 index,
  127. u32 data)
  128. {
  129. return __smsc95xx_write_reg(dev, index, data, 1);
  130. }
  131. static int __must_check smsc95xx_read_reg(struct usbnet *dev, u32 index,
  132. u32 *data)
  133. {
  134. return __smsc95xx_read_reg(dev, index, data, 0);
  135. }
  136. static int __must_check smsc95xx_write_reg(struct usbnet *dev, u32 index,
  137. u32 data)
  138. {
  139. return __smsc95xx_write_reg(dev, index, data, 0);
  140. }
  141. /* Loop until the read is completed with timeout
  142. * called with phy_mutex held */
  143. static int __must_check __smsc95xx_phy_wait_not_busy(struct usbnet *dev,
  144. int in_pm)
  145. {
  146. unsigned long start_time = jiffies;
  147. u32 val;
  148. int ret;
  149. do {
  150. ret = __smsc95xx_read_reg(dev, MII_ADDR, &val, in_pm);
  151. if (ret < 0) {
  152. netdev_warn(dev->net, "Error reading MII_ACCESS\n");
  153. return ret;
  154. }
  155. if (!(val & MII_BUSY_))
  156. return 0;
  157. } while (!time_after(jiffies, start_time + HZ));
  158. return -EIO;
  159. }
  160. static int __smsc95xx_mdio_read(struct net_device *netdev, int phy_id, int idx,
  161. int in_pm)
  162. {
  163. struct usbnet *dev = netdev_priv(netdev);
  164. u32 val, addr;
  165. int ret;
  166. mutex_lock(&dev->phy_mutex);
  167. /* confirm MII not busy */
  168. ret = __smsc95xx_phy_wait_not_busy(dev, in_pm);
  169. if (ret < 0) {
  170. netdev_warn(dev->net, "MII is busy in smsc95xx_mdio_read\n");
  171. goto done;
  172. }
  173. /* set the address, index & direction (read from PHY) */
  174. phy_id &= dev->mii.phy_id_mask;
  175. idx &= dev->mii.reg_num_mask;
  176. addr = (phy_id << 11) | (idx << 6) | MII_READ_ | MII_BUSY_;
  177. ret = __smsc95xx_write_reg(dev, MII_ADDR, addr, in_pm);
  178. if (ret < 0) {
  179. netdev_warn(dev->net, "Error writing MII_ADDR\n");
  180. goto done;
  181. }
  182. ret = __smsc95xx_phy_wait_not_busy(dev, in_pm);
  183. if (ret < 0) {
  184. netdev_warn(dev->net, "Timed out reading MII reg %02X\n", idx);
  185. goto done;
  186. }
  187. ret = __smsc95xx_read_reg(dev, MII_DATA, &val, in_pm);
  188. if (ret < 0) {
  189. netdev_warn(dev->net, "Error reading MII_DATA\n");
  190. goto done;
  191. }
  192. ret = (u16)(val & 0xFFFF);
  193. done:
  194. mutex_unlock(&dev->phy_mutex);
  195. return ret;
  196. }
  197. static void __smsc95xx_mdio_write(struct net_device *netdev, int phy_id,
  198. int idx, int regval, int in_pm)
  199. {
  200. struct usbnet *dev = netdev_priv(netdev);
  201. u32 val, addr;
  202. int ret;
  203. mutex_lock(&dev->phy_mutex);
  204. /* confirm MII not busy */
  205. ret = __smsc95xx_phy_wait_not_busy(dev, in_pm);
  206. if (ret < 0) {
  207. netdev_warn(dev->net, "MII is busy in smsc95xx_mdio_write\n");
  208. goto done;
  209. }
  210. val = regval;
  211. ret = __smsc95xx_write_reg(dev, MII_DATA, val, in_pm);
  212. if (ret < 0) {
  213. netdev_warn(dev->net, "Error writing MII_DATA\n");
  214. goto done;
  215. }
  216. /* set the address, index & direction (write to PHY) */
  217. phy_id &= dev->mii.phy_id_mask;
  218. idx &= dev->mii.reg_num_mask;
  219. addr = (phy_id << 11) | (idx << 6) | MII_WRITE_ | MII_BUSY_;
  220. ret = __smsc95xx_write_reg(dev, MII_ADDR, addr, in_pm);
  221. if (ret < 0) {
  222. netdev_warn(dev->net, "Error writing MII_ADDR\n");
  223. goto done;
  224. }
  225. ret = __smsc95xx_phy_wait_not_busy(dev, in_pm);
  226. if (ret < 0) {
  227. netdev_warn(dev->net, "Timed out writing MII reg %02X\n", idx);
  228. goto done;
  229. }
  230. done:
  231. mutex_unlock(&dev->phy_mutex);
  232. }
  233. static int smsc95xx_mdio_read_nopm(struct net_device *netdev, int phy_id,
  234. int idx)
  235. {
  236. return __smsc95xx_mdio_read(netdev, phy_id, idx, 1);
  237. }
  238. static void smsc95xx_mdio_write_nopm(struct net_device *netdev, int phy_id,
  239. int idx, int regval)
  240. {
  241. __smsc95xx_mdio_write(netdev, phy_id, idx, regval, 1);
  242. }
  243. static int smsc95xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
  244. {
  245. return __smsc95xx_mdio_read(netdev, phy_id, idx, 0);
  246. }
  247. static void smsc95xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
  248. int regval)
  249. {
  250. __smsc95xx_mdio_write(netdev, phy_id, idx, regval, 0);
  251. }
  252. static int __must_check smsc95xx_wait_eeprom(struct usbnet *dev)
  253. {
  254. unsigned long start_time = jiffies;
  255. u32 val;
  256. int ret;
  257. do {
  258. ret = smsc95xx_read_reg(dev, E2P_CMD, &val);
  259. if (ret < 0) {
  260. netdev_warn(dev->net, "Error reading E2P_CMD\n");
  261. return ret;
  262. }
  263. if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
  264. break;
  265. udelay(40);
  266. } while (!time_after(jiffies, start_time + HZ));
  267. if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
  268. netdev_warn(dev->net, "EEPROM read operation timeout\n");
  269. return -EIO;
  270. }
  271. return 0;
  272. }
  273. static int __must_check smsc95xx_eeprom_confirm_not_busy(struct usbnet *dev)
  274. {
  275. unsigned long start_time = jiffies;
  276. u32 val;
  277. int ret;
  278. do {
  279. ret = smsc95xx_read_reg(dev, E2P_CMD, &val);
  280. if (ret < 0) {
  281. netdev_warn(dev->net, "Error reading E2P_CMD\n");
  282. return ret;
  283. }
  284. if (!(val & E2P_CMD_BUSY_))
  285. return 0;
  286. udelay(40);
  287. } while (!time_after(jiffies, start_time + HZ));
  288. netdev_warn(dev->net, "EEPROM is busy\n");
  289. return -EIO;
  290. }
  291. static int smsc95xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
  292. u8 *data)
  293. {
  294. u32 val;
  295. int i, ret;
  296. BUG_ON(!dev);
  297. BUG_ON(!data);
  298. ret = smsc95xx_eeprom_confirm_not_busy(dev);
  299. if (ret)
  300. return ret;
  301. for (i = 0; i < length; i++) {
  302. val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
  303. ret = smsc95xx_write_reg(dev, E2P_CMD, val);
  304. if (ret < 0) {
  305. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  306. return ret;
  307. }
  308. ret = smsc95xx_wait_eeprom(dev);
  309. if (ret < 0)
  310. return ret;
  311. ret = smsc95xx_read_reg(dev, E2P_DATA, &val);
  312. if (ret < 0) {
  313. netdev_warn(dev->net, "Error reading E2P_DATA\n");
  314. return ret;
  315. }
  316. data[i] = val & 0xFF;
  317. offset++;
  318. }
  319. return 0;
  320. }
  321. static int smsc95xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
  322. u8 *data)
  323. {
  324. u32 val;
  325. int i, ret;
  326. BUG_ON(!dev);
  327. BUG_ON(!data);
  328. ret = smsc95xx_eeprom_confirm_not_busy(dev);
  329. if (ret)
  330. return ret;
  331. /* Issue write/erase enable command */
  332. val = E2P_CMD_BUSY_ | E2P_CMD_EWEN_;
  333. ret = smsc95xx_write_reg(dev, E2P_CMD, val);
  334. if (ret < 0) {
  335. netdev_warn(dev->net, "Error writing E2P_DATA\n");
  336. return ret;
  337. }
  338. ret = smsc95xx_wait_eeprom(dev);
  339. if (ret < 0)
  340. return ret;
  341. for (i = 0; i < length; i++) {
  342. /* Fill data register */
  343. val = data[i];
  344. ret = smsc95xx_write_reg(dev, E2P_DATA, val);
  345. if (ret < 0) {
  346. netdev_warn(dev->net, "Error writing E2P_DATA\n");
  347. return ret;
  348. }
  349. /* Send "write" command */
  350. val = E2P_CMD_BUSY_ | E2P_CMD_WRITE_ | (offset & E2P_CMD_ADDR_);
  351. ret = smsc95xx_write_reg(dev, E2P_CMD, val);
  352. if (ret < 0) {
  353. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  354. return ret;
  355. }
  356. ret = smsc95xx_wait_eeprom(dev);
  357. if (ret < 0)
  358. return ret;
  359. offset++;
  360. }
  361. return 0;
  362. }
  363. static int __must_check smsc95xx_write_reg_async(struct usbnet *dev, u16 index,
  364. u32 data)
  365. {
  366. const u16 size = 4;
  367. u32 buf;
  368. int ret;
  369. buf = data;
  370. cpu_to_le32s(&buf);
  371. ret = usbnet_write_cmd_async(dev, USB_VENDOR_REQUEST_WRITE_REGISTER,
  372. USB_DIR_OUT | USB_TYPE_VENDOR |
  373. USB_RECIP_DEVICE,
  374. 0, index, &buf, size);
  375. if (ret < 0)
  376. netdev_warn(dev->net, "Error write async cmd, sts=%d\n",
  377. ret);
  378. return ret;
  379. }
  380. /* returns hash bit number for given MAC address
  381. * example:
  382. * 01 00 5E 00 00 01 -> returns bit number 31 */
  383. static unsigned int smsc95xx_hash(char addr[ETH_ALEN])
  384. {
  385. return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
  386. }
  387. static void smsc95xx_set_multicast(struct net_device *netdev)
  388. {
  389. struct usbnet *dev = netdev_priv(netdev);
  390. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  391. unsigned long flags;
  392. int ret;
  393. pdata->hash_hi = 0;
  394. pdata->hash_lo = 0;
  395. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  396. if (dev->net->flags & IFF_PROMISC) {
  397. netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
  398. pdata->mac_cr |= MAC_CR_PRMS_;
  399. pdata->mac_cr &= ~(MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  400. } else if (dev->net->flags & IFF_ALLMULTI) {
  401. netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
  402. pdata->mac_cr |= MAC_CR_MCPAS_;
  403. pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_HPFILT_);
  404. } else if (!netdev_mc_empty(dev->net)) {
  405. struct netdev_hw_addr *ha;
  406. pdata->mac_cr |= MAC_CR_HPFILT_;
  407. pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_);
  408. netdev_for_each_mc_addr(ha, netdev) {
  409. u32 bitnum = smsc95xx_hash(ha->addr);
  410. u32 mask = 0x01 << (bitnum & 0x1F);
  411. if (bitnum & 0x20)
  412. pdata->hash_hi |= mask;
  413. else
  414. pdata->hash_lo |= mask;
  415. }
  416. netif_dbg(dev, drv, dev->net, "HASHH=0x%08X, HASHL=0x%08X\n",
  417. pdata->hash_hi, pdata->hash_lo);
  418. } else {
  419. netif_dbg(dev, drv, dev->net, "receive own packets only\n");
  420. pdata->mac_cr &=
  421. ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  422. }
  423. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  424. /* Initiate async writes, as we can't wait for completion here */
  425. ret = smsc95xx_write_reg_async(dev, HASHH, pdata->hash_hi);
  426. if (ret < 0)
  427. netdev_warn(dev->net, "failed to initiate async write to HASHH\n");
  428. ret = smsc95xx_write_reg_async(dev, HASHL, pdata->hash_lo);
  429. if (ret < 0)
  430. netdev_warn(dev->net, "failed to initiate async write to HASHL\n");
  431. ret = smsc95xx_write_reg_async(dev, MAC_CR, pdata->mac_cr);
  432. if (ret < 0)
  433. netdev_warn(dev->net, "failed to initiate async write to MAC_CR\n");
  434. }
  435. static int smsc95xx_phy_update_flowcontrol(struct usbnet *dev, u8 duplex,
  436. u16 lcladv, u16 rmtadv)
  437. {
  438. u32 flow = 0, afc_cfg;
  439. int ret = smsc95xx_read_reg(dev, AFC_CFG, &afc_cfg);
  440. if (ret < 0)
  441. return ret;
  442. if (duplex == DUPLEX_FULL) {
  443. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  444. if (cap & FLOW_CTRL_RX)
  445. flow = 0xFFFF0002;
  446. if (cap & FLOW_CTRL_TX) {
  447. afc_cfg |= 0xF;
  448. flow |= 0xFFFF0000;
  449. } else {
  450. afc_cfg &= ~0xF;
  451. }
  452. netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
  453. cap & FLOW_CTRL_RX ? "enabled" : "disabled",
  454. cap & FLOW_CTRL_TX ? "enabled" : "disabled");
  455. } else {
  456. netif_dbg(dev, link, dev->net, "half duplex\n");
  457. afc_cfg |= 0xF;
  458. }
  459. ret = smsc95xx_write_reg(dev, FLOW, flow);
  460. if (ret < 0)
  461. return ret;
  462. return smsc95xx_write_reg(dev, AFC_CFG, afc_cfg);
  463. }
  464. static int smsc95xx_link_reset(struct usbnet *dev)
  465. {
  466. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  467. struct mii_if_info *mii = &dev->mii;
  468. struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
  469. unsigned long flags;
  470. u16 lcladv, rmtadv;
  471. int ret;
  472. /* clear interrupt status */
  473. ret = smsc95xx_mdio_read(dev->net, mii->phy_id, PHY_INT_SRC);
  474. if (ret < 0)
  475. return ret;
  476. ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_);
  477. if (ret < 0)
  478. return ret;
  479. mii_check_media(mii, 1, 1);
  480. mii_ethtool_gset(&dev->mii, &ecmd);
  481. lcladv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
  482. rmtadv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
  483. netif_dbg(dev, link, dev->net,
  484. "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n",
  485. ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv);
  486. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  487. if (ecmd.duplex != DUPLEX_FULL) {
  488. pdata->mac_cr &= ~MAC_CR_FDPX_;
  489. pdata->mac_cr |= MAC_CR_RCVOWN_;
  490. } else {
  491. pdata->mac_cr &= ~MAC_CR_RCVOWN_;
  492. pdata->mac_cr |= MAC_CR_FDPX_;
  493. }
  494. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  495. ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  496. if (ret < 0)
  497. return ret;
  498. ret = smsc95xx_phy_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
  499. if (ret < 0)
  500. netdev_warn(dev->net, "Error updating PHY flow control\n");
  501. return ret;
  502. }
  503. static void smsc95xx_status(struct usbnet *dev, struct urb *urb)
  504. {
  505. u32 intdata;
  506. if (urb->actual_length != 4) {
  507. netdev_warn(dev->net, "unexpected urb length %d\n",
  508. urb->actual_length);
  509. return;
  510. }
  511. memcpy(&intdata, urb->transfer_buffer, 4);
  512. le32_to_cpus(&intdata);
  513. netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
  514. if (intdata & INT_ENP_PHY_INT_)
  515. usbnet_defer_kevent(dev, EVENT_LINK_RESET);
  516. else
  517. netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
  518. intdata);
  519. }
  520. static void set_carrier(struct usbnet *dev, bool link)
  521. {
  522. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  523. if (pdata->link_ok == link)
  524. return;
  525. pdata->link_ok = link;
  526. if (link)
  527. usbnet_link_change(dev, 1, 0);
  528. else
  529. usbnet_link_change(dev, 0, 0);
  530. }
  531. static void check_carrier(struct work_struct *work)
  532. {
  533. struct smsc95xx_priv *pdata = container_of(work, struct smsc95xx_priv,
  534. carrier_check.work);
  535. struct usbnet *dev = pdata->dev;
  536. int ret;
  537. if (pdata->suspend_flags != 0)
  538. return;
  539. ret = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMSR);
  540. if (ret < 0) {
  541. netdev_warn(dev->net, "Failed to read MII_BMSR\n");
  542. return;
  543. }
  544. if (ret & BMSR_LSTATUS)
  545. set_carrier(dev, 1);
  546. else
  547. set_carrier(dev, 0);
  548. schedule_delayed_work(&pdata->carrier_check, CARRIER_CHECK_DELAY);
  549. }
  550. /* Enable or disable Tx & Rx checksum offload engines */
  551. static int smsc95xx_set_features(struct net_device *netdev,
  552. netdev_features_t features)
  553. {
  554. struct usbnet *dev = netdev_priv(netdev);
  555. u32 read_buf;
  556. int ret;
  557. ret = smsc95xx_read_reg(dev, COE_CR, &read_buf);
  558. if (ret < 0)
  559. return ret;
  560. if (features & NETIF_F_IP_CSUM)
  561. read_buf |= Tx_COE_EN_;
  562. else
  563. read_buf &= ~Tx_COE_EN_;
  564. if (features & NETIF_F_RXCSUM)
  565. read_buf |= Rx_COE_EN_;
  566. else
  567. read_buf &= ~Rx_COE_EN_;
  568. ret = smsc95xx_write_reg(dev, COE_CR, read_buf);
  569. if (ret < 0)
  570. return ret;
  571. netif_dbg(dev, hw, dev->net, "COE_CR = 0x%08x\n", read_buf);
  572. return 0;
  573. }
  574. static int smsc95xx_ethtool_get_eeprom_len(struct net_device *net)
  575. {
  576. return MAX_EEPROM_SIZE;
  577. }
  578. static int smsc95xx_ethtool_get_eeprom(struct net_device *netdev,
  579. struct ethtool_eeprom *ee, u8 *data)
  580. {
  581. struct usbnet *dev = netdev_priv(netdev);
  582. ee->magic = LAN95XX_EEPROM_MAGIC;
  583. return smsc95xx_read_eeprom(dev, ee->offset, ee->len, data);
  584. }
  585. static int smsc95xx_ethtool_set_eeprom(struct net_device *netdev,
  586. struct ethtool_eeprom *ee, u8 *data)
  587. {
  588. struct usbnet *dev = netdev_priv(netdev);
  589. if (ee->magic != LAN95XX_EEPROM_MAGIC) {
  590. netdev_warn(dev->net, "EEPROM: magic value mismatch, magic = 0x%x\n",
  591. ee->magic);
  592. return -EINVAL;
  593. }
  594. return smsc95xx_write_eeprom(dev, ee->offset, ee->len, data);
  595. }
  596. static int smsc95xx_ethtool_getregslen(struct net_device *netdev)
  597. {
  598. /* all smsc95xx registers */
  599. return COE_CR - ID_REV + sizeof(u32);
  600. }
  601. static void
  602. smsc95xx_ethtool_getregs(struct net_device *netdev, struct ethtool_regs *regs,
  603. void *buf)
  604. {
  605. struct usbnet *dev = netdev_priv(netdev);
  606. unsigned int i, j;
  607. int retval;
  608. u32 *data = buf;
  609. retval = smsc95xx_read_reg(dev, ID_REV, &regs->version);
  610. if (retval < 0) {
  611. netdev_warn(netdev, "REGS: cannot read ID_REV\n");
  612. return;
  613. }
  614. for (i = ID_REV, j = 0; i <= COE_CR; i += (sizeof(u32)), j++) {
  615. retval = smsc95xx_read_reg(dev, i, &data[j]);
  616. if (retval < 0) {
  617. netdev_warn(netdev, "REGS: cannot read reg[%x]\n", i);
  618. return;
  619. }
  620. }
  621. }
  622. static void smsc95xx_ethtool_get_wol(struct net_device *net,
  623. struct ethtool_wolinfo *wolinfo)
  624. {
  625. struct usbnet *dev = netdev_priv(net);
  626. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  627. wolinfo->supported = SUPPORTED_WAKE;
  628. wolinfo->wolopts = pdata->wolopts;
  629. }
  630. static int smsc95xx_ethtool_set_wol(struct net_device *net,
  631. struct ethtool_wolinfo *wolinfo)
  632. {
  633. struct usbnet *dev = netdev_priv(net);
  634. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  635. int ret;
  636. pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE;
  637. ret = device_set_wakeup_enable(&dev->udev->dev, pdata->wolopts);
  638. if (ret < 0)
  639. netdev_warn(dev->net, "device_set_wakeup_enable error %d\n", ret);
  640. return ret;
  641. }
  642. static int get_mdix_status(struct net_device *net)
  643. {
  644. struct usbnet *dev = netdev_priv(net);
  645. u32 val;
  646. int buf;
  647. buf = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, SPECIAL_CTRL_STS);
  648. if (buf & SPECIAL_CTRL_STS_OVRRD_AMDIX_) {
  649. if (buf & SPECIAL_CTRL_STS_AMDIX_ENABLE_)
  650. return ETH_TP_MDI_AUTO;
  651. else if (buf & SPECIAL_CTRL_STS_AMDIX_STATE_)
  652. return ETH_TP_MDI_X;
  653. } else {
  654. buf = smsc95xx_read_reg(dev, STRAP_STATUS, &val);
  655. if (val & STRAP_STATUS_AMDIX_EN_)
  656. return ETH_TP_MDI_AUTO;
  657. }
  658. return ETH_TP_MDI;
  659. }
  660. static void set_mdix_status(struct net_device *net, __u8 mdix_ctrl)
  661. {
  662. struct usbnet *dev = netdev_priv(net);
  663. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  664. int buf;
  665. if ((pdata->chip_id == ID_REV_CHIP_ID_9500A_) ||
  666. (pdata->chip_id == ID_REV_CHIP_ID_9530_) ||
  667. (pdata->chip_id == ID_REV_CHIP_ID_89530_) ||
  668. (pdata->chip_id == ID_REV_CHIP_ID_9730_)) {
  669. /* Extend Manual AutoMDIX timer for 9500A/9500Ai */
  670. buf = smsc95xx_mdio_read(dev->net, dev->mii.phy_id,
  671. PHY_EDPD_CONFIG);
  672. buf |= PHY_EDPD_CONFIG_EXT_CROSSOVER_;
  673. smsc95xx_mdio_write(dev->net, dev->mii.phy_id,
  674. PHY_EDPD_CONFIG, buf);
  675. }
  676. if (mdix_ctrl == ETH_TP_MDI) {
  677. buf = smsc95xx_mdio_read(dev->net, dev->mii.phy_id,
  678. SPECIAL_CTRL_STS);
  679. buf |= SPECIAL_CTRL_STS_OVRRD_AMDIX_;
  680. buf &= ~(SPECIAL_CTRL_STS_AMDIX_ENABLE_ |
  681. SPECIAL_CTRL_STS_AMDIX_STATE_);
  682. smsc95xx_mdio_write(dev->net, dev->mii.phy_id,
  683. SPECIAL_CTRL_STS, buf);
  684. } else if (mdix_ctrl == ETH_TP_MDI_X) {
  685. buf = smsc95xx_mdio_read(dev->net, dev->mii.phy_id,
  686. SPECIAL_CTRL_STS);
  687. buf |= SPECIAL_CTRL_STS_OVRRD_AMDIX_;
  688. buf &= ~(SPECIAL_CTRL_STS_AMDIX_ENABLE_ |
  689. SPECIAL_CTRL_STS_AMDIX_STATE_);
  690. buf |= SPECIAL_CTRL_STS_AMDIX_STATE_;
  691. smsc95xx_mdio_write(dev->net, dev->mii.phy_id,
  692. SPECIAL_CTRL_STS, buf);
  693. } else if (mdix_ctrl == ETH_TP_MDI_AUTO) {
  694. buf = smsc95xx_mdio_read(dev->net, dev->mii.phy_id,
  695. SPECIAL_CTRL_STS);
  696. buf &= ~SPECIAL_CTRL_STS_OVRRD_AMDIX_;
  697. buf &= ~(SPECIAL_CTRL_STS_AMDIX_ENABLE_ |
  698. SPECIAL_CTRL_STS_AMDIX_STATE_);
  699. buf |= SPECIAL_CTRL_STS_AMDIX_ENABLE_;
  700. smsc95xx_mdio_write(dev->net, dev->mii.phy_id,
  701. SPECIAL_CTRL_STS, buf);
  702. }
  703. pdata->mdix_ctrl = mdix_ctrl;
  704. }
  705. static int smsc95xx_get_link_ksettings(struct net_device *net,
  706. struct ethtool_link_ksettings *cmd)
  707. {
  708. struct usbnet *dev = netdev_priv(net);
  709. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  710. int retval;
  711. retval = usbnet_get_link_ksettings(net, cmd);
  712. cmd->base.eth_tp_mdix = pdata->mdix_ctrl;
  713. cmd->base.eth_tp_mdix_ctrl = pdata->mdix_ctrl;
  714. return retval;
  715. }
  716. static int smsc95xx_set_link_ksettings(struct net_device *net,
  717. const struct ethtool_link_ksettings *cmd)
  718. {
  719. struct usbnet *dev = netdev_priv(net);
  720. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  721. int retval;
  722. if (pdata->mdix_ctrl != cmd->base.eth_tp_mdix_ctrl)
  723. set_mdix_status(net, cmd->base.eth_tp_mdix_ctrl);
  724. retval = usbnet_set_link_ksettings(net, cmd);
  725. return retval;
  726. }
  727. static const struct ethtool_ops smsc95xx_ethtool_ops = {
  728. .get_link = usbnet_get_link,
  729. .nway_reset = usbnet_nway_reset,
  730. .get_drvinfo = usbnet_get_drvinfo,
  731. .get_msglevel = usbnet_get_msglevel,
  732. .set_msglevel = usbnet_set_msglevel,
  733. .get_eeprom_len = smsc95xx_ethtool_get_eeprom_len,
  734. .get_eeprom = smsc95xx_ethtool_get_eeprom,
  735. .set_eeprom = smsc95xx_ethtool_set_eeprom,
  736. .get_regs_len = smsc95xx_ethtool_getregslen,
  737. .get_regs = smsc95xx_ethtool_getregs,
  738. .get_wol = smsc95xx_ethtool_get_wol,
  739. .set_wol = smsc95xx_ethtool_set_wol,
  740. .get_link_ksettings = smsc95xx_get_link_ksettings,
  741. .set_link_ksettings = smsc95xx_set_link_ksettings,
  742. .get_ts_info = ethtool_op_get_ts_info,
  743. };
  744. static int smsc95xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  745. {
  746. struct usbnet *dev = netdev_priv(netdev);
  747. if (!netif_running(netdev))
  748. return -EINVAL;
  749. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  750. }
  751. static void smsc95xx_init_mac_address(struct usbnet *dev)
  752. {
  753. const u8 *mac_addr;
  754. /* maybe the boot loader passed the MAC address in devicetree */
  755. mac_addr = of_get_mac_address(dev->udev->dev.of_node);
  756. if (mac_addr) {
  757. memcpy(dev->net->dev_addr, mac_addr, ETH_ALEN);
  758. return;
  759. }
  760. /* try reading mac address from EEPROM */
  761. if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
  762. dev->net->dev_addr) == 0) {
  763. if (is_valid_ether_addr(dev->net->dev_addr)) {
  764. /* eeprom values are valid so use them */
  765. netif_dbg(dev, ifup, dev->net, "MAC address read from EEPROM\n");
  766. return;
  767. }
  768. }
  769. /* no useful static MAC address found. generate a random one */
  770. eth_hw_addr_random(dev->net);
  771. netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
  772. }
  773. static int smsc95xx_set_mac_address(struct usbnet *dev)
  774. {
  775. u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
  776. dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
  777. u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
  778. int ret;
  779. ret = smsc95xx_write_reg(dev, ADDRL, addr_lo);
  780. if (ret < 0)
  781. return ret;
  782. return smsc95xx_write_reg(dev, ADDRH, addr_hi);
  783. }
  784. /* starts the TX path */
  785. static int smsc95xx_start_tx_path(struct usbnet *dev)
  786. {
  787. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  788. unsigned long flags;
  789. int ret;
  790. /* Enable Tx at MAC */
  791. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  792. pdata->mac_cr |= MAC_CR_TXEN_;
  793. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  794. ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  795. if (ret < 0)
  796. return ret;
  797. /* Enable Tx at SCSRs */
  798. return smsc95xx_write_reg(dev, TX_CFG, TX_CFG_ON_);
  799. }
  800. /* Starts the Receive path */
  801. static int smsc95xx_start_rx_path(struct usbnet *dev, int in_pm)
  802. {
  803. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  804. unsigned long flags;
  805. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  806. pdata->mac_cr |= MAC_CR_RXEN_;
  807. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  808. return __smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr, in_pm);
  809. }
  810. static int smsc95xx_phy_initialize(struct usbnet *dev)
  811. {
  812. int bmcr, ret, timeout = 0;
  813. /* Initialize MII structure */
  814. dev->mii.dev = dev->net;
  815. dev->mii.mdio_read = smsc95xx_mdio_read;
  816. dev->mii.mdio_write = smsc95xx_mdio_write;
  817. dev->mii.phy_id_mask = 0x1f;
  818. dev->mii.reg_num_mask = 0x1f;
  819. dev->mii.phy_id = SMSC95XX_INTERNAL_PHY_ID;
  820. /* reset phy and wait for reset to complete */
  821. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  822. do {
  823. msleep(10);
  824. bmcr = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
  825. timeout++;
  826. } while ((bmcr & BMCR_RESET) && (timeout < 100));
  827. if (timeout >= 100) {
  828. netdev_warn(dev->net, "timeout on PHY Reset");
  829. return -EIO;
  830. }
  831. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  832. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
  833. ADVERTISE_PAUSE_ASYM);
  834. /* read to clear */
  835. ret = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
  836. if (ret < 0) {
  837. netdev_warn(dev->net, "Failed to read PHY_INT_SRC during init\n");
  838. return ret;
  839. }
  840. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
  841. PHY_INT_MASK_DEFAULT_);
  842. mii_nway_restart(&dev->mii);
  843. netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
  844. return 0;
  845. }
  846. static int smsc95xx_reset(struct usbnet *dev)
  847. {
  848. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  849. u32 read_buf, write_buf, burst_cap;
  850. int ret = 0, timeout;
  851. netif_dbg(dev, ifup, dev->net, "entering smsc95xx_reset\n");
  852. ret = smsc95xx_write_reg(dev, HW_CFG, HW_CFG_LRST_);
  853. if (ret < 0)
  854. return ret;
  855. timeout = 0;
  856. do {
  857. msleep(10);
  858. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  859. if (ret < 0)
  860. return ret;
  861. timeout++;
  862. } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
  863. if (timeout >= 100) {
  864. netdev_warn(dev->net, "timeout waiting for completion of Lite Reset\n");
  865. return ret;
  866. }
  867. ret = smsc95xx_write_reg(dev, PM_CTRL, PM_CTL_PHY_RST_);
  868. if (ret < 0)
  869. return ret;
  870. timeout = 0;
  871. do {
  872. msleep(10);
  873. ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf);
  874. if (ret < 0)
  875. return ret;
  876. timeout++;
  877. } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
  878. if (timeout >= 100) {
  879. netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
  880. return ret;
  881. }
  882. ret = smsc95xx_set_mac_address(dev);
  883. if (ret < 0)
  884. return ret;
  885. netif_dbg(dev, ifup, dev->net, "MAC Address: %pM\n",
  886. dev->net->dev_addr);
  887. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  888. if (ret < 0)
  889. return ret;
  890. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG : 0x%08x\n",
  891. read_buf);
  892. read_buf |= HW_CFG_BIR_;
  893. ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
  894. if (ret < 0)
  895. return ret;
  896. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  897. if (ret < 0)
  898. return ret;
  899. netif_dbg(dev, ifup, dev->net,
  900. "Read Value from HW_CFG after writing HW_CFG_BIR_: 0x%08x\n",
  901. read_buf);
  902. if (!turbo_mode) {
  903. burst_cap = 0;
  904. dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
  905. } else if (dev->udev->speed == USB_SPEED_HIGH) {
  906. burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
  907. dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
  908. } else {
  909. burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
  910. dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
  911. }
  912. netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld\n",
  913. (ulong)dev->rx_urb_size);
  914. ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap);
  915. if (ret < 0)
  916. return ret;
  917. ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf);
  918. if (ret < 0)
  919. return ret;
  920. netif_dbg(dev, ifup, dev->net,
  921. "Read Value from BURST_CAP after writing: 0x%08x\n",
  922. read_buf);
  923. ret = smsc95xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
  924. if (ret < 0)
  925. return ret;
  926. ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf);
  927. if (ret < 0)
  928. return ret;
  929. netif_dbg(dev, ifup, dev->net,
  930. "Read Value from BULK_IN_DLY after writing: 0x%08x\n",
  931. read_buf);
  932. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  933. if (ret < 0)
  934. return ret;
  935. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG: 0x%08x\n",
  936. read_buf);
  937. if (turbo_mode)
  938. read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
  939. read_buf &= ~HW_CFG_RXDOFF_;
  940. /* set Rx data offset=2, Make IP header aligns on word boundary. */
  941. read_buf |= NET_IP_ALIGN << 9;
  942. ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
  943. if (ret < 0)
  944. return ret;
  945. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  946. if (ret < 0)
  947. return ret;
  948. netif_dbg(dev, ifup, dev->net,
  949. "Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
  950. ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_);
  951. if (ret < 0)
  952. return ret;
  953. ret = smsc95xx_read_reg(dev, ID_REV, &read_buf);
  954. if (ret < 0)
  955. return ret;
  956. netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", read_buf);
  957. /* Configure GPIO pins as LED outputs */
  958. write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
  959. LED_GPIO_CFG_FDX_LED;
  960. ret = smsc95xx_write_reg(dev, LED_GPIO_CFG, write_buf);
  961. if (ret < 0)
  962. return ret;
  963. /* Init Tx */
  964. ret = smsc95xx_write_reg(dev, FLOW, 0);
  965. if (ret < 0)
  966. return ret;
  967. ret = smsc95xx_write_reg(dev, AFC_CFG, AFC_CFG_DEFAULT);
  968. if (ret < 0)
  969. return ret;
  970. /* Don't need mac_cr_lock during initialisation */
  971. ret = smsc95xx_read_reg(dev, MAC_CR, &pdata->mac_cr);
  972. if (ret < 0)
  973. return ret;
  974. /* Init Rx */
  975. /* Set Vlan */
  976. ret = smsc95xx_write_reg(dev, VLAN1, (u32)ETH_P_8021Q);
  977. if (ret < 0)
  978. return ret;
  979. /* Enable or disable checksum offload engines */
  980. ret = smsc95xx_set_features(dev->net, dev->net->features);
  981. if (ret < 0) {
  982. netdev_warn(dev->net, "Failed to set checksum offload features\n");
  983. return ret;
  984. }
  985. smsc95xx_set_multicast(dev->net);
  986. ret = smsc95xx_phy_initialize(dev);
  987. if (ret < 0) {
  988. netdev_warn(dev->net, "Failed to init PHY\n");
  989. return ret;
  990. }
  991. ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf);
  992. if (ret < 0)
  993. return ret;
  994. /* enable PHY interrupts */
  995. read_buf |= INT_EP_CTL_PHY_INT_;
  996. ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf);
  997. if (ret < 0)
  998. return ret;
  999. ret = smsc95xx_start_tx_path(dev);
  1000. if (ret < 0) {
  1001. netdev_warn(dev->net, "Failed to start TX path\n");
  1002. return ret;
  1003. }
  1004. ret = smsc95xx_start_rx_path(dev, 0);
  1005. if (ret < 0) {
  1006. netdev_warn(dev->net, "Failed to start RX path\n");
  1007. return ret;
  1008. }
  1009. netif_dbg(dev, ifup, dev->net, "smsc95xx_reset, return 0\n");
  1010. return 0;
  1011. }
  1012. static const struct net_device_ops smsc95xx_netdev_ops = {
  1013. .ndo_open = usbnet_open,
  1014. .ndo_stop = usbnet_stop,
  1015. .ndo_start_xmit = usbnet_start_xmit,
  1016. .ndo_tx_timeout = usbnet_tx_timeout,
  1017. .ndo_change_mtu = usbnet_change_mtu,
  1018. .ndo_get_stats64 = usbnet_get_stats64,
  1019. .ndo_set_mac_address = eth_mac_addr,
  1020. .ndo_validate_addr = eth_validate_addr,
  1021. .ndo_do_ioctl = smsc95xx_ioctl,
  1022. .ndo_set_rx_mode = smsc95xx_set_multicast,
  1023. .ndo_set_features = smsc95xx_set_features,
  1024. };
  1025. static int smsc95xx_bind(struct usbnet *dev, struct usb_interface *intf)
  1026. {
  1027. struct smsc95xx_priv *pdata = NULL;
  1028. u32 val;
  1029. int ret;
  1030. printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
  1031. ret = usbnet_get_endpoints(dev, intf);
  1032. if (ret < 0) {
  1033. netdev_warn(dev->net, "usbnet_get_endpoints failed: %d\n", ret);
  1034. return ret;
  1035. }
  1036. dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc95xx_priv),
  1037. GFP_KERNEL);
  1038. pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1039. if (!pdata)
  1040. return -ENOMEM;
  1041. spin_lock_init(&pdata->mac_cr_lock);
  1042. /* LAN95xx devices do not alter the computed checksum of 0 to 0xffff.
  1043. * RFC 2460, ipv6 UDP calculated checksum yields a result of zero must
  1044. * be changed to 0xffff. RFC 768, ipv4 UDP computed checksum is zero,
  1045. * it is transmitted as all ones. The zero transmitted checksum means
  1046. * transmitter generated no checksum. Hence, enable csum offload only
  1047. * for ipv4 packets.
  1048. */
  1049. if (DEFAULT_TX_CSUM_ENABLE)
  1050. dev->net->features |= NETIF_F_IP_CSUM;
  1051. if (DEFAULT_RX_CSUM_ENABLE)
  1052. dev->net->features |= NETIF_F_RXCSUM;
  1053. dev->net->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
  1054. smsc95xx_init_mac_address(dev);
  1055. /* Init all registers */
  1056. ret = smsc95xx_reset(dev);
  1057. /* detect device revision as different features may be available */
  1058. ret = smsc95xx_read_reg(dev, ID_REV, &val);
  1059. if (ret < 0)
  1060. return ret;
  1061. val >>= 16;
  1062. pdata->chip_id = val;
  1063. pdata->mdix_ctrl = get_mdix_status(dev->net);
  1064. if ((val == ID_REV_CHIP_ID_9500A_) || (val == ID_REV_CHIP_ID_9530_) ||
  1065. (val == ID_REV_CHIP_ID_89530_) || (val == ID_REV_CHIP_ID_9730_))
  1066. pdata->features = (FEATURE_8_WAKEUP_FILTERS |
  1067. FEATURE_PHY_NLP_CROSSOVER |
  1068. FEATURE_REMOTE_WAKEUP);
  1069. else if (val == ID_REV_CHIP_ID_9512_)
  1070. pdata->features = FEATURE_8_WAKEUP_FILTERS;
  1071. dev->net->netdev_ops = &smsc95xx_netdev_ops;
  1072. dev->net->ethtool_ops = &smsc95xx_ethtool_ops;
  1073. dev->net->flags |= IFF_MULTICAST;
  1074. dev->net->hard_header_len += SMSC95XX_TX_OVERHEAD_CSUM;
  1075. dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
  1076. pdata->dev = dev;
  1077. INIT_DELAYED_WORK(&pdata->carrier_check, check_carrier);
  1078. schedule_delayed_work(&pdata->carrier_check, CARRIER_CHECK_DELAY);
  1079. return 0;
  1080. }
  1081. static void smsc95xx_unbind(struct usbnet *dev, struct usb_interface *intf)
  1082. {
  1083. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1084. if (pdata) {
  1085. cancel_delayed_work(&pdata->carrier_check);
  1086. netif_dbg(dev, ifdown, dev->net, "free pdata\n");
  1087. kfree(pdata);
  1088. pdata = NULL;
  1089. dev->data[0] = 0;
  1090. }
  1091. }
  1092. static u32 smsc_crc(const u8 *buffer, size_t len, int filter)
  1093. {
  1094. u32 crc = bitrev16(crc16(0xFFFF, buffer, len));
  1095. return crc << ((filter % 2) * 16);
  1096. }
  1097. static int smsc95xx_enable_phy_wakeup_interrupts(struct usbnet *dev, u16 mask)
  1098. {
  1099. struct mii_if_info *mii = &dev->mii;
  1100. int ret;
  1101. netdev_dbg(dev->net, "enabling PHY wakeup interrupts\n");
  1102. /* read to clear */
  1103. ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_SRC);
  1104. if (ret < 0)
  1105. return ret;
  1106. /* enable interrupt source */
  1107. ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_MASK);
  1108. if (ret < 0)
  1109. return ret;
  1110. ret |= mask;
  1111. smsc95xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_INT_MASK, ret);
  1112. return 0;
  1113. }
  1114. static int smsc95xx_link_ok_nopm(struct usbnet *dev)
  1115. {
  1116. struct mii_if_info *mii = &dev->mii;
  1117. int ret;
  1118. /* first, a dummy read, needed to latch some MII phys */
  1119. ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  1120. if (ret < 0)
  1121. return ret;
  1122. ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  1123. if (ret < 0)
  1124. return ret;
  1125. return !!(ret & BMSR_LSTATUS);
  1126. }
  1127. static int smsc95xx_enter_suspend0(struct usbnet *dev)
  1128. {
  1129. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1130. u32 val;
  1131. int ret;
  1132. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  1133. if (ret < 0)
  1134. return ret;
  1135. val &= (~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_));
  1136. val |= PM_CTL_SUS_MODE_0;
  1137. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1138. if (ret < 0)
  1139. return ret;
  1140. /* clear wol status */
  1141. val &= ~PM_CTL_WUPS_;
  1142. val |= PM_CTL_WUPS_WOL_;
  1143. /* enable energy detection */
  1144. if (pdata->wolopts & WAKE_PHY)
  1145. val |= PM_CTL_WUPS_ED_;
  1146. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1147. if (ret < 0)
  1148. return ret;
  1149. /* read back PM_CTRL */
  1150. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  1151. if (ret < 0)
  1152. return ret;
  1153. pdata->suspend_flags |= SUSPEND_SUSPEND0;
  1154. return 0;
  1155. }
  1156. static int smsc95xx_enter_suspend1(struct usbnet *dev)
  1157. {
  1158. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1159. struct mii_if_info *mii = &dev->mii;
  1160. u32 val;
  1161. int ret;
  1162. /* reconfigure link pulse detection timing for
  1163. * compatibility with non-standard link partners
  1164. */
  1165. if (pdata->features & FEATURE_PHY_NLP_CROSSOVER)
  1166. smsc95xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_EDPD_CONFIG,
  1167. PHY_EDPD_CONFIG_DEFAULT);
  1168. /* enable energy detect power-down mode */
  1169. ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_MODE_CTRL_STS);
  1170. if (ret < 0)
  1171. return ret;
  1172. ret |= MODE_CTRL_STS_EDPWRDOWN_;
  1173. smsc95xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_MODE_CTRL_STS, ret);
  1174. /* enter SUSPEND1 mode */
  1175. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  1176. if (ret < 0)
  1177. return ret;
  1178. val &= ~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_);
  1179. val |= PM_CTL_SUS_MODE_1;
  1180. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1181. if (ret < 0)
  1182. return ret;
  1183. /* clear wol status, enable energy detection */
  1184. val &= ~PM_CTL_WUPS_;
  1185. val |= (PM_CTL_WUPS_ED_ | PM_CTL_ED_EN_);
  1186. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1187. if (ret < 0)
  1188. return ret;
  1189. pdata->suspend_flags |= SUSPEND_SUSPEND1;
  1190. return 0;
  1191. }
  1192. static int smsc95xx_enter_suspend2(struct usbnet *dev)
  1193. {
  1194. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1195. u32 val;
  1196. int ret;
  1197. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  1198. if (ret < 0)
  1199. return ret;
  1200. val &= ~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_);
  1201. val |= PM_CTL_SUS_MODE_2;
  1202. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1203. if (ret < 0)
  1204. return ret;
  1205. pdata->suspend_flags |= SUSPEND_SUSPEND2;
  1206. return 0;
  1207. }
  1208. static int smsc95xx_enter_suspend3(struct usbnet *dev)
  1209. {
  1210. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1211. u32 val;
  1212. int ret;
  1213. ret = smsc95xx_read_reg_nopm(dev, RX_FIFO_INF, &val);
  1214. if (ret < 0)
  1215. return ret;
  1216. if (val & RX_FIFO_INF_USED_) {
  1217. netdev_info(dev->net, "rx fifo not empty in autosuspend\n");
  1218. return -EBUSY;
  1219. }
  1220. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  1221. if (ret < 0)
  1222. return ret;
  1223. val &= ~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_);
  1224. val |= PM_CTL_SUS_MODE_3 | PM_CTL_RES_CLR_WKP_STS;
  1225. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1226. if (ret < 0)
  1227. return ret;
  1228. /* clear wol status */
  1229. val &= ~PM_CTL_WUPS_;
  1230. val |= PM_CTL_WUPS_WOL_;
  1231. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1232. if (ret < 0)
  1233. return ret;
  1234. pdata->suspend_flags |= SUSPEND_SUSPEND3;
  1235. return 0;
  1236. }
  1237. static int smsc95xx_autosuspend(struct usbnet *dev, u32 link_up)
  1238. {
  1239. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1240. int ret;
  1241. if (!netif_running(dev->net)) {
  1242. /* interface is ifconfig down so fully power down hw */
  1243. netdev_dbg(dev->net, "autosuspend entering SUSPEND2\n");
  1244. return smsc95xx_enter_suspend2(dev);
  1245. }
  1246. if (!link_up) {
  1247. /* link is down so enter EDPD mode, but only if device can
  1248. * reliably resume from it. This check should be redundant
  1249. * as current FEATURE_REMOTE_WAKEUP parts also support
  1250. * FEATURE_PHY_NLP_CROSSOVER but it's included for clarity */
  1251. if (!(pdata->features & FEATURE_PHY_NLP_CROSSOVER)) {
  1252. netdev_warn(dev->net, "EDPD not supported\n");
  1253. return -EBUSY;
  1254. }
  1255. netdev_dbg(dev->net, "autosuspend entering SUSPEND1\n");
  1256. /* enable PHY wakeup events for if cable is attached */
  1257. ret = smsc95xx_enable_phy_wakeup_interrupts(dev,
  1258. PHY_INT_MASK_ANEG_COMP_);
  1259. if (ret < 0) {
  1260. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1261. return ret;
  1262. }
  1263. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1264. return smsc95xx_enter_suspend1(dev);
  1265. }
  1266. /* enable PHY wakeup events so we remote wakeup if cable is pulled */
  1267. ret = smsc95xx_enable_phy_wakeup_interrupts(dev,
  1268. PHY_INT_MASK_LINK_DOWN_);
  1269. if (ret < 0) {
  1270. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1271. return ret;
  1272. }
  1273. netdev_dbg(dev->net, "autosuspend entering SUSPEND3\n");
  1274. return smsc95xx_enter_suspend3(dev);
  1275. }
  1276. static int smsc95xx_suspend(struct usb_interface *intf, pm_message_t message)
  1277. {
  1278. struct usbnet *dev = usb_get_intfdata(intf);
  1279. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1280. u32 val, link_up;
  1281. int ret;
  1282. ret = usbnet_suspend(intf, message);
  1283. if (ret < 0) {
  1284. netdev_warn(dev->net, "usbnet_suspend error\n");
  1285. return ret;
  1286. }
  1287. if (pdata->suspend_flags) {
  1288. netdev_warn(dev->net, "error during last resume\n");
  1289. pdata->suspend_flags = 0;
  1290. }
  1291. /* determine if link is up using only _nopm functions */
  1292. link_up = smsc95xx_link_ok_nopm(dev);
  1293. if (message.event == PM_EVENT_AUTO_SUSPEND &&
  1294. (pdata->features & FEATURE_REMOTE_WAKEUP)) {
  1295. ret = smsc95xx_autosuspend(dev, link_up);
  1296. goto done;
  1297. }
  1298. /* if we get this far we're not autosuspending */
  1299. /* if no wol options set, or if link is down and we're not waking on
  1300. * PHY activity, enter lowest power SUSPEND2 mode
  1301. */
  1302. if (!(pdata->wolopts & SUPPORTED_WAKE) ||
  1303. !(link_up || (pdata->wolopts & WAKE_PHY))) {
  1304. netdev_info(dev->net, "entering SUSPEND2 mode\n");
  1305. /* disable energy detect (link up) & wake up events */
  1306. ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
  1307. if (ret < 0)
  1308. goto done;
  1309. val &= ~(WUCSR_MPEN_ | WUCSR_WAKE_EN_);
  1310. ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
  1311. if (ret < 0)
  1312. goto done;
  1313. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  1314. if (ret < 0)
  1315. goto done;
  1316. val &= ~(PM_CTL_ED_EN_ | PM_CTL_WOL_EN_);
  1317. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1318. if (ret < 0)
  1319. goto done;
  1320. ret = smsc95xx_enter_suspend2(dev);
  1321. goto done;
  1322. }
  1323. if (pdata->wolopts & WAKE_PHY) {
  1324. ret = smsc95xx_enable_phy_wakeup_interrupts(dev,
  1325. (PHY_INT_MASK_ANEG_COMP_ | PHY_INT_MASK_LINK_DOWN_));
  1326. if (ret < 0) {
  1327. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1328. goto done;
  1329. }
  1330. /* if link is down then configure EDPD and enter SUSPEND1,
  1331. * otherwise enter SUSPEND0 below
  1332. */
  1333. if (!link_up) {
  1334. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1335. ret = smsc95xx_enter_suspend1(dev);
  1336. goto done;
  1337. }
  1338. }
  1339. if (pdata->wolopts & (WAKE_BCAST | WAKE_MCAST | WAKE_ARP | WAKE_UCAST)) {
  1340. u32 *filter_mask = kzalloc(sizeof(u32) * 32, GFP_KERNEL);
  1341. u32 command[2];
  1342. u32 offset[2];
  1343. u32 crc[4];
  1344. int wuff_filter_count =
  1345. (pdata->features & FEATURE_8_WAKEUP_FILTERS) ?
  1346. LAN9500A_WUFF_NUM : LAN9500_WUFF_NUM;
  1347. int i, filter = 0;
  1348. if (!filter_mask) {
  1349. netdev_warn(dev->net, "Unable to allocate filter_mask\n");
  1350. ret = -ENOMEM;
  1351. goto done;
  1352. }
  1353. memset(command, 0, sizeof(command));
  1354. memset(offset, 0, sizeof(offset));
  1355. memset(crc, 0, sizeof(crc));
  1356. if (pdata->wolopts & WAKE_BCAST) {
  1357. const u8 bcast[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
  1358. netdev_info(dev->net, "enabling broadcast detection\n");
  1359. filter_mask[filter * 4] = 0x003F;
  1360. filter_mask[filter * 4 + 1] = 0x00;
  1361. filter_mask[filter * 4 + 2] = 0x00;
  1362. filter_mask[filter * 4 + 3] = 0x00;
  1363. command[filter/4] |= 0x05UL << ((filter % 4) * 8);
  1364. offset[filter/4] |= 0x00 << ((filter % 4) * 8);
  1365. crc[filter/2] |= smsc_crc(bcast, 6, filter);
  1366. filter++;
  1367. }
  1368. if (pdata->wolopts & WAKE_MCAST) {
  1369. const u8 mcast[] = {0x01, 0x00, 0x5E};
  1370. netdev_info(dev->net, "enabling multicast detection\n");
  1371. filter_mask[filter * 4] = 0x0007;
  1372. filter_mask[filter * 4 + 1] = 0x00;
  1373. filter_mask[filter * 4 + 2] = 0x00;
  1374. filter_mask[filter * 4 + 3] = 0x00;
  1375. command[filter/4] |= 0x09UL << ((filter % 4) * 8);
  1376. offset[filter/4] |= 0x00 << ((filter % 4) * 8);
  1377. crc[filter/2] |= smsc_crc(mcast, 3, filter);
  1378. filter++;
  1379. }
  1380. if (pdata->wolopts & WAKE_ARP) {
  1381. const u8 arp[] = {0x08, 0x06};
  1382. netdev_info(dev->net, "enabling ARP detection\n");
  1383. filter_mask[filter * 4] = 0x0003;
  1384. filter_mask[filter * 4 + 1] = 0x00;
  1385. filter_mask[filter * 4 + 2] = 0x00;
  1386. filter_mask[filter * 4 + 3] = 0x00;
  1387. command[filter/4] |= 0x05UL << ((filter % 4) * 8);
  1388. offset[filter/4] |= 0x0C << ((filter % 4) * 8);
  1389. crc[filter/2] |= smsc_crc(arp, 2, filter);
  1390. filter++;
  1391. }
  1392. if (pdata->wolopts & WAKE_UCAST) {
  1393. netdev_info(dev->net, "enabling unicast detection\n");
  1394. filter_mask[filter * 4] = 0x003F;
  1395. filter_mask[filter * 4 + 1] = 0x00;
  1396. filter_mask[filter * 4 + 2] = 0x00;
  1397. filter_mask[filter * 4 + 3] = 0x00;
  1398. command[filter/4] |= 0x01UL << ((filter % 4) * 8);
  1399. offset[filter/4] |= 0x00 << ((filter % 4) * 8);
  1400. crc[filter/2] |= smsc_crc(dev->net->dev_addr, ETH_ALEN, filter);
  1401. filter++;
  1402. }
  1403. for (i = 0; i < (wuff_filter_count * 4); i++) {
  1404. ret = smsc95xx_write_reg_nopm(dev, WUFF, filter_mask[i]);
  1405. if (ret < 0) {
  1406. kfree(filter_mask);
  1407. goto done;
  1408. }
  1409. }
  1410. kfree(filter_mask);
  1411. for (i = 0; i < (wuff_filter_count / 4); i++) {
  1412. ret = smsc95xx_write_reg_nopm(dev, WUFF, command[i]);
  1413. if (ret < 0)
  1414. goto done;
  1415. }
  1416. for (i = 0; i < (wuff_filter_count / 4); i++) {
  1417. ret = smsc95xx_write_reg_nopm(dev, WUFF, offset[i]);
  1418. if (ret < 0)
  1419. goto done;
  1420. }
  1421. for (i = 0; i < (wuff_filter_count / 2); i++) {
  1422. ret = smsc95xx_write_reg_nopm(dev, WUFF, crc[i]);
  1423. if (ret < 0)
  1424. goto done;
  1425. }
  1426. /* clear any pending pattern match packet status */
  1427. ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
  1428. if (ret < 0)
  1429. goto done;
  1430. val |= WUCSR_WUFR_;
  1431. ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
  1432. if (ret < 0)
  1433. goto done;
  1434. }
  1435. if (pdata->wolopts & WAKE_MAGIC) {
  1436. /* clear any pending magic packet status */
  1437. ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
  1438. if (ret < 0)
  1439. goto done;
  1440. val |= WUCSR_MPR_;
  1441. ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
  1442. if (ret < 0)
  1443. goto done;
  1444. }
  1445. /* enable/disable wakeup sources */
  1446. ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
  1447. if (ret < 0)
  1448. goto done;
  1449. if (pdata->wolopts & (WAKE_BCAST | WAKE_MCAST | WAKE_ARP | WAKE_UCAST)) {
  1450. netdev_info(dev->net, "enabling pattern match wakeup\n");
  1451. val |= WUCSR_WAKE_EN_;
  1452. } else {
  1453. netdev_info(dev->net, "disabling pattern match wakeup\n");
  1454. val &= ~WUCSR_WAKE_EN_;
  1455. }
  1456. if (pdata->wolopts & WAKE_MAGIC) {
  1457. netdev_info(dev->net, "enabling magic packet wakeup\n");
  1458. val |= WUCSR_MPEN_;
  1459. } else {
  1460. netdev_info(dev->net, "disabling magic packet wakeup\n");
  1461. val &= ~WUCSR_MPEN_;
  1462. }
  1463. ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
  1464. if (ret < 0)
  1465. goto done;
  1466. /* enable wol wakeup source */
  1467. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  1468. if (ret < 0)
  1469. goto done;
  1470. val |= PM_CTL_WOL_EN_;
  1471. /* phy energy detect wakeup source */
  1472. if (pdata->wolopts & WAKE_PHY)
  1473. val |= PM_CTL_ED_EN_;
  1474. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1475. if (ret < 0)
  1476. goto done;
  1477. /* enable receiver to enable frame reception */
  1478. smsc95xx_start_rx_path(dev, 1);
  1479. /* some wol options are enabled, so enter SUSPEND0 */
  1480. netdev_info(dev->net, "entering SUSPEND0 mode\n");
  1481. ret = smsc95xx_enter_suspend0(dev);
  1482. done:
  1483. /*
  1484. * TODO: resume() might need to handle the suspend failure
  1485. * in system sleep
  1486. */
  1487. if (ret && PMSG_IS_AUTO(message))
  1488. usbnet_resume(intf);
  1489. return ret;
  1490. }
  1491. static int smsc95xx_resume(struct usb_interface *intf)
  1492. {
  1493. struct usbnet *dev = usb_get_intfdata(intf);
  1494. struct smsc95xx_priv *pdata;
  1495. u8 suspend_flags;
  1496. int ret;
  1497. u32 val;
  1498. BUG_ON(!dev);
  1499. pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1500. suspend_flags = pdata->suspend_flags;
  1501. netdev_dbg(dev->net, "resume suspend_flags=0x%02x\n", suspend_flags);
  1502. /* do this first to ensure it's cleared even in error case */
  1503. pdata->suspend_flags = 0;
  1504. schedule_delayed_work(&pdata->carrier_check, CARRIER_CHECK_DELAY);
  1505. if (suspend_flags & SUSPEND_ALLMODES) {
  1506. /* clear wake-up sources */
  1507. ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
  1508. if (ret < 0)
  1509. return ret;
  1510. val &= ~(WUCSR_WAKE_EN_ | WUCSR_MPEN_);
  1511. ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
  1512. if (ret < 0)
  1513. return ret;
  1514. /* clear wake-up status */
  1515. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  1516. if (ret < 0)
  1517. return ret;
  1518. val &= ~PM_CTL_WOL_EN_;
  1519. val |= PM_CTL_WUPS_;
  1520. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1521. if (ret < 0)
  1522. return ret;
  1523. }
  1524. ret = usbnet_resume(intf);
  1525. if (ret < 0)
  1526. netdev_warn(dev->net, "usbnet_resume error\n");
  1527. return ret;
  1528. }
  1529. static int smsc95xx_reset_resume(struct usb_interface *intf)
  1530. {
  1531. struct usbnet *dev = usb_get_intfdata(intf);
  1532. int ret;
  1533. ret = smsc95xx_reset(dev);
  1534. if (ret < 0)
  1535. return ret;
  1536. return smsc95xx_resume(intf);
  1537. }
  1538. static void smsc95xx_rx_csum_offload(struct sk_buff *skb)
  1539. {
  1540. skb->csum = *(u16 *)(skb_tail_pointer(skb) - 2);
  1541. skb->ip_summed = CHECKSUM_COMPLETE;
  1542. skb_trim(skb, skb->len - 2);
  1543. }
  1544. static int smsc95xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
  1545. {
  1546. /* This check is no longer done by usbnet */
  1547. if (skb->len < dev->net->hard_header_len)
  1548. return 0;
  1549. while (skb->len > 0) {
  1550. u32 header, align_count;
  1551. struct sk_buff *ax_skb;
  1552. unsigned char *packet;
  1553. u16 size;
  1554. memcpy(&header, skb->data, sizeof(header));
  1555. le32_to_cpus(&header);
  1556. skb_pull(skb, 4 + NET_IP_ALIGN);
  1557. packet = skb->data;
  1558. /* get the packet length */
  1559. size = (u16)((header & RX_STS_FL_) >> 16);
  1560. align_count = (4 - ((size + NET_IP_ALIGN) % 4)) % 4;
  1561. if (unlikely(header & RX_STS_ES_)) {
  1562. netif_dbg(dev, rx_err, dev->net,
  1563. "Error header=0x%08x\n", header);
  1564. dev->net->stats.rx_errors++;
  1565. dev->net->stats.rx_dropped++;
  1566. if (header & RX_STS_CRC_) {
  1567. dev->net->stats.rx_crc_errors++;
  1568. } else {
  1569. if (header & (RX_STS_TL_ | RX_STS_RF_))
  1570. dev->net->stats.rx_frame_errors++;
  1571. if ((header & RX_STS_LE_) &&
  1572. (!(header & RX_STS_FT_)))
  1573. dev->net->stats.rx_length_errors++;
  1574. }
  1575. } else {
  1576. /* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */
  1577. if (unlikely(size > (ETH_FRAME_LEN + 12))) {
  1578. netif_dbg(dev, rx_err, dev->net,
  1579. "size err header=0x%08x\n", header);
  1580. return 0;
  1581. }
  1582. /* last frame in this batch */
  1583. if (skb->len == size) {
  1584. if (dev->net->features & NETIF_F_RXCSUM)
  1585. smsc95xx_rx_csum_offload(skb);
  1586. skb_trim(skb, skb->len - 4); /* remove fcs */
  1587. skb->truesize = size + sizeof(struct sk_buff);
  1588. return 1;
  1589. }
  1590. ax_skb = skb_clone(skb, GFP_ATOMIC);
  1591. if (unlikely(!ax_skb)) {
  1592. netdev_warn(dev->net, "Error allocating skb\n");
  1593. return 0;
  1594. }
  1595. ax_skb->len = size;
  1596. ax_skb->data = packet;
  1597. skb_set_tail_pointer(ax_skb, size);
  1598. if (dev->net->features & NETIF_F_RXCSUM)
  1599. smsc95xx_rx_csum_offload(ax_skb);
  1600. skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
  1601. ax_skb->truesize = size + sizeof(struct sk_buff);
  1602. usbnet_skb_return(dev, ax_skb);
  1603. }
  1604. skb_pull(skb, size);
  1605. /* padding bytes before the next frame starts */
  1606. if (skb->len)
  1607. skb_pull(skb, align_count);
  1608. }
  1609. return 1;
  1610. }
  1611. static u32 smsc95xx_calc_csum_preamble(struct sk_buff *skb)
  1612. {
  1613. u16 low_16 = (u16)skb_checksum_start_offset(skb);
  1614. u16 high_16 = low_16 + skb->csum_offset;
  1615. return (high_16 << 16) | low_16;
  1616. }
  1617. static struct sk_buff *smsc95xx_tx_fixup(struct usbnet *dev,
  1618. struct sk_buff *skb, gfp_t flags)
  1619. {
  1620. bool csum = skb->ip_summed == CHECKSUM_PARTIAL;
  1621. int overhead = csum ? SMSC95XX_TX_OVERHEAD_CSUM : SMSC95XX_TX_OVERHEAD;
  1622. u32 tx_cmd_a, tx_cmd_b;
  1623. /* We do not advertise SG, so skbs should be already linearized */
  1624. BUG_ON(skb_shinfo(skb)->nr_frags);
  1625. /* Make writable and expand header space by overhead if required */
  1626. if (skb_cow_head(skb, overhead)) {
  1627. /* Must deallocate here as returning NULL to indicate error
  1628. * means the skb won't be deallocated in the caller.
  1629. */
  1630. dev_kfree_skb_any(skb);
  1631. return NULL;
  1632. }
  1633. if (csum) {
  1634. if (skb->len <= 45) {
  1635. /* workaround - hardware tx checksum does not work
  1636. * properly with extremely small packets */
  1637. long csstart = skb_checksum_start_offset(skb);
  1638. __wsum calc = csum_partial(skb->data + csstart,
  1639. skb->len - csstart, 0);
  1640. *((__sum16 *)(skb->data + csstart
  1641. + skb->csum_offset)) = csum_fold(calc);
  1642. csum = false;
  1643. } else {
  1644. u32 csum_preamble = smsc95xx_calc_csum_preamble(skb);
  1645. skb_push(skb, 4);
  1646. cpu_to_le32s(&csum_preamble);
  1647. memcpy(skb->data, &csum_preamble, 4);
  1648. }
  1649. }
  1650. skb_push(skb, 4);
  1651. tx_cmd_b = (u32)(skb->len - 4);
  1652. if (csum)
  1653. tx_cmd_b |= TX_CMD_B_CSUM_ENABLE;
  1654. cpu_to_le32s(&tx_cmd_b);
  1655. memcpy(skb->data, &tx_cmd_b, 4);
  1656. skb_push(skb, 4);
  1657. tx_cmd_a = (u32)(skb->len - 8) | TX_CMD_A_FIRST_SEG_ |
  1658. TX_CMD_A_LAST_SEG_;
  1659. cpu_to_le32s(&tx_cmd_a);
  1660. memcpy(skb->data, &tx_cmd_a, 4);
  1661. return skb;
  1662. }
  1663. static int smsc95xx_manage_power(struct usbnet *dev, int on)
  1664. {
  1665. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1666. dev->intf->needs_remote_wakeup = on;
  1667. if (pdata->features & FEATURE_REMOTE_WAKEUP)
  1668. return 0;
  1669. /* this chip revision isn't capable of remote wakeup */
  1670. netdev_info(dev->net, "hardware isn't capable of remote wakeup\n");
  1671. if (on)
  1672. usb_autopm_get_interface_no_resume(dev->intf);
  1673. else
  1674. usb_autopm_put_interface(dev->intf);
  1675. return 0;
  1676. }
  1677. static const struct driver_info smsc95xx_info = {
  1678. .description = "smsc95xx USB 2.0 Ethernet",
  1679. .bind = smsc95xx_bind,
  1680. .unbind = smsc95xx_unbind,
  1681. .link_reset = smsc95xx_link_reset,
  1682. .reset = smsc95xx_reset,
  1683. .rx_fixup = smsc95xx_rx_fixup,
  1684. .tx_fixup = smsc95xx_tx_fixup,
  1685. .status = smsc95xx_status,
  1686. .manage_power = smsc95xx_manage_power,
  1687. .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
  1688. };
  1689. static const struct usb_device_id products[] = {
  1690. {
  1691. /* SMSC9500 USB Ethernet Device */
  1692. USB_DEVICE(0x0424, 0x9500),
  1693. .driver_info = (unsigned long) &smsc95xx_info,
  1694. },
  1695. {
  1696. /* SMSC9505 USB Ethernet Device */
  1697. USB_DEVICE(0x0424, 0x9505),
  1698. .driver_info = (unsigned long) &smsc95xx_info,
  1699. },
  1700. {
  1701. /* SMSC9500A USB Ethernet Device */
  1702. USB_DEVICE(0x0424, 0x9E00),
  1703. .driver_info = (unsigned long) &smsc95xx_info,
  1704. },
  1705. {
  1706. /* SMSC9505A USB Ethernet Device */
  1707. USB_DEVICE(0x0424, 0x9E01),
  1708. .driver_info = (unsigned long) &smsc95xx_info,
  1709. },
  1710. {
  1711. /* SMSC9512/9514 USB Hub & Ethernet Device */
  1712. USB_DEVICE(0x0424, 0xec00),
  1713. .driver_info = (unsigned long) &smsc95xx_info,
  1714. },
  1715. {
  1716. /* SMSC9500 USB Ethernet Device (SAL10) */
  1717. USB_DEVICE(0x0424, 0x9900),
  1718. .driver_info = (unsigned long) &smsc95xx_info,
  1719. },
  1720. {
  1721. /* SMSC9505 USB Ethernet Device (SAL10) */
  1722. USB_DEVICE(0x0424, 0x9901),
  1723. .driver_info = (unsigned long) &smsc95xx_info,
  1724. },
  1725. {
  1726. /* SMSC9500A USB Ethernet Device (SAL10) */
  1727. USB_DEVICE(0x0424, 0x9902),
  1728. .driver_info = (unsigned long) &smsc95xx_info,
  1729. },
  1730. {
  1731. /* SMSC9505A USB Ethernet Device (SAL10) */
  1732. USB_DEVICE(0x0424, 0x9903),
  1733. .driver_info = (unsigned long) &smsc95xx_info,
  1734. },
  1735. {
  1736. /* SMSC9512/9514 USB Hub & Ethernet Device (SAL10) */
  1737. USB_DEVICE(0x0424, 0x9904),
  1738. .driver_info = (unsigned long) &smsc95xx_info,
  1739. },
  1740. {
  1741. /* SMSC9500A USB Ethernet Device (HAL) */
  1742. USB_DEVICE(0x0424, 0x9905),
  1743. .driver_info = (unsigned long) &smsc95xx_info,
  1744. },
  1745. {
  1746. /* SMSC9505A USB Ethernet Device (HAL) */
  1747. USB_DEVICE(0x0424, 0x9906),
  1748. .driver_info = (unsigned long) &smsc95xx_info,
  1749. },
  1750. {
  1751. /* SMSC9500 USB Ethernet Device (Alternate ID) */
  1752. USB_DEVICE(0x0424, 0x9907),
  1753. .driver_info = (unsigned long) &smsc95xx_info,
  1754. },
  1755. {
  1756. /* SMSC9500A USB Ethernet Device (Alternate ID) */
  1757. USB_DEVICE(0x0424, 0x9908),
  1758. .driver_info = (unsigned long) &smsc95xx_info,
  1759. },
  1760. {
  1761. /* SMSC9512/9514 USB Hub & Ethernet Device (Alternate ID) */
  1762. USB_DEVICE(0x0424, 0x9909),
  1763. .driver_info = (unsigned long) &smsc95xx_info,
  1764. },
  1765. {
  1766. /* SMSC LAN9530 USB Ethernet Device */
  1767. USB_DEVICE(0x0424, 0x9530),
  1768. .driver_info = (unsigned long) &smsc95xx_info,
  1769. },
  1770. {
  1771. /* SMSC LAN9730 USB Ethernet Device */
  1772. USB_DEVICE(0x0424, 0x9730),
  1773. .driver_info = (unsigned long) &smsc95xx_info,
  1774. },
  1775. {
  1776. /* SMSC LAN89530 USB Ethernet Device */
  1777. USB_DEVICE(0x0424, 0x9E08),
  1778. .driver_info = (unsigned long) &smsc95xx_info,
  1779. },
  1780. { }, /* END */
  1781. };
  1782. MODULE_DEVICE_TABLE(usb, products);
  1783. static struct usb_driver smsc95xx_driver = {
  1784. .name = "smsc95xx",
  1785. .id_table = products,
  1786. .probe = usbnet_probe,
  1787. .suspend = smsc95xx_suspend,
  1788. .resume = smsc95xx_resume,
  1789. .reset_resume = smsc95xx_reset_resume,
  1790. .disconnect = usbnet_disconnect,
  1791. .disable_hub_initiated_lpm = 1,
  1792. .supports_autosuspend = 1,
  1793. };
  1794. module_usb_driver(smsc95xx_driver);
  1795. MODULE_AUTHOR("Nancy Lin");
  1796. MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
  1797. MODULE_DESCRIPTION("SMSC95XX USB 2.0 Ethernet Devices");
  1798. MODULE_LICENSE("GPL");