broadcom.c 19 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726
  1. /*
  2. * drivers/net/phy/broadcom.c
  3. *
  4. * Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet
  5. * transceivers.
  6. *
  7. * Copyright (c) 2006 Maciej W. Rozycki
  8. *
  9. * Inspired by code written by Amy Fong.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License
  13. * as published by the Free Software Foundation; either version
  14. * 2 of the License, or (at your option) any later version.
  15. */
  16. #include "bcm-phy-lib.h"
  17. #include <linux/module.h>
  18. #include <linux/phy.h>
  19. #include <linux/brcmphy.h>
  20. #include <linux/of.h>
  21. #define BRCM_PHY_MODEL(phydev) \
  22. ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
  23. #define BRCM_PHY_REV(phydev) \
  24. ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
  25. MODULE_DESCRIPTION("Broadcom PHY driver");
  26. MODULE_AUTHOR("Maciej W. Rozycki");
  27. MODULE_LICENSE("GPL");
  28. static int bcm54210e_config_init(struct phy_device *phydev)
  29. {
  30. int val;
  31. val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
  32. val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
  33. val |= MII_BCM54XX_AUXCTL_MISC_WREN;
  34. bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, val);
  35. val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
  36. val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
  37. bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
  38. return 0;
  39. }
  40. static int bcm54612e_config_init(struct phy_device *phydev)
  41. {
  42. /* Clear TX internal delay unless requested. */
  43. if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
  44. (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {
  45. /* Disable TXD to GTXCLK clock delay (default set) */
  46. /* Bit 9 is the only field in shadow register 00011 */
  47. bcm_phy_write_shadow(phydev, 0x03, 0);
  48. }
  49. /* Clear RX internal delay unless requested. */
  50. if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
  51. (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
  52. u16 reg;
  53. reg = bcm54xx_auxctl_read(phydev,
  54. MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
  55. /* Disable RXD to RXC delay (default set) */
  56. reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
  57. /* Clear shadow selector field */
  58. reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
  59. bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
  60. MII_BCM54XX_AUXCTL_MISC_WREN | reg);
  61. }
  62. return 0;
  63. }
  64. static int bcm5481x_config(struct phy_device *phydev)
  65. {
  66. int rc, val;
  67. /* handling PHY's internal RX clock delay */
  68. val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
  69. val |= MII_BCM54XX_AUXCTL_MISC_WREN;
  70. if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
  71. phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
  72. /* Disable RGMII RXC-RXD skew */
  73. val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
  74. }
  75. if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
  76. phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
  77. /* Enable RGMII RXC-RXD skew */
  78. val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
  79. }
  80. rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
  81. val);
  82. if (rc < 0)
  83. return rc;
  84. /* handling PHY's internal TX clock delay */
  85. val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
  86. if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
  87. phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
  88. /* Disable internal TX clock delay */
  89. val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
  90. }
  91. if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
  92. phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
  93. /* Enable internal TX clock delay */
  94. val |= BCM54810_SHD_CLK_CTL_GTXCLK_EN;
  95. }
  96. rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
  97. if (rc < 0)
  98. return rc;
  99. return 0;
  100. }
  101. /* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
  102. static int bcm50610_a0_workaround(struct phy_device *phydev)
  103. {
  104. int err;
  105. err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH0,
  106. MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN |
  107. MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF);
  108. if (err < 0)
  109. return err;
  110. err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH3,
  111. MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ);
  112. if (err < 0)
  113. return err;
  114. err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75,
  115. MII_BCM54XX_EXP_EXP75_VDACCTRL);
  116. if (err < 0)
  117. return err;
  118. err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP96,
  119. MII_BCM54XX_EXP_EXP96_MYST);
  120. if (err < 0)
  121. return err;
  122. err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP97,
  123. MII_BCM54XX_EXP_EXP97_MYST);
  124. return err;
  125. }
  126. static int bcm54xx_phydsp_config(struct phy_device *phydev)
  127. {
  128. int err, err2;
  129. /* Enable the SMDSP clock */
  130. err = bcm54xx_auxctl_write(phydev,
  131. MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
  132. MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA |
  133. MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
  134. if (err < 0)
  135. return err;
  136. if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
  137. BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) {
  138. /* Clear bit 9 to fix a phy interop issue. */
  139. err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08,
  140. MII_BCM54XX_EXP_EXP08_RJCT_2MHZ);
  141. if (err < 0)
  142. goto error;
  143. if (phydev->drv->phy_id == PHY_ID_BCM50610) {
  144. err = bcm50610_a0_workaround(phydev);
  145. if (err < 0)
  146. goto error;
  147. }
  148. }
  149. if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) {
  150. int val;
  151. val = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP75);
  152. if (val < 0)
  153. goto error;
  154. val |= MII_BCM54XX_EXP_EXP75_CM_OSC;
  155. err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, val);
  156. }
  157. error:
  158. /* Disable the SMDSP clock */
  159. err2 = bcm54xx_auxctl_write(phydev,
  160. MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
  161. MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
  162. /* Return the first error reported. */
  163. return err ? err : err2;
  164. }
  165. static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev)
  166. {
  167. u32 orig;
  168. int val;
  169. bool clk125en = true;
  170. /* Abort if we are using an untested phy. */
  171. if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM57780 &&
  172. BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 &&
  173. BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M)
  174. return;
  175. val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
  176. if (val < 0)
  177. return;
  178. orig = val;
  179. if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
  180. BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
  181. BRCM_PHY_REV(phydev) >= 0x3) {
  182. /*
  183. * Here, bit 0 _disables_ CLK125 when set.
  184. * This bit is set by default.
  185. */
  186. clk125en = false;
  187. } else {
  188. if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) {
  189. /* Here, bit 0 _enables_ CLK125 when set */
  190. val &= ~BCM54XX_SHD_SCR3_DEF_CLK125;
  191. clk125en = false;
  192. }
  193. }
  194. if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
  195. val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS;
  196. else
  197. val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
  198. if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY)
  199. val |= BCM54XX_SHD_SCR3_TRDDAPD;
  200. if (orig != val)
  201. bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
  202. val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD);
  203. if (val < 0)
  204. return;
  205. orig = val;
  206. if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
  207. val |= BCM54XX_SHD_APD_EN;
  208. else
  209. val &= ~BCM54XX_SHD_APD_EN;
  210. if (orig != val)
  211. bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val);
  212. }
  213. static int bcm54xx_config_init(struct phy_device *phydev)
  214. {
  215. int reg, err, val;
  216. reg = phy_read(phydev, MII_BCM54XX_ECR);
  217. if (reg < 0)
  218. return reg;
  219. /* Mask interrupts globally. */
  220. reg |= MII_BCM54XX_ECR_IM;
  221. err = phy_write(phydev, MII_BCM54XX_ECR, reg);
  222. if (err < 0)
  223. return err;
  224. /* Unmask events we are interested in. */
  225. reg = ~(MII_BCM54XX_INT_DUPLEX |
  226. MII_BCM54XX_INT_SPEED |
  227. MII_BCM54XX_INT_LINK);
  228. err = phy_write(phydev, MII_BCM54XX_IMR, reg);
  229. if (err < 0)
  230. return err;
  231. if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
  232. BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
  233. (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE))
  234. bcm_phy_write_shadow(phydev, BCM54XX_SHD_RGMII_MODE, 0);
  235. if ((phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) ||
  236. (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) ||
  237. (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
  238. bcm54xx_adjust_rxrefclk(phydev);
  239. if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54210E) {
  240. err = bcm54210e_config_init(phydev);
  241. if (err)
  242. return err;
  243. } else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54612E) {
  244. err = bcm54612e_config_init(phydev);
  245. if (err)
  246. return err;
  247. } else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
  248. /* For BCM54810, we need to disable BroadR-Reach function */
  249. val = bcm_phy_read_exp(phydev,
  250. BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
  251. val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
  252. err = bcm_phy_write_exp(phydev,
  253. BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
  254. val);
  255. if (err < 0)
  256. return err;
  257. }
  258. bcm54xx_phydsp_config(phydev);
  259. return 0;
  260. }
  261. static int bcm5482_config_init(struct phy_device *phydev)
  262. {
  263. int err, reg;
  264. err = bcm54xx_config_init(phydev);
  265. if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
  266. /*
  267. * Enable secondary SerDes and its use as an LED source
  268. */
  269. reg = bcm_phy_read_shadow(phydev, BCM5482_SHD_SSD);
  270. bcm_phy_write_shadow(phydev, BCM5482_SHD_SSD,
  271. reg |
  272. BCM5482_SHD_SSD_LEDM |
  273. BCM5482_SHD_SSD_EN);
  274. /*
  275. * Enable SGMII slave mode and auto-detection
  276. */
  277. reg = BCM5482_SSD_SGMII_SLAVE | MII_BCM54XX_EXP_SEL_SSD;
  278. err = bcm_phy_read_exp(phydev, reg);
  279. if (err < 0)
  280. return err;
  281. err = bcm_phy_write_exp(phydev, reg, err |
  282. BCM5482_SSD_SGMII_SLAVE_EN |
  283. BCM5482_SSD_SGMII_SLAVE_AD);
  284. if (err < 0)
  285. return err;
  286. /*
  287. * Disable secondary SerDes powerdown
  288. */
  289. reg = BCM5482_SSD_1000BX_CTL | MII_BCM54XX_EXP_SEL_SSD;
  290. err = bcm_phy_read_exp(phydev, reg);
  291. if (err < 0)
  292. return err;
  293. err = bcm_phy_write_exp(phydev, reg,
  294. err & ~BCM5482_SSD_1000BX_CTL_PWRDOWN);
  295. if (err < 0)
  296. return err;
  297. /*
  298. * Select 1000BASE-X register set (primary SerDes)
  299. */
  300. reg = bcm_phy_read_shadow(phydev, BCM5482_SHD_MODE);
  301. bcm_phy_write_shadow(phydev, BCM5482_SHD_MODE,
  302. reg | BCM5482_SHD_MODE_1000BX);
  303. /*
  304. * LED1=ACTIVITYLED, LED3=LINKSPD[2]
  305. * (Use LED1 as secondary SerDes ACTIVITY LED)
  306. */
  307. bcm_phy_write_shadow(phydev, BCM5482_SHD_LEDS1,
  308. BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_ACTIVITYLED) |
  309. BCM5482_SHD_LEDS1_LED3(BCM_LED_SRC_LINKSPD2));
  310. /*
  311. * Auto-negotiation doesn't seem to work quite right
  312. * in this mode, so we disable it and force it to the
  313. * right speed/duplex setting. Only 'link status'
  314. * is important.
  315. */
  316. phydev->autoneg = AUTONEG_DISABLE;
  317. phydev->speed = SPEED_1000;
  318. phydev->duplex = DUPLEX_FULL;
  319. }
  320. return err;
  321. }
  322. static int bcm5482_read_status(struct phy_device *phydev)
  323. {
  324. int err;
  325. err = genphy_read_status(phydev);
  326. if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
  327. /*
  328. * Only link status matters for 1000Base-X mode, so force
  329. * 1000 Mbit/s full-duplex status
  330. */
  331. if (phydev->link) {
  332. phydev->speed = SPEED_1000;
  333. phydev->duplex = DUPLEX_FULL;
  334. }
  335. }
  336. return err;
  337. }
  338. static int bcm5481_config_aneg(struct phy_device *phydev)
  339. {
  340. struct device_node *np = phydev->mdio.dev.of_node;
  341. int ret;
  342. /* Aneg firsly. */
  343. ret = genphy_config_aneg(phydev);
  344. /* Then we can set up the delay. */
  345. bcm5481x_config(phydev);
  346. if (of_property_read_bool(np, "enet-phy-lane-swap")) {
  347. /* Lane Swap - Undocumented register...magic! */
  348. ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9,
  349. 0x11B);
  350. if (ret < 0)
  351. return ret;
  352. }
  353. return ret;
  354. }
  355. static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
  356. {
  357. int val;
  358. val = phy_read(phydev, reg);
  359. if (val < 0)
  360. return val;
  361. return phy_write(phydev, reg, val | set);
  362. }
  363. static int brcm_fet_config_init(struct phy_device *phydev)
  364. {
  365. int reg, err, err2, brcmtest;
  366. /* Reset the PHY to bring it to a known state. */
  367. err = phy_write(phydev, MII_BMCR, BMCR_RESET);
  368. if (err < 0)
  369. return err;
  370. reg = phy_read(phydev, MII_BRCM_FET_INTREG);
  371. if (reg < 0)
  372. return reg;
  373. /* Unmask events we are interested in and mask interrupts globally. */
  374. reg = MII_BRCM_FET_IR_DUPLEX_EN |
  375. MII_BRCM_FET_IR_SPEED_EN |
  376. MII_BRCM_FET_IR_LINK_EN |
  377. MII_BRCM_FET_IR_ENABLE |
  378. MII_BRCM_FET_IR_MASK;
  379. err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
  380. if (err < 0)
  381. return err;
  382. /* Enable shadow register access */
  383. brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
  384. if (brcmtest < 0)
  385. return brcmtest;
  386. reg = brcmtest | MII_BRCM_FET_BT_SRE;
  387. err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
  388. if (err < 0)
  389. return err;
  390. /* Set the LED mode */
  391. reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4);
  392. if (reg < 0) {
  393. err = reg;
  394. goto done;
  395. }
  396. reg &= ~MII_BRCM_FET_SHDW_AM4_LED_MASK;
  397. reg |= MII_BRCM_FET_SHDW_AM4_LED_MODE1;
  398. err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg);
  399. if (err < 0)
  400. goto done;
  401. /* Enable auto MDIX */
  402. err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_MISCCTRL,
  403. MII_BRCM_FET_SHDW_MC_FAME);
  404. if (err < 0)
  405. goto done;
  406. if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) {
  407. /* Enable auto power down */
  408. err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
  409. MII_BRCM_FET_SHDW_AS2_APDE);
  410. }
  411. done:
  412. /* Disable shadow register access */
  413. err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
  414. if (!err)
  415. err = err2;
  416. return err;
  417. }
  418. static int brcm_fet_ack_interrupt(struct phy_device *phydev)
  419. {
  420. int reg;
  421. /* Clear pending interrupts. */
  422. reg = phy_read(phydev, MII_BRCM_FET_INTREG);
  423. if (reg < 0)
  424. return reg;
  425. return 0;
  426. }
  427. static int brcm_fet_config_intr(struct phy_device *phydev)
  428. {
  429. int reg, err;
  430. reg = phy_read(phydev, MII_BRCM_FET_INTREG);
  431. if (reg < 0)
  432. return reg;
  433. if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
  434. reg &= ~MII_BRCM_FET_IR_MASK;
  435. else
  436. reg |= MII_BRCM_FET_IR_MASK;
  437. err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
  438. return err;
  439. }
  440. static struct phy_driver broadcom_drivers[] = {
  441. {
  442. .phy_id = PHY_ID_BCM5411,
  443. .phy_id_mask = 0xfffffff0,
  444. .name = "Broadcom BCM5411",
  445. .features = PHY_GBIT_FEATURES,
  446. .flags = PHY_HAS_INTERRUPT,
  447. .config_init = bcm54xx_config_init,
  448. .config_aneg = genphy_config_aneg,
  449. .read_status = genphy_read_status,
  450. .ack_interrupt = bcm_phy_ack_intr,
  451. .config_intr = bcm_phy_config_intr,
  452. }, {
  453. .phy_id = PHY_ID_BCM5421,
  454. .phy_id_mask = 0xfffffff0,
  455. .name = "Broadcom BCM5421",
  456. .features = PHY_GBIT_FEATURES,
  457. .flags = PHY_HAS_INTERRUPT,
  458. .config_init = bcm54xx_config_init,
  459. .config_aneg = genphy_config_aneg,
  460. .read_status = genphy_read_status,
  461. .ack_interrupt = bcm_phy_ack_intr,
  462. .config_intr = bcm_phy_config_intr,
  463. }, {
  464. .phy_id = PHY_ID_BCM54210E,
  465. .phy_id_mask = 0xfffffff0,
  466. .name = "Broadcom BCM54210E",
  467. .features = PHY_GBIT_FEATURES,
  468. .flags = PHY_HAS_INTERRUPT,
  469. .config_init = bcm54xx_config_init,
  470. .config_aneg = genphy_config_aneg,
  471. .read_status = genphy_read_status,
  472. .ack_interrupt = bcm_phy_ack_intr,
  473. .config_intr = bcm_phy_config_intr,
  474. }, {
  475. .phy_id = PHY_ID_BCM5461,
  476. .phy_id_mask = 0xfffffff0,
  477. .name = "Broadcom BCM5461",
  478. .features = PHY_GBIT_FEATURES,
  479. .flags = PHY_HAS_INTERRUPT,
  480. .config_init = bcm54xx_config_init,
  481. .config_aneg = genphy_config_aneg,
  482. .read_status = genphy_read_status,
  483. .ack_interrupt = bcm_phy_ack_intr,
  484. .config_intr = bcm_phy_config_intr,
  485. }, {
  486. .phy_id = PHY_ID_BCM54612E,
  487. .phy_id_mask = 0xfffffff0,
  488. .name = "Broadcom BCM54612E",
  489. .features = PHY_GBIT_FEATURES,
  490. .flags = PHY_HAS_INTERRUPT,
  491. .config_init = bcm54xx_config_init,
  492. .config_aneg = genphy_config_aneg,
  493. .read_status = genphy_read_status,
  494. .ack_interrupt = bcm_phy_ack_intr,
  495. .config_intr = bcm_phy_config_intr,
  496. }, {
  497. .phy_id = PHY_ID_BCM54616S,
  498. .phy_id_mask = 0xfffffff0,
  499. .name = "Broadcom BCM54616S",
  500. .features = PHY_GBIT_FEATURES,
  501. .flags = PHY_HAS_INTERRUPT,
  502. .config_init = bcm54xx_config_init,
  503. .config_aneg = genphy_config_aneg,
  504. .read_status = genphy_read_status,
  505. .ack_interrupt = bcm_phy_ack_intr,
  506. .config_intr = bcm_phy_config_intr,
  507. }, {
  508. .phy_id = PHY_ID_BCM5464,
  509. .phy_id_mask = 0xfffffff0,
  510. .name = "Broadcom BCM5464",
  511. .features = PHY_GBIT_FEATURES,
  512. .flags = PHY_HAS_INTERRUPT,
  513. .config_init = bcm54xx_config_init,
  514. .config_aneg = genphy_config_aneg,
  515. .read_status = genphy_read_status,
  516. .ack_interrupt = bcm_phy_ack_intr,
  517. .config_intr = bcm_phy_config_intr,
  518. }, {
  519. .phy_id = PHY_ID_BCM5481,
  520. .phy_id_mask = 0xfffffff0,
  521. .name = "Broadcom BCM5481",
  522. .features = PHY_GBIT_FEATURES,
  523. .flags = PHY_HAS_INTERRUPT,
  524. .config_init = bcm54xx_config_init,
  525. .config_aneg = bcm5481_config_aneg,
  526. .read_status = genphy_read_status,
  527. .ack_interrupt = bcm_phy_ack_intr,
  528. .config_intr = bcm_phy_config_intr,
  529. }, {
  530. .phy_id = PHY_ID_BCM54810,
  531. .phy_id_mask = 0xfffffff0,
  532. .name = "Broadcom BCM54810",
  533. .features = PHY_GBIT_FEATURES,
  534. .flags = PHY_HAS_INTERRUPT,
  535. .config_init = bcm54xx_config_init,
  536. .config_aneg = bcm5481_config_aneg,
  537. .read_status = genphy_read_status,
  538. .ack_interrupt = bcm_phy_ack_intr,
  539. .config_intr = bcm_phy_config_intr,
  540. }, {
  541. .phy_id = PHY_ID_BCM5482,
  542. .phy_id_mask = 0xfffffff0,
  543. .name = "Broadcom BCM5482",
  544. .features = PHY_GBIT_FEATURES,
  545. .flags = PHY_HAS_INTERRUPT,
  546. .config_init = bcm5482_config_init,
  547. .config_aneg = genphy_config_aneg,
  548. .read_status = bcm5482_read_status,
  549. .ack_interrupt = bcm_phy_ack_intr,
  550. .config_intr = bcm_phy_config_intr,
  551. }, {
  552. .phy_id = PHY_ID_BCM50610,
  553. .phy_id_mask = 0xfffffff0,
  554. .name = "Broadcom BCM50610",
  555. .features = PHY_GBIT_FEATURES,
  556. .flags = PHY_HAS_INTERRUPT,
  557. .config_init = bcm54xx_config_init,
  558. .config_aneg = genphy_config_aneg,
  559. .read_status = genphy_read_status,
  560. .ack_interrupt = bcm_phy_ack_intr,
  561. .config_intr = bcm_phy_config_intr,
  562. }, {
  563. .phy_id = PHY_ID_BCM50610M,
  564. .phy_id_mask = 0xfffffff0,
  565. .name = "Broadcom BCM50610M",
  566. .features = PHY_GBIT_FEATURES,
  567. .flags = PHY_HAS_INTERRUPT,
  568. .config_init = bcm54xx_config_init,
  569. .config_aneg = genphy_config_aneg,
  570. .read_status = genphy_read_status,
  571. .ack_interrupt = bcm_phy_ack_intr,
  572. .config_intr = bcm_phy_config_intr,
  573. }, {
  574. .phy_id = PHY_ID_BCM57780,
  575. .phy_id_mask = 0xfffffff0,
  576. .name = "Broadcom BCM57780",
  577. .features = PHY_GBIT_FEATURES,
  578. .flags = PHY_HAS_INTERRUPT,
  579. .config_init = bcm54xx_config_init,
  580. .config_aneg = genphy_config_aneg,
  581. .read_status = genphy_read_status,
  582. .ack_interrupt = bcm_phy_ack_intr,
  583. .config_intr = bcm_phy_config_intr,
  584. }, {
  585. .phy_id = PHY_ID_BCMAC131,
  586. .phy_id_mask = 0xfffffff0,
  587. .name = "Broadcom BCMAC131",
  588. .features = PHY_BASIC_FEATURES,
  589. .flags = PHY_HAS_INTERRUPT,
  590. .config_init = brcm_fet_config_init,
  591. .config_aneg = genphy_config_aneg,
  592. .read_status = genphy_read_status,
  593. .ack_interrupt = brcm_fet_ack_interrupt,
  594. .config_intr = brcm_fet_config_intr,
  595. }, {
  596. .phy_id = PHY_ID_BCM5241,
  597. .phy_id_mask = 0xfffffff0,
  598. .name = "Broadcom BCM5241",
  599. .features = PHY_BASIC_FEATURES,
  600. .flags = PHY_HAS_INTERRUPT,
  601. .config_init = brcm_fet_config_init,
  602. .config_aneg = genphy_config_aneg,
  603. .read_status = genphy_read_status,
  604. .ack_interrupt = brcm_fet_ack_interrupt,
  605. .config_intr = brcm_fet_config_intr,
  606. } };
  607. module_phy_driver(broadcom_drivers);
  608. static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
  609. { PHY_ID_BCM5411, 0xfffffff0 },
  610. { PHY_ID_BCM5421, 0xfffffff0 },
  611. { PHY_ID_BCM54210E, 0xfffffff0 },
  612. { PHY_ID_BCM5461, 0xfffffff0 },
  613. { PHY_ID_BCM54612E, 0xfffffff0 },
  614. { PHY_ID_BCM54616S, 0xfffffff0 },
  615. { PHY_ID_BCM5464, 0xfffffff0 },
  616. { PHY_ID_BCM5481, 0xfffffff0 },
  617. { PHY_ID_BCM54810, 0xfffffff0 },
  618. { PHY_ID_BCM5482, 0xfffffff0 },
  619. { PHY_ID_BCM50610, 0xfffffff0 },
  620. { PHY_ID_BCM50610M, 0xfffffff0 },
  621. { PHY_ID_BCM57780, 0xfffffff0 },
  622. { PHY_ID_BCMAC131, 0xfffffff0 },
  623. { PHY_ID_BCM5241, 0xfffffff0 },
  624. { }
  625. };
  626. MODULE_DEVICE_TABLE(mdio, broadcom_tbl);