qca_spi.c 24 KB

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  1. /*
  2. * Copyright (c) 2011, 2012, Qualcomm Atheros Communications Inc.
  3. * Copyright (c) 2014, I2SE GmbH
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software
  6. * for any purpose with or without fee is hereby granted, provided
  7. * that the above copyright notice and this permission notice appear
  8. * in all copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL
  13. * THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR
  14. * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
  15. * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,
  16. * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  17. * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. /* This module implements the Qualcomm Atheros SPI protocol for
  20. * kernel-based SPI device; it is essentially an Ethernet-to-SPI
  21. * serial converter;
  22. */
  23. #include <linux/errno.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/if_arp.h>
  26. #include <linux/if_ether.h>
  27. #include <linux/init.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/jiffies.h>
  30. #include <linux/kernel.h>
  31. #include <linux/kthread.h>
  32. #include <linux/module.h>
  33. #include <linux/moduleparam.h>
  34. #include <linux/netdevice.h>
  35. #include <linux/of.h>
  36. #include <linux/of_device.h>
  37. #include <linux/of_net.h>
  38. #include <linux/sched.h>
  39. #include <linux/skbuff.h>
  40. #include <linux/spi/spi.h>
  41. #include <linux/types.h>
  42. #include "qca_7k.h"
  43. #include "qca_7k_common.h"
  44. #include "qca_debug.h"
  45. #include "qca_spi.h"
  46. #define MAX_DMA_BURST_LEN 5000
  47. /* Modules parameters */
  48. #define QCASPI_CLK_SPEED_MIN 1000000
  49. #define QCASPI_CLK_SPEED_MAX 16000000
  50. #define QCASPI_CLK_SPEED 8000000
  51. static int qcaspi_clkspeed;
  52. module_param(qcaspi_clkspeed, int, 0);
  53. MODULE_PARM_DESC(qcaspi_clkspeed, "SPI bus clock speed (Hz). Use 1000000-16000000.");
  54. #define QCASPI_BURST_LEN_MIN 1
  55. #define QCASPI_BURST_LEN_MAX MAX_DMA_BURST_LEN
  56. static int qcaspi_burst_len = MAX_DMA_BURST_LEN;
  57. module_param(qcaspi_burst_len, int, 0);
  58. MODULE_PARM_DESC(qcaspi_burst_len, "Number of data bytes per burst. Use 1-5000.");
  59. #define QCASPI_PLUGGABLE_MIN 0
  60. #define QCASPI_PLUGGABLE_MAX 1
  61. static int qcaspi_pluggable = QCASPI_PLUGGABLE_MIN;
  62. module_param(qcaspi_pluggable, int, 0);
  63. MODULE_PARM_DESC(qcaspi_pluggable, "Pluggable SPI connection (yes/no).");
  64. #define QCASPI_TX_TIMEOUT (1 * HZ)
  65. #define QCASPI_QCA7K_REBOOT_TIME_MS 1000
  66. static void
  67. start_spi_intr_handling(struct qcaspi *qca, u16 *intr_cause)
  68. {
  69. *intr_cause = 0;
  70. qcaspi_write_register(qca, SPI_REG_INTR_ENABLE, 0);
  71. qcaspi_read_register(qca, SPI_REG_INTR_CAUSE, intr_cause);
  72. netdev_dbg(qca->net_dev, "interrupts: 0x%04x\n", *intr_cause);
  73. }
  74. static void
  75. end_spi_intr_handling(struct qcaspi *qca, u16 intr_cause)
  76. {
  77. u16 intr_enable = (SPI_INT_CPU_ON |
  78. SPI_INT_PKT_AVLBL |
  79. SPI_INT_RDBUF_ERR |
  80. SPI_INT_WRBUF_ERR);
  81. qcaspi_write_register(qca, SPI_REG_INTR_CAUSE, intr_cause);
  82. qcaspi_write_register(qca, SPI_REG_INTR_ENABLE, intr_enable);
  83. netdev_dbg(qca->net_dev, "acking int: 0x%04x\n", intr_cause);
  84. }
  85. static u32
  86. qcaspi_write_burst(struct qcaspi *qca, u8 *src, u32 len)
  87. {
  88. __be16 cmd;
  89. struct spi_message *msg = &qca->spi_msg2;
  90. struct spi_transfer *transfer = &qca->spi_xfer2[0];
  91. int ret;
  92. cmd = cpu_to_be16(QCA7K_SPI_WRITE | QCA7K_SPI_EXTERNAL);
  93. transfer->tx_buf = &cmd;
  94. transfer->rx_buf = NULL;
  95. transfer->len = QCASPI_CMD_LEN;
  96. transfer = &qca->spi_xfer2[1];
  97. transfer->tx_buf = src;
  98. transfer->rx_buf = NULL;
  99. transfer->len = len;
  100. ret = spi_sync(qca->spi_dev, msg);
  101. if (ret || (msg->actual_length != QCASPI_CMD_LEN + len)) {
  102. qcaspi_spi_error(qca);
  103. return 0;
  104. }
  105. return len;
  106. }
  107. static u32
  108. qcaspi_write_legacy(struct qcaspi *qca, u8 *src, u32 len)
  109. {
  110. struct spi_message *msg = &qca->spi_msg1;
  111. struct spi_transfer *transfer = &qca->spi_xfer1;
  112. int ret;
  113. transfer->tx_buf = src;
  114. transfer->rx_buf = NULL;
  115. transfer->len = len;
  116. ret = spi_sync(qca->spi_dev, msg);
  117. if (ret || (msg->actual_length != len)) {
  118. qcaspi_spi_error(qca);
  119. return 0;
  120. }
  121. return len;
  122. }
  123. static u32
  124. qcaspi_read_burst(struct qcaspi *qca, u8 *dst, u32 len)
  125. {
  126. struct spi_message *msg = &qca->spi_msg2;
  127. __be16 cmd;
  128. struct spi_transfer *transfer = &qca->spi_xfer2[0];
  129. int ret;
  130. cmd = cpu_to_be16(QCA7K_SPI_READ | QCA7K_SPI_EXTERNAL);
  131. transfer->tx_buf = &cmd;
  132. transfer->rx_buf = NULL;
  133. transfer->len = QCASPI_CMD_LEN;
  134. transfer = &qca->spi_xfer2[1];
  135. transfer->tx_buf = NULL;
  136. transfer->rx_buf = dst;
  137. transfer->len = len;
  138. ret = spi_sync(qca->spi_dev, msg);
  139. if (ret || (msg->actual_length != QCASPI_CMD_LEN + len)) {
  140. qcaspi_spi_error(qca);
  141. return 0;
  142. }
  143. return len;
  144. }
  145. static u32
  146. qcaspi_read_legacy(struct qcaspi *qca, u8 *dst, u32 len)
  147. {
  148. struct spi_message *msg = &qca->spi_msg1;
  149. struct spi_transfer *transfer = &qca->spi_xfer1;
  150. int ret;
  151. transfer->tx_buf = NULL;
  152. transfer->rx_buf = dst;
  153. transfer->len = len;
  154. ret = spi_sync(qca->spi_dev, msg);
  155. if (ret || (msg->actual_length != len)) {
  156. qcaspi_spi_error(qca);
  157. return 0;
  158. }
  159. return len;
  160. }
  161. static int
  162. qcaspi_tx_cmd(struct qcaspi *qca, u16 cmd)
  163. {
  164. __be16 tx_data;
  165. struct spi_message *msg = &qca->spi_msg1;
  166. struct spi_transfer *transfer = &qca->spi_xfer1;
  167. int ret;
  168. tx_data = cpu_to_be16(cmd);
  169. transfer->len = sizeof(tx_data);
  170. transfer->tx_buf = &tx_data;
  171. transfer->rx_buf = NULL;
  172. ret = spi_sync(qca->spi_dev, msg);
  173. if (!ret)
  174. ret = msg->status;
  175. if (ret)
  176. qcaspi_spi_error(qca);
  177. return ret;
  178. }
  179. static int
  180. qcaspi_tx_frame(struct qcaspi *qca, struct sk_buff *skb)
  181. {
  182. u32 count;
  183. u32 written;
  184. u32 offset;
  185. u32 len;
  186. len = skb->len;
  187. qcaspi_write_register(qca, SPI_REG_BFR_SIZE, len);
  188. if (qca->legacy_mode)
  189. qcaspi_tx_cmd(qca, QCA7K_SPI_WRITE | QCA7K_SPI_EXTERNAL);
  190. offset = 0;
  191. while (len) {
  192. count = len;
  193. if (count > qca->burst_len)
  194. count = qca->burst_len;
  195. if (qca->legacy_mode) {
  196. written = qcaspi_write_legacy(qca,
  197. skb->data + offset,
  198. count);
  199. } else {
  200. written = qcaspi_write_burst(qca,
  201. skb->data + offset,
  202. count);
  203. }
  204. if (written != count)
  205. return -1;
  206. offset += count;
  207. len -= count;
  208. }
  209. return 0;
  210. }
  211. static int
  212. qcaspi_transmit(struct qcaspi *qca)
  213. {
  214. struct net_device_stats *n_stats = &qca->net_dev->stats;
  215. u16 available = 0;
  216. u32 pkt_len;
  217. u16 new_head;
  218. u16 packets = 0;
  219. if (qca->txr.skb[qca->txr.head] == NULL)
  220. return 0;
  221. qcaspi_read_register(qca, SPI_REG_WRBUF_SPC_AVA, &available);
  222. while (qca->txr.skb[qca->txr.head]) {
  223. pkt_len = qca->txr.skb[qca->txr.head]->len + QCASPI_HW_PKT_LEN;
  224. if (available < pkt_len) {
  225. if (packets == 0)
  226. qca->stats.write_buf_miss++;
  227. break;
  228. }
  229. if (qcaspi_tx_frame(qca, qca->txr.skb[qca->txr.head]) == -1) {
  230. qca->stats.write_err++;
  231. return -1;
  232. }
  233. packets++;
  234. n_stats->tx_packets++;
  235. n_stats->tx_bytes += qca->txr.skb[qca->txr.head]->len;
  236. available -= pkt_len;
  237. /* remove the skb from the queue */
  238. /* XXX After inconsistent lock states netif_tx_lock()
  239. * has been replaced by netif_tx_lock_bh() and so on.
  240. */
  241. netif_tx_lock_bh(qca->net_dev);
  242. dev_kfree_skb(qca->txr.skb[qca->txr.head]);
  243. qca->txr.skb[qca->txr.head] = NULL;
  244. qca->txr.size -= pkt_len;
  245. new_head = qca->txr.head + 1;
  246. if (new_head >= qca->txr.count)
  247. new_head = 0;
  248. qca->txr.head = new_head;
  249. if (netif_queue_stopped(qca->net_dev))
  250. netif_wake_queue(qca->net_dev);
  251. netif_tx_unlock_bh(qca->net_dev);
  252. }
  253. return 0;
  254. }
  255. static int
  256. qcaspi_receive(struct qcaspi *qca)
  257. {
  258. struct net_device *net_dev = qca->net_dev;
  259. struct net_device_stats *n_stats = &net_dev->stats;
  260. u16 available = 0;
  261. u32 bytes_read;
  262. u8 *cp;
  263. /* Allocate rx SKB if we don't have one available. */
  264. if (!qca->rx_skb) {
  265. qca->rx_skb = netdev_alloc_skb_ip_align(net_dev,
  266. net_dev->mtu +
  267. VLAN_ETH_HLEN);
  268. if (!qca->rx_skb) {
  269. netdev_dbg(net_dev, "out of RX resources\n");
  270. qca->stats.out_of_mem++;
  271. return -1;
  272. }
  273. }
  274. /* Read the packet size. */
  275. qcaspi_read_register(qca, SPI_REG_RDBUF_BYTE_AVA, &available);
  276. netdev_dbg(net_dev, "qcaspi_receive: SPI_REG_RDBUF_BYTE_AVA: Value: %08x\n",
  277. available);
  278. if (available == 0) {
  279. netdev_dbg(net_dev, "qcaspi_receive called without any data being available!\n");
  280. return -1;
  281. }
  282. qcaspi_write_register(qca, SPI_REG_BFR_SIZE, available);
  283. if (qca->legacy_mode)
  284. qcaspi_tx_cmd(qca, QCA7K_SPI_READ | QCA7K_SPI_EXTERNAL);
  285. while (available) {
  286. u32 count = available;
  287. if (count > qca->burst_len)
  288. count = qca->burst_len;
  289. if (qca->legacy_mode) {
  290. bytes_read = qcaspi_read_legacy(qca, qca->rx_buffer,
  291. count);
  292. } else {
  293. bytes_read = qcaspi_read_burst(qca, qca->rx_buffer,
  294. count);
  295. }
  296. netdev_dbg(net_dev, "available: %d, byte read: %d\n",
  297. available, bytes_read);
  298. if (bytes_read) {
  299. available -= bytes_read;
  300. } else {
  301. qca->stats.read_err++;
  302. return -1;
  303. }
  304. cp = qca->rx_buffer;
  305. while ((bytes_read--) && (qca->rx_skb)) {
  306. s32 retcode;
  307. retcode = qcafrm_fsm_decode(&qca->frm_handle,
  308. qca->rx_skb->data,
  309. skb_tailroom(qca->rx_skb),
  310. *cp);
  311. cp++;
  312. switch (retcode) {
  313. case QCAFRM_GATHER:
  314. case QCAFRM_NOHEAD:
  315. break;
  316. case QCAFRM_NOTAIL:
  317. netdev_dbg(net_dev, "no RX tail\n");
  318. n_stats->rx_errors++;
  319. n_stats->rx_dropped++;
  320. break;
  321. case QCAFRM_INVLEN:
  322. netdev_dbg(net_dev, "invalid RX length\n");
  323. n_stats->rx_errors++;
  324. n_stats->rx_dropped++;
  325. break;
  326. default:
  327. qca->rx_skb->dev = qca->net_dev;
  328. n_stats->rx_packets++;
  329. n_stats->rx_bytes += retcode;
  330. skb_put(qca->rx_skb, retcode);
  331. qca->rx_skb->protocol = eth_type_trans(
  332. qca->rx_skb, qca->rx_skb->dev);
  333. qca->rx_skb->ip_summed = CHECKSUM_UNNECESSARY;
  334. netif_rx_ni(qca->rx_skb);
  335. qca->rx_skb = netdev_alloc_skb_ip_align(net_dev,
  336. net_dev->mtu + VLAN_ETH_HLEN);
  337. if (!qca->rx_skb) {
  338. netdev_dbg(net_dev, "out of RX resources\n");
  339. n_stats->rx_errors++;
  340. qca->stats.out_of_mem++;
  341. break;
  342. }
  343. }
  344. }
  345. }
  346. return 0;
  347. }
  348. /* Check that tx ring stores only so much bytes
  349. * that fit into the internal QCA buffer.
  350. */
  351. static int
  352. qcaspi_tx_ring_has_space(struct tx_ring *txr)
  353. {
  354. if (txr->skb[txr->tail])
  355. return 0;
  356. return (txr->size + QCAFRM_MAX_LEN < QCASPI_HW_BUF_LEN) ? 1 : 0;
  357. }
  358. /* Flush the tx ring. This function is only safe to
  359. * call from the qcaspi_spi_thread.
  360. */
  361. static void
  362. qcaspi_flush_tx_ring(struct qcaspi *qca)
  363. {
  364. int i;
  365. /* XXX After inconsistent lock states netif_tx_lock()
  366. * has been replaced by netif_tx_lock_bh() and so on.
  367. */
  368. netif_tx_lock_bh(qca->net_dev);
  369. for (i = 0; i < TX_RING_MAX_LEN; i++) {
  370. if (qca->txr.skb[i]) {
  371. dev_kfree_skb(qca->txr.skb[i]);
  372. qca->txr.skb[i] = NULL;
  373. qca->net_dev->stats.tx_dropped++;
  374. }
  375. }
  376. qca->txr.tail = 0;
  377. qca->txr.head = 0;
  378. qca->txr.size = 0;
  379. netif_tx_unlock_bh(qca->net_dev);
  380. }
  381. static void
  382. qcaspi_qca7k_sync(struct qcaspi *qca, int event)
  383. {
  384. u16 signature = 0;
  385. u16 spi_config;
  386. u16 wrbuf_space = 0;
  387. static u16 reset_count;
  388. if (event == QCASPI_EVENT_CPUON) {
  389. /* Read signature twice, if not valid
  390. * go back to unknown state.
  391. */
  392. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  393. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  394. if (signature != QCASPI_GOOD_SIGNATURE) {
  395. qca->sync = QCASPI_SYNC_UNKNOWN;
  396. netdev_dbg(qca->net_dev, "sync: got CPU on, but signature was invalid, restart\n");
  397. } else {
  398. /* ensure that the WRBUF is empty */
  399. qcaspi_read_register(qca, SPI_REG_WRBUF_SPC_AVA,
  400. &wrbuf_space);
  401. if (wrbuf_space != QCASPI_HW_BUF_LEN) {
  402. netdev_dbg(qca->net_dev, "sync: got CPU on, but wrbuf not empty. reset!\n");
  403. qca->sync = QCASPI_SYNC_UNKNOWN;
  404. } else {
  405. netdev_dbg(qca->net_dev, "sync: got CPU on, now in sync\n");
  406. qca->sync = QCASPI_SYNC_READY;
  407. return;
  408. }
  409. }
  410. }
  411. switch (qca->sync) {
  412. case QCASPI_SYNC_READY:
  413. /* Read signature, if not valid go to unknown state. */
  414. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  415. if (signature != QCASPI_GOOD_SIGNATURE) {
  416. qca->sync = QCASPI_SYNC_UNKNOWN;
  417. netdev_dbg(qca->net_dev, "sync: bad signature, restart\n");
  418. /* don't reset right away */
  419. return;
  420. }
  421. break;
  422. case QCASPI_SYNC_UNKNOWN:
  423. /* Read signature, if not valid stay in unknown state */
  424. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  425. if (signature != QCASPI_GOOD_SIGNATURE) {
  426. netdev_dbg(qca->net_dev, "sync: could not read signature to reset device, retry.\n");
  427. return;
  428. }
  429. /* TODO: use GPIO to reset QCA7000 in legacy mode*/
  430. netdev_dbg(qca->net_dev, "sync: resetting device.\n");
  431. qcaspi_read_register(qca, SPI_REG_SPI_CONFIG, &spi_config);
  432. spi_config |= QCASPI_SLAVE_RESET_BIT;
  433. qcaspi_write_register(qca, SPI_REG_SPI_CONFIG, spi_config);
  434. qca->sync = QCASPI_SYNC_RESET;
  435. qca->stats.trig_reset++;
  436. reset_count = 0;
  437. break;
  438. case QCASPI_SYNC_RESET:
  439. reset_count++;
  440. netdev_dbg(qca->net_dev, "sync: waiting for CPU on, count %u.\n",
  441. reset_count);
  442. if (reset_count >= QCASPI_RESET_TIMEOUT) {
  443. /* reset did not seem to take place, try again */
  444. qca->sync = QCASPI_SYNC_UNKNOWN;
  445. qca->stats.reset_timeout++;
  446. netdev_dbg(qca->net_dev, "sync: reset timeout, restarting process.\n");
  447. }
  448. break;
  449. }
  450. }
  451. static int
  452. qcaspi_spi_thread(void *data)
  453. {
  454. struct qcaspi *qca = data;
  455. u16 intr_cause = 0;
  456. netdev_info(qca->net_dev, "SPI thread created\n");
  457. while (!kthread_should_stop()) {
  458. set_current_state(TASK_INTERRUPTIBLE);
  459. if ((qca->intr_req == qca->intr_svc) &&
  460. (qca->txr.skb[qca->txr.head] == NULL) &&
  461. (qca->sync == QCASPI_SYNC_READY))
  462. schedule();
  463. set_current_state(TASK_RUNNING);
  464. netdev_dbg(qca->net_dev, "have work to do. int: %d, tx_skb: %p\n",
  465. qca->intr_req - qca->intr_svc,
  466. qca->txr.skb[qca->txr.head]);
  467. qcaspi_qca7k_sync(qca, QCASPI_EVENT_UPDATE);
  468. if (qca->sync != QCASPI_SYNC_READY) {
  469. netdev_dbg(qca->net_dev, "sync: not ready %u, turn off carrier and flush\n",
  470. (unsigned int)qca->sync);
  471. netif_stop_queue(qca->net_dev);
  472. netif_carrier_off(qca->net_dev);
  473. qcaspi_flush_tx_ring(qca);
  474. msleep(QCASPI_QCA7K_REBOOT_TIME_MS);
  475. }
  476. if (qca->intr_svc != qca->intr_req) {
  477. qca->intr_svc = qca->intr_req;
  478. start_spi_intr_handling(qca, &intr_cause);
  479. if (intr_cause & SPI_INT_CPU_ON) {
  480. qcaspi_qca7k_sync(qca, QCASPI_EVENT_CPUON);
  481. /* not synced. */
  482. if (qca->sync != QCASPI_SYNC_READY)
  483. continue;
  484. qca->stats.device_reset++;
  485. netif_wake_queue(qca->net_dev);
  486. netif_carrier_on(qca->net_dev);
  487. }
  488. if (intr_cause & SPI_INT_RDBUF_ERR) {
  489. /* restart sync */
  490. netdev_dbg(qca->net_dev, "===> rdbuf error!\n");
  491. qca->stats.read_buf_err++;
  492. qca->sync = QCASPI_SYNC_UNKNOWN;
  493. continue;
  494. }
  495. if (intr_cause & SPI_INT_WRBUF_ERR) {
  496. /* restart sync */
  497. netdev_dbg(qca->net_dev, "===> wrbuf error!\n");
  498. qca->stats.write_buf_err++;
  499. qca->sync = QCASPI_SYNC_UNKNOWN;
  500. continue;
  501. }
  502. /* can only handle other interrupts
  503. * if sync has occurred
  504. */
  505. if (qca->sync == QCASPI_SYNC_READY) {
  506. if (intr_cause & SPI_INT_PKT_AVLBL)
  507. qcaspi_receive(qca);
  508. }
  509. end_spi_intr_handling(qca, intr_cause);
  510. }
  511. if (qca->sync == QCASPI_SYNC_READY)
  512. qcaspi_transmit(qca);
  513. }
  514. set_current_state(TASK_RUNNING);
  515. netdev_info(qca->net_dev, "SPI thread exit\n");
  516. return 0;
  517. }
  518. static irqreturn_t
  519. qcaspi_intr_handler(int irq, void *data)
  520. {
  521. struct qcaspi *qca = data;
  522. qca->intr_req++;
  523. if (qca->spi_thread &&
  524. qca->spi_thread->state != TASK_RUNNING)
  525. wake_up_process(qca->spi_thread);
  526. return IRQ_HANDLED;
  527. }
  528. static int
  529. qcaspi_netdev_open(struct net_device *dev)
  530. {
  531. struct qcaspi *qca = netdev_priv(dev);
  532. int ret = 0;
  533. if (!qca)
  534. return -EINVAL;
  535. qca->intr_req = 1;
  536. qca->intr_svc = 0;
  537. qca->sync = QCASPI_SYNC_UNKNOWN;
  538. qcafrm_fsm_init_spi(&qca->frm_handle);
  539. qca->spi_thread = kthread_run((void *)qcaspi_spi_thread,
  540. qca, "%s", dev->name);
  541. if (IS_ERR(qca->spi_thread)) {
  542. netdev_err(dev, "%s: unable to start kernel thread.\n",
  543. QCASPI_DRV_NAME);
  544. return PTR_ERR(qca->spi_thread);
  545. }
  546. ret = request_irq(qca->spi_dev->irq, qcaspi_intr_handler, 0,
  547. dev->name, qca);
  548. if (ret) {
  549. netdev_err(dev, "%s: unable to get IRQ %d (irqval=%d).\n",
  550. QCASPI_DRV_NAME, qca->spi_dev->irq, ret);
  551. kthread_stop(qca->spi_thread);
  552. return ret;
  553. }
  554. netif_start_queue(qca->net_dev);
  555. return 0;
  556. }
  557. static int
  558. qcaspi_netdev_close(struct net_device *dev)
  559. {
  560. struct qcaspi *qca = netdev_priv(dev);
  561. netif_stop_queue(dev);
  562. qcaspi_write_register(qca, SPI_REG_INTR_ENABLE, 0);
  563. free_irq(qca->spi_dev->irq, qca);
  564. kthread_stop(qca->spi_thread);
  565. qca->spi_thread = NULL;
  566. qcaspi_flush_tx_ring(qca);
  567. return 0;
  568. }
  569. static netdev_tx_t
  570. qcaspi_netdev_xmit(struct sk_buff *skb, struct net_device *dev)
  571. {
  572. u32 frame_len;
  573. u8 *ptmp;
  574. struct qcaspi *qca = netdev_priv(dev);
  575. u16 new_tail;
  576. struct sk_buff *tskb;
  577. u8 pad_len = 0;
  578. if (skb->len < QCAFRM_MIN_LEN)
  579. pad_len = QCAFRM_MIN_LEN - skb->len;
  580. if (qca->txr.skb[qca->txr.tail]) {
  581. netdev_warn(qca->net_dev, "queue was unexpectedly full!\n");
  582. netif_stop_queue(qca->net_dev);
  583. qca->stats.ring_full++;
  584. return NETDEV_TX_BUSY;
  585. }
  586. if ((skb_headroom(skb) < QCAFRM_HEADER_LEN) ||
  587. (skb_tailroom(skb) < QCAFRM_FOOTER_LEN + pad_len)) {
  588. tskb = skb_copy_expand(skb, QCAFRM_HEADER_LEN,
  589. QCAFRM_FOOTER_LEN + pad_len, GFP_ATOMIC);
  590. if (!tskb) {
  591. netdev_dbg(qca->net_dev, "could not allocate tx_buff\n");
  592. qca->stats.out_of_mem++;
  593. return NETDEV_TX_BUSY;
  594. }
  595. dev_kfree_skb(skb);
  596. skb = tskb;
  597. }
  598. frame_len = skb->len + pad_len;
  599. ptmp = skb_push(skb, QCAFRM_HEADER_LEN);
  600. qcafrm_create_header(ptmp, frame_len);
  601. if (pad_len) {
  602. ptmp = skb_put_zero(skb, pad_len);
  603. }
  604. ptmp = skb_put(skb, QCAFRM_FOOTER_LEN);
  605. qcafrm_create_footer(ptmp);
  606. netdev_dbg(qca->net_dev, "Tx-ing packet: Size: 0x%08x\n",
  607. skb->len);
  608. qca->txr.size += skb->len + QCASPI_HW_PKT_LEN;
  609. new_tail = qca->txr.tail + 1;
  610. if (new_tail >= qca->txr.count)
  611. new_tail = 0;
  612. qca->txr.skb[qca->txr.tail] = skb;
  613. qca->txr.tail = new_tail;
  614. if (!qcaspi_tx_ring_has_space(&qca->txr)) {
  615. netif_stop_queue(qca->net_dev);
  616. qca->stats.ring_full++;
  617. }
  618. netif_trans_update(dev);
  619. if (qca->spi_thread &&
  620. qca->spi_thread->state != TASK_RUNNING)
  621. wake_up_process(qca->spi_thread);
  622. return NETDEV_TX_OK;
  623. }
  624. static void
  625. qcaspi_netdev_tx_timeout(struct net_device *dev)
  626. {
  627. struct qcaspi *qca = netdev_priv(dev);
  628. netdev_info(qca->net_dev, "Transmit timeout at %ld, latency %ld\n",
  629. jiffies, jiffies - dev_trans_start(dev));
  630. qca->net_dev->stats.tx_errors++;
  631. /* Trigger tx queue flush and QCA7000 reset */
  632. qca->sync = QCASPI_SYNC_UNKNOWN;
  633. }
  634. static int
  635. qcaspi_netdev_init(struct net_device *dev)
  636. {
  637. struct qcaspi *qca = netdev_priv(dev);
  638. dev->mtu = QCAFRM_MAX_MTU;
  639. dev->type = ARPHRD_ETHER;
  640. qca->clkspeed = qcaspi_clkspeed;
  641. qca->burst_len = qcaspi_burst_len;
  642. qca->spi_thread = NULL;
  643. qca->buffer_size = (dev->mtu + VLAN_ETH_HLEN + QCAFRM_HEADER_LEN +
  644. QCAFRM_FOOTER_LEN + 4) * 4;
  645. memset(&qca->stats, 0, sizeof(struct qcaspi_stats));
  646. qca->rx_buffer = kmalloc(qca->buffer_size, GFP_KERNEL);
  647. if (!qca->rx_buffer)
  648. return -ENOBUFS;
  649. qca->rx_skb = netdev_alloc_skb_ip_align(dev, qca->net_dev->mtu +
  650. VLAN_ETH_HLEN);
  651. if (!qca->rx_skb) {
  652. kfree(qca->rx_buffer);
  653. netdev_info(qca->net_dev, "Failed to allocate RX sk_buff.\n");
  654. return -ENOBUFS;
  655. }
  656. return 0;
  657. }
  658. static void
  659. qcaspi_netdev_uninit(struct net_device *dev)
  660. {
  661. struct qcaspi *qca = netdev_priv(dev);
  662. kfree(qca->rx_buffer);
  663. qca->buffer_size = 0;
  664. if (qca->rx_skb)
  665. dev_kfree_skb(qca->rx_skb);
  666. }
  667. static const struct net_device_ops qcaspi_netdev_ops = {
  668. .ndo_init = qcaspi_netdev_init,
  669. .ndo_uninit = qcaspi_netdev_uninit,
  670. .ndo_open = qcaspi_netdev_open,
  671. .ndo_stop = qcaspi_netdev_close,
  672. .ndo_start_xmit = qcaspi_netdev_xmit,
  673. .ndo_set_mac_address = eth_mac_addr,
  674. .ndo_tx_timeout = qcaspi_netdev_tx_timeout,
  675. .ndo_validate_addr = eth_validate_addr,
  676. };
  677. static void
  678. qcaspi_netdev_setup(struct net_device *dev)
  679. {
  680. struct qcaspi *qca = NULL;
  681. dev->netdev_ops = &qcaspi_netdev_ops;
  682. qcaspi_set_ethtool_ops(dev);
  683. dev->watchdog_timeo = QCASPI_TX_TIMEOUT;
  684. dev->priv_flags &= ~IFF_TX_SKB_SHARING;
  685. dev->tx_queue_len = 100;
  686. /* MTU range: 46 - 1500 */
  687. dev->min_mtu = QCAFRM_MIN_MTU;
  688. dev->max_mtu = QCAFRM_MAX_MTU;
  689. qca = netdev_priv(dev);
  690. memset(qca, 0, sizeof(struct qcaspi));
  691. memset(&qca->spi_xfer1, 0, sizeof(struct spi_transfer));
  692. memset(&qca->spi_xfer2, 0, sizeof(struct spi_transfer) * 2);
  693. spi_message_init(&qca->spi_msg1);
  694. spi_message_add_tail(&qca->spi_xfer1, &qca->spi_msg1);
  695. spi_message_init(&qca->spi_msg2);
  696. spi_message_add_tail(&qca->spi_xfer2[0], &qca->spi_msg2);
  697. spi_message_add_tail(&qca->spi_xfer2[1], &qca->spi_msg2);
  698. memset(&qca->txr, 0, sizeof(qca->txr));
  699. qca->txr.count = TX_RING_MAX_LEN;
  700. }
  701. static const struct of_device_id qca_spi_of_match[] = {
  702. { .compatible = "qca,qca7000" },
  703. { /* sentinel */ }
  704. };
  705. MODULE_DEVICE_TABLE(of, qca_spi_of_match);
  706. static int
  707. qca_spi_probe(struct spi_device *spi)
  708. {
  709. struct qcaspi *qca = NULL;
  710. struct net_device *qcaspi_devs = NULL;
  711. u8 legacy_mode = 0;
  712. u16 signature;
  713. const char *mac;
  714. if (!spi->dev.of_node) {
  715. dev_err(&spi->dev, "Missing device tree\n");
  716. return -EINVAL;
  717. }
  718. legacy_mode = of_property_read_bool(spi->dev.of_node,
  719. "qca,legacy-mode");
  720. if (qcaspi_clkspeed == 0) {
  721. if (spi->max_speed_hz)
  722. qcaspi_clkspeed = spi->max_speed_hz;
  723. else
  724. qcaspi_clkspeed = QCASPI_CLK_SPEED;
  725. }
  726. if ((qcaspi_clkspeed < QCASPI_CLK_SPEED_MIN) ||
  727. (qcaspi_clkspeed > QCASPI_CLK_SPEED_MAX)) {
  728. dev_info(&spi->dev, "Invalid clkspeed: %d\n",
  729. qcaspi_clkspeed);
  730. return -EINVAL;
  731. }
  732. if ((qcaspi_burst_len < QCASPI_BURST_LEN_MIN) ||
  733. (qcaspi_burst_len > QCASPI_BURST_LEN_MAX)) {
  734. dev_info(&spi->dev, "Invalid burst len: %d\n",
  735. qcaspi_burst_len);
  736. return -EINVAL;
  737. }
  738. if ((qcaspi_pluggable < QCASPI_PLUGGABLE_MIN) ||
  739. (qcaspi_pluggable > QCASPI_PLUGGABLE_MAX)) {
  740. dev_info(&spi->dev, "Invalid pluggable: %d\n",
  741. qcaspi_pluggable);
  742. return -EINVAL;
  743. }
  744. dev_info(&spi->dev, "ver=%s, clkspeed=%d, burst_len=%d, pluggable=%d\n",
  745. QCASPI_DRV_VERSION,
  746. qcaspi_clkspeed,
  747. qcaspi_burst_len,
  748. qcaspi_pluggable);
  749. spi->mode = SPI_MODE_3;
  750. spi->max_speed_hz = qcaspi_clkspeed;
  751. if (spi_setup(spi) < 0) {
  752. dev_err(&spi->dev, "Unable to setup SPI device\n");
  753. return -EFAULT;
  754. }
  755. qcaspi_devs = alloc_etherdev(sizeof(struct qcaspi));
  756. if (!qcaspi_devs)
  757. return -ENOMEM;
  758. qcaspi_netdev_setup(qcaspi_devs);
  759. SET_NETDEV_DEV(qcaspi_devs, &spi->dev);
  760. qca = netdev_priv(qcaspi_devs);
  761. if (!qca) {
  762. free_netdev(qcaspi_devs);
  763. dev_err(&spi->dev, "Fail to retrieve private structure\n");
  764. return -ENOMEM;
  765. }
  766. qca->net_dev = qcaspi_devs;
  767. qca->spi_dev = spi;
  768. qca->legacy_mode = legacy_mode;
  769. spi_set_drvdata(spi, qcaspi_devs);
  770. mac = of_get_mac_address(spi->dev.of_node);
  771. if (mac)
  772. ether_addr_copy(qca->net_dev->dev_addr, mac);
  773. if (!is_valid_ether_addr(qca->net_dev->dev_addr)) {
  774. eth_hw_addr_random(qca->net_dev);
  775. dev_info(&spi->dev, "Using random MAC address: %pM\n",
  776. qca->net_dev->dev_addr);
  777. }
  778. netif_carrier_off(qca->net_dev);
  779. if (!qcaspi_pluggable) {
  780. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  781. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  782. if (signature != QCASPI_GOOD_SIGNATURE) {
  783. dev_err(&spi->dev, "Invalid signature (0x%04X)\n",
  784. signature);
  785. free_netdev(qcaspi_devs);
  786. return -EFAULT;
  787. }
  788. }
  789. if (register_netdev(qcaspi_devs)) {
  790. dev_info(&spi->dev, "Unable to register net device %s\n",
  791. qcaspi_devs->name);
  792. free_netdev(qcaspi_devs);
  793. return -EFAULT;
  794. }
  795. qcaspi_init_device_debugfs(qca);
  796. return 0;
  797. }
  798. static int
  799. qca_spi_remove(struct spi_device *spi)
  800. {
  801. struct net_device *qcaspi_devs = spi_get_drvdata(spi);
  802. struct qcaspi *qca = netdev_priv(qcaspi_devs);
  803. qcaspi_remove_device_debugfs(qca);
  804. unregister_netdev(qcaspi_devs);
  805. free_netdev(qcaspi_devs);
  806. return 0;
  807. }
  808. static const struct spi_device_id qca_spi_id[] = {
  809. { "qca7000", 0 },
  810. { /* sentinel */ }
  811. };
  812. MODULE_DEVICE_TABLE(spi, qca_spi_id);
  813. static struct spi_driver qca_spi_driver = {
  814. .driver = {
  815. .name = QCASPI_DRV_NAME,
  816. .of_match_table = qca_spi_of_match,
  817. },
  818. .id_table = qca_spi_id,
  819. .probe = qca_spi_probe,
  820. .remove = qca_spi_remove,
  821. };
  822. module_spi_driver(qca_spi_driver);
  823. MODULE_DESCRIPTION("Qualcomm Atheros QCA7000 SPI Driver");
  824. MODULE_AUTHOR("Qualcomm Atheros Communications");
  825. MODULE_AUTHOR("Stefan Wahren <stefan.wahren@i2se.com>");
  826. MODULE_LICENSE("Dual BSD/GPL");
  827. MODULE_VERSION(QCASPI_DRV_VERSION);