emac.c 19 KB

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  1. /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. /* Qualcomm Technologies, Inc. EMAC Gigabit Ethernet Driver */
  13. #include <linux/if_ether.h>
  14. #include <linux/if_vlan.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/io.h>
  17. #include <linux/module.h>
  18. #include <linux/of.h>
  19. #include <linux/of_net.h>
  20. #include <linux/of_device.h>
  21. #include <linux/phy.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/acpi.h>
  24. #include "emac.h"
  25. #include "emac-mac.h"
  26. #include "emac-phy.h"
  27. #include "emac-sgmii.h"
  28. #define EMAC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
  29. NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
  30. #define EMAC_RRD_SIZE 4
  31. /* The RRD size if timestamping is enabled: */
  32. #define EMAC_TS_RRD_SIZE 6
  33. #define EMAC_TPD_SIZE 4
  34. #define EMAC_RFD_SIZE 2
  35. #define REG_MAC_RX_STATUS_BIN EMAC_RXMAC_STATC_REG0
  36. #define REG_MAC_RX_STATUS_END EMAC_RXMAC_STATC_REG22
  37. #define REG_MAC_TX_STATUS_BIN EMAC_TXMAC_STATC_REG0
  38. #define REG_MAC_TX_STATUS_END EMAC_TXMAC_STATC_REG24
  39. #define RXQ0_NUM_RFD_PREF_DEF 8
  40. #define TXQ0_NUM_TPD_PREF_DEF 5
  41. #define EMAC_PREAMBLE_DEF 7
  42. #define DMAR_DLY_CNT_DEF 15
  43. #define DMAW_DLY_CNT_DEF 4
  44. #define IMR_NORMAL_MASK (ISR_ERROR | ISR_OVER | ISR_TX_PKT)
  45. #define ISR_TX_PKT (\
  46. TX_PKT_INT |\
  47. TX_PKT_INT1 |\
  48. TX_PKT_INT2 |\
  49. TX_PKT_INT3)
  50. #define ISR_OVER (\
  51. RFD0_UR_INT |\
  52. RFD1_UR_INT |\
  53. RFD2_UR_INT |\
  54. RFD3_UR_INT |\
  55. RFD4_UR_INT |\
  56. RXF_OF_INT |\
  57. TXF_UR_INT)
  58. #define ISR_ERROR (\
  59. DMAR_TO_INT |\
  60. DMAW_TO_INT |\
  61. TXQ_TO_INT)
  62. /* in sync with enum emac_clk_id */
  63. static const char * const emac_clk_name[] = {
  64. "axi_clk", "cfg_ahb_clk", "high_speed_clk", "mdio_clk", "tx_clk",
  65. "rx_clk", "sys_clk"
  66. };
  67. void emac_reg_update32(void __iomem *addr, u32 mask, u32 val)
  68. {
  69. u32 data = readl(addr);
  70. writel(((data & ~mask) | val), addr);
  71. }
  72. /* reinitialize */
  73. int emac_reinit_locked(struct emac_adapter *adpt)
  74. {
  75. int ret;
  76. mutex_lock(&adpt->reset_lock);
  77. emac_mac_down(adpt);
  78. emac_sgmii_reset(adpt);
  79. ret = emac_mac_up(adpt);
  80. mutex_unlock(&adpt->reset_lock);
  81. return ret;
  82. }
  83. /* NAPI */
  84. static int emac_napi_rtx(struct napi_struct *napi, int budget)
  85. {
  86. struct emac_rx_queue *rx_q =
  87. container_of(napi, struct emac_rx_queue, napi);
  88. struct emac_adapter *adpt = netdev_priv(rx_q->netdev);
  89. struct emac_irq *irq = rx_q->irq;
  90. int work_done = 0;
  91. emac_mac_rx_process(adpt, rx_q, &work_done, budget);
  92. if (work_done < budget) {
  93. napi_complete_done(napi, work_done);
  94. irq->mask |= rx_q->intr;
  95. writel(irq->mask, adpt->base + EMAC_INT_MASK);
  96. }
  97. return work_done;
  98. }
  99. /* Transmit the packet */
  100. static int emac_start_xmit(struct sk_buff *skb, struct net_device *netdev)
  101. {
  102. struct emac_adapter *adpt = netdev_priv(netdev);
  103. return emac_mac_tx_buf_send(adpt, &adpt->tx_q, skb);
  104. }
  105. irqreturn_t emac_isr(int _irq, void *data)
  106. {
  107. struct emac_irq *irq = data;
  108. struct emac_adapter *adpt =
  109. container_of(irq, struct emac_adapter, irq);
  110. struct emac_rx_queue *rx_q = &adpt->rx_q;
  111. u32 isr, status;
  112. /* disable the interrupt */
  113. writel(0, adpt->base + EMAC_INT_MASK);
  114. isr = readl_relaxed(adpt->base + EMAC_INT_STATUS);
  115. status = isr & irq->mask;
  116. if (status == 0)
  117. goto exit;
  118. if (status & ISR_ERROR) {
  119. netif_warn(adpt, intr, adpt->netdev,
  120. "warning: error irq status 0x%lx\n",
  121. status & ISR_ERROR);
  122. /* reset MAC */
  123. schedule_work(&adpt->work_thread);
  124. }
  125. /* Schedule the napi for receive queue with interrupt
  126. * status bit set
  127. */
  128. if (status & rx_q->intr) {
  129. if (napi_schedule_prep(&rx_q->napi)) {
  130. irq->mask &= ~rx_q->intr;
  131. __napi_schedule(&rx_q->napi);
  132. }
  133. }
  134. if (status & TX_PKT_INT)
  135. emac_mac_tx_process(adpt, &adpt->tx_q);
  136. if (status & ISR_OVER)
  137. net_warn_ratelimited("warning: TX/RX overflow\n");
  138. exit:
  139. /* enable the interrupt */
  140. writel(irq->mask, adpt->base + EMAC_INT_MASK);
  141. return IRQ_HANDLED;
  142. }
  143. /* Configure VLAN tag strip/insert feature */
  144. static int emac_set_features(struct net_device *netdev,
  145. netdev_features_t features)
  146. {
  147. netdev_features_t changed = features ^ netdev->features;
  148. struct emac_adapter *adpt = netdev_priv(netdev);
  149. /* We only need to reprogram the hardware if the VLAN tag features
  150. * have changed, and if it's already running.
  151. */
  152. if (!(changed & (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX)))
  153. return 0;
  154. if (!netif_running(netdev))
  155. return 0;
  156. /* emac_mac_mode_config() uses netdev->features to configure the EMAC,
  157. * so make sure it's set first.
  158. */
  159. netdev->features = features;
  160. return emac_reinit_locked(adpt);
  161. }
  162. /* Configure Multicast and Promiscuous modes */
  163. static void emac_rx_mode_set(struct net_device *netdev)
  164. {
  165. struct emac_adapter *adpt = netdev_priv(netdev);
  166. struct netdev_hw_addr *ha;
  167. emac_mac_mode_config(adpt);
  168. /* update multicast address filtering */
  169. emac_mac_multicast_addr_clear(adpt);
  170. netdev_for_each_mc_addr(ha, netdev)
  171. emac_mac_multicast_addr_set(adpt, ha->addr);
  172. }
  173. /* Change the Maximum Transfer Unit (MTU) */
  174. static int emac_change_mtu(struct net_device *netdev, int new_mtu)
  175. {
  176. struct emac_adapter *adpt = netdev_priv(netdev);
  177. netif_info(adpt, hw, adpt->netdev,
  178. "changing MTU from %d to %d\n", netdev->mtu,
  179. new_mtu);
  180. netdev->mtu = new_mtu;
  181. if (netif_running(netdev))
  182. return emac_reinit_locked(adpt);
  183. return 0;
  184. }
  185. /* Called when the network interface is made active */
  186. static int emac_open(struct net_device *netdev)
  187. {
  188. struct emac_adapter *adpt = netdev_priv(netdev);
  189. struct emac_irq *irq = &adpt->irq;
  190. int ret;
  191. ret = request_irq(irq->irq, emac_isr, 0, "emac-core0", irq);
  192. if (ret) {
  193. netdev_err(adpt->netdev, "could not request emac-core0 irq\n");
  194. return ret;
  195. }
  196. /* allocate rx/tx dma buffer & descriptors */
  197. ret = emac_mac_rx_tx_rings_alloc_all(adpt);
  198. if (ret) {
  199. netdev_err(adpt->netdev, "error allocating rx/tx rings\n");
  200. free_irq(irq->irq, irq);
  201. return ret;
  202. }
  203. ret = emac_mac_up(adpt);
  204. if (ret) {
  205. emac_mac_rx_tx_rings_free_all(adpt);
  206. free_irq(irq->irq, irq);
  207. return ret;
  208. }
  209. ret = adpt->phy.open(adpt);
  210. if (ret) {
  211. emac_mac_down(adpt);
  212. emac_mac_rx_tx_rings_free_all(adpt);
  213. free_irq(irq->irq, irq);
  214. return ret;
  215. }
  216. return 0;
  217. }
  218. /* Called when the network interface is disabled */
  219. static int emac_close(struct net_device *netdev)
  220. {
  221. struct emac_adapter *adpt = netdev_priv(netdev);
  222. mutex_lock(&adpt->reset_lock);
  223. adpt->phy.close(adpt);
  224. emac_mac_down(adpt);
  225. emac_mac_rx_tx_rings_free_all(adpt);
  226. free_irq(adpt->irq.irq, &adpt->irq);
  227. mutex_unlock(&adpt->reset_lock);
  228. return 0;
  229. }
  230. /* Respond to a TX hang */
  231. static void emac_tx_timeout(struct net_device *netdev)
  232. {
  233. struct emac_adapter *adpt = netdev_priv(netdev);
  234. schedule_work(&adpt->work_thread);
  235. }
  236. /* IOCTL support for the interface */
  237. static int emac_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
  238. {
  239. if (!netif_running(netdev))
  240. return -EINVAL;
  241. if (!netdev->phydev)
  242. return -ENODEV;
  243. return phy_mii_ioctl(netdev->phydev, ifr, cmd);
  244. }
  245. /**
  246. * emac_update_hw_stats - read the EMAC stat registers
  247. *
  248. * Reads the stats registers and write the values to adpt->stats.
  249. *
  250. * adpt->stats.lock must be held while calling this function,
  251. * and while reading from adpt->stats.
  252. */
  253. void emac_update_hw_stats(struct emac_adapter *adpt)
  254. {
  255. struct emac_stats *stats = &adpt->stats;
  256. u64 *stats_itr = &adpt->stats.rx_ok;
  257. void __iomem *base = adpt->base;
  258. unsigned int addr;
  259. addr = REG_MAC_RX_STATUS_BIN;
  260. while (addr <= REG_MAC_RX_STATUS_END) {
  261. *stats_itr += readl_relaxed(base + addr);
  262. stats_itr++;
  263. addr += sizeof(u32);
  264. }
  265. /* additional rx status */
  266. stats->rx_crc_align += readl_relaxed(base + EMAC_RXMAC_STATC_REG23);
  267. stats->rx_jabbers += readl_relaxed(base + EMAC_RXMAC_STATC_REG24);
  268. /* update tx status */
  269. addr = REG_MAC_TX_STATUS_BIN;
  270. stats_itr = &stats->tx_ok;
  271. while (addr <= REG_MAC_TX_STATUS_END) {
  272. *stats_itr += readl_relaxed(base + addr);
  273. stats_itr++;
  274. addr += sizeof(u32);
  275. }
  276. /* additional tx status */
  277. stats->tx_col += readl_relaxed(base + EMAC_TXMAC_STATC_REG25);
  278. }
  279. /* Provide network statistics info for the interface */
  280. static void emac_get_stats64(struct net_device *netdev,
  281. struct rtnl_link_stats64 *net_stats)
  282. {
  283. struct emac_adapter *adpt = netdev_priv(netdev);
  284. struct emac_stats *stats = &adpt->stats;
  285. spin_lock(&stats->lock);
  286. emac_update_hw_stats(adpt);
  287. /* return parsed statistics */
  288. net_stats->rx_packets = stats->rx_ok;
  289. net_stats->tx_packets = stats->tx_ok;
  290. net_stats->rx_bytes = stats->rx_byte_cnt;
  291. net_stats->tx_bytes = stats->tx_byte_cnt;
  292. net_stats->multicast = stats->rx_mcast;
  293. net_stats->collisions = stats->tx_1_col + stats->tx_2_col * 2 +
  294. stats->tx_late_col + stats->tx_abort_col;
  295. net_stats->rx_errors = stats->rx_frag + stats->rx_fcs_err +
  296. stats->rx_len_err + stats->rx_sz_ov +
  297. stats->rx_align_err;
  298. net_stats->rx_fifo_errors = stats->rx_rxf_ov;
  299. net_stats->rx_length_errors = stats->rx_len_err;
  300. net_stats->rx_crc_errors = stats->rx_fcs_err;
  301. net_stats->rx_frame_errors = stats->rx_align_err;
  302. net_stats->rx_over_errors = stats->rx_rxf_ov;
  303. net_stats->rx_missed_errors = stats->rx_rxf_ov;
  304. net_stats->tx_errors = stats->tx_late_col + stats->tx_abort_col +
  305. stats->tx_underrun + stats->tx_trunc;
  306. net_stats->tx_fifo_errors = stats->tx_underrun;
  307. net_stats->tx_aborted_errors = stats->tx_abort_col;
  308. net_stats->tx_window_errors = stats->tx_late_col;
  309. spin_unlock(&stats->lock);
  310. }
  311. static const struct net_device_ops emac_netdev_ops = {
  312. .ndo_open = emac_open,
  313. .ndo_stop = emac_close,
  314. .ndo_validate_addr = eth_validate_addr,
  315. .ndo_start_xmit = emac_start_xmit,
  316. .ndo_set_mac_address = eth_mac_addr,
  317. .ndo_change_mtu = emac_change_mtu,
  318. .ndo_do_ioctl = emac_ioctl,
  319. .ndo_tx_timeout = emac_tx_timeout,
  320. .ndo_get_stats64 = emac_get_stats64,
  321. .ndo_set_features = emac_set_features,
  322. .ndo_set_rx_mode = emac_rx_mode_set,
  323. };
  324. /* Watchdog task routine, called to reinitialize the EMAC */
  325. static void emac_work_thread(struct work_struct *work)
  326. {
  327. struct emac_adapter *adpt =
  328. container_of(work, struct emac_adapter, work_thread);
  329. emac_reinit_locked(adpt);
  330. }
  331. /* Initialize various data structures */
  332. static void emac_init_adapter(struct emac_adapter *adpt)
  333. {
  334. u32 reg;
  335. adpt->rrd_size = EMAC_RRD_SIZE;
  336. adpt->tpd_size = EMAC_TPD_SIZE;
  337. adpt->rfd_size = EMAC_RFD_SIZE;
  338. /* descriptors */
  339. adpt->tx_desc_cnt = EMAC_DEF_TX_DESCS;
  340. adpt->rx_desc_cnt = EMAC_DEF_RX_DESCS;
  341. /* dma */
  342. adpt->dma_order = emac_dma_ord_out;
  343. adpt->dmar_block = emac_dma_req_4096;
  344. adpt->dmaw_block = emac_dma_req_128;
  345. adpt->dmar_dly_cnt = DMAR_DLY_CNT_DEF;
  346. adpt->dmaw_dly_cnt = DMAW_DLY_CNT_DEF;
  347. adpt->tpd_burst = TXQ0_NUM_TPD_PREF_DEF;
  348. adpt->rfd_burst = RXQ0_NUM_RFD_PREF_DEF;
  349. /* irq moderator */
  350. reg = ((EMAC_DEF_RX_IRQ_MOD >> 1) << IRQ_MODERATOR2_INIT_SHFT) |
  351. ((EMAC_DEF_TX_IRQ_MOD >> 1) << IRQ_MODERATOR_INIT_SHFT);
  352. adpt->irq_mod = reg;
  353. /* others */
  354. adpt->preamble = EMAC_PREAMBLE_DEF;
  355. /* default to automatic flow control */
  356. adpt->automatic = true;
  357. /* Disable single-pause-frame mode by default */
  358. adpt->single_pause_mode = false;
  359. }
  360. /* Get the clock */
  361. static int emac_clks_get(struct platform_device *pdev,
  362. struct emac_adapter *adpt)
  363. {
  364. unsigned int i;
  365. for (i = 0; i < EMAC_CLK_CNT; i++) {
  366. struct clk *clk = devm_clk_get(&pdev->dev, emac_clk_name[i]);
  367. if (IS_ERR(clk)) {
  368. dev_err(&pdev->dev,
  369. "could not claim clock %s (error=%li)\n",
  370. emac_clk_name[i], PTR_ERR(clk));
  371. return PTR_ERR(clk);
  372. }
  373. adpt->clk[i] = clk;
  374. }
  375. return 0;
  376. }
  377. /* Initialize clocks */
  378. static int emac_clks_phase1_init(struct platform_device *pdev,
  379. struct emac_adapter *adpt)
  380. {
  381. int ret;
  382. /* On ACPI platforms, clocks are controlled by firmware and/or
  383. * ACPI, not by drivers.
  384. */
  385. if (has_acpi_companion(&pdev->dev))
  386. return 0;
  387. ret = emac_clks_get(pdev, adpt);
  388. if (ret)
  389. return ret;
  390. ret = clk_prepare_enable(adpt->clk[EMAC_CLK_AXI]);
  391. if (ret)
  392. return ret;
  393. ret = clk_prepare_enable(adpt->clk[EMAC_CLK_CFG_AHB]);
  394. if (ret)
  395. return ret;
  396. ret = clk_set_rate(adpt->clk[EMAC_CLK_HIGH_SPEED], 19200000);
  397. if (ret)
  398. return ret;
  399. return clk_prepare_enable(adpt->clk[EMAC_CLK_HIGH_SPEED]);
  400. }
  401. /* Enable clocks; needs emac_clks_phase1_init to be called before */
  402. static int emac_clks_phase2_init(struct platform_device *pdev,
  403. struct emac_adapter *adpt)
  404. {
  405. int ret;
  406. if (has_acpi_companion(&pdev->dev))
  407. return 0;
  408. ret = clk_set_rate(adpt->clk[EMAC_CLK_TX], 125000000);
  409. if (ret)
  410. return ret;
  411. ret = clk_prepare_enable(adpt->clk[EMAC_CLK_TX]);
  412. if (ret)
  413. return ret;
  414. ret = clk_set_rate(adpt->clk[EMAC_CLK_HIGH_SPEED], 125000000);
  415. if (ret)
  416. return ret;
  417. ret = clk_set_rate(adpt->clk[EMAC_CLK_MDIO], 25000000);
  418. if (ret)
  419. return ret;
  420. ret = clk_prepare_enable(adpt->clk[EMAC_CLK_MDIO]);
  421. if (ret)
  422. return ret;
  423. ret = clk_prepare_enable(adpt->clk[EMAC_CLK_RX]);
  424. if (ret)
  425. return ret;
  426. return clk_prepare_enable(adpt->clk[EMAC_CLK_SYS]);
  427. }
  428. static void emac_clks_teardown(struct emac_adapter *adpt)
  429. {
  430. unsigned int i;
  431. for (i = 0; i < EMAC_CLK_CNT; i++)
  432. clk_disable_unprepare(adpt->clk[i]);
  433. }
  434. /* Get the resources */
  435. static int emac_probe_resources(struct platform_device *pdev,
  436. struct emac_adapter *adpt)
  437. {
  438. struct net_device *netdev = adpt->netdev;
  439. struct resource *res;
  440. char maddr[ETH_ALEN];
  441. int ret = 0;
  442. /* get mac address */
  443. if (device_get_mac_address(&pdev->dev, maddr, ETH_ALEN))
  444. ether_addr_copy(netdev->dev_addr, maddr);
  445. else
  446. eth_hw_addr_random(netdev);
  447. /* Core 0 interrupt */
  448. ret = platform_get_irq(pdev, 0);
  449. if (ret < 0) {
  450. dev_err(&pdev->dev,
  451. "error: missing core0 irq resource (error=%i)\n", ret);
  452. return ret;
  453. }
  454. adpt->irq.irq = ret;
  455. /* base register address */
  456. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  457. adpt->base = devm_ioremap_resource(&pdev->dev, res);
  458. if (IS_ERR(adpt->base))
  459. return PTR_ERR(adpt->base);
  460. /* CSR register address */
  461. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  462. adpt->csr = devm_ioremap_resource(&pdev->dev, res);
  463. if (IS_ERR(adpt->csr))
  464. return PTR_ERR(adpt->csr);
  465. netdev->base_addr = (unsigned long)adpt->base;
  466. return 0;
  467. }
  468. static const struct of_device_id emac_dt_match[] = {
  469. {
  470. .compatible = "qcom,fsm9900-emac",
  471. },
  472. {}
  473. };
  474. MODULE_DEVICE_TABLE(of, emac_dt_match);
  475. #if IS_ENABLED(CONFIG_ACPI)
  476. static const struct acpi_device_id emac_acpi_match[] = {
  477. {
  478. .id = "QCOM8070",
  479. },
  480. {}
  481. };
  482. MODULE_DEVICE_TABLE(acpi, emac_acpi_match);
  483. #endif
  484. static int emac_probe(struct platform_device *pdev)
  485. {
  486. struct net_device *netdev;
  487. struct emac_adapter *adpt;
  488. struct emac_sgmii *phy;
  489. u16 devid, revid;
  490. u32 reg;
  491. int ret;
  492. /* The EMAC itself is capable of 64-bit DMA, so try that first. */
  493. ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
  494. if (ret) {
  495. /* Some platforms may restrict the EMAC's address bus to less
  496. * then the size of DDR. In this case, we need to try a
  497. * smaller mask. We could try every possible smaller mask,
  498. * but that's overkill. Instead, just fall to 32-bit, which
  499. * should always work.
  500. */
  501. ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
  502. if (ret) {
  503. dev_err(&pdev->dev, "could not set DMA mask\n");
  504. return ret;
  505. }
  506. }
  507. netdev = alloc_etherdev(sizeof(struct emac_adapter));
  508. if (!netdev)
  509. return -ENOMEM;
  510. dev_set_drvdata(&pdev->dev, netdev);
  511. SET_NETDEV_DEV(netdev, &pdev->dev);
  512. emac_set_ethtool_ops(netdev);
  513. adpt = netdev_priv(netdev);
  514. adpt->netdev = netdev;
  515. adpt->msg_enable = EMAC_MSG_DEFAULT;
  516. phy = &adpt->phy;
  517. atomic_set(&phy->decode_error_count, 0);
  518. mutex_init(&adpt->reset_lock);
  519. spin_lock_init(&adpt->stats.lock);
  520. adpt->irq.mask = RX_PKT_INT0 | IMR_NORMAL_MASK;
  521. ret = emac_probe_resources(pdev, adpt);
  522. if (ret)
  523. goto err_undo_netdev;
  524. /* initialize clocks */
  525. ret = emac_clks_phase1_init(pdev, adpt);
  526. if (ret) {
  527. dev_err(&pdev->dev, "could not initialize clocks\n");
  528. goto err_undo_netdev;
  529. }
  530. netdev->watchdog_timeo = EMAC_WATCHDOG_TIME;
  531. netdev->irq = adpt->irq.irq;
  532. netdev->netdev_ops = &emac_netdev_ops;
  533. emac_init_adapter(adpt);
  534. /* init external phy */
  535. ret = emac_phy_config(pdev, adpt);
  536. if (ret)
  537. goto err_undo_clocks;
  538. /* init internal sgmii phy */
  539. ret = emac_sgmii_config(pdev, adpt);
  540. if (ret)
  541. goto err_undo_mdiobus;
  542. /* enable clocks */
  543. ret = emac_clks_phase2_init(pdev, adpt);
  544. if (ret) {
  545. dev_err(&pdev->dev, "could not initialize clocks\n");
  546. goto err_undo_mdiobus;
  547. }
  548. /* set hw features */
  549. netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_RXCSUM |
  550. NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
  551. NETIF_F_HW_VLAN_CTAG_TX;
  552. netdev->hw_features = netdev->features;
  553. netdev->vlan_features |= NETIF_F_SG | NETIF_F_HW_CSUM |
  554. NETIF_F_TSO | NETIF_F_TSO6;
  555. /* MTU range: 46 - 9194 */
  556. netdev->min_mtu = EMAC_MIN_ETH_FRAME_SIZE -
  557. (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
  558. netdev->max_mtu = EMAC_MAX_ETH_FRAME_SIZE -
  559. (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
  560. INIT_WORK(&adpt->work_thread, emac_work_thread);
  561. /* Initialize queues */
  562. emac_mac_rx_tx_ring_init_all(pdev, adpt);
  563. netif_napi_add(netdev, &adpt->rx_q.napi, emac_napi_rtx,
  564. NAPI_POLL_WEIGHT);
  565. ret = register_netdev(netdev);
  566. if (ret) {
  567. dev_err(&pdev->dev, "could not register net device\n");
  568. goto err_undo_napi;
  569. }
  570. reg = readl_relaxed(adpt->base + EMAC_DMA_MAS_CTRL);
  571. devid = (reg & DEV_ID_NUM_BMSK) >> DEV_ID_NUM_SHFT;
  572. revid = (reg & DEV_REV_NUM_BMSK) >> DEV_REV_NUM_SHFT;
  573. reg = readl_relaxed(adpt->base + EMAC_CORE_HW_VERSION);
  574. netif_info(adpt, probe, netdev,
  575. "hardware id %d.%d, hardware version %d.%d.%d\n",
  576. devid, revid,
  577. (reg & MAJOR_BMSK) >> MAJOR_SHFT,
  578. (reg & MINOR_BMSK) >> MINOR_SHFT,
  579. (reg & STEP_BMSK) >> STEP_SHFT);
  580. return 0;
  581. err_undo_napi:
  582. netif_napi_del(&adpt->rx_q.napi);
  583. err_undo_mdiobus:
  584. put_device(&adpt->phydev->mdio.dev);
  585. mdiobus_unregister(adpt->mii_bus);
  586. err_undo_clocks:
  587. emac_clks_teardown(adpt);
  588. err_undo_netdev:
  589. free_netdev(netdev);
  590. return ret;
  591. }
  592. static int emac_remove(struct platform_device *pdev)
  593. {
  594. struct net_device *netdev = dev_get_drvdata(&pdev->dev);
  595. struct emac_adapter *adpt = netdev_priv(netdev);
  596. unregister_netdev(netdev);
  597. netif_napi_del(&adpt->rx_q.napi);
  598. emac_clks_teardown(adpt);
  599. put_device(&adpt->phydev->mdio.dev);
  600. mdiobus_unregister(adpt->mii_bus);
  601. free_netdev(netdev);
  602. if (adpt->phy.digital)
  603. iounmap(adpt->phy.digital);
  604. iounmap(adpt->phy.base);
  605. return 0;
  606. }
  607. static void emac_shutdown(struct platform_device *pdev)
  608. {
  609. struct net_device *netdev = dev_get_drvdata(&pdev->dev);
  610. struct emac_adapter *adpt = netdev_priv(netdev);
  611. struct emac_sgmii *sgmii = &adpt->phy;
  612. if (netdev->flags & IFF_UP) {
  613. /* Closing the SGMII turns off its interrupts */
  614. sgmii->close(adpt);
  615. /* Resetting the MAC turns off all DMA and its interrupts */
  616. emac_mac_reset(adpt);
  617. }
  618. }
  619. static struct platform_driver emac_platform_driver = {
  620. .probe = emac_probe,
  621. .remove = emac_remove,
  622. .driver = {
  623. .name = "qcom-emac",
  624. .of_match_table = emac_dt_match,
  625. .acpi_match_table = ACPI_PTR(emac_acpi_match),
  626. },
  627. .shutdown = emac_shutdown,
  628. };
  629. module_platform_driver(emac_platform_driver);
  630. MODULE_LICENSE("GPL v2");
  631. MODULE_ALIAS("platform:qcom-emac");