qed_l2.c 80 KB

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  1. /* QLogic qed NIC Driver
  2. * Copyright (c) 2015-2017 QLogic Corporation
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and /or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/types.h>
  33. #include <asm/byteorder.h>
  34. #include <asm/param.h>
  35. #include <linux/delay.h>
  36. #include <linux/dma-mapping.h>
  37. #include <linux/etherdevice.h>
  38. #include <linux/interrupt.h>
  39. #include <linux/kernel.h>
  40. #include <linux/module.h>
  41. #include <linux/pci.h>
  42. #include <linux/slab.h>
  43. #include <linux/stddef.h>
  44. #include <linux/string.h>
  45. #include <linux/workqueue.h>
  46. #include <linux/bitops.h>
  47. #include <linux/bug.h>
  48. #include <linux/vmalloc.h>
  49. #include "qed.h"
  50. #include <linux/qed/qed_chain.h>
  51. #include "qed_cxt.h"
  52. #include "qed_dev_api.h"
  53. #include <linux/qed/qed_eth_if.h>
  54. #include "qed_hsi.h"
  55. #include "qed_hw.h"
  56. #include "qed_int.h"
  57. #include "qed_l2.h"
  58. #include "qed_mcp.h"
  59. #include "qed_reg_addr.h"
  60. #include "qed_sp.h"
  61. #include "qed_sriov.h"
  62. #define QED_MAX_SGES_NUM 16
  63. #define CRC32_POLY 0x1edc6f41
  64. struct qed_l2_info {
  65. u32 queues;
  66. unsigned long **pp_qid_usage;
  67. /* The lock is meant to synchronize access to the qid usage */
  68. struct mutex lock;
  69. };
  70. int qed_l2_alloc(struct qed_hwfn *p_hwfn)
  71. {
  72. struct qed_l2_info *p_l2_info;
  73. unsigned long **pp_qids;
  74. u32 i;
  75. if (!QED_IS_L2_PERSONALITY(p_hwfn))
  76. return 0;
  77. p_l2_info = kzalloc(sizeof(*p_l2_info), GFP_KERNEL);
  78. if (!p_l2_info)
  79. return -ENOMEM;
  80. p_hwfn->p_l2_info = p_l2_info;
  81. if (IS_PF(p_hwfn->cdev)) {
  82. p_l2_info->queues = RESC_NUM(p_hwfn, QED_L2_QUEUE);
  83. } else {
  84. u8 rx = 0, tx = 0;
  85. qed_vf_get_num_rxqs(p_hwfn, &rx);
  86. qed_vf_get_num_txqs(p_hwfn, &tx);
  87. p_l2_info->queues = max_t(u8, rx, tx);
  88. }
  89. pp_qids = kzalloc(sizeof(unsigned long *) * p_l2_info->queues,
  90. GFP_KERNEL);
  91. if (!pp_qids)
  92. return -ENOMEM;
  93. p_l2_info->pp_qid_usage = pp_qids;
  94. for (i = 0; i < p_l2_info->queues; i++) {
  95. pp_qids[i] = kzalloc(MAX_QUEUES_PER_QZONE / 8, GFP_KERNEL);
  96. if (!pp_qids[i])
  97. return -ENOMEM;
  98. }
  99. return 0;
  100. }
  101. void qed_l2_setup(struct qed_hwfn *p_hwfn)
  102. {
  103. if (p_hwfn->hw_info.personality != QED_PCI_ETH &&
  104. p_hwfn->hw_info.personality != QED_PCI_ETH_ROCE)
  105. return;
  106. mutex_init(&p_hwfn->p_l2_info->lock);
  107. }
  108. void qed_l2_free(struct qed_hwfn *p_hwfn)
  109. {
  110. u32 i;
  111. if (p_hwfn->hw_info.personality != QED_PCI_ETH &&
  112. p_hwfn->hw_info.personality != QED_PCI_ETH_ROCE)
  113. return;
  114. if (!p_hwfn->p_l2_info)
  115. return;
  116. if (!p_hwfn->p_l2_info->pp_qid_usage)
  117. goto out_l2_info;
  118. /* Free until hit first uninitialized entry */
  119. for (i = 0; i < p_hwfn->p_l2_info->queues; i++) {
  120. if (!p_hwfn->p_l2_info->pp_qid_usage[i])
  121. break;
  122. kfree(p_hwfn->p_l2_info->pp_qid_usage[i]);
  123. }
  124. kfree(p_hwfn->p_l2_info->pp_qid_usage);
  125. out_l2_info:
  126. kfree(p_hwfn->p_l2_info);
  127. p_hwfn->p_l2_info = NULL;
  128. }
  129. static bool qed_eth_queue_qid_usage_add(struct qed_hwfn *p_hwfn,
  130. struct qed_queue_cid *p_cid)
  131. {
  132. struct qed_l2_info *p_l2_info = p_hwfn->p_l2_info;
  133. u16 queue_id = p_cid->rel.queue_id;
  134. bool b_rc = true;
  135. u8 first;
  136. mutex_lock(&p_l2_info->lock);
  137. if (queue_id >= p_l2_info->queues) {
  138. DP_NOTICE(p_hwfn,
  139. "Requested to increase usage for qzone %04x out of %08x\n",
  140. queue_id, p_l2_info->queues);
  141. b_rc = false;
  142. goto out;
  143. }
  144. first = (u8)find_first_zero_bit(p_l2_info->pp_qid_usage[queue_id],
  145. MAX_QUEUES_PER_QZONE);
  146. if (first >= MAX_QUEUES_PER_QZONE) {
  147. b_rc = false;
  148. goto out;
  149. }
  150. __set_bit(first, p_l2_info->pp_qid_usage[queue_id]);
  151. p_cid->qid_usage_idx = first;
  152. out:
  153. mutex_unlock(&p_l2_info->lock);
  154. return b_rc;
  155. }
  156. static void qed_eth_queue_qid_usage_del(struct qed_hwfn *p_hwfn,
  157. struct qed_queue_cid *p_cid)
  158. {
  159. mutex_lock(&p_hwfn->p_l2_info->lock);
  160. clear_bit(p_cid->qid_usage_idx,
  161. p_hwfn->p_l2_info->pp_qid_usage[p_cid->rel.queue_id]);
  162. mutex_unlock(&p_hwfn->p_l2_info->lock);
  163. }
  164. void qed_eth_queue_cid_release(struct qed_hwfn *p_hwfn,
  165. struct qed_queue_cid *p_cid)
  166. {
  167. bool b_legacy_vf = !!(p_cid->vf_legacy & QED_QCID_LEGACY_VF_CID);
  168. if (IS_PF(p_hwfn->cdev) && !b_legacy_vf)
  169. _qed_cxt_release_cid(p_hwfn, p_cid->cid, p_cid->vfid);
  170. /* For PF's VFs we maintain the index inside queue-zone in IOV */
  171. if (p_cid->vfid == QED_QUEUE_CID_SELF)
  172. qed_eth_queue_qid_usage_del(p_hwfn, p_cid);
  173. vfree(p_cid);
  174. }
  175. /* The internal is only meant to be directly called by PFs initializeing CIDs
  176. * for their VFs.
  177. */
  178. static struct qed_queue_cid *
  179. _qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn,
  180. u16 opaque_fid,
  181. u32 cid,
  182. struct qed_queue_start_common_params *p_params,
  183. bool b_is_rx,
  184. struct qed_queue_cid_vf_params *p_vf_params)
  185. {
  186. struct qed_queue_cid *p_cid;
  187. int rc;
  188. p_cid = vmalloc(sizeof(*p_cid));
  189. if (!p_cid)
  190. return NULL;
  191. memset(p_cid, 0, sizeof(*p_cid));
  192. p_cid->opaque_fid = opaque_fid;
  193. p_cid->cid = cid;
  194. p_cid->p_owner = p_hwfn;
  195. /* Fill in parameters */
  196. p_cid->rel.vport_id = p_params->vport_id;
  197. p_cid->rel.queue_id = p_params->queue_id;
  198. p_cid->rel.stats_id = p_params->stats_id;
  199. p_cid->sb_igu_id = p_params->p_sb->igu_sb_id;
  200. p_cid->b_is_rx = b_is_rx;
  201. p_cid->sb_idx = p_params->sb_idx;
  202. /* Fill-in bits related to VFs' queues if information was provided */
  203. if (p_vf_params) {
  204. p_cid->vfid = p_vf_params->vfid;
  205. p_cid->vf_qid = p_vf_params->vf_qid;
  206. p_cid->vf_legacy = p_vf_params->vf_legacy;
  207. } else {
  208. p_cid->vfid = QED_QUEUE_CID_SELF;
  209. }
  210. /* Don't try calculating the absolute indices for VFs */
  211. if (IS_VF(p_hwfn->cdev)) {
  212. p_cid->abs = p_cid->rel;
  213. goto out;
  214. }
  215. /* Calculate the engine-absolute indices of the resources.
  216. * This would guarantee they're valid later on.
  217. * In some cases [SBs] we already have the right values.
  218. */
  219. rc = qed_fw_vport(p_hwfn, p_cid->rel.vport_id, &p_cid->abs.vport_id);
  220. if (rc)
  221. goto fail;
  222. rc = qed_fw_l2_queue(p_hwfn, p_cid->rel.queue_id, &p_cid->abs.queue_id);
  223. if (rc)
  224. goto fail;
  225. /* In case of a PF configuring its VF's queues, the stats-id is already
  226. * absolute [since there's a single index that's suitable per-VF].
  227. */
  228. if (p_cid->vfid == QED_QUEUE_CID_SELF) {
  229. rc = qed_fw_vport(p_hwfn, p_cid->rel.stats_id,
  230. &p_cid->abs.stats_id);
  231. if (rc)
  232. goto fail;
  233. } else {
  234. p_cid->abs.stats_id = p_cid->rel.stats_id;
  235. }
  236. out:
  237. /* VF-images have provided the qid_usage_idx on their own.
  238. * Otherwise, we need to allocate a unique one.
  239. */
  240. if (!p_vf_params) {
  241. if (!qed_eth_queue_qid_usage_add(p_hwfn, p_cid))
  242. goto fail;
  243. } else {
  244. p_cid->qid_usage_idx = p_vf_params->qid_usage_idx;
  245. }
  246. DP_VERBOSE(p_hwfn,
  247. QED_MSG_SP,
  248. "opaque_fid: %04x CID %08x vport %02x [%02x] qzone %04x.%02x [%04x] stats %02x [%02x] SB %04x PI %02x\n",
  249. p_cid->opaque_fid,
  250. p_cid->cid,
  251. p_cid->rel.vport_id,
  252. p_cid->abs.vport_id,
  253. p_cid->rel.queue_id,
  254. p_cid->qid_usage_idx,
  255. p_cid->abs.queue_id,
  256. p_cid->rel.stats_id,
  257. p_cid->abs.stats_id, p_cid->sb_igu_id, p_cid->sb_idx);
  258. return p_cid;
  259. fail:
  260. vfree(p_cid);
  261. return NULL;
  262. }
  263. struct qed_queue_cid *
  264. qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn,
  265. u16 opaque_fid,
  266. struct qed_queue_start_common_params *p_params,
  267. bool b_is_rx,
  268. struct qed_queue_cid_vf_params *p_vf_params)
  269. {
  270. struct qed_queue_cid *p_cid;
  271. u8 vfid = QED_CXT_PF_CID;
  272. bool b_legacy_vf = false;
  273. u32 cid = 0;
  274. /* In case of legacy VFs, The CID can be derived from the additional
  275. * VF parameters - the VF assumes queue X uses CID X, so we can simply
  276. * use the vf_qid for this purpose as well.
  277. */
  278. if (p_vf_params) {
  279. vfid = p_vf_params->vfid;
  280. if (p_vf_params->vf_legacy & QED_QCID_LEGACY_VF_CID) {
  281. b_legacy_vf = true;
  282. cid = p_vf_params->vf_qid;
  283. }
  284. }
  285. /* Get a unique firmware CID for this queue, in case it's a PF.
  286. * VF's don't need a CID as the queue configuration will be done
  287. * by PF.
  288. */
  289. if (IS_PF(p_hwfn->cdev) && !b_legacy_vf) {
  290. if (_qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH,
  291. &cid, vfid)) {
  292. DP_NOTICE(p_hwfn, "Failed to acquire cid\n");
  293. return NULL;
  294. }
  295. }
  296. p_cid = _qed_eth_queue_to_cid(p_hwfn, opaque_fid, cid,
  297. p_params, b_is_rx, p_vf_params);
  298. if (!p_cid && IS_PF(p_hwfn->cdev) && !b_legacy_vf)
  299. _qed_cxt_release_cid(p_hwfn, cid, vfid);
  300. return p_cid;
  301. }
  302. static struct qed_queue_cid *
  303. qed_eth_queue_to_cid_pf(struct qed_hwfn *p_hwfn,
  304. u16 opaque_fid,
  305. bool b_is_rx,
  306. struct qed_queue_start_common_params *p_params)
  307. {
  308. return qed_eth_queue_to_cid(p_hwfn, opaque_fid, p_params, b_is_rx,
  309. NULL);
  310. }
  311. int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn,
  312. struct qed_sp_vport_start_params *p_params)
  313. {
  314. struct vport_start_ramrod_data *p_ramrod = NULL;
  315. struct qed_spq_entry *p_ent = NULL;
  316. struct qed_sp_init_data init_data;
  317. u8 abs_vport_id = 0;
  318. int rc = -EINVAL;
  319. u16 rx_mode = 0;
  320. rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
  321. if (rc)
  322. return rc;
  323. memset(&init_data, 0, sizeof(init_data));
  324. init_data.cid = qed_spq_get_cid(p_hwfn);
  325. init_data.opaque_fid = p_params->opaque_fid;
  326. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  327. rc = qed_sp_init_request(p_hwfn, &p_ent,
  328. ETH_RAMROD_VPORT_START,
  329. PROTOCOLID_ETH, &init_data);
  330. if (rc)
  331. return rc;
  332. p_ramrod = &p_ent->ramrod.vport_start;
  333. p_ramrod->vport_id = abs_vport_id;
  334. p_ramrod->mtu = cpu_to_le16(p_params->mtu);
  335. p_ramrod->handle_ptp_pkts = p_params->handle_ptp_pkts;
  336. p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan;
  337. p_ramrod->drop_ttl0_en = p_params->drop_ttl0;
  338. p_ramrod->untagged = p_params->only_untagged;
  339. SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
  340. SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
  341. p_ramrod->rx_mode.state = cpu_to_le16(rx_mode);
  342. /* TPA related fields */
  343. memset(&p_ramrod->tpa_param, 0, sizeof(struct eth_vport_tpa_param));
  344. p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
  345. switch (p_params->tpa_mode) {
  346. case QED_TPA_MODE_GRO:
  347. p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
  348. p_ramrod->tpa_param.tpa_max_size = (u16)-1;
  349. p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
  350. p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
  351. p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
  352. p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
  353. p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
  354. p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
  355. break;
  356. default:
  357. break;
  358. }
  359. p_ramrod->tx_switching_en = p_params->tx_switching;
  360. p_ramrod->ctl_frame_mac_check_en = !!p_params->check_mac;
  361. p_ramrod->ctl_frame_ethtype_check_en = !!p_params->check_ethtype;
  362. /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
  363. p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev,
  364. p_params->concrete_fid);
  365. return qed_spq_post(p_hwfn, p_ent, NULL);
  366. }
  367. static int qed_sp_vport_start(struct qed_hwfn *p_hwfn,
  368. struct qed_sp_vport_start_params *p_params)
  369. {
  370. if (IS_VF(p_hwfn->cdev)) {
  371. return qed_vf_pf_vport_start(p_hwfn, p_params->vport_id,
  372. p_params->mtu,
  373. p_params->remove_inner_vlan,
  374. p_params->tpa_mode,
  375. p_params->max_buffers_per_cqe,
  376. p_params->only_untagged);
  377. }
  378. return qed_sp_eth_vport_start(p_hwfn, p_params);
  379. }
  380. static int
  381. qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn,
  382. struct vport_update_ramrod_data *p_ramrod,
  383. struct qed_rss_params *p_rss)
  384. {
  385. struct eth_vport_rss_config *p_config;
  386. u16 capabilities = 0;
  387. int i, table_size;
  388. int rc = 0;
  389. if (!p_rss) {
  390. p_ramrod->common.update_rss_flg = 0;
  391. return rc;
  392. }
  393. p_config = &p_ramrod->rss_config;
  394. BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE != ETH_RSS_IND_TABLE_ENTRIES_NUM);
  395. rc = qed_fw_rss_eng(p_hwfn, p_rss->rss_eng_id, &p_config->rss_id);
  396. if (rc)
  397. return rc;
  398. p_ramrod->common.update_rss_flg = p_rss->update_rss_config;
  399. p_config->update_rss_capabilities = p_rss->update_rss_capabilities;
  400. p_config->update_rss_ind_table = p_rss->update_rss_ind_table;
  401. p_config->update_rss_key = p_rss->update_rss_key;
  402. p_config->rss_mode = p_rss->rss_enable ?
  403. ETH_VPORT_RSS_MODE_REGULAR :
  404. ETH_VPORT_RSS_MODE_DISABLED;
  405. SET_FIELD(capabilities,
  406. ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
  407. !!(p_rss->rss_caps & QED_RSS_IPV4));
  408. SET_FIELD(capabilities,
  409. ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
  410. !!(p_rss->rss_caps & QED_RSS_IPV6));
  411. SET_FIELD(capabilities,
  412. ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
  413. !!(p_rss->rss_caps & QED_RSS_IPV4_TCP));
  414. SET_FIELD(capabilities,
  415. ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
  416. !!(p_rss->rss_caps & QED_RSS_IPV6_TCP));
  417. SET_FIELD(capabilities,
  418. ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
  419. !!(p_rss->rss_caps & QED_RSS_IPV4_UDP));
  420. SET_FIELD(capabilities,
  421. ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
  422. !!(p_rss->rss_caps & QED_RSS_IPV6_UDP));
  423. p_config->tbl_size = p_rss->rss_table_size_log;
  424. p_config->capabilities = cpu_to_le16(capabilities);
  425. DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
  426. "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
  427. p_ramrod->common.update_rss_flg,
  428. p_config->rss_mode,
  429. p_config->update_rss_capabilities,
  430. p_config->capabilities,
  431. p_config->update_rss_ind_table, p_config->update_rss_key);
  432. table_size = min_t(int, QED_RSS_IND_TABLE_SIZE,
  433. 1 << p_config->tbl_size);
  434. for (i = 0; i < table_size; i++) {
  435. struct qed_queue_cid *p_queue = p_rss->rss_ind_table[i];
  436. if (!p_queue)
  437. return -EINVAL;
  438. p_config->indirection_table[i] =
  439. cpu_to_le16(p_queue->abs.queue_id);
  440. }
  441. DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
  442. "Configured RSS indirection table [%d entries]:\n",
  443. table_size);
  444. for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i += 0x10) {
  445. DP_VERBOSE(p_hwfn,
  446. NETIF_MSG_IFUP,
  447. "%04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x\n",
  448. le16_to_cpu(p_config->indirection_table[i]),
  449. le16_to_cpu(p_config->indirection_table[i + 1]),
  450. le16_to_cpu(p_config->indirection_table[i + 2]),
  451. le16_to_cpu(p_config->indirection_table[i + 3]),
  452. le16_to_cpu(p_config->indirection_table[i + 4]),
  453. le16_to_cpu(p_config->indirection_table[i + 5]),
  454. le16_to_cpu(p_config->indirection_table[i + 6]),
  455. le16_to_cpu(p_config->indirection_table[i + 7]),
  456. le16_to_cpu(p_config->indirection_table[i + 8]),
  457. le16_to_cpu(p_config->indirection_table[i + 9]),
  458. le16_to_cpu(p_config->indirection_table[i + 10]),
  459. le16_to_cpu(p_config->indirection_table[i + 11]),
  460. le16_to_cpu(p_config->indirection_table[i + 12]),
  461. le16_to_cpu(p_config->indirection_table[i + 13]),
  462. le16_to_cpu(p_config->indirection_table[i + 14]),
  463. le16_to_cpu(p_config->indirection_table[i + 15]));
  464. }
  465. for (i = 0; i < 10; i++)
  466. p_config->rss_key[i] = cpu_to_le32(p_rss->rss_key[i]);
  467. return rc;
  468. }
  469. static void
  470. qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn,
  471. struct vport_update_ramrod_data *p_ramrod,
  472. struct qed_filter_accept_flags accept_flags)
  473. {
  474. p_ramrod->common.update_rx_mode_flg =
  475. accept_flags.update_rx_mode_config;
  476. p_ramrod->common.update_tx_mode_flg =
  477. accept_flags.update_tx_mode_config;
  478. /* Set Rx mode accept flags */
  479. if (p_ramrod->common.update_rx_mode_flg) {
  480. u8 accept_filter = accept_flags.rx_accept_filter;
  481. u16 state = 0;
  482. SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
  483. !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) ||
  484. !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)));
  485. SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
  486. !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED));
  487. SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
  488. !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) ||
  489. !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
  490. SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
  491. (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
  492. !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
  493. SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
  494. !!(accept_filter & QED_ACCEPT_BCAST));
  495. p_ramrod->rx_mode.state = cpu_to_le16(state);
  496. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  497. "p_ramrod->rx_mode.state = 0x%x\n", state);
  498. }
  499. /* Set Tx mode accept flags */
  500. if (p_ramrod->common.update_tx_mode_flg) {
  501. u8 accept_filter = accept_flags.tx_accept_filter;
  502. u16 state = 0;
  503. SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
  504. !!(accept_filter & QED_ACCEPT_NONE));
  505. SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
  506. !!(accept_filter & QED_ACCEPT_NONE));
  507. SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
  508. (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
  509. !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
  510. SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
  511. !!(accept_filter & QED_ACCEPT_BCAST));
  512. p_ramrod->tx_mode.state = cpu_to_le16(state);
  513. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  514. "p_ramrod->tx_mode.state = 0x%x\n", state);
  515. }
  516. }
  517. static void
  518. qed_sp_vport_update_sge_tpa(struct qed_hwfn *p_hwfn,
  519. struct vport_update_ramrod_data *p_ramrod,
  520. struct qed_sge_tpa_params *p_params)
  521. {
  522. struct eth_vport_tpa_param *p_tpa;
  523. if (!p_params) {
  524. p_ramrod->common.update_tpa_param_flg = 0;
  525. p_ramrod->common.update_tpa_en_flg = 0;
  526. p_ramrod->common.update_tpa_param_flg = 0;
  527. return;
  528. }
  529. p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg;
  530. p_tpa = &p_ramrod->tpa_param;
  531. p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg;
  532. p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg;
  533. p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg;
  534. p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg;
  535. p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg;
  536. p_tpa->max_buff_num = p_params->max_buffers_per_cqe;
  537. p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg;
  538. p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg;
  539. p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg;
  540. p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num;
  541. p_tpa->tpa_max_size = p_params->tpa_max_size;
  542. p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start;
  543. p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont;
  544. }
  545. static void
  546. qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn,
  547. struct vport_update_ramrod_data *p_ramrod,
  548. struct qed_sp_vport_update_params *p_params)
  549. {
  550. int i;
  551. memset(&p_ramrod->approx_mcast.bins, 0,
  552. sizeof(p_ramrod->approx_mcast.bins));
  553. if (!p_params->update_approx_mcast_flg)
  554. return;
  555. p_ramrod->common.update_approx_mcast_flg = 1;
  556. for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
  557. u32 *p_bins = (u32 *)p_params->bins;
  558. p_ramrod->approx_mcast.bins[i] = cpu_to_le32(p_bins[i]);
  559. }
  560. }
  561. int qed_sp_vport_update(struct qed_hwfn *p_hwfn,
  562. struct qed_sp_vport_update_params *p_params,
  563. enum spq_mode comp_mode,
  564. struct qed_spq_comp_cb *p_comp_data)
  565. {
  566. struct qed_rss_params *p_rss_params = p_params->rss_params;
  567. struct vport_update_ramrod_data_cmn *p_cmn;
  568. struct qed_sp_init_data init_data;
  569. struct vport_update_ramrod_data *p_ramrod = NULL;
  570. struct qed_spq_entry *p_ent = NULL;
  571. u8 abs_vport_id = 0, val;
  572. int rc = -EINVAL;
  573. if (IS_VF(p_hwfn->cdev)) {
  574. rc = qed_vf_pf_vport_update(p_hwfn, p_params);
  575. return rc;
  576. }
  577. rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
  578. if (rc)
  579. return rc;
  580. memset(&init_data, 0, sizeof(init_data));
  581. init_data.cid = qed_spq_get_cid(p_hwfn);
  582. init_data.opaque_fid = p_params->opaque_fid;
  583. init_data.comp_mode = comp_mode;
  584. init_data.p_comp_data = p_comp_data;
  585. rc = qed_sp_init_request(p_hwfn, &p_ent,
  586. ETH_RAMROD_VPORT_UPDATE,
  587. PROTOCOLID_ETH, &init_data);
  588. if (rc)
  589. return rc;
  590. /* Copy input params to ramrod according to FW struct */
  591. p_ramrod = &p_ent->ramrod.vport_update;
  592. p_cmn = &p_ramrod->common;
  593. p_cmn->vport_id = abs_vport_id;
  594. p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
  595. p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
  596. p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
  597. p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
  598. p_cmn->accept_any_vlan = p_params->accept_any_vlan;
  599. val = p_params->update_accept_any_vlan_flg;
  600. p_cmn->update_accept_any_vlan_flg = val;
  601. p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg;
  602. val = p_params->update_inner_vlan_removal_flg;
  603. p_cmn->update_inner_vlan_removal_en_flg = val;
  604. p_cmn->default_vlan_en = p_params->default_vlan_enable_flg;
  605. val = p_params->update_default_vlan_enable_flg;
  606. p_cmn->update_default_vlan_en_flg = val;
  607. p_cmn->default_vlan = cpu_to_le16(p_params->default_vlan);
  608. p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg;
  609. p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg;
  610. p_ramrod->common.tx_switching_en = p_params->tx_switching_flg;
  611. p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg;
  612. p_cmn->anti_spoofing_en = p_params->anti_spoofing_en;
  613. val = p_params->update_anti_spoofing_en_flg;
  614. p_ramrod->common.update_anti_spoofing_en_flg = val;
  615. rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
  616. if (rc) {
  617. /* Return spq entry which is taken in qed_sp_init_request()*/
  618. qed_spq_return_entry(p_hwfn, p_ent);
  619. return rc;
  620. }
  621. /* Update mcast bins for VFs, PF doesn't use this functionality */
  622. qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
  623. qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
  624. qed_sp_vport_update_sge_tpa(p_hwfn, p_ramrod, p_params->sge_tpa_params);
  625. return qed_spq_post(p_hwfn, p_ent, NULL);
  626. }
  627. int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, u16 opaque_fid, u8 vport_id)
  628. {
  629. struct vport_stop_ramrod_data *p_ramrod;
  630. struct qed_sp_init_data init_data;
  631. struct qed_spq_entry *p_ent;
  632. u8 abs_vport_id = 0;
  633. int rc;
  634. if (IS_VF(p_hwfn->cdev))
  635. return qed_vf_pf_vport_stop(p_hwfn);
  636. rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id);
  637. if (rc)
  638. return rc;
  639. memset(&init_data, 0, sizeof(init_data));
  640. init_data.cid = qed_spq_get_cid(p_hwfn);
  641. init_data.opaque_fid = opaque_fid;
  642. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  643. rc = qed_sp_init_request(p_hwfn, &p_ent,
  644. ETH_RAMROD_VPORT_STOP,
  645. PROTOCOLID_ETH, &init_data);
  646. if (rc)
  647. return rc;
  648. p_ramrod = &p_ent->ramrod.vport_stop;
  649. p_ramrod->vport_id = abs_vport_id;
  650. return qed_spq_post(p_hwfn, p_ent, NULL);
  651. }
  652. static int
  653. qed_vf_pf_accept_flags(struct qed_hwfn *p_hwfn,
  654. struct qed_filter_accept_flags *p_accept_flags)
  655. {
  656. struct qed_sp_vport_update_params s_params;
  657. memset(&s_params, 0, sizeof(s_params));
  658. memcpy(&s_params.accept_flags, p_accept_flags,
  659. sizeof(struct qed_filter_accept_flags));
  660. return qed_vf_pf_vport_update(p_hwfn, &s_params);
  661. }
  662. static int qed_filter_accept_cmd(struct qed_dev *cdev,
  663. u8 vport,
  664. struct qed_filter_accept_flags accept_flags,
  665. u8 update_accept_any_vlan,
  666. u8 accept_any_vlan,
  667. enum spq_mode comp_mode,
  668. struct qed_spq_comp_cb *p_comp_data)
  669. {
  670. struct qed_sp_vport_update_params vport_update_params;
  671. int i, rc;
  672. /* Prepare and send the vport rx_mode change */
  673. memset(&vport_update_params, 0, sizeof(vport_update_params));
  674. vport_update_params.vport_id = vport;
  675. vport_update_params.accept_flags = accept_flags;
  676. vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
  677. vport_update_params.accept_any_vlan = accept_any_vlan;
  678. for_each_hwfn(cdev, i) {
  679. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  680. vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
  681. if (IS_VF(cdev)) {
  682. rc = qed_vf_pf_accept_flags(p_hwfn, &accept_flags);
  683. if (rc)
  684. return rc;
  685. continue;
  686. }
  687. rc = qed_sp_vport_update(p_hwfn, &vport_update_params,
  688. comp_mode, p_comp_data);
  689. if (rc) {
  690. DP_ERR(cdev, "Update rx_mode failed %d\n", rc);
  691. return rc;
  692. }
  693. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  694. "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
  695. accept_flags.rx_accept_filter,
  696. accept_flags.tx_accept_filter);
  697. if (update_accept_any_vlan)
  698. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  699. "accept_any_vlan=%d configured\n",
  700. accept_any_vlan);
  701. }
  702. return 0;
  703. }
  704. int qed_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn,
  705. struct qed_queue_cid *p_cid,
  706. u16 bd_max_bytes,
  707. dma_addr_t bd_chain_phys_addr,
  708. dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size)
  709. {
  710. struct rx_queue_start_ramrod_data *p_ramrod = NULL;
  711. struct qed_spq_entry *p_ent = NULL;
  712. struct qed_sp_init_data init_data;
  713. int rc = -EINVAL;
  714. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  715. "opaque_fid=0x%x, cid=0x%x, rx_qzone=0x%x, vport_id=0x%x, sb_id=0x%x\n",
  716. p_cid->opaque_fid, p_cid->cid,
  717. p_cid->abs.queue_id, p_cid->abs.vport_id, p_cid->sb_igu_id);
  718. /* Get SPQ entry */
  719. memset(&init_data, 0, sizeof(init_data));
  720. init_data.cid = p_cid->cid;
  721. init_data.opaque_fid = p_cid->opaque_fid;
  722. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  723. rc = qed_sp_init_request(p_hwfn, &p_ent,
  724. ETH_RAMROD_RX_QUEUE_START,
  725. PROTOCOLID_ETH, &init_data);
  726. if (rc)
  727. return rc;
  728. p_ramrod = &p_ent->ramrod.rx_queue_start;
  729. p_ramrod->sb_id = cpu_to_le16(p_cid->sb_igu_id);
  730. p_ramrod->sb_index = p_cid->sb_idx;
  731. p_ramrod->vport_id = p_cid->abs.vport_id;
  732. p_ramrod->stats_counter_id = p_cid->abs.stats_id;
  733. p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
  734. p_ramrod->complete_cqe_flg = 0;
  735. p_ramrod->complete_event_flg = 1;
  736. p_ramrod->bd_max_bytes = cpu_to_le16(bd_max_bytes);
  737. DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
  738. p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size);
  739. DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
  740. if (p_cid->vfid != QED_QUEUE_CID_SELF) {
  741. bool b_legacy_vf = !!(p_cid->vf_legacy &
  742. QED_QCID_LEGACY_VF_RX_PROD);
  743. p_ramrod->vf_rx_prod_index = p_cid->vf_qid;
  744. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  745. "Queue%s is meant for VF rxq[%02x]\n",
  746. b_legacy_vf ? " [legacy]" : "", p_cid->vf_qid);
  747. p_ramrod->vf_rx_prod_use_zone_a = b_legacy_vf;
  748. }
  749. return qed_spq_post(p_hwfn, p_ent, NULL);
  750. }
  751. static int
  752. qed_eth_pf_rx_queue_start(struct qed_hwfn *p_hwfn,
  753. struct qed_queue_cid *p_cid,
  754. u16 bd_max_bytes,
  755. dma_addr_t bd_chain_phys_addr,
  756. dma_addr_t cqe_pbl_addr,
  757. u16 cqe_pbl_size, void __iomem **pp_prod)
  758. {
  759. u32 init_prod_val = 0;
  760. *pp_prod = p_hwfn->regview +
  761. GTT_BAR0_MAP_REG_MSDM_RAM +
  762. MSTORM_ETH_PF_PRODS_OFFSET(p_cid->abs.queue_id);
  763. /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
  764. __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
  765. (u32 *)(&init_prod_val));
  766. return qed_eth_rxq_start_ramrod(p_hwfn, p_cid,
  767. bd_max_bytes,
  768. bd_chain_phys_addr,
  769. cqe_pbl_addr, cqe_pbl_size);
  770. }
  771. static int
  772. qed_eth_rx_queue_start(struct qed_hwfn *p_hwfn,
  773. u16 opaque_fid,
  774. struct qed_queue_start_common_params *p_params,
  775. u16 bd_max_bytes,
  776. dma_addr_t bd_chain_phys_addr,
  777. dma_addr_t cqe_pbl_addr,
  778. u16 cqe_pbl_size,
  779. struct qed_rxq_start_ret_params *p_ret_params)
  780. {
  781. struct qed_queue_cid *p_cid;
  782. int rc;
  783. /* Allocate a CID for the queue */
  784. p_cid = qed_eth_queue_to_cid_pf(p_hwfn, opaque_fid, true, p_params);
  785. if (!p_cid)
  786. return -ENOMEM;
  787. if (IS_PF(p_hwfn->cdev)) {
  788. rc = qed_eth_pf_rx_queue_start(p_hwfn, p_cid,
  789. bd_max_bytes,
  790. bd_chain_phys_addr,
  791. cqe_pbl_addr, cqe_pbl_size,
  792. &p_ret_params->p_prod);
  793. } else {
  794. rc = qed_vf_pf_rxq_start(p_hwfn, p_cid,
  795. bd_max_bytes,
  796. bd_chain_phys_addr,
  797. cqe_pbl_addr,
  798. cqe_pbl_size, &p_ret_params->p_prod);
  799. }
  800. /* Provide the caller with a reference to as handler */
  801. if (rc)
  802. qed_eth_queue_cid_release(p_hwfn, p_cid);
  803. else
  804. p_ret_params->p_handle = (void *)p_cid;
  805. return rc;
  806. }
  807. int qed_sp_eth_rx_queues_update(struct qed_hwfn *p_hwfn,
  808. void **pp_rxq_handles,
  809. u8 num_rxqs,
  810. u8 complete_cqe_flg,
  811. u8 complete_event_flg,
  812. enum spq_mode comp_mode,
  813. struct qed_spq_comp_cb *p_comp_data)
  814. {
  815. struct rx_queue_update_ramrod_data *p_ramrod = NULL;
  816. struct qed_spq_entry *p_ent = NULL;
  817. struct qed_sp_init_data init_data;
  818. struct qed_queue_cid *p_cid;
  819. int rc = -EINVAL;
  820. u8 i;
  821. memset(&init_data, 0, sizeof(init_data));
  822. init_data.comp_mode = comp_mode;
  823. init_data.p_comp_data = p_comp_data;
  824. for (i = 0; i < num_rxqs; i++) {
  825. p_cid = ((struct qed_queue_cid **)pp_rxq_handles)[i];
  826. /* Get SPQ entry */
  827. init_data.cid = p_cid->cid;
  828. init_data.opaque_fid = p_cid->opaque_fid;
  829. rc = qed_sp_init_request(p_hwfn, &p_ent,
  830. ETH_RAMROD_RX_QUEUE_UPDATE,
  831. PROTOCOLID_ETH, &init_data);
  832. if (rc)
  833. return rc;
  834. p_ramrod = &p_ent->ramrod.rx_queue_update;
  835. p_ramrod->vport_id = p_cid->abs.vport_id;
  836. p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
  837. p_ramrod->complete_cqe_flg = complete_cqe_flg;
  838. p_ramrod->complete_event_flg = complete_event_flg;
  839. rc = qed_spq_post(p_hwfn, p_ent, NULL);
  840. if (rc)
  841. return rc;
  842. }
  843. return rc;
  844. }
  845. static int
  846. qed_eth_pf_rx_queue_stop(struct qed_hwfn *p_hwfn,
  847. struct qed_queue_cid *p_cid,
  848. bool b_eq_completion_only, bool b_cqe_completion)
  849. {
  850. struct rx_queue_stop_ramrod_data *p_ramrod = NULL;
  851. struct qed_spq_entry *p_ent = NULL;
  852. struct qed_sp_init_data init_data;
  853. int rc;
  854. memset(&init_data, 0, sizeof(init_data));
  855. init_data.cid = p_cid->cid;
  856. init_data.opaque_fid = p_cid->opaque_fid;
  857. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  858. rc = qed_sp_init_request(p_hwfn, &p_ent,
  859. ETH_RAMROD_RX_QUEUE_STOP,
  860. PROTOCOLID_ETH, &init_data);
  861. if (rc)
  862. return rc;
  863. p_ramrod = &p_ent->ramrod.rx_queue_stop;
  864. p_ramrod->vport_id = p_cid->abs.vport_id;
  865. p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
  866. /* Cleaning the queue requires the completion to arrive there.
  867. * In addition, VFs require the answer to come as eqe to PF.
  868. */
  869. p_ramrod->complete_cqe_flg = ((p_cid->vfid == QED_QUEUE_CID_SELF) &&
  870. !b_eq_completion_only) ||
  871. b_cqe_completion;
  872. p_ramrod->complete_event_flg = (p_cid->vfid != QED_QUEUE_CID_SELF) ||
  873. b_eq_completion_only;
  874. return qed_spq_post(p_hwfn, p_ent, NULL);
  875. }
  876. int qed_eth_rx_queue_stop(struct qed_hwfn *p_hwfn,
  877. void *p_rxq,
  878. bool eq_completion_only, bool cqe_completion)
  879. {
  880. struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_rxq;
  881. int rc = -EINVAL;
  882. if (IS_PF(p_hwfn->cdev))
  883. rc = qed_eth_pf_rx_queue_stop(p_hwfn, p_cid,
  884. eq_completion_only,
  885. cqe_completion);
  886. else
  887. rc = qed_vf_pf_rxq_stop(p_hwfn, p_cid, cqe_completion);
  888. if (!rc)
  889. qed_eth_queue_cid_release(p_hwfn, p_cid);
  890. return rc;
  891. }
  892. int
  893. qed_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn,
  894. struct qed_queue_cid *p_cid,
  895. dma_addr_t pbl_addr, u16 pbl_size, u16 pq_id)
  896. {
  897. struct tx_queue_start_ramrod_data *p_ramrod = NULL;
  898. struct qed_spq_entry *p_ent = NULL;
  899. struct qed_sp_init_data init_data;
  900. int rc = -EINVAL;
  901. /* Get SPQ entry */
  902. memset(&init_data, 0, sizeof(init_data));
  903. init_data.cid = p_cid->cid;
  904. init_data.opaque_fid = p_cid->opaque_fid;
  905. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  906. rc = qed_sp_init_request(p_hwfn, &p_ent,
  907. ETH_RAMROD_TX_QUEUE_START,
  908. PROTOCOLID_ETH, &init_data);
  909. if (rc)
  910. return rc;
  911. p_ramrod = &p_ent->ramrod.tx_queue_start;
  912. p_ramrod->vport_id = p_cid->abs.vport_id;
  913. p_ramrod->sb_id = cpu_to_le16(p_cid->sb_igu_id);
  914. p_ramrod->sb_index = p_cid->sb_idx;
  915. p_ramrod->stats_counter_id = p_cid->abs.stats_id;
  916. p_ramrod->queue_zone_id = cpu_to_le16(p_cid->abs.queue_id);
  917. p_ramrod->same_as_last_id = cpu_to_le16(p_cid->abs.queue_id);
  918. p_ramrod->pbl_size = cpu_to_le16(pbl_size);
  919. DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr);
  920. p_ramrod->qm_pq_id = cpu_to_le16(pq_id);
  921. return qed_spq_post(p_hwfn, p_ent, NULL);
  922. }
  923. static int
  924. qed_eth_pf_tx_queue_start(struct qed_hwfn *p_hwfn,
  925. struct qed_queue_cid *p_cid,
  926. u8 tc,
  927. dma_addr_t pbl_addr,
  928. u16 pbl_size, void __iomem **pp_doorbell)
  929. {
  930. int rc;
  931. rc = qed_eth_txq_start_ramrod(p_hwfn, p_cid,
  932. pbl_addr, pbl_size,
  933. qed_get_cm_pq_idx_mcos(p_hwfn, tc));
  934. if (rc)
  935. return rc;
  936. /* Provide the caller with the necessary return values */
  937. *pp_doorbell = p_hwfn->doorbells +
  938. qed_db_addr(p_cid->cid, DQ_DEMS_LEGACY);
  939. return 0;
  940. }
  941. static int
  942. qed_eth_tx_queue_start(struct qed_hwfn *p_hwfn,
  943. u16 opaque_fid,
  944. struct qed_queue_start_common_params *p_params,
  945. u8 tc,
  946. dma_addr_t pbl_addr,
  947. u16 pbl_size,
  948. struct qed_txq_start_ret_params *p_ret_params)
  949. {
  950. struct qed_queue_cid *p_cid;
  951. int rc;
  952. p_cid = qed_eth_queue_to_cid_pf(p_hwfn, opaque_fid, false, p_params);
  953. if (!p_cid)
  954. return -EINVAL;
  955. if (IS_PF(p_hwfn->cdev))
  956. rc = qed_eth_pf_tx_queue_start(p_hwfn, p_cid, tc,
  957. pbl_addr, pbl_size,
  958. &p_ret_params->p_doorbell);
  959. else
  960. rc = qed_vf_pf_txq_start(p_hwfn, p_cid,
  961. pbl_addr, pbl_size,
  962. &p_ret_params->p_doorbell);
  963. if (rc)
  964. qed_eth_queue_cid_release(p_hwfn, p_cid);
  965. else
  966. p_ret_params->p_handle = (void *)p_cid;
  967. return rc;
  968. }
  969. static int
  970. qed_eth_pf_tx_queue_stop(struct qed_hwfn *p_hwfn, struct qed_queue_cid *p_cid)
  971. {
  972. struct qed_spq_entry *p_ent = NULL;
  973. struct qed_sp_init_data init_data;
  974. int rc;
  975. memset(&init_data, 0, sizeof(init_data));
  976. init_data.cid = p_cid->cid;
  977. init_data.opaque_fid = p_cid->opaque_fid;
  978. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  979. rc = qed_sp_init_request(p_hwfn, &p_ent,
  980. ETH_RAMROD_TX_QUEUE_STOP,
  981. PROTOCOLID_ETH, &init_data);
  982. if (rc)
  983. return rc;
  984. return qed_spq_post(p_hwfn, p_ent, NULL);
  985. }
  986. int qed_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, void *p_handle)
  987. {
  988. struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_handle;
  989. int rc;
  990. if (IS_PF(p_hwfn->cdev))
  991. rc = qed_eth_pf_tx_queue_stop(p_hwfn, p_cid);
  992. else
  993. rc = qed_vf_pf_txq_stop(p_hwfn, p_cid);
  994. if (!rc)
  995. qed_eth_queue_cid_release(p_hwfn, p_cid);
  996. return rc;
  997. }
  998. static enum eth_filter_action qed_filter_action(enum qed_filter_opcode opcode)
  999. {
  1000. enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
  1001. switch (opcode) {
  1002. case QED_FILTER_ADD:
  1003. action = ETH_FILTER_ACTION_ADD;
  1004. break;
  1005. case QED_FILTER_REMOVE:
  1006. action = ETH_FILTER_ACTION_REMOVE;
  1007. break;
  1008. case QED_FILTER_FLUSH:
  1009. action = ETH_FILTER_ACTION_REMOVE_ALL;
  1010. break;
  1011. default:
  1012. action = MAX_ETH_FILTER_ACTION;
  1013. }
  1014. return action;
  1015. }
  1016. static int
  1017. qed_filter_ucast_common(struct qed_hwfn *p_hwfn,
  1018. u16 opaque_fid,
  1019. struct qed_filter_ucast *p_filter_cmd,
  1020. struct vport_filter_update_ramrod_data **pp_ramrod,
  1021. struct qed_spq_entry **pp_ent,
  1022. enum spq_mode comp_mode,
  1023. struct qed_spq_comp_cb *p_comp_data)
  1024. {
  1025. u8 vport_to_add_to = 0, vport_to_remove_from = 0;
  1026. struct vport_filter_update_ramrod_data *p_ramrod;
  1027. struct eth_filter_cmd *p_first_filter;
  1028. struct eth_filter_cmd *p_second_filter;
  1029. struct qed_sp_init_data init_data;
  1030. enum eth_filter_action action;
  1031. int rc;
  1032. rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
  1033. &vport_to_remove_from);
  1034. if (rc)
  1035. return rc;
  1036. rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
  1037. &vport_to_add_to);
  1038. if (rc)
  1039. return rc;
  1040. /* Get SPQ entry */
  1041. memset(&init_data, 0, sizeof(init_data));
  1042. init_data.cid = qed_spq_get_cid(p_hwfn);
  1043. init_data.opaque_fid = opaque_fid;
  1044. init_data.comp_mode = comp_mode;
  1045. init_data.p_comp_data = p_comp_data;
  1046. rc = qed_sp_init_request(p_hwfn, pp_ent,
  1047. ETH_RAMROD_FILTERS_UPDATE,
  1048. PROTOCOLID_ETH, &init_data);
  1049. if (rc)
  1050. return rc;
  1051. *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
  1052. p_ramrod = *pp_ramrod;
  1053. p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
  1054. p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
  1055. switch (p_filter_cmd->opcode) {
  1056. case QED_FILTER_REPLACE:
  1057. case QED_FILTER_MOVE:
  1058. p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break;
  1059. default:
  1060. p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break;
  1061. }
  1062. p_first_filter = &p_ramrod->filter_cmds[0];
  1063. p_second_filter = &p_ramrod->filter_cmds[1];
  1064. switch (p_filter_cmd->type) {
  1065. case QED_FILTER_MAC:
  1066. p_first_filter->type = ETH_FILTER_TYPE_MAC; break;
  1067. case QED_FILTER_VLAN:
  1068. p_first_filter->type = ETH_FILTER_TYPE_VLAN; break;
  1069. case QED_FILTER_MAC_VLAN:
  1070. p_first_filter->type = ETH_FILTER_TYPE_PAIR; break;
  1071. case QED_FILTER_INNER_MAC:
  1072. p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break;
  1073. case QED_FILTER_INNER_VLAN:
  1074. p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break;
  1075. case QED_FILTER_INNER_PAIR:
  1076. p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break;
  1077. case QED_FILTER_INNER_MAC_VNI_PAIR:
  1078. p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
  1079. break;
  1080. case QED_FILTER_MAC_VNI_PAIR:
  1081. p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break;
  1082. case QED_FILTER_VNI:
  1083. p_first_filter->type = ETH_FILTER_TYPE_VNI; break;
  1084. }
  1085. if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
  1086. (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
  1087. (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
  1088. (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
  1089. (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
  1090. (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) {
  1091. qed_set_fw_mac_addr(&p_first_filter->mac_msb,
  1092. &p_first_filter->mac_mid,
  1093. &p_first_filter->mac_lsb,
  1094. (u8 *)p_filter_cmd->mac);
  1095. }
  1096. if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
  1097. (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
  1098. (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
  1099. (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
  1100. p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan);
  1101. if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
  1102. (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
  1103. (p_first_filter->type == ETH_FILTER_TYPE_VNI))
  1104. p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni);
  1105. if (p_filter_cmd->opcode == QED_FILTER_MOVE) {
  1106. p_second_filter->type = p_first_filter->type;
  1107. p_second_filter->mac_msb = p_first_filter->mac_msb;
  1108. p_second_filter->mac_mid = p_first_filter->mac_mid;
  1109. p_second_filter->mac_lsb = p_first_filter->mac_lsb;
  1110. p_second_filter->vlan_id = p_first_filter->vlan_id;
  1111. p_second_filter->vni = p_first_filter->vni;
  1112. p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
  1113. p_first_filter->vport_id = vport_to_remove_from;
  1114. p_second_filter->action = ETH_FILTER_ACTION_ADD;
  1115. p_second_filter->vport_id = vport_to_add_to;
  1116. } else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) {
  1117. p_first_filter->vport_id = vport_to_add_to;
  1118. memcpy(p_second_filter, p_first_filter,
  1119. sizeof(*p_second_filter));
  1120. p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL;
  1121. p_second_filter->action = ETH_FILTER_ACTION_ADD;
  1122. } else {
  1123. action = qed_filter_action(p_filter_cmd->opcode);
  1124. if (action == MAX_ETH_FILTER_ACTION) {
  1125. DP_NOTICE(p_hwfn,
  1126. "%d is not supported yet\n",
  1127. p_filter_cmd->opcode);
  1128. return -EINVAL;
  1129. }
  1130. p_first_filter->action = action;
  1131. p_first_filter->vport_id = (p_filter_cmd->opcode ==
  1132. QED_FILTER_REMOVE) ?
  1133. vport_to_remove_from :
  1134. vport_to_add_to;
  1135. }
  1136. return 0;
  1137. }
  1138. int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn,
  1139. u16 opaque_fid,
  1140. struct qed_filter_ucast *p_filter_cmd,
  1141. enum spq_mode comp_mode,
  1142. struct qed_spq_comp_cb *p_comp_data)
  1143. {
  1144. struct vport_filter_update_ramrod_data *p_ramrod = NULL;
  1145. struct qed_spq_entry *p_ent = NULL;
  1146. struct eth_filter_cmd_header *p_header;
  1147. int rc;
  1148. rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
  1149. &p_ramrod, &p_ent,
  1150. comp_mode, p_comp_data);
  1151. if (rc) {
  1152. DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
  1153. return rc;
  1154. }
  1155. p_header = &p_ramrod->filter_cmd_hdr;
  1156. p_header->assert_on_error = p_filter_cmd->assert_on_error;
  1157. rc = qed_spq_post(p_hwfn, p_ent, NULL);
  1158. if (rc) {
  1159. DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc);
  1160. return rc;
  1161. }
  1162. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  1163. "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
  1164. (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" :
  1165. ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ?
  1166. "REMOVE" :
  1167. ((p_filter_cmd->opcode == QED_FILTER_MOVE) ?
  1168. "MOVE" : "REPLACE")),
  1169. (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" :
  1170. ((p_filter_cmd->type == QED_FILTER_VLAN) ?
  1171. "VLAN" : "MAC & VLAN"),
  1172. p_ramrod->filter_cmd_hdr.cmd_cnt,
  1173. p_filter_cmd->is_rx_filter,
  1174. p_filter_cmd->is_tx_filter);
  1175. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  1176. "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
  1177. p_filter_cmd->vport_to_add_to,
  1178. p_filter_cmd->vport_to_remove_from,
  1179. p_filter_cmd->mac[0],
  1180. p_filter_cmd->mac[1],
  1181. p_filter_cmd->mac[2],
  1182. p_filter_cmd->mac[3],
  1183. p_filter_cmd->mac[4],
  1184. p_filter_cmd->mac[5],
  1185. p_filter_cmd->vlan);
  1186. return 0;
  1187. }
  1188. /*******************************************************************************
  1189. * Description:
  1190. * Calculates crc 32 on a buffer
  1191. * Note: crc32_length MUST be aligned to 8
  1192. * Return:
  1193. ******************************************************************************/
  1194. static u32 qed_calc_crc32c(u8 *crc32_packet,
  1195. u32 crc32_length, u32 crc32_seed, u8 complement)
  1196. {
  1197. u32 byte = 0, bit = 0, crc32_result = crc32_seed;
  1198. u8 msb = 0, current_byte = 0;
  1199. if ((!crc32_packet) ||
  1200. (crc32_length == 0) ||
  1201. ((crc32_length % 8) != 0))
  1202. return crc32_result;
  1203. for (byte = 0; byte < crc32_length; byte++) {
  1204. current_byte = crc32_packet[byte];
  1205. for (bit = 0; bit < 8; bit++) {
  1206. msb = (u8)(crc32_result >> 31);
  1207. crc32_result = crc32_result << 1;
  1208. if (msb != (0x1 & (current_byte >> bit))) {
  1209. crc32_result = crc32_result ^ CRC32_POLY;
  1210. crc32_result |= 1; /*crc32_result[0] = 1;*/
  1211. }
  1212. }
  1213. }
  1214. return crc32_result;
  1215. }
  1216. static u32 qed_crc32c_le(u32 seed, u8 *mac, u32 len)
  1217. {
  1218. u32 packet_buf[2] = { 0 };
  1219. memcpy((u8 *)(&packet_buf[0]), &mac[0], 6);
  1220. return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
  1221. }
  1222. u8 qed_mcast_bin_from_mac(u8 *mac)
  1223. {
  1224. u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
  1225. mac, ETH_ALEN);
  1226. return crc & 0xff;
  1227. }
  1228. static int
  1229. qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn,
  1230. u16 opaque_fid,
  1231. struct qed_filter_mcast *p_filter_cmd,
  1232. enum spq_mode comp_mode,
  1233. struct qed_spq_comp_cb *p_comp_data)
  1234. {
  1235. unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
  1236. struct vport_update_ramrod_data *p_ramrod = NULL;
  1237. struct qed_spq_entry *p_ent = NULL;
  1238. struct qed_sp_init_data init_data;
  1239. u8 abs_vport_id = 0;
  1240. int rc, i;
  1241. if (p_filter_cmd->opcode == QED_FILTER_ADD)
  1242. rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
  1243. &abs_vport_id);
  1244. else
  1245. rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
  1246. &abs_vport_id);
  1247. if (rc)
  1248. return rc;
  1249. /* Get SPQ entry */
  1250. memset(&init_data, 0, sizeof(init_data));
  1251. init_data.cid = qed_spq_get_cid(p_hwfn);
  1252. init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
  1253. init_data.comp_mode = comp_mode;
  1254. init_data.p_comp_data = p_comp_data;
  1255. rc = qed_sp_init_request(p_hwfn, &p_ent,
  1256. ETH_RAMROD_VPORT_UPDATE,
  1257. PROTOCOLID_ETH, &init_data);
  1258. if (rc) {
  1259. DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
  1260. return rc;
  1261. }
  1262. p_ramrod = &p_ent->ramrod.vport_update;
  1263. p_ramrod->common.update_approx_mcast_flg = 1;
  1264. /* explicitly clear out the entire vector */
  1265. memset(&p_ramrod->approx_mcast.bins, 0,
  1266. sizeof(p_ramrod->approx_mcast.bins));
  1267. memset(bins, 0, sizeof(unsigned long) *
  1268. ETH_MULTICAST_MAC_BINS_IN_REGS);
  1269. /* filter ADD op is explicit set op and it removes
  1270. * any existing filters for the vport
  1271. */
  1272. if (p_filter_cmd->opcode == QED_FILTER_ADD) {
  1273. for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
  1274. u32 bit;
  1275. bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]);
  1276. __set_bit(bit, bins);
  1277. }
  1278. /* Convert to correct endianity */
  1279. for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
  1280. struct vport_update_ramrod_mcast *p_ramrod_bins;
  1281. u32 *p_bins = (u32 *)bins;
  1282. p_ramrod_bins = &p_ramrod->approx_mcast;
  1283. p_ramrod_bins->bins[i] = cpu_to_le32(p_bins[i]);
  1284. }
  1285. }
  1286. p_ramrod->common.vport_id = abs_vport_id;
  1287. return qed_spq_post(p_hwfn, p_ent, NULL);
  1288. }
  1289. static int qed_filter_mcast_cmd(struct qed_dev *cdev,
  1290. struct qed_filter_mcast *p_filter_cmd,
  1291. enum spq_mode comp_mode,
  1292. struct qed_spq_comp_cb *p_comp_data)
  1293. {
  1294. int rc = 0;
  1295. int i;
  1296. /* only ADD and REMOVE operations are supported for multi-cast */
  1297. if ((p_filter_cmd->opcode != QED_FILTER_ADD &&
  1298. (p_filter_cmd->opcode != QED_FILTER_REMOVE)) ||
  1299. (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS))
  1300. return -EINVAL;
  1301. for_each_hwfn(cdev, i) {
  1302. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1303. u16 opaque_fid;
  1304. if (IS_VF(cdev)) {
  1305. qed_vf_pf_filter_mcast(p_hwfn, p_filter_cmd);
  1306. continue;
  1307. }
  1308. opaque_fid = p_hwfn->hw_info.opaque_fid;
  1309. rc = qed_sp_eth_filter_mcast(p_hwfn,
  1310. opaque_fid,
  1311. p_filter_cmd,
  1312. comp_mode, p_comp_data);
  1313. }
  1314. return rc;
  1315. }
  1316. static int qed_filter_ucast_cmd(struct qed_dev *cdev,
  1317. struct qed_filter_ucast *p_filter_cmd,
  1318. enum spq_mode comp_mode,
  1319. struct qed_spq_comp_cb *p_comp_data)
  1320. {
  1321. int rc = 0;
  1322. int i;
  1323. for_each_hwfn(cdev, i) {
  1324. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1325. u16 opaque_fid;
  1326. if (IS_VF(cdev)) {
  1327. rc = qed_vf_pf_filter_ucast(p_hwfn, p_filter_cmd);
  1328. continue;
  1329. }
  1330. opaque_fid = p_hwfn->hw_info.opaque_fid;
  1331. rc = qed_sp_eth_filter_ucast(p_hwfn,
  1332. opaque_fid,
  1333. p_filter_cmd,
  1334. comp_mode, p_comp_data);
  1335. if (rc)
  1336. break;
  1337. }
  1338. return rc;
  1339. }
  1340. /* Statistics related code */
  1341. static void __qed_get_vport_pstats_addrlen(struct qed_hwfn *p_hwfn,
  1342. u32 *p_addr,
  1343. u32 *p_len, u16 statistics_bin)
  1344. {
  1345. if (IS_PF(p_hwfn->cdev)) {
  1346. *p_addr = BAR0_MAP_REG_PSDM_RAM +
  1347. PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
  1348. *p_len = sizeof(struct eth_pstorm_per_queue_stat);
  1349. } else {
  1350. struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
  1351. struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
  1352. *p_addr = p_resp->pfdev_info.stats_info.pstats.address;
  1353. *p_len = p_resp->pfdev_info.stats_info.pstats.len;
  1354. }
  1355. }
  1356. static void __qed_get_vport_pstats(struct qed_hwfn *p_hwfn,
  1357. struct qed_ptt *p_ptt,
  1358. struct qed_eth_stats *p_stats,
  1359. u16 statistics_bin)
  1360. {
  1361. struct eth_pstorm_per_queue_stat pstats;
  1362. u32 pstats_addr = 0, pstats_len = 0;
  1363. __qed_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
  1364. statistics_bin);
  1365. memset(&pstats, 0, sizeof(pstats));
  1366. qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);
  1367. p_stats->common.tx_ucast_bytes +=
  1368. HILO_64_REGPAIR(pstats.sent_ucast_bytes);
  1369. p_stats->common.tx_mcast_bytes +=
  1370. HILO_64_REGPAIR(pstats.sent_mcast_bytes);
  1371. p_stats->common.tx_bcast_bytes +=
  1372. HILO_64_REGPAIR(pstats.sent_bcast_bytes);
  1373. p_stats->common.tx_ucast_pkts +=
  1374. HILO_64_REGPAIR(pstats.sent_ucast_pkts);
  1375. p_stats->common.tx_mcast_pkts +=
  1376. HILO_64_REGPAIR(pstats.sent_mcast_pkts);
  1377. p_stats->common.tx_bcast_pkts +=
  1378. HILO_64_REGPAIR(pstats.sent_bcast_pkts);
  1379. p_stats->common.tx_err_drop_pkts +=
  1380. HILO_64_REGPAIR(pstats.error_drop_pkts);
  1381. }
  1382. static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn,
  1383. struct qed_ptt *p_ptt,
  1384. struct qed_eth_stats *p_stats,
  1385. u16 statistics_bin)
  1386. {
  1387. struct tstorm_per_port_stat tstats;
  1388. u32 tstats_addr, tstats_len;
  1389. if (IS_PF(p_hwfn->cdev)) {
  1390. tstats_addr = BAR0_MAP_REG_TSDM_RAM +
  1391. TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
  1392. tstats_len = sizeof(struct tstorm_per_port_stat);
  1393. } else {
  1394. struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
  1395. struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
  1396. tstats_addr = p_resp->pfdev_info.stats_info.tstats.address;
  1397. tstats_len = p_resp->pfdev_info.stats_info.tstats.len;
  1398. }
  1399. memset(&tstats, 0, sizeof(tstats));
  1400. qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);
  1401. p_stats->common.mftag_filter_discards +=
  1402. HILO_64_REGPAIR(tstats.mftag_filter_discard);
  1403. p_stats->common.mac_filter_discards +=
  1404. HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
  1405. }
  1406. static void __qed_get_vport_ustats_addrlen(struct qed_hwfn *p_hwfn,
  1407. u32 *p_addr,
  1408. u32 *p_len, u16 statistics_bin)
  1409. {
  1410. if (IS_PF(p_hwfn->cdev)) {
  1411. *p_addr = BAR0_MAP_REG_USDM_RAM +
  1412. USTORM_QUEUE_STAT_OFFSET(statistics_bin);
  1413. *p_len = sizeof(struct eth_ustorm_per_queue_stat);
  1414. } else {
  1415. struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
  1416. struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
  1417. *p_addr = p_resp->pfdev_info.stats_info.ustats.address;
  1418. *p_len = p_resp->pfdev_info.stats_info.ustats.len;
  1419. }
  1420. }
  1421. static void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn,
  1422. struct qed_ptt *p_ptt,
  1423. struct qed_eth_stats *p_stats,
  1424. u16 statistics_bin)
  1425. {
  1426. struct eth_ustorm_per_queue_stat ustats;
  1427. u32 ustats_addr = 0, ustats_len = 0;
  1428. __qed_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
  1429. statistics_bin);
  1430. memset(&ustats, 0, sizeof(ustats));
  1431. qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);
  1432. p_stats->common.rx_ucast_bytes +=
  1433. HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
  1434. p_stats->common.rx_mcast_bytes +=
  1435. HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
  1436. p_stats->common.rx_bcast_bytes +=
  1437. HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
  1438. p_stats->common.rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
  1439. p_stats->common.rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
  1440. p_stats->common.rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
  1441. }
  1442. static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn,
  1443. u32 *p_addr,
  1444. u32 *p_len, u16 statistics_bin)
  1445. {
  1446. if (IS_PF(p_hwfn->cdev)) {
  1447. *p_addr = BAR0_MAP_REG_MSDM_RAM +
  1448. MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
  1449. *p_len = sizeof(struct eth_mstorm_per_queue_stat);
  1450. } else {
  1451. struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
  1452. struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
  1453. *p_addr = p_resp->pfdev_info.stats_info.mstats.address;
  1454. *p_len = p_resp->pfdev_info.stats_info.mstats.len;
  1455. }
  1456. }
  1457. static void __qed_get_vport_mstats(struct qed_hwfn *p_hwfn,
  1458. struct qed_ptt *p_ptt,
  1459. struct qed_eth_stats *p_stats,
  1460. u16 statistics_bin)
  1461. {
  1462. struct eth_mstorm_per_queue_stat mstats;
  1463. u32 mstats_addr = 0, mstats_len = 0;
  1464. __qed_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
  1465. statistics_bin);
  1466. memset(&mstats, 0, sizeof(mstats));
  1467. qed_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);
  1468. p_stats->common.no_buff_discards +=
  1469. HILO_64_REGPAIR(mstats.no_buff_discard);
  1470. p_stats->common.packet_too_big_discard +=
  1471. HILO_64_REGPAIR(mstats.packet_too_big_discard);
  1472. p_stats->common.ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard);
  1473. p_stats->common.tpa_coalesced_pkts +=
  1474. HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
  1475. p_stats->common.tpa_coalesced_events +=
  1476. HILO_64_REGPAIR(mstats.tpa_coalesced_events);
  1477. p_stats->common.tpa_aborts_num +=
  1478. HILO_64_REGPAIR(mstats.tpa_aborts_num);
  1479. p_stats->common.tpa_coalesced_bytes +=
  1480. HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
  1481. }
  1482. static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn,
  1483. struct qed_ptt *p_ptt,
  1484. struct qed_eth_stats *p_stats)
  1485. {
  1486. struct qed_eth_stats_common *p_common = &p_stats->common;
  1487. struct port_stats port_stats;
  1488. int j;
  1489. memset(&port_stats, 0, sizeof(port_stats));
  1490. qed_memcpy_from(p_hwfn, p_ptt, &port_stats,
  1491. p_hwfn->mcp_info->port_addr +
  1492. offsetof(struct public_port, stats),
  1493. sizeof(port_stats));
  1494. p_common->rx_64_byte_packets += port_stats.eth.r64;
  1495. p_common->rx_65_to_127_byte_packets += port_stats.eth.r127;
  1496. p_common->rx_128_to_255_byte_packets += port_stats.eth.r255;
  1497. p_common->rx_256_to_511_byte_packets += port_stats.eth.r511;
  1498. p_common->rx_512_to_1023_byte_packets += port_stats.eth.r1023;
  1499. p_common->rx_1024_to_1518_byte_packets += port_stats.eth.r1518;
  1500. p_common->rx_crc_errors += port_stats.eth.rfcs;
  1501. p_common->rx_mac_crtl_frames += port_stats.eth.rxcf;
  1502. p_common->rx_pause_frames += port_stats.eth.rxpf;
  1503. p_common->rx_pfc_frames += port_stats.eth.rxpp;
  1504. p_common->rx_align_errors += port_stats.eth.raln;
  1505. p_common->rx_carrier_errors += port_stats.eth.rfcr;
  1506. p_common->rx_oversize_packets += port_stats.eth.rovr;
  1507. p_common->rx_jabbers += port_stats.eth.rjbr;
  1508. p_common->rx_undersize_packets += port_stats.eth.rund;
  1509. p_common->rx_fragments += port_stats.eth.rfrg;
  1510. p_common->tx_64_byte_packets += port_stats.eth.t64;
  1511. p_common->tx_65_to_127_byte_packets += port_stats.eth.t127;
  1512. p_common->tx_128_to_255_byte_packets += port_stats.eth.t255;
  1513. p_common->tx_256_to_511_byte_packets += port_stats.eth.t511;
  1514. p_common->tx_512_to_1023_byte_packets += port_stats.eth.t1023;
  1515. p_common->tx_1024_to_1518_byte_packets += port_stats.eth.t1518;
  1516. p_common->tx_pause_frames += port_stats.eth.txpf;
  1517. p_common->tx_pfc_frames += port_stats.eth.txpp;
  1518. p_common->rx_mac_bytes += port_stats.eth.rbyte;
  1519. p_common->rx_mac_uc_packets += port_stats.eth.rxuca;
  1520. p_common->rx_mac_mc_packets += port_stats.eth.rxmca;
  1521. p_common->rx_mac_bc_packets += port_stats.eth.rxbca;
  1522. p_common->rx_mac_frames_ok += port_stats.eth.rxpok;
  1523. p_common->tx_mac_bytes += port_stats.eth.tbyte;
  1524. p_common->tx_mac_uc_packets += port_stats.eth.txuca;
  1525. p_common->tx_mac_mc_packets += port_stats.eth.txmca;
  1526. p_common->tx_mac_bc_packets += port_stats.eth.txbca;
  1527. p_common->tx_mac_ctrl_frames += port_stats.eth.txcf;
  1528. for (j = 0; j < 8; j++) {
  1529. p_common->brb_truncates += port_stats.brb.brb_truncate[j];
  1530. p_common->brb_discards += port_stats.brb.brb_discard[j];
  1531. }
  1532. if (QED_IS_BB(p_hwfn->cdev)) {
  1533. struct qed_eth_stats_bb *p_bb = &p_stats->bb;
  1534. p_bb->rx_1519_to_1522_byte_packets +=
  1535. port_stats.eth.u0.bb0.r1522;
  1536. p_bb->rx_1519_to_2047_byte_packets +=
  1537. port_stats.eth.u0.bb0.r2047;
  1538. p_bb->rx_2048_to_4095_byte_packets +=
  1539. port_stats.eth.u0.bb0.r4095;
  1540. p_bb->rx_4096_to_9216_byte_packets +=
  1541. port_stats.eth.u0.bb0.r9216;
  1542. p_bb->rx_9217_to_16383_byte_packets +=
  1543. port_stats.eth.u0.bb0.r16383;
  1544. p_bb->tx_1519_to_2047_byte_packets +=
  1545. port_stats.eth.u1.bb1.t2047;
  1546. p_bb->tx_2048_to_4095_byte_packets +=
  1547. port_stats.eth.u1.bb1.t4095;
  1548. p_bb->tx_4096_to_9216_byte_packets +=
  1549. port_stats.eth.u1.bb1.t9216;
  1550. p_bb->tx_9217_to_16383_byte_packets +=
  1551. port_stats.eth.u1.bb1.t16383;
  1552. p_bb->tx_lpi_entry_count += port_stats.eth.u2.bb2.tlpiec;
  1553. p_bb->tx_total_collisions += port_stats.eth.u2.bb2.tncl;
  1554. } else {
  1555. struct qed_eth_stats_ah *p_ah = &p_stats->ah;
  1556. p_ah->rx_1519_to_max_byte_packets +=
  1557. port_stats.eth.u0.ah0.r1519_to_max;
  1558. p_ah->tx_1519_to_max_byte_packets =
  1559. port_stats.eth.u1.ah1.t1519_to_max;
  1560. }
  1561. }
  1562. static void __qed_get_vport_stats(struct qed_hwfn *p_hwfn,
  1563. struct qed_ptt *p_ptt,
  1564. struct qed_eth_stats *stats,
  1565. u16 statistics_bin, bool b_get_port_stats)
  1566. {
  1567. __qed_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
  1568. __qed_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
  1569. __qed_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin);
  1570. __qed_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
  1571. if (b_get_port_stats && p_hwfn->mcp_info)
  1572. __qed_get_vport_port_stats(p_hwfn, p_ptt, stats);
  1573. }
  1574. static void _qed_get_vport_stats(struct qed_dev *cdev,
  1575. struct qed_eth_stats *stats)
  1576. {
  1577. u8 fw_vport = 0;
  1578. int i;
  1579. memset(stats, 0, sizeof(*stats));
  1580. for_each_hwfn(cdev, i) {
  1581. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1582. struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
  1583. : NULL;
  1584. if (IS_PF(cdev)) {
  1585. /* The main vport index is relative first */
  1586. if (qed_fw_vport(p_hwfn, 0, &fw_vport)) {
  1587. DP_ERR(p_hwfn, "No vport available!\n");
  1588. goto out;
  1589. }
  1590. }
  1591. if (IS_PF(cdev) && !p_ptt) {
  1592. DP_ERR(p_hwfn, "Failed to acquire ptt\n");
  1593. continue;
  1594. }
  1595. __qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
  1596. IS_PF(cdev) ? true : false);
  1597. out:
  1598. if (IS_PF(cdev) && p_ptt)
  1599. qed_ptt_release(p_hwfn, p_ptt);
  1600. }
  1601. }
  1602. void qed_get_vport_stats(struct qed_dev *cdev, struct qed_eth_stats *stats)
  1603. {
  1604. u32 i;
  1605. if (!cdev) {
  1606. memset(stats, 0, sizeof(*stats));
  1607. return;
  1608. }
  1609. _qed_get_vport_stats(cdev, stats);
  1610. if (!cdev->reset_stats)
  1611. return;
  1612. /* Reduce the statistics baseline */
  1613. for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++)
  1614. ((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i];
  1615. }
  1616. /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
  1617. void qed_reset_vport_stats(struct qed_dev *cdev)
  1618. {
  1619. int i;
  1620. for_each_hwfn(cdev, i) {
  1621. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1622. struct eth_mstorm_per_queue_stat mstats;
  1623. struct eth_ustorm_per_queue_stat ustats;
  1624. struct eth_pstorm_per_queue_stat pstats;
  1625. struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
  1626. : NULL;
  1627. u32 addr = 0, len = 0;
  1628. if (IS_PF(cdev) && !p_ptt) {
  1629. DP_ERR(p_hwfn, "Failed to acquire ptt\n");
  1630. continue;
  1631. }
  1632. memset(&mstats, 0, sizeof(mstats));
  1633. __qed_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
  1634. qed_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
  1635. memset(&ustats, 0, sizeof(ustats));
  1636. __qed_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
  1637. qed_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
  1638. memset(&pstats, 0, sizeof(pstats));
  1639. __qed_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
  1640. qed_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
  1641. if (IS_PF(cdev))
  1642. qed_ptt_release(p_hwfn, p_ptt);
  1643. }
  1644. /* PORT statistics are not necessarily reset, so we need to
  1645. * read and create a baseline for future statistics.
  1646. */
  1647. if (!cdev->reset_stats)
  1648. DP_INFO(cdev, "Reset stats not allocated\n");
  1649. else
  1650. _qed_get_vport_stats(cdev, cdev->reset_stats);
  1651. }
  1652. static void
  1653. qed_arfs_mode_configure(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
  1654. struct qed_arfs_config_params *p_cfg_params)
  1655. {
  1656. if (p_cfg_params->arfs_enable) {
  1657. qed_set_rfs_mode_enable(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
  1658. p_cfg_params->tcp, p_cfg_params->udp,
  1659. p_cfg_params->ipv4, p_cfg_params->ipv6);
  1660. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  1661. "tcp = %s, udp = %s, ipv4 = %s, ipv6 =%s\n",
  1662. p_cfg_params->tcp ? "Enable" : "Disable",
  1663. p_cfg_params->udp ? "Enable" : "Disable",
  1664. p_cfg_params->ipv4 ? "Enable" : "Disable",
  1665. p_cfg_params->ipv6 ? "Enable" : "Disable");
  1666. } else {
  1667. qed_set_rfs_mode_disable(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
  1668. }
  1669. DP_VERBOSE(p_hwfn, QED_MSG_SP, "Configured ARFS mode : %s\n",
  1670. p_cfg_params->arfs_enable ? "Enable" : "Disable");
  1671. }
  1672. static int
  1673. qed_configure_rfs_ntuple_filter(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
  1674. struct qed_spq_comp_cb *p_cb,
  1675. dma_addr_t p_addr, u16 length, u16 qid,
  1676. u8 vport_id, bool b_is_add)
  1677. {
  1678. struct rx_update_gft_filter_data *p_ramrod = NULL;
  1679. struct qed_spq_entry *p_ent = NULL;
  1680. struct qed_sp_init_data init_data;
  1681. u16 abs_rx_q_id = 0;
  1682. u8 abs_vport_id = 0;
  1683. int rc = -EINVAL;
  1684. rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id);
  1685. if (rc)
  1686. return rc;
  1687. rc = qed_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id);
  1688. if (rc)
  1689. return rc;
  1690. /* Get SPQ entry */
  1691. memset(&init_data, 0, sizeof(init_data));
  1692. init_data.cid = qed_spq_get_cid(p_hwfn);
  1693. init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
  1694. if (p_cb) {
  1695. init_data.comp_mode = QED_SPQ_MODE_CB;
  1696. init_data.p_comp_data = p_cb;
  1697. } else {
  1698. init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
  1699. }
  1700. rc = qed_sp_init_request(p_hwfn, &p_ent,
  1701. ETH_RAMROD_GFT_UPDATE_FILTER,
  1702. PROTOCOLID_ETH, &init_data);
  1703. if (rc)
  1704. return rc;
  1705. p_ramrod = &p_ent->ramrod.rx_update_gft;
  1706. DMA_REGPAIR_LE(p_ramrod->pkt_hdr_addr, p_addr);
  1707. p_ramrod->pkt_hdr_length = cpu_to_le16(length);
  1708. p_ramrod->rx_qid_or_action_icid = cpu_to_le16(abs_rx_q_id);
  1709. p_ramrod->vport_id = abs_vport_id;
  1710. p_ramrod->filter_type = RFS_FILTER_TYPE;
  1711. p_ramrod->filter_action = b_is_add ? GFT_ADD_FILTER : GFT_DELETE_FILTER;
  1712. DP_VERBOSE(p_hwfn, QED_MSG_SP,
  1713. "V[%0x], Q[%04x] - %s filter from 0x%llx [length %04xb]\n",
  1714. abs_vport_id, abs_rx_q_id,
  1715. b_is_add ? "Adding" : "Removing", (u64)p_addr, length);
  1716. return qed_spq_post(p_hwfn, p_ent, NULL);
  1717. }
  1718. int qed_get_rxq_coalesce(struct qed_hwfn *p_hwfn,
  1719. struct qed_ptt *p_ptt,
  1720. struct qed_queue_cid *p_cid, u16 *p_rx_coal)
  1721. {
  1722. u32 coalesce, address, is_valid;
  1723. struct cau_sb_entry sb_entry;
  1724. u8 timer_res;
  1725. int rc;
  1726. rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
  1727. p_cid->sb_igu_id * sizeof(u64),
  1728. (u64)(uintptr_t)&sb_entry, 2, 0);
  1729. if (rc) {
  1730. DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
  1731. return rc;
  1732. }
  1733. timer_res = GET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0);
  1734. address = BAR0_MAP_REG_USDM_RAM +
  1735. USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
  1736. coalesce = qed_rd(p_hwfn, p_ptt, address);
  1737. is_valid = GET_FIELD(coalesce, COALESCING_TIMESET_VALID);
  1738. if (!is_valid)
  1739. return -EINVAL;
  1740. coalesce = GET_FIELD(coalesce, COALESCING_TIMESET_TIMESET);
  1741. *p_rx_coal = (u16)(coalesce << timer_res);
  1742. return 0;
  1743. }
  1744. int qed_get_txq_coalesce(struct qed_hwfn *p_hwfn,
  1745. struct qed_ptt *p_ptt,
  1746. struct qed_queue_cid *p_cid, u16 *p_tx_coal)
  1747. {
  1748. u32 coalesce, address, is_valid;
  1749. struct cau_sb_entry sb_entry;
  1750. u8 timer_res;
  1751. int rc;
  1752. rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
  1753. p_cid->sb_igu_id * sizeof(u64),
  1754. (u64)(uintptr_t)&sb_entry, 2, 0);
  1755. if (rc) {
  1756. DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
  1757. return rc;
  1758. }
  1759. timer_res = GET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1);
  1760. address = BAR0_MAP_REG_XSDM_RAM +
  1761. XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
  1762. coalesce = qed_rd(p_hwfn, p_ptt, address);
  1763. is_valid = GET_FIELD(coalesce, COALESCING_TIMESET_VALID);
  1764. if (!is_valid)
  1765. return -EINVAL;
  1766. coalesce = GET_FIELD(coalesce, COALESCING_TIMESET_TIMESET);
  1767. *p_tx_coal = (u16)(coalesce << timer_res);
  1768. return 0;
  1769. }
  1770. int qed_get_queue_coalesce(struct qed_hwfn *p_hwfn, u16 *p_coal, void *handle)
  1771. {
  1772. struct qed_queue_cid *p_cid = handle;
  1773. struct qed_ptt *p_ptt;
  1774. int rc = 0;
  1775. if (IS_VF(p_hwfn->cdev)) {
  1776. rc = qed_vf_pf_get_coalesce(p_hwfn, p_coal, p_cid);
  1777. if (rc)
  1778. DP_NOTICE(p_hwfn, "Unable to read queue coalescing\n");
  1779. return rc;
  1780. }
  1781. p_ptt = qed_ptt_acquire(p_hwfn);
  1782. if (!p_ptt)
  1783. return -EAGAIN;
  1784. if (p_cid->b_is_rx) {
  1785. rc = qed_get_rxq_coalesce(p_hwfn, p_ptt, p_cid, p_coal);
  1786. if (rc)
  1787. goto out;
  1788. } else {
  1789. rc = qed_get_txq_coalesce(p_hwfn, p_ptt, p_cid, p_coal);
  1790. if (rc)
  1791. goto out;
  1792. }
  1793. out:
  1794. qed_ptt_release(p_hwfn, p_ptt);
  1795. return rc;
  1796. }
  1797. static int qed_fill_eth_dev_info(struct qed_dev *cdev,
  1798. struct qed_dev_eth_info *info)
  1799. {
  1800. int i;
  1801. memset(info, 0, sizeof(*info));
  1802. info->num_tc = 1;
  1803. if (IS_PF(cdev)) {
  1804. int max_vf_vlan_filters = 0;
  1805. int max_vf_mac_filters = 0;
  1806. if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
  1807. u16 num_queues = 0;
  1808. /* Since the feature controls only queue-zones,
  1809. * make sure we have the contexts [rx, tx, xdp] to
  1810. * match.
  1811. */
  1812. for_each_hwfn(cdev, i) {
  1813. struct qed_hwfn *hwfn = &cdev->hwfns[i];
  1814. u16 l2_queues = (u16)FEAT_NUM(hwfn,
  1815. QED_PF_L2_QUE);
  1816. u16 cids;
  1817. cids = hwfn->pf_params.eth_pf_params.num_cons;
  1818. num_queues += min_t(u16, l2_queues, cids / 3);
  1819. }
  1820. /* queues might theoretically be >256, but interrupts'
  1821. * upper-limit guarantes that it would fit in a u8.
  1822. */
  1823. if (cdev->int_params.fp_msix_cnt) {
  1824. u8 irqs = cdev->int_params.fp_msix_cnt;
  1825. info->num_queues = (u8)min_t(u16,
  1826. num_queues, irqs);
  1827. }
  1828. } else {
  1829. info->num_queues = cdev->num_hwfns;
  1830. }
  1831. if (IS_QED_SRIOV(cdev)) {
  1832. max_vf_vlan_filters = cdev->p_iov_info->total_vfs *
  1833. QED_ETH_VF_NUM_VLAN_FILTERS;
  1834. max_vf_mac_filters = cdev->p_iov_info->total_vfs *
  1835. QED_ETH_VF_NUM_MAC_FILTERS;
  1836. }
  1837. info->num_vlan_filters = RESC_NUM(QED_LEADING_HWFN(cdev),
  1838. QED_VLAN) -
  1839. max_vf_vlan_filters;
  1840. info->num_mac_filters = RESC_NUM(QED_LEADING_HWFN(cdev),
  1841. QED_MAC) -
  1842. max_vf_mac_filters;
  1843. ether_addr_copy(info->port_mac,
  1844. cdev->hwfns[0].hw_info.hw_mac_addr);
  1845. info->xdp_supported = true;
  1846. } else {
  1847. u16 total_cids = 0;
  1848. /* Determine queues & XDP support */
  1849. for_each_hwfn(cdev, i) {
  1850. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1851. u8 queues, cids;
  1852. qed_vf_get_num_cids(p_hwfn, &cids);
  1853. qed_vf_get_num_rxqs(p_hwfn, &queues);
  1854. info->num_queues += queues;
  1855. total_cids += cids;
  1856. }
  1857. /* Enable VF XDP in case PF guarntees sufficient connections */
  1858. if (total_cids >= info->num_queues * 3)
  1859. info->xdp_supported = true;
  1860. qed_vf_get_num_vlan_filters(&cdev->hwfns[0],
  1861. (u8 *)&info->num_vlan_filters);
  1862. qed_vf_get_num_mac_filters(&cdev->hwfns[0],
  1863. (u8 *)&info->num_mac_filters);
  1864. qed_vf_get_port_mac(&cdev->hwfns[0], info->port_mac);
  1865. info->is_legacy = !!cdev->hwfns[0].vf_iov_info->b_pre_fp_hsi;
  1866. }
  1867. qed_fill_dev_info(cdev, &info->common);
  1868. if (IS_VF(cdev))
  1869. eth_zero_addr(info->common.hw_mac);
  1870. return 0;
  1871. }
  1872. static void qed_register_eth_ops(struct qed_dev *cdev,
  1873. struct qed_eth_cb_ops *ops, void *cookie)
  1874. {
  1875. cdev->protocol_ops.eth = ops;
  1876. cdev->ops_cookie = cookie;
  1877. /* For VF, we start bulletin reading */
  1878. if (IS_VF(cdev))
  1879. qed_vf_start_iov_wq(cdev);
  1880. }
  1881. static bool qed_check_mac(struct qed_dev *cdev, u8 *mac)
  1882. {
  1883. if (IS_PF(cdev))
  1884. return true;
  1885. return qed_vf_check_mac(&cdev->hwfns[0], mac);
  1886. }
  1887. static int qed_start_vport(struct qed_dev *cdev,
  1888. struct qed_start_vport_params *params)
  1889. {
  1890. int rc, i;
  1891. for_each_hwfn(cdev, i) {
  1892. struct qed_sp_vport_start_params start = { 0 };
  1893. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1894. start.tpa_mode = params->gro_enable ? QED_TPA_MODE_GRO :
  1895. QED_TPA_MODE_NONE;
  1896. start.remove_inner_vlan = params->remove_inner_vlan;
  1897. start.only_untagged = true; /* untagged only */
  1898. start.drop_ttl0 = params->drop_ttl0;
  1899. start.opaque_fid = p_hwfn->hw_info.opaque_fid;
  1900. start.concrete_fid = p_hwfn->hw_info.concrete_fid;
  1901. start.handle_ptp_pkts = params->handle_ptp_pkts;
  1902. start.vport_id = params->vport_id;
  1903. start.max_buffers_per_cqe = 16;
  1904. start.mtu = params->mtu;
  1905. rc = qed_sp_vport_start(p_hwfn, &start);
  1906. if (rc) {
  1907. DP_ERR(cdev, "Failed to start VPORT\n");
  1908. return rc;
  1909. }
  1910. rc = qed_hw_start_fastpath(p_hwfn);
  1911. if (rc) {
  1912. DP_ERR(cdev, "Failed to start VPORT fastpath\n");
  1913. return rc;
  1914. }
  1915. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  1916. "Started V-PORT %d with MTU %d\n",
  1917. start.vport_id, start.mtu);
  1918. }
  1919. if (params->clear_stats)
  1920. qed_reset_vport_stats(cdev);
  1921. return 0;
  1922. }
  1923. static int qed_stop_vport(struct qed_dev *cdev, u8 vport_id)
  1924. {
  1925. int rc, i;
  1926. for_each_hwfn(cdev, i) {
  1927. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  1928. rc = qed_sp_vport_stop(p_hwfn,
  1929. p_hwfn->hw_info.opaque_fid, vport_id);
  1930. if (rc) {
  1931. DP_ERR(cdev, "Failed to stop VPORT\n");
  1932. return rc;
  1933. }
  1934. }
  1935. return 0;
  1936. }
  1937. static int qed_update_vport_rss(struct qed_dev *cdev,
  1938. struct qed_update_vport_rss_params *input,
  1939. struct qed_rss_params *rss)
  1940. {
  1941. int i, fn;
  1942. /* Update configuration with what's correct regardless of CMT */
  1943. rss->update_rss_config = 1;
  1944. rss->rss_enable = 1;
  1945. rss->update_rss_capabilities = 1;
  1946. rss->update_rss_ind_table = 1;
  1947. rss->update_rss_key = 1;
  1948. rss->rss_caps = input->rss_caps;
  1949. memcpy(rss->rss_key, input->rss_key, QED_RSS_KEY_SIZE * sizeof(u32));
  1950. /* In regular scenario, we'd simply need to take input handlers.
  1951. * But in CMT, we'd have to split the handlers according to the
  1952. * engine they were configured on. We'd then have to understand
  1953. * whether RSS is really required, since 2-queues on CMT doesn't
  1954. * require RSS.
  1955. */
  1956. if (cdev->num_hwfns == 1) {
  1957. memcpy(rss->rss_ind_table,
  1958. input->rss_ind_table,
  1959. QED_RSS_IND_TABLE_SIZE * sizeof(void *));
  1960. rss->rss_table_size_log = 7;
  1961. return 0;
  1962. }
  1963. /* Start by copying the non-spcific information to the 2nd copy */
  1964. memcpy(&rss[1], &rss[0], sizeof(struct qed_rss_params));
  1965. /* CMT should be round-robin */
  1966. for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
  1967. struct qed_queue_cid *cid = input->rss_ind_table[i];
  1968. struct qed_rss_params *t_rss;
  1969. if (cid->p_owner == QED_LEADING_HWFN(cdev))
  1970. t_rss = &rss[0];
  1971. else
  1972. t_rss = &rss[1];
  1973. t_rss->rss_ind_table[i / cdev->num_hwfns] = cid;
  1974. }
  1975. /* Make sure RSS is actually required */
  1976. for_each_hwfn(cdev, fn) {
  1977. for (i = 1; i < QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns; i++) {
  1978. if (rss[fn].rss_ind_table[i] !=
  1979. rss[fn].rss_ind_table[0])
  1980. break;
  1981. }
  1982. if (i == QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns) {
  1983. DP_VERBOSE(cdev, NETIF_MSG_IFUP,
  1984. "CMT - 1 queue per-hwfn; Disabling RSS\n");
  1985. return -EINVAL;
  1986. }
  1987. rss[fn].rss_table_size_log = 6;
  1988. }
  1989. return 0;
  1990. }
  1991. static int qed_update_vport(struct qed_dev *cdev,
  1992. struct qed_update_vport_params *params)
  1993. {
  1994. struct qed_sp_vport_update_params sp_params;
  1995. struct qed_rss_params *rss;
  1996. int rc = 0, i;
  1997. if (!cdev)
  1998. return -ENODEV;
  1999. rss = vzalloc(sizeof(*rss) * cdev->num_hwfns);
  2000. if (!rss)
  2001. return -ENOMEM;
  2002. memset(&sp_params, 0, sizeof(sp_params));
  2003. /* Translate protocol params into sp params */
  2004. sp_params.vport_id = params->vport_id;
  2005. sp_params.update_vport_active_rx_flg = params->update_vport_active_flg;
  2006. sp_params.update_vport_active_tx_flg = params->update_vport_active_flg;
  2007. sp_params.vport_active_rx_flg = params->vport_active_flg;
  2008. sp_params.vport_active_tx_flg = params->vport_active_flg;
  2009. sp_params.update_tx_switching_flg = params->update_tx_switching_flg;
  2010. sp_params.tx_switching_flg = params->tx_switching_flg;
  2011. sp_params.accept_any_vlan = params->accept_any_vlan;
  2012. sp_params.update_accept_any_vlan_flg =
  2013. params->update_accept_any_vlan_flg;
  2014. /* Prepare the RSS configuration */
  2015. if (params->update_rss_flg)
  2016. if (qed_update_vport_rss(cdev, &params->rss_params, rss))
  2017. params->update_rss_flg = 0;
  2018. for_each_hwfn(cdev, i) {
  2019. struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
  2020. if (params->update_rss_flg)
  2021. sp_params.rss_params = &rss[i];
  2022. sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
  2023. rc = qed_sp_vport_update(p_hwfn, &sp_params,
  2024. QED_SPQ_MODE_EBLOCK,
  2025. NULL);
  2026. if (rc) {
  2027. DP_ERR(cdev, "Failed to update VPORT\n");
  2028. goto out;
  2029. }
  2030. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  2031. "Updated V-PORT %d: active_flag %d [update %d]\n",
  2032. params->vport_id, params->vport_active_flg,
  2033. params->update_vport_active_flg);
  2034. }
  2035. out:
  2036. vfree(rss);
  2037. return rc;
  2038. }
  2039. static int qed_start_rxq(struct qed_dev *cdev,
  2040. u8 rss_num,
  2041. struct qed_queue_start_common_params *p_params,
  2042. u16 bd_max_bytes,
  2043. dma_addr_t bd_chain_phys_addr,
  2044. dma_addr_t cqe_pbl_addr,
  2045. u16 cqe_pbl_size,
  2046. struct qed_rxq_start_ret_params *ret_params)
  2047. {
  2048. struct qed_hwfn *p_hwfn;
  2049. int rc, hwfn_index;
  2050. hwfn_index = rss_num % cdev->num_hwfns;
  2051. p_hwfn = &cdev->hwfns[hwfn_index];
  2052. p_params->queue_id = p_params->queue_id / cdev->num_hwfns;
  2053. p_params->stats_id = p_params->vport_id;
  2054. rc = qed_eth_rx_queue_start(p_hwfn,
  2055. p_hwfn->hw_info.opaque_fid,
  2056. p_params,
  2057. bd_max_bytes,
  2058. bd_chain_phys_addr,
  2059. cqe_pbl_addr, cqe_pbl_size, ret_params);
  2060. if (rc) {
  2061. DP_ERR(cdev, "Failed to start RXQ#%d\n", p_params->queue_id);
  2062. return rc;
  2063. }
  2064. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  2065. "Started RX-Q %d [rss_num %d] on V-PORT %d and SB igu %d\n",
  2066. p_params->queue_id, rss_num, p_params->vport_id,
  2067. p_params->p_sb->igu_sb_id);
  2068. return 0;
  2069. }
  2070. static int qed_stop_rxq(struct qed_dev *cdev, u8 rss_id, void *handle)
  2071. {
  2072. int rc, hwfn_index;
  2073. struct qed_hwfn *p_hwfn;
  2074. hwfn_index = rss_id % cdev->num_hwfns;
  2075. p_hwfn = &cdev->hwfns[hwfn_index];
  2076. rc = qed_eth_rx_queue_stop(p_hwfn, handle, false, false);
  2077. if (rc) {
  2078. DP_ERR(cdev, "Failed to stop RXQ#%02x\n", rss_id);
  2079. return rc;
  2080. }
  2081. return 0;
  2082. }
  2083. static int qed_start_txq(struct qed_dev *cdev,
  2084. u8 rss_num,
  2085. struct qed_queue_start_common_params *p_params,
  2086. dma_addr_t pbl_addr,
  2087. u16 pbl_size,
  2088. struct qed_txq_start_ret_params *ret_params)
  2089. {
  2090. struct qed_hwfn *p_hwfn;
  2091. int rc, hwfn_index;
  2092. hwfn_index = rss_num % cdev->num_hwfns;
  2093. p_hwfn = &cdev->hwfns[hwfn_index];
  2094. p_params->queue_id = p_params->queue_id / cdev->num_hwfns;
  2095. p_params->stats_id = p_params->vport_id;
  2096. rc = qed_eth_tx_queue_start(p_hwfn,
  2097. p_hwfn->hw_info.opaque_fid,
  2098. p_params, 0,
  2099. pbl_addr, pbl_size, ret_params);
  2100. if (rc) {
  2101. DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id);
  2102. return rc;
  2103. }
  2104. DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
  2105. "Started TX-Q %d [rss_num %d] on V-PORT %d and SB igu %d\n",
  2106. p_params->queue_id, rss_num, p_params->vport_id,
  2107. p_params->p_sb->igu_sb_id);
  2108. return 0;
  2109. }
  2110. #define QED_HW_STOP_RETRY_LIMIT (10)
  2111. static int qed_fastpath_stop(struct qed_dev *cdev)
  2112. {
  2113. int rc;
  2114. rc = qed_hw_stop_fastpath(cdev);
  2115. if (rc) {
  2116. DP_ERR(cdev, "Failed to stop Fastpath\n");
  2117. return rc;
  2118. }
  2119. return 0;
  2120. }
  2121. static int qed_stop_txq(struct qed_dev *cdev, u8 rss_id, void *handle)
  2122. {
  2123. struct qed_hwfn *p_hwfn;
  2124. int rc, hwfn_index;
  2125. hwfn_index = rss_id % cdev->num_hwfns;
  2126. p_hwfn = &cdev->hwfns[hwfn_index];
  2127. rc = qed_eth_tx_queue_stop(p_hwfn, handle);
  2128. if (rc) {
  2129. DP_ERR(cdev, "Failed to stop TXQ#%02x\n", rss_id);
  2130. return rc;
  2131. }
  2132. return 0;
  2133. }
  2134. static int qed_tunn_configure(struct qed_dev *cdev,
  2135. struct qed_tunn_params *tunn_params)
  2136. {
  2137. struct qed_tunnel_info tunn_info;
  2138. int i, rc;
  2139. memset(&tunn_info, 0, sizeof(tunn_info));
  2140. if (tunn_params->update_vxlan_port) {
  2141. tunn_info.vxlan_port.b_update_port = true;
  2142. tunn_info.vxlan_port.port = tunn_params->vxlan_port;
  2143. }
  2144. if (tunn_params->update_geneve_port) {
  2145. tunn_info.geneve_port.b_update_port = true;
  2146. tunn_info.geneve_port.port = tunn_params->geneve_port;
  2147. }
  2148. for_each_hwfn(cdev, i) {
  2149. struct qed_hwfn *hwfn = &cdev->hwfns[i];
  2150. struct qed_ptt *p_ptt;
  2151. struct qed_tunnel_info *tun;
  2152. tun = &hwfn->cdev->tunnel;
  2153. if (IS_PF(cdev)) {
  2154. p_ptt = qed_ptt_acquire(hwfn);
  2155. if (!p_ptt)
  2156. return -EAGAIN;
  2157. } else {
  2158. p_ptt = NULL;
  2159. }
  2160. rc = qed_sp_pf_update_tunn_cfg(hwfn, p_ptt, &tunn_info,
  2161. QED_SPQ_MODE_EBLOCK, NULL);
  2162. if (rc) {
  2163. if (IS_PF(cdev))
  2164. qed_ptt_release(hwfn, p_ptt);
  2165. return rc;
  2166. }
  2167. if (IS_PF_SRIOV(hwfn)) {
  2168. u16 vxlan_port, geneve_port;
  2169. int j;
  2170. vxlan_port = tun->vxlan_port.port;
  2171. geneve_port = tun->geneve_port.port;
  2172. qed_for_each_vf(hwfn, j) {
  2173. qed_iov_bulletin_set_udp_ports(hwfn, j,
  2174. vxlan_port,
  2175. geneve_port);
  2176. }
  2177. qed_schedule_iov(hwfn, QED_IOV_WQ_BULLETIN_UPDATE_FLAG);
  2178. }
  2179. if (IS_PF(cdev))
  2180. qed_ptt_release(hwfn, p_ptt);
  2181. }
  2182. return 0;
  2183. }
  2184. static int qed_configure_filter_rx_mode(struct qed_dev *cdev,
  2185. enum qed_filter_rx_mode_type type)
  2186. {
  2187. struct qed_filter_accept_flags accept_flags;
  2188. memset(&accept_flags, 0, sizeof(accept_flags));
  2189. accept_flags.update_rx_mode_config = 1;
  2190. accept_flags.update_tx_mode_config = 1;
  2191. accept_flags.rx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
  2192. QED_ACCEPT_MCAST_MATCHED |
  2193. QED_ACCEPT_BCAST;
  2194. accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
  2195. QED_ACCEPT_MCAST_MATCHED |
  2196. QED_ACCEPT_BCAST;
  2197. if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
  2198. accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED |
  2199. QED_ACCEPT_MCAST_UNMATCHED;
  2200. accept_flags.tx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
  2201. } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
  2202. accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
  2203. accept_flags.tx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
  2204. }
  2205. return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false,
  2206. QED_SPQ_MODE_CB, NULL);
  2207. }
  2208. static int qed_configure_filter_ucast(struct qed_dev *cdev,
  2209. struct qed_filter_ucast_params *params)
  2210. {
  2211. struct qed_filter_ucast ucast;
  2212. if (!params->vlan_valid && !params->mac_valid) {
  2213. DP_NOTICE(cdev,
  2214. "Tried configuring a unicast filter, but both MAC and VLAN are not set\n");
  2215. return -EINVAL;
  2216. }
  2217. memset(&ucast, 0, sizeof(ucast));
  2218. switch (params->type) {
  2219. case QED_FILTER_XCAST_TYPE_ADD:
  2220. ucast.opcode = QED_FILTER_ADD;
  2221. break;
  2222. case QED_FILTER_XCAST_TYPE_DEL:
  2223. ucast.opcode = QED_FILTER_REMOVE;
  2224. break;
  2225. case QED_FILTER_XCAST_TYPE_REPLACE:
  2226. ucast.opcode = QED_FILTER_REPLACE;
  2227. break;
  2228. default:
  2229. DP_NOTICE(cdev, "Unknown unicast filter type %d\n",
  2230. params->type);
  2231. }
  2232. if (params->vlan_valid && params->mac_valid) {
  2233. ucast.type = QED_FILTER_MAC_VLAN;
  2234. ether_addr_copy(ucast.mac, params->mac);
  2235. ucast.vlan = params->vlan;
  2236. } else if (params->mac_valid) {
  2237. ucast.type = QED_FILTER_MAC;
  2238. ether_addr_copy(ucast.mac, params->mac);
  2239. } else {
  2240. ucast.type = QED_FILTER_VLAN;
  2241. ucast.vlan = params->vlan;
  2242. }
  2243. ucast.is_rx_filter = true;
  2244. ucast.is_tx_filter = true;
  2245. return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL);
  2246. }
  2247. static int qed_configure_filter_mcast(struct qed_dev *cdev,
  2248. struct qed_filter_mcast_params *params)
  2249. {
  2250. struct qed_filter_mcast mcast;
  2251. int i;
  2252. memset(&mcast, 0, sizeof(mcast));
  2253. switch (params->type) {
  2254. case QED_FILTER_XCAST_TYPE_ADD:
  2255. mcast.opcode = QED_FILTER_ADD;
  2256. break;
  2257. case QED_FILTER_XCAST_TYPE_DEL:
  2258. mcast.opcode = QED_FILTER_REMOVE;
  2259. break;
  2260. default:
  2261. DP_NOTICE(cdev, "Unknown multicast filter type %d\n",
  2262. params->type);
  2263. }
  2264. mcast.num_mc_addrs = params->num;
  2265. for (i = 0; i < mcast.num_mc_addrs; i++)
  2266. ether_addr_copy(mcast.mac[i], params->mac[i]);
  2267. return qed_filter_mcast_cmd(cdev, &mcast, QED_SPQ_MODE_CB, NULL);
  2268. }
  2269. static int qed_configure_filter(struct qed_dev *cdev,
  2270. struct qed_filter_params *params)
  2271. {
  2272. enum qed_filter_rx_mode_type accept_flags;
  2273. switch (params->type) {
  2274. case QED_FILTER_TYPE_UCAST:
  2275. return qed_configure_filter_ucast(cdev, &params->filter.ucast);
  2276. case QED_FILTER_TYPE_MCAST:
  2277. return qed_configure_filter_mcast(cdev, &params->filter.mcast);
  2278. case QED_FILTER_TYPE_RX_MODE:
  2279. accept_flags = params->filter.accept_flags;
  2280. return qed_configure_filter_rx_mode(cdev, accept_flags);
  2281. default:
  2282. DP_NOTICE(cdev, "Unknown filter type %d\n", (int)params->type);
  2283. return -EINVAL;
  2284. }
  2285. }
  2286. static int qed_configure_arfs_searcher(struct qed_dev *cdev, bool en_searcher)
  2287. {
  2288. struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
  2289. struct qed_arfs_config_params arfs_config_params;
  2290. memset(&arfs_config_params, 0, sizeof(arfs_config_params));
  2291. arfs_config_params.tcp = true;
  2292. arfs_config_params.udp = true;
  2293. arfs_config_params.ipv4 = true;
  2294. arfs_config_params.ipv6 = true;
  2295. arfs_config_params.arfs_enable = en_searcher;
  2296. qed_arfs_mode_configure(p_hwfn, p_hwfn->p_arfs_ptt,
  2297. &arfs_config_params);
  2298. return 0;
  2299. }
  2300. static void
  2301. qed_arfs_sp_response_handler(struct qed_hwfn *p_hwfn,
  2302. void *cookie, union event_ring_data *data,
  2303. u8 fw_return_code)
  2304. {
  2305. struct qed_common_cb_ops *op = p_hwfn->cdev->protocol_ops.common;
  2306. void *dev = p_hwfn->cdev->ops_cookie;
  2307. op->arfs_filter_op(dev, cookie, fw_return_code);
  2308. }
  2309. static int qed_ntuple_arfs_filter_config(struct qed_dev *cdev, void *cookie,
  2310. dma_addr_t mapping, u16 length,
  2311. u16 vport_id, u16 rx_queue_id,
  2312. bool add_filter)
  2313. {
  2314. struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
  2315. struct qed_spq_comp_cb cb;
  2316. int rc = -EINVAL;
  2317. cb.function = qed_arfs_sp_response_handler;
  2318. cb.cookie = cookie;
  2319. rc = qed_configure_rfs_ntuple_filter(p_hwfn, p_hwfn->p_arfs_ptt,
  2320. &cb, mapping, length, rx_queue_id,
  2321. vport_id, add_filter);
  2322. if (rc)
  2323. DP_NOTICE(p_hwfn,
  2324. "Failed to issue a-RFS filter configuration\n");
  2325. else
  2326. DP_VERBOSE(p_hwfn, NETIF_MSG_DRV,
  2327. "Successfully issued a-RFS filter configuration\n");
  2328. return rc;
  2329. }
  2330. static int qed_get_coalesce(struct qed_dev *cdev, u16 *coal, void *handle)
  2331. {
  2332. struct qed_queue_cid *p_cid = handle;
  2333. struct qed_hwfn *p_hwfn;
  2334. int rc;
  2335. p_hwfn = p_cid->p_owner;
  2336. rc = qed_get_queue_coalesce(p_hwfn, coal, handle);
  2337. if (rc)
  2338. DP_NOTICE(p_hwfn, "Unable to read queue coalescing\n");
  2339. return rc;
  2340. }
  2341. static int qed_fp_cqe_completion(struct qed_dev *dev,
  2342. u8 rss_id, struct eth_slow_path_rx_cqe *cqe)
  2343. {
  2344. return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns],
  2345. cqe);
  2346. }
  2347. #ifdef CONFIG_QED_SRIOV
  2348. extern const struct qed_iov_hv_ops qed_iov_ops_pass;
  2349. #endif
  2350. #ifdef CONFIG_DCB
  2351. extern const struct qed_eth_dcbnl_ops qed_dcbnl_ops_pass;
  2352. #endif
  2353. extern const struct qed_eth_ptp_ops qed_ptp_ops_pass;
  2354. static const struct qed_eth_ops qed_eth_ops_pass = {
  2355. .common = &qed_common_ops_pass,
  2356. #ifdef CONFIG_QED_SRIOV
  2357. .iov = &qed_iov_ops_pass,
  2358. #endif
  2359. #ifdef CONFIG_DCB
  2360. .dcb = &qed_dcbnl_ops_pass,
  2361. #endif
  2362. .ptp = &qed_ptp_ops_pass,
  2363. .fill_dev_info = &qed_fill_eth_dev_info,
  2364. .register_ops = &qed_register_eth_ops,
  2365. .check_mac = &qed_check_mac,
  2366. .vport_start = &qed_start_vport,
  2367. .vport_stop = &qed_stop_vport,
  2368. .vport_update = &qed_update_vport,
  2369. .q_rx_start = &qed_start_rxq,
  2370. .q_rx_stop = &qed_stop_rxq,
  2371. .q_tx_start = &qed_start_txq,
  2372. .q_tx_stop = &qed_stop_txq,
  2373. .filter_config = &qed_configure_filter,
  2374. .fastpath_stop = &qed_fastpath_stop,
  2375. .eth_cqe_completion = &qed_fp_cqe_completion,
  2376. .get_vport_stats = &qed_get_vport_stats,
  2377. .tunn_config = &qed_tunn_configure,
  2378. .ntuple_filter_config = &qed_ntuple_arfs_filter_config,
  2379. .configure_arfs_searcher = &qed_configure_arfs_searcher,
  2380. .get_coalesce = &qed_get_coalesce,
  2381. };
  2382. const struct qed_eth_ops *qed_get_eth_ops(void)
  2383. {
  2384. return &qed_eth_ops_pass;
  2385. }
  2386. EXPORT_SYMBOL(qed_get_eth_ops);
  2387. void qed_put_eth_ops(void)
  2388. {
  2389. /* TODO - reference count for module? */
  2390. }
  2391. EXPORT_SYMBOL(qed_put_eth_ops);