resource_tracker.c 133 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies.
  4. * All rights reserved.
  5. * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
  6. *
  7. * This software is available to you under a choice of one of two
  8. * licenses. You may choose to be licensed under the terms of the GNU
  9. * General Public License (GPL) Version 2, available from the file
  10. * COPYING in the main directory of this source tree, or the
  11. * OpenIB.org BSD license below:
  12. *
  13. * Redistribution and use in source and binary forms, with or
  14. * without modification, are permitted provided that the following
  15. * conditions are met:
  16. *
  17. * - Redistributions of source code must retain the above
  18. * copyright notice, this list of conditions and the following
  19. * disclaimer.
  20. *
  21. * - Redistributions in binary form must reproduce the above
  22. * copyright notice, this list of conditions and the following
  23. * disclaimer in the documentation and/or other materials
  24. * provided with the distribution.
  25. *
  26. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33. * SOFTWARE.
  34. */
  35. #include <linux/sched.h>
  36. #include <linux/pci.h>
  37. #include <linux/errno.h>
  38. #include <linux/kernel.h>
  39. #include <linux/io.h>
  40. #include <linux/slab.h>
  41. #include <linux/mlx4/cmd.h>
  42. #include <linux/mlx4/qp.h>
  43. #include <linux/if_ether.h>
  44. #include <linux/etherdevice.h>
  45. #include "mlx4.h"
  46. #include "fw.h"
  47. #include "mlx4_stats.h"
  48. #define MLX4_MAC_VALID (1ull << 63)
  49. #define MLX4_PF_COUNTERS_PER_PORT 2
  50. #define MLX4_VF_COUNTERS_PER_PORT 1
  51. struct mac_res {
  52. struct list_head list;
  53. u64 mac;
  54. int ref_count;
  55. u8 smac_index;
  56. u8 port;
  57. };
  58. struct vlan_res {
  59. struct list_head list;
  60. u16 vlan;
  61. int ref_count;
  62. int vlan_index;
  63. u8 port;
  64. };
  65. struct res_common {
  66. struct list_head list;
  67. struct rb_node node;
  68. u64 res_id;
  69. int owner;
  70. int state;
  71. int from_state;
  72. int to_state;
  73. int removing;
  74. const char *func_name;
  75. };
  76. enum {
  77. RES_ANY_BUSY = 1
  78. };
  79. struct res_gid {
  80. struct list_head list;
  81. u8 gid[16];
  82. enum mlx4_protocol prot;
  83. enum mlx4_steer_type steer;
  84. u64 reg_id;
  85. };
  86. enum res_qp_states {
  87. RES_QP_BUSY = RES_ANY_BUSY,
  88. /* QP number was allocated */
  89. RES_QP_RESERVED,
  90. /* ICM memory for QP context was mapped */
  91. RES_QP_MAPPED,
  92. /* QP is in hw ownership */
  93. RES_QP_HW
  94. };
  95. struct res_qp {
  96. struct res_common com;
  97. struct res_mtt *mtt;
  98. struct res_cq *rcq;
  99. struct res_cq *scq;
  100. struct res_srq *srq;
  101. struct list_head mcg_list;
  102. spinlock_t mcg_spl;
  103. int local_qpn;
  104. atomic_t ref_count;
  105. u32 qpc_flags;
  106. /* saved qp params before VST enforcement in order to restore on VGT */
  107. u8 sched_queue;
  108. __be32 param3;
  109. u8 vlan_control;
  110. u8 fvl_rx;
  111. u8 pri_path_fl;
  112. u8 vlan_index;
  113. u8 feup;
  114. };
  115. enum res_mtt_states {
  116. RES_MTT_BUSY = RES_ANY_BUSY,
  117. RES_MTT_ALLOCATED,
  118. };
  119. static inline const char *mtt_states_str(enum res_mtt_states state)
  120. {
  121. switch (state) {
  122. case RES_MTT_BUSY: return "RES_MTT_BUSY";
  123. case RES_MTT_ALLOCATED: return "RES_MTT_ALLOCATED";
  124. default: return "Unknown";
  125. }
  126. }
  127. struct res_mtt {
  128. struct res_common com;
  129. int order;
  130. atomic_t ref_count;
  131. };
  132. enum res_mpt_states {
  133. RES_MPT_BUSY = RES_ANY_BUSY,
  134. RES_MPT_RESERVED,
  135. RES_MPT_MAPPED,
  136. RES_MPT_HW,
  137. };
  138. struct res_mpt {
  139. struct res_common com;
  140. struct res_mtt *mtt;
  141. int key;
  142. };
  143. enum res_eq_states {
  144. RES_EQ_BUSY = RES_ANY_BUSY,
  145. RES_EQ_RESERVED,
  146. RES_EQ_HW,
  147. };
  148. struct res_eq {
  149. struct res_common com;
  150. struct res_mtt *mtt;
  151. };
  152. enum res_cq_states {
  153. RES_CQ_BUSY = RES_ANY_BUSY,
  154. RES_CQ_ALLOCATED,
  155. RES_CQ_HW,
  156. };
  157. struct res_cq {
  158. struct res_common com;
  159. struct res_mtt *mtt;
  160. atomic_t ref_count;
  161. };
  162. enum res_srq_states {
  163. RES_SRQ_BUSY = RES_ANY_BUSY,
  164. RES_SRQ_ALLOCATED,
  165. RES_SRQ_HW,
  166. };
  167. struct res_srq {
  168. struct res_common com;
  169. struct res_mtt *mtt;
  170. struct res_cq *cq;
  171. atomic_t ref_count;
  172. };
  173. enum res_counter_states {
  174. RES_COUNTER_BUSY = RES_ANY_BUSY,
  175. RES_COUNTER_ALLOCATED,
  176. };
  177. struct res_counter {
  178. struct res_common com;
  179. int port;
  180. };
  181. enum res_xrcdn_states {
  182. RES_XRCD_BUSY = RES_ANY_BUSY,
  183. RES_XRCD_ALLOCATED,
  184. };
  185. struct res_xrcdn {
  186. struct res_common com;
  187. int port;
  188. };
  189. enum res_fs_rule_states {
  190. RES_FS_RULE_BUSY = RES_ANY_BUSY,
  191. RES_FS_RULE_ALLOCATED,
  192. };
  193. struct res_fs_rule {
  194. struct res_common com;
  195. int qpn;
  196. /* VF DMFS mbox with port flipped */
  197. void *mirr_mbox;
  198. /* > 0 --> apply mirror when getting into HA mode */
  199. /* = 0 --> un-apply mirror when getting out of HA mode */
  200. u32 mirr_mbox_size;
  201. struct list_head mirr_list;
  202. u64 mirr_rule_id;
  203. };
  204. static void *res_tracker_lookup(struct rb_root *root, u64 res_id)
  205. {
  206. struct rb_node *node = root->rb_node;
  207. while (node) {
  208. struct res_common *res = rb_entry(node, struct res_common,
  209. node);
  210. if (res_id < res->res_id)
  211. node = node->rb_left;
  212. else if (res_id > res->res_id)
  213. node = node->rb_right;
  214. else
  215. return res;
  216. }
  217. return NULL;
  218. }
  219. static int res_tracker_insert(struct rb_root *root, struct res_common *res)
  220. {
  221. struct rb_node **new = &(root->rb_node), *parent = NULL;
  222. /* Figure out where to put new node */
  223. while (*new) {
  224. struct res_common *this = rb_entry(*new, struct res_common,
  225. node);
  226. parent = *new;
  227. if (res->res_id < this->res_id)
  228. new = &((*new)->rb_left);
  229. else if (res->res_id > this->res_id)
  230. new = &((*new)->rb_right);
  231. else
  232. return -EEXIST;
  233. }
  234. /* Add new node and rebalance tree. */
  235. rb_link_node(&res->node, parent, new);
  236. rb_insert_color(&res->node, root);
  237. return 0;
  238. }
  239. enum qp_transition {
  240. QP_TRANS_INIT2RTR,
  241. QP_TRANS_RTR2RTS,
  242. QP_TRANS_RTS2RTS,
  243. QP_TRANS_SQERR2RTS,
  244. QP_TRANS_SQD2SQD,
  245. QP_TRANS_SQD2RTS
  246. };
  247. /* For Debug uses */
  248. static const char *resource_str(enum mlx4_resource rt)
  249. {
  250. switch (rt) {
  251. case RES_QP: return "RES_QP";
  252. case RES_CQ: return "RES_CQ";
  253. case RES_SRQ: return "RES_SRQ";
  254. case RES_MPT: return "RES_MPT";
  255. case RES_MTT: return "RES_MTT";
  256. case RES_MAC: return "RES_MAC";
  257. case RES_VLAN: return "RES_VLAN";
  258. case RES_EQ: return "RES_EQ";
  259. case RES_COUNTER: return "RES_COUNTER";
  260. case RES_FS_RULE: return "RES_FS_RULE";
  261. case RES_XRCD: return "RES_XRCD";
  262. default: return "Unknown resource type !!!";
  263. };
  264. }
  265. static void rem_slave_vlans(struct mlx4_dev *dev, int slave);
  266. static inline int mlx4_grant_resource(struct mlx4_dev *dev, int slave,
  267. enum mlx4_resource res_type, int count,
  268. int port)
  269. {
  270. struct mlx4_priv *priv = mlx4_priv(dev);
  271. struct resource_allocator *res_alloc =
  272. &priv->mfunc.master.res_tracker.res_alloc[res_type];
  273. int err = -EDQUOT;
  274. int allocated, free, reserved, guaranteed, from_free;
  275. int from_rsvd;
  276. if (slave > dev->persist->num_vfs)
  277. return -EINVAL;
  278. spin_lock(&res_alloc->alloc_lock);
  279. allocated = (port > 0) ?
  280. res_alloc->allocated[(port - 1) *
  281. (dev->persist->num_vfs + 1) + slave] :
  282. res_alloc->allocated[slave];
  283. free = (port > 0) ? res_alloc->res_port_free[port - 1] :
  284. res_alloc->res_free;
  285. reserved = (port > 0) ? res_alloc->res_port_rsvd[port - 1] :
  286. res_alloc->res_reserved;
  287. guaranteed = res_alloc->guaranteed[slave];
  288. if (allocated + count > res_alloc->quota[slave]) {
  289. mlx4_warn(dev, "VF %d port %d res %s: quota exceeded, count %d alloc %d quota %d\n",
  290. slave, port, resource_str(res_type), count,
  291. allocated, res_alloc->quota[slave]);
  292. goto out;
  293. }
  294. if (allocated + count <= guaranteed) {
  295. err = 0;
  296. from_rsvd = count;
  297. } else {
  298. /* portion may need to be obtained from free area */
  299. if (guaranteed - allocated > 0)
  300. from_free = count - (guaranteed - allocated);
  301. else
  302. from_free = count;
  303. from_rsvd = count - from_free;
  304. if (free - from_free >= reserved)
  305. err = 0;
  306. else
  307. mlx4_warn(dev, "VF %d port %d res %s: free pool empty, free %d from_free %d rsvd %d\n",
  308. slave, port, resource_str(res_type), free,
  309. from_free, reserved);
  310. }
  311. if (!err) {
  312. /* grant the request */
  313. if (port > 0) {
  314. res_alloc->allocated[(port - 1) *
  315. (dev->persist->num_vfs + 1) + slave] += count;
  316. res_alloc->res_port_free[port - 1] -= count;
  317. res_alloc->res_port_rsvd[port - 1] -= from_rsvd;
  318. } else {
  319. res_alloc->allocated[slave] += count;
  320. res_alloc->res_free -= count;
  321. res_alloc->res_reserved -= from_rsvd;
  322. }
  323. }
  324. out:
  325. spin_unlock(&res_alloc->alloc_lock);
  326. return err;
  327. }
  328. static inline void mlx4_release_resource(struct mlx4_dev *dev, int slave,
  329. enum mlx4_resource res_type, int count,
  330. int port)
  331. {
  332. struct mlx4_priv *priv = mlx4_priv(dev);
  333. struct resource_allocator *res_alloc =
  334. &priv->mfunc.master.res_tracker.res_alloc[res_type];
  335. int allocated, guaranteed, from_rsvd;
  336. if (slave > dev->persist->num_vfs)
  337. return;
  338. spin_lock(&res_alloc->alloc_lock);
  339. allocated = (port > 0) ?
  340. res_alloc->allocated[(port - 1) *
  341. (dev->persist->num_vfs + 1) + slave] :
  342. res_alloc->allocated[slave];
  343. guaranteed = res_alloc->guaranteed[slave];
  344. if (allocated - count >= guaranteed) {
  345. from_rsvd = 0;
  346. } else {
  347. /* portion may need to be returned to reserved area */
  348. if (allocated - guaranteed > 0)
  349. from_rsvd = count - (allocated - guaranteed);
  350. else
  351. from_rsvd = count;
  352. }
  353. if (port > 0) {
  354. res_alloc->allocated[(port - 1) *
  355. (dev->persist->num_vfs + 1) + slave] -= count;
  356. res_alloc->res_port_free[port - 1] += count;
  357. res_alloc->res_port_rsvd[port - 1] += from_rsvd;
  358. } else {
  359. res_alloc->allocated[slave] -= count;
  360. res_alloc->res_free += count;
  361. res_alloc->res_reserved += from_rsvd;
  362. }
  363. spin_unlock(&res_alloc->alloc_lock);
  364. return;
  365. }
  366. static inline void initialize_res_quotas(struct mlx4_dev *dev,
  367. struct resource_allocator *res_alloc,
  368. enum mlx4_resource res_type,
  369. int vf, int num_instances)
  370. {
  371. res_alloc->guaranteed[vf] = num_instances /
  372. (2 * (dev->persist->num_vfs + 1));
  373. res_alloc->quota[vf] = (num_instances / 2) + res_alloc->guaranteed[vf];
  374. if (vf == mlx4_master_func_num(dev)) {
  375. res_alloc->res_free = num_instances;
  376. if (res_type == RES_MTT) {
  377. /* reserved mtts will be taken out of the PF allocation */
  378. res_alloc->res_free += dev->caps.reserved_mtts;
  379. res_alloc->guaranteed[vf] += dev->caps.reserved_mtts;
  380. res_alloc->quota[vf] += dev->caps.reserved_mtts;
  381. }
  382. }
  383. }
  384. void mlx4_init_quotas(struct mlx4_dev *dev)
  385. {
  386. struct mlx4_priv *priv = mlx4_priv(dev);
  387. int pf;
  388. /* quotas for VFs are initialized in mlx4_slave_cap */
  389. if (mlx4_is_slave(dev))
  390. return;
  391. if (!mlx4_is_mfunc(dev)) {
  392. dev->quotas.qp = dev->caps.num_qps - dev->caps.reserved_qps -
  393. mlx4_num_reserved_sqps(dev);
  394. dev->quotas.cq = dev->caps.num_cqs - dev->caps.reserved_cqs;
  395. dev->quotas.srq = dev->caps.num_srqs - dev->caps.reserved_srqs;
  396. dev->quotas.mtt = dev->caps.num_mtts - dev->caps.reserved_mtts;
  397. dev->quotas.mpt = dev->caps.num_mpts - dev->caps.reserved_mrws;
  398. return;
  399. }
  400. pf = mlx4_master_func_num(dev);
  401. dev->quotas.qp =
  402. priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[pf];
  403. dev->quotas.cq =
  404. priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[pf];
  405. dev->quotas.srq =
  406. priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[pf];
  407. dev->quotas.mtt =
  408. priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[pf];
  409. dev->quotas.mpt =
  410. priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[pf];
  411. }
  412. static int get_max_gauranteed_vfs_counter(struct mlx4_dev *dev)
  413. {
  414. /* reduce the sink counter */
  415. return (dev->caps.max_counters - 1 -
  416. (MLX4_PF_COUNTERS_PER_PORT * MLX4_MAX_PORTS))
  417. / MLX4_MAX_PORTS;
  418. }
  419. int mlx4_init_resource_tracker(struct mlx4_dev *dev)
  420. {
  421. struct mlx4_priv *priv = mlx4_priv(dev);
  422. int i, j;
  423. int t;
  424. int max_vfs_guarantee_counter = get_max_gauranteed_vfs_counter(dev);
  425. priv->mfunc.master.res_tracker.slave_list =
  426. kzalloc(dev->num_slaves * sizeof(struct slave_list),
  427. GFP_KERNEL);
  428. if (!priv->mfunc.master.res_tracker.slave_list)
  429. return -ENOMEM;
  430. for (i = 0 ; i < dev->num_slaves; i++) {
  431. for (t = 0; t < MLX4_NUM_OF_RESOURCE_TYPE; ++t)
  432. INIT_LIST_HEAD(&priv->mfunc.master.res_tracker.
  433. slave_list[i].res_list[t]);
  434. mutex_init(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
  435. }
  436. mlx4_dbg(dev, "Started init_resource_tracker: %ld slaves\n",
  437. dev->num_slaves);
  438. for (i = 0 ; i < MLX4_NUM_OF_RESOURCE_TYPE; i++)
  439. priv->mfunc.master.res_tracker.res_tree[i] = RB_ROOT;
  440. for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
  441. struct resource_allocator *res_alloc =
  442. &priv->mfunc.master.res_tracker.res_alloc[i];
  443. res_alloc->quota = kmalloc((dev->persist->num_vfs + 1) *
  444. sizeof(int), GFP_KERNEL);
  445. res_alloc->guaranteed = kmalloc((dev->persist->num_vfs + 1) *
  446. sizeof(int), GFP_KERNEL);
  447. if (i == RES_MAC || i == RES_VLAN)
  448. res_alloc->allocated = kzalloc(MLX4_MAX_PORTS *
  449. (dev->persist->num_vfs
  450. + 1) *
  451. sizeof(int), GFP_KERNEL);
  452. else
  453. res_alloc->allocated = kzalloc((dev->persist->
  454. num_vfs + 1) *
  455. sizeof(int), GFP_KERNEL);
  456. /* Reduce the sink counter */
  457. if (i == RES_COUNTER)
  458. res_alloc->res_free = dev->caps.max_counters - 1;
  459. if (!res_alloc->quota || !res_alloc->guaranteed ||
  460. !res_alloc->allocated)
  461. goto no_mem_err;
  462. spin_lock_init(&res_alloc->alloc_lock);
  463. for (t = 0; t < dev->persist->num_vfs + 1; t++) {
  464. struct mlx4_active_ports actv_ports =
  465. mlx4_get_active_ports(dev, t);
  466. switch (i) {
  467. case RES_QP:
  468. initialize_res_quotas(dev, res_alloc, RES_QP,
  469. t, dev->caps.num_qps -
  470. dev->caps.reserved_qps -
  471. mlx4_num_reserved_sqps(dev));
  472. break;
  473. case RES_CQ:
  474. initialize_res_quotas(dev, res_alloc, RES_CQ,
  475. t, dev->caps.num_cqs -
  476. dev->caps.reserved_cqs);
  477. break;
  478. case RES_SRQ:
  479. initialize_res_quotas(dev, res_alloc, RES_SRQ,
  480. t, dev->caps.num_srqs -
  481. dev->caps.reserved_srqs);
  482. break;
  483. case RES_MPT:
  484. initialize_res_quotas(dev, res_alloc, RES_MPT,
  485. t, dev->caps.num_mpts -
  486. dev->caps.reserved_mrws);
  487. break;
  488. case RES_MTT:
  489. initialize_res_quotas(dev, res_alloc, RES_MTT,
  490. t, dev->caps.num_mtts -
  491. dev->caps.reserved_mtts);
  492. break;
  493. case RES_MAC:
  494. if (t == mlx4_master_func_num(dev)) {
  495. int max_vfs_pport = 0;
  496. /* Calculate the max vfs per port for */
  497. /* both ports. */
  498. for (j = 0; j < dev->caps.num_ports;
  499. j++) {
  500. struct mlx4_slaves_pport slaves_pport =
  501. mlx4_phys_to_slaves_pport(dev, j + 1);
  502. unsigned current_slaves =
  503. bitmap_weight(slaves_pport.slaves,
  504. dev->caps.num_ports) - 1;
  505. if (max_vfs_pport < current_slaves)
  506. max_vfs_pport =
  507. current_slaves;
  508. }
  509. res_alloc->quota[t] =
  510. MLX4_MAX_MAC_NUM -
  511. 2 * max_vfs_pport;
  512. res_alloc->guaranteed[t] = 2;
  513. for (j = 0; j < MLX4_MAX_PORTS; j++)
  514. res_alloc->res_port_free[j] =
  515. MLX4_MAX_MAC_NUM;
  516. } else {
  517. res_alloc->quota[t] = MLX4_MAX_MAC_NUM;
  518. res_alloc->guaranteed[t] = 2;
  519. }
  520. break;
  521. case RES_VLAN:
  522. if (t == mlx4_master_func_num(dev)) {
  523. res_alloc->quota[t] = MLX4_MAX_VLAN_NUM;
  524. res_alloc->guaranteed[t] = MLX4_MAX_VLAN_NUM / 2;
  525. for (j = 0; j < MLX4_MAX_PORTS; j++)
  526. res_alloc->res_port_free[j] =
  527. res_alloc->quota[t];
  528. } else {
  529. res_alloc->quota[t] = MLX4_MAX_VLAN_NUM / 2;
  530. res_alloc->guaranteed[t] = 0;
  531. }
  532. break;
  533. case RES_COUNTER:
  534. res_alloc->quota[t] = dev->caps.max_counters;
  535. if (t == mlx4_master_func_num(dev))
  536. res_alloc->guaranteed[t] =
  537. MLX4_PF_COUNTERS_PER_PORT *
  538. MLX4_MAX_PORTS;
  539. else if (t <= max_vfs_guarantee_counter)
  540. res_alloc->guaranteed[t] =
  541. MLX4_VF_COUNTERS_PER_PORT *
  542. MLX4_MAX_PORTS;
  543. else
  544. res_alloc->guaranteed[t] = 0;
  545. res_alloc->res_free -= res_alloc->guaranteed[t];
  546. break;
  547. default:
  548. break;
  549. }
  550. if (i == RES_MAC || i == RES_VLAN) {
  551. for (j = 0; j < dev->caps.num_ports; j++)
  552. if (test_bit(j, actv_ports.ports))
  553. res_alloc->res_port_rsvd[j] +=
  554. res_alloc->guaranteed[t];
  555. } else {
  556. res_alloc->res_reserved += res_alloc->guaranteed[t];
  557. }
  558. }
  559. }
  560. spin_lock_init(&priv->mfunc.master.res_tracker.lock);
  561. return 0;
  562. no_mem_err:
  563. for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
  564. kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated);
  565. priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL;
  566. kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed);
  567. priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL;
  568. kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota);
  569. priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL;
  570. }
  571. return -ENOMEM;
  572. }
  573. void mlx4_free_resource_tracker(struct mlx4_dev *dev,
  574. enum mlx4_res_tracker_free_type type)
  575. {
  576. struct mlx4_priv *priv = mlx4_priv(dev);
  577. int i;
  578. if (priv->mfunc.master.res_tracker.slave_list) {
  579. if (type != RES_TR_FREE_STRUCTS_ONLY) {
  580. for (i = 0; i < dev->num_slaves; i++) {
  581. if (type == RES_TR_FREE_ALL ||
  582. dev->caps.function != i)
  583. mlx4_delete_all_resources_for_slave(dev, i);
  584. }
  585. /* free master's vlans */
  586. i = dev->caps.function;
  587. mlx4_reset_roce_gids(dev, i);
  588. mutex_lock(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
  589. rem_slave_vlans(dev, i);
  590. mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
  591. }
  592. if (type != RES_TR_FREE_SLAVES_ONLY) {
  593. for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
  594. kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated);
  595. priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL;
  596. kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed);
  597. priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL;
  598. kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota);
  599. priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL;
  600. }
  601. kfree(priv->mfunc.master.res_tracker.slave_list);
  602. priv->mfunc.master.res_tracker.slave_list = NULL;
  603. }
  604. }
  605. }
  606. static void update_pkey_index(struct mlx4_dev *dev, int slave,
  607. struct mlx4_cmd_mailbox *inbox)
  608. {
  609. u8 sched = *(u8 *)(inbox->buf + 64);
  610. u8 orig_index = *(u8 *)(inbox->buf + 35);
  611. u8 new_index;
  612. struct mlx4_priv *priv = mlx4_priv(dev);
  613. int port;
  614. port = (sched >> 6 & 1) + 1;
  615. new_index = priv->virt2phys_pkey[slave][port - 1][orig_index];
  616. *(u8 *)(inbox->buf + 35) = new_index;
  617. }
  618. static void update_gid(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *inbox,
  619. u8 slave)
  620. {
  621. struct mlx4_qp_context *qp_ctx = inbox->buf + 8;
  622. enum mlx4_qp_optpar optpar = be32_to_cpu(*(__be32 *) inbox->buf);
  623. u32 ts = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
  624. int port;
  625. if (MLX4_QP_ST_UD == ts) {
  626. port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
  627. if (mlx4_is_eth(dev, port))
  628. qp_ctx->pri_path.mgid_index =
  629. mlx4_get_base_gid_ix(dev, slave, port) | 0x80;
  630. else
  631. qp_ctx->pri_path.mgid_index = slave | 0x80;
  632. } else if (MLX4_QP_ST_RC == ts || MLX4_QP_ST_XRC == ts || MLX4_QP_ST_UC == ts) {
  633. if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH) {
  634. port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
  635. if (mlx4_is_eth(dev, port)) {
  636. qp_ctx->pri_path.mgid_index +=
  637. mlx4_get_base_gid_ix(dev, slave, port);
  638. qp_ctx->pri_path.mgid_index &= 0x7f;
  639. } else {
  640. qp_ctx->pri_path.mgid_index = slave & 0x7F;
  641. }
  642. }
  643. if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
  644. port = (qp_ctx->alt_path.sched_queue >> 6 & 1) + 1;
  645. if (mlx4_is_eth(dev, port)) {
  646. qp_ctx->alt_path.mgid_index +=
  647. mlx4_get_base_gid_ix(dev, slave, port);
  648. qp_ctx->alt_path.mgid_index &= 0x7f;
  649. } else {
  650. qp_ctx->alt_path.mgid_index = slave & 0x7F;
  651. }
  652. }
  653. }
  654. }
  655. static int handle_counter(struct mlx4_dev *dev, struct mlx4_qp_context *qpc,
  656. u8 slave, int port);
  657. static int update_vport_qp_param(struct mlx4_dev *dev,
  658. struct mlx4_cmd_mailbox *inbox,
  659. u8 slave, u32 qpn)
  660. {
  661. struct mlx4_qp_context *qpc = inbox->buf + 8;
  662. struct mlx4_vport_oper_state *vp_oper;
  663. struct mlx4_priv *priv;
  664. u32 qp_type;
  665. int port, err = 0;
  666. port = (qpc->pri_path.sched_queue & 0x40) ? 2 : 1;
  667. priv = mlx4_priv(dev);
  668. vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
  669. qp_type = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
  670. err = handle_counter(dev, qpc, slave, port);
  671. if (err)
  672. goto out;
  673. if (MLX4_VGT != vp_oper->state.default_vlan) {
  674. /* the reserved QPs (special, proxy, tunnel)
  675. * do not operate over vlans
  676. */
  677. if (mlx4_is_qp_reserved(dev, qpn))
  678. return 0;
  679. /* force strip vlan by clear vsd, MLX QP refers to Raw Ethernet */
  680. if (qp_type == MLX4_QP_ST_UD ||
  681. (qp_type == MLX4_QP_ST_MLX && mlx4_is_eth(dev, port))) {
  682. if (dev->caps.bmme_flags & MLX4_BMME_FLAG_VSD_INIT2RTR) {
  683. *(__be32 *)inbox->buf =
  684. cpu_to_be32(be32_to_cpu(*(__be32 *)inbox->buf) |
  685. MLX4_QP_OPTPAR_VLAN_STRIPPING);
  686. qpc->param3 &= ~cpu_to_be32(MLX4_STRIP_VLAN);
  687. } else {
  688. struct mlx4_update_qp_params params = {.flags = 0};
  689. err = mlx4_update_qp(dev, qpn, MLX4_UPDATE_QP_VSD, &params);
  690. if (err)
  691. goto out;
  692. }
  693. }
  694. /* preserve IF_COUNTER flag */
  695. qpc->pri_path.vlan_control &=
  696. MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
  697. if (vp_oper->state.link_state == IFLA_VF_LINK_STATE_DISABLE &&
  698. dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP) {
  699. qpc->pri_path.vlan_control |=
  700. MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
  701. MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
  702. MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED |
  703. MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
  704. MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED |
  705. MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
  706. } else if (0 != vp_oper->state.default_vlan) {
  707. if (vp_oper->state.vlan_proto == htons(ETH_P_8021AD)) {
  708. /* vst QinQ should block untagged on TX,
  709. * but cvlan is in payload and phv is set so
  710. * hw see it as untagged. Block tagged instead.
  711. */
  712. qpc->pri_path.vlan_control |=
  713. MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
  714. MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
  715. MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
  716. MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
  717. } else { /* vst 802.1Q */
  718. qpc->pri_path.vlan_control |=
  719. MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
  720. MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
  721. MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
  722. }
  723. } else { /* priority tagged */
  724. qpc->pri_path.vlan_control |=
  725. MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
  726. MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
  727. }
  728. qpc->pri_path.fvl_rx |= MLX4_FVL_RX_FORCE_ETH_VLAN;
  729. qpc->pri_path.vlan_index = vp_oper->vlan_idx;
  730. qpc->pri_path.fl |= MLX4_FL_ETH_HIDE_CQE_VLAN;
  731. if (vp_oper->state.vlan_proto == htons(ETH_P_8021AD))
  732. qpc->pri_path.fl |= MLX4_FL_SV;
  733. else
  734. qpc->pri_path.fl |= MLX4_FL_CV;
  735. qpc->pri_path.feup |= MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN;
  736. qpc->pri_path.sched_queue &= 0xC7;
  737. qpc->pri_path.sched_queue |= (vp_oper->state.default_qos) << 3;
  738. qpc->qos_vport = vp_oper->state.qos_vport;
  739. }
  740. if (vp_oper->state.spoofchk) {
  741. qpc->pri_path.feup |= MLX4_FSM_FORCE_ETH_SRC_MAC;
  742. qpc->pri_path.grh_mylmc = (0x80 & qpc->pri_path.grh_mylmc) + vp_oper->mac_idx;
  743. }
  744. out:
  745. return err;
  746. }
  747. static int mpt_mask(struct mlx4_dev *dev)
  748. {
  749. return dev->caps.num_mpts - 1;
  750. }
  751. static const char *mlx4_resource_type_to_str(enum mlx4_resource t)
  752. {
  753. switch (t) {
  754. case RES_QP:
  755. return "QP";
  756. case RES_CQ:
  757. return "CQ";
  758. case RES_SRQ:
  759. return "SRQ";
  760. case RES_XRCD:
  761. return "XRCD";
  762. case RES_MPT:
  763. return "MPT";
  764. case RES_MTT:
  765. return "MTT";
  766. case RES_MAC:
  767. return "MAC";
  768. case RES_VLAN:
  769. return "VLAN";
  770. case RES_COUNTER:
  771. return "COUNTER";
  772. case RES_FS_RULE:
  773. return "FS_RULE";
  774. case RES_EQ:
  775. return "EQ";
  776. default:
  777. return "INVALID RESOURCE";
  778. }
  779. }
  780. static void *find_res(struct mlx4_dev *dev, u64 res_id,
  781. enum mlx4_resource type)
  782. {
  783. struct mlx4_priv *priv = mlx4_priv(dev);
  784. return res_tracker_lookup(&priv->mfunc.master.res_tracker.res_tree[type],
  785. res_id);
  786. }
  787. static int _get_res(struct mlx4_dev *dev, int slave, u64 res_id,
  788. enum mlx4_resource type,
  789. void *res, const char *func_name)
  790. {
  791. struct res_common *r;
  792. int err = 0;
  793. spin_lock_irq(mlx4_tlock(dev));
  794. r = find_res(dev, res_id, type);
  795. if (!r) {
  796. err = -ENONET;
  797. goto exit;
  798. }
  799. if (r->state == RES_ANY_BUSY) {
  800. mlx4_warn(dev,
  801. "%s(%d) trying to get resource %llx of type %s, but it's already taken by %s\n",
  802. func_name, slave, res_id, mlx4_resource_type_to_str(type),
  803. r->func_name);
  804. err = -EBUSY;
  805. goto exit;
  806. }
  807. if (r->owner != slave) {
  808. err = -EPERM;
  809. goto exit;
  810. }
  811. r->from_state = r->state;
  812. r->state = RES_ANY_BUSY;
  813. r->func_name = func_name;
  814. if (res)
  815. *((struct res_common **)res) = r;
  816. exit:
  817. spin_unlock_irq(mlx4_tlock(dev));
  818. return err;
  819. }
  820. #define get_res(dev, slave, res_id, type, res) \
  821. _get_res((dev), (slave), (res_id), (type), (res), __func__)
  822. int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
  823. enum mlx4_resource type,
  824. u64 res_id, int *slave)
  825. {
  826. struct res_common *r;
  827. int err = -ENOENT;
  828. int id = res_id;
  829. if (type == RES_QP)
  830. id &= 0x7fffff;
  831. spin_lock(mlx4_tlock(dev));
  832. r = find_res(dev, id, type);
  833. if (r) {
  834. *slave = r->owner;
  835. err = 0;
  836. }
  837. spin_unlock(mlx4_tlock(dev));
  838. return err;
  839. }
  840. static void put_res(struct mlx4_dev *dev, int slave, u64 res_id,
  841. enum mlx4_resource type)
  842. {
  843. struct res_common *r;
  844. spin_lock_irq(mlx4_tlock(dev));
  845. r = find_res(dev, res_id, type);
  846. if (r) {
  847. r->state = r->from_state;
  848. r->func_name = "";
  849. }
  850. spin_unlock_irq(mlx4_tlock(dev));
  851. }
  852. static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  853. u64 in_param, u64 *out_param, int port);
  854. static int handle_existing_counter(struct mlx4_dev *dev, u8 slave, int port,
  855. int counter_index)
  856. {
  857. struct res_common *r;
  858. struct res_counter *counter;
  859. int ret = 0;
  860. if (counter_index == MLX4_SINK_COUNTER_INDEX(dev))
  861. return ret;
  862. spin_lock_irq(mlx4_tlock(dev));
  863. r = find_res(dev, counter_index, RES_COUNTER);
  864. if (!r || r->owner != slave) {
  865. ret = -EINVAL;
  866. } else {
  867. counter = container_of(r, struct res_counter, com);
  868. if (!counter->port)
  869. counter->port = port;
  870. }
  871. spin_unlock_irq(mlx4_tlock(dev));
  872. return ret;
  873. }
  874. static int handle_unexisting_counter(struct mlx4_dev *dev,
  875. struct mlx4_qp_context *qpc, u8 slave,
  876. int port)
  877. {
  878. struct mlx4_priv *priv = mlx4_priv(dev);
  879. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  880. struct res_common *tmp;
  881. struct res_counter *counter;
  882. u64 counter_idx = MLX4_SINK_COUNTER_INDEX(dev);
  883. int err = 0;
  884. spin_lock_irq(mlx4_tlock(dev));
  885. list_for_each_entry(tmp,
  886. &tracker->slave_list[slave].res_list[RES_COUNTER],
  887. list) {
  888. counter = container_of(tmp, struct res_counter, com);
  889. if (port == counter->port) {
  890. qpc->pri_path.counter_index = counter->com.res_id;
  891. spin_unlock_irq(mlx4_tlock(dev));
  892. return 0;
  893. }
  894. }
  895. spin_unlock_irq(mlx4_tlock(dev));
  896. /* No existing counter, need to allocate a new counter */
  897. err = counter_alloc_res(dev, slave, RES_OP_RESERVE, 0, 0, &counter_idx,
  898. port);
  899. if (err == -ENOENT) {
  900. err = 0;
  901. } else if (err && err != -ENOSPC) {
  902. mlx4_err(dev, "%s: failed to create new counter for slave %d err %d\n",
  903. __func__, slave, err);
  904. } else {
  905. qpc->pri_path.counter_index = counter_idx;
  906. mlx4_dbg(dev, "%s: alloc new counter for slave %d index %d\n",
  907. __func__, slave, qpc->pri_path.counter_index);
  908. err = 0;
  909. }
  910. return err;
  911. }
  912. static int handle_counter(struct mlx4_dev *dev, struct mlx4_qp_context *qpc,
  913. u8 slave, int port)
  914. {
  915. if (qpc->pri_path.counter_index != MLX4_SINK_COUNTER_INDEX(dev))
  916. return handle_existing_counter(dev, slave, port,
  917. qpc->pri_path.counter_index);
  918. return handle_unexisting_counter(dev, qpc, slave, port);
  919. }
  920. static struct res_common *alloc_qp_tr(int id)
  921. {
  922. struct res_qp *ret;
  923. ret = kzalloc(sizeof(*ret), GFP_KERNEL);
  924. if (!ret)
  925. return NULL;
  926. ret->com.res_id = id;
  927. ret->com.state = RES_QP_RESERVED;
  928. ret->local_qpn = id;
  929. INIT_LIST_HEAD(&ret->mcg_list);
  930. spin_lock_init(&ret->mcg_spl);
  931. atomic_set(&ret->ref_count, 0);
  932. return &ret->com;
  933. }
  934. static struct res_common *alloc_mtt_tr(int id, int order)
  935. {
  936. struct res_mtt *ret;
  937. ret = kzalloc(sizeof(*ret), GFP_KERNEL);
  938. if (!ret)
  939. return NULL;
  940. ret->com.res_id = id;
  941. ret->order = order;
  942. ret->com.state = RES_MTT_ALLOCATED;
  943. atomic_set(&ret->ref_count, 0);
  944. return &ret->com;
  945. }
  946. static struct res_common *alloc_mpt_tr(int id, int key)
  947. {
  948. struct res_mpt *ret;
  949. ret = kzalloc(sizeof(*ret), GFP_KERNEL);
  950. if (!ret)
  951. return NULL;
  952. ret->com.res_id = id;
  953. ret->com.state = RES_MPT_RESERVED;
  954. ret->key = key;
  955. return &ret->com;
  956. }
  957. static struct res_common *alloc_eq_tr(int id)
  958. {
  959. struct res_eq *ret;
  960. ret = kzalloc(sizeof(*ret), GFP_KERNEL);
  961. if (!ret)
  962. return NULL;
  963. ret->com.res_id = id;
  964. ret->com.state = RES_EQ_RESERVED;
  965. return &ret->com;
  966. }
  967. static struct res_common *alloc_cq_tr(int id)
  968. {
  969. struct res_cq *ret;
  970. ret = kzalloc(sizeof(*ret), GFP_KERNEL);
  971. if (!ret)
  972. return NULL;
  973. ret->com.res_id = id;
  974. ret->com.state = RES_CQ_ALLOCATED;
  975. atomic_set(&ret->ref_count, 0);
  976. return &ret->com;
  977. }
  978. static struct res_common *alloc_srq_tr(int id)
  979. {
  980. struct res_srq *ret;
  981. ret = kzalloc(sizeof(*ret), GFP_KERNEL);
  982. if (!ret)
  983. return NULL;
  984. ret->com.res_id = id;
  985. ret->com.state = RES_SRQ_ALLOCATED;
  986. atomic_set(&ret->ref_count, 0);
  987. return &ret->com;
  988. }
  989. static struct res_common *alloc_counter_tr(int id, int port)
  990. {
  991. struct res_counter *ret;
  992. ret = kzalloc(sizeof(*ret), GFP_KERNEL);
  993. if (!ret)
  994. return NULL;
  995. ret->com.res_id = id;
  996. ret->com.state = RES_COUNTER_ALLOCATED;
  997. ret->port = port;
  998. return &ret->com;
  999. }
  1000. static struct res_common *alloc_xrcdn_tr(int id)
  1001. {
  1002. struct res_xrcdn *ret;
  1003. ret = kzalloc(sizeof(*ret), GFP_KERNEL);
  1004. if (!ret)
  1005. return NULL;
  1006. ret->com.res_id = id;
  1007. ret->com.state = RES_XRCD_ALLOCATED;
  1008. return &ret->com;
  1009. }
  1010. static struct res_common *alloc_fs_rule_tr(u64 id, int qpn)
  1011. {
  1012. struct res_fs_rule *ret;
  1013. ret = kzalloc(sizeof(*ret), GFP_KERNEL);
  1014. if (!ret)
  1015. return NULL;
  1016. ret->com.res_id = id;
  1017. ret->com.state = RES_FS_RULE_ALLOCATED;
  1018. ret->qpn = qpn;
  1019. return &ret->com;
  1020. }
  1021. static struct res_common *alloc_tr(u64 id, enum mlx4_resource type, int slave,
  1022. int extra)
  1023. {
  1024. struct res_common *ret;
  1025. switch (type) {
  1026. case RES_QP:
  1027. ret = alloc_qp_tr(id);
  1028. break;
  1029. case RES_MPT:
  1030. ret = alloc_mpt_tr(id, extra);
  1031. break;
  1032. case RES_MTT:
  1033. ret = alloc_mtt_tr(id, extra);
  1034. break;
  1035. case RES_EQ:
  1036. ret = alloc_eq_tr(id);
  1037. break;
  1038. case RES_CQ:
  1039. ret = alloc_cq_tr(id);
  1040. break;
  1041. case RES_SRQ:
  1042. ret = alloc_srq_tr(id);
  1043. break;
  1044. case RES_MAC:
  1045. pr_err("implementation missing\n");
  1046. return NULL;
  1047. case RES_COUNTER:
  1048. ret = alloc_counter_tr(id, extra);
  1049. break;
  1050. case RES_XRCD:
  1051. ret = alloc_xrcdn_tr(id);
  1052. break;
  1053. case RES_FS_RULE:
  1054. ret = alloc_fs_rule_tr(id, extra);
  1055. break;
  1056. default:
  1057. return NULL;
  1058. }
  1059. if (ret)
  1060. ret->owner = slave;
  1061. return ret;
  1062. }
  1063. int mlx4_calc_vf_counters(struct mlx4_dev *dev, int slave, int port,
  1064. struct mlx4_counter *data)
  1065. {
  1066. struct mlx4_priv *priv = mlx4_priv(dev);
  1067. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1068. struct res_common *tmp;
  1069. struct res_counter *counter;
  1070. int *counters_arr;
  1071. int i = 0, err = 0;
  1072. memset(data, 0, sizeof(*data));
  1073. counters_arr = kmalloc_array(dev->caps.max_counters,
  1074. sizeof(*counters_arr), GFP_KERNEL);
  1075. if (!counters_arr)
  1076. return -ENOMEM;
  1077. spin_lock_irq(mlx4_tlock(dev));
  1078. list_for_each_entry(tmp,
  1079. &tracker->slave_list[slave].res_list[RES_COUNTER],
  1080. list) {
  1081. counter = container_of(tmp, struct res_counter, com);
  1082. if (counter->port == port) {
  1083. counters_arr[i] = (int)tmp->res_id;
  1084. i++;
  1085. }
  1086. }
  1087. spin_unlock_irq(mlx4_tlock(dev));
  1088. counters_arr[i] = -1;
  1089. i = 0;
  1090. while (counters_arr[i] != -1) {
  1091. err = mlx4_get_counter_stats(dev, counters_arr[i], data,
  1092. 0);
  1093. if (err) {
  1094. memset(data, 0, sizeof(*data));
  1095. goto table_changed;
  1096. }
  1097. i++;
  1098. }
  1099. table_changed:
  1100. kfree(counters_arr);
  1101. return 0;
  1102. }
  1103. static int add_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
  1104. enum mlx4_resource type, int extra)
  1105. {
  1106. int i;
  1107. int err;
  1108. struct mlx4_priv *priv = mlx4_priv(dev);
  1109. struct res_common **res_arr;
  1110. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1111. struct rb_root *root = &tracker->res_tree[type];
  1112. res_arr = kcalloc(count, sizeof(*res_arr), GFP_KERNEL);
  1113. if (!res_arr)
  1114. return -ENOMEM;
  1115. for (i = 0; i < count; ++i) {
  1116. res_arr[i] = alloc_tr(base + i, type, slave, extra);
  1117. if (!res_arr[i]) {
  1118. for (--i; i >= 0; --i)
  1119. kfree(res_arr[i]);
  1120. kfree(res_arr);
  1121. return -ENOMEM;
  1122. }
  1123. }
  1124. spin_lock_irq(mlx4_tlock(dev));
  1125. for (i = 0; i < count; ++i) {
  1126. if (find_res(dev, base + i, type)) {
  1127. err = -EEXIST;
  1128. goto undo;
  1129. }
  1130. err = res_tracker_insert(root, res_arr[i]);
  1131. if (err)
  1132. goto undo;
  1133. list_add_tail(&res_arr[i]->list,
  1134. &tracker->slave_list[slave].res_list[type]);
  1135. }
  1136. spin_unlock_irq(mlx4_tlock(dev));
  1137. kfree(res_arr);
  1138. return 0;
  1139. undo:
  1140. for (--i; i >= 0; --i) {
  1141. rb_erase(&res_arr[i]->node, root);
  1142. list_del_init(&res_arr[i]->list);
  1143. }
  1144. spin_unlock_irq(mlx4_tlock(dev));
  1145. for (i = 0; i < count; ++i)
  1146. kfree(res_arr[i]);
  1147. kfree(res_arr);
  1148. return err;
  1149. }
  1150. static int remove_qp_ok(struct res_qp *res)
  1151. {
  1152. if (res->com.state == RES_QP_BUSY || atomic_read(&res->ref_count) ||
  1153. !list_empty(&res->mcg_list)) {
  1154. pr_err("resource tracker: fail to remove qp, state %d, ref_count %d\n",
  1155. res->com.state, atomic_read(&res->ref_count));
  1156. return -EBUSY;
  1157. } else if (res->com.state != RES_QP_RESERVED) {
  1158. return -EPERM;
  1159. }
  1160. return 0;
  1161. }
  1162. static int remove_mtt_ok(struct res_mtt *res, int order)
  1163. {
  1164. if (res->com.state == RES_MTT_BUSY ||
  1165. atomic_read(&res->ref_count)) {
  1166. pr_devel("%s-%d: state %s, ref_count %d\n",
  1167. __func__, __LINE__,
  1168. mtt_states_str(res->com.state),
  1169. atomic_read(&res->ref_count));
  1170. return -EBUSY;
  1171. } else if (res->com.state != RES_MTT_ALLOCATED)
  1172. return -EPERM;
  1173. else if (res->order != order)
  1174. return -EINVAL;
  1175. return 0;
  1176. }
  1177. static int remove_mpt_ok(struct res_mpt *res)
  1178. {
  1179. if (res->com.state == RES_MPT_BUSY)
  1180. return -EBUSY;
  1181. else if (res->com.state != RES_MPT_RESERVED)
  1182. return -EPERM;
  1183. return 0;
  1184. }
  1185. static int remove_eq_ok(struct res_eq *res)
  1186. {
  1187. if (res->com.state == RES_MPT_BUSY)
  1188. return -EBUSY;
  1189. else if (res->com.state != RES_MPT_RESERVED)
  1190. return -EPERM;
  1191. return 0;
  1192. }
  1193. static int remove_counter_ok(struct res_counter *res)
  1194. {
  1195. if (res->com.state == RES_COUNTER_BUSY)
  1196. return -EBUSY;
  1197. else if (res->com.state != RES_COUNTER_ALLOCATED)
  1198. return -EPERM;
  1199. return 0;
  1200. }
  1201. static int remove_xrcdn_ok(struct res_xrcdn *res)
  1202. {
  1203. if (res->com.state == RES_XRCD_BUSY)
  1204. return -EBUSY;
  1205. else if (res->com.state != RES_XRCD_ALLOCATED)
  1206. return -EPERM;
  1207. return 0;
  1208. }
  1209. static int remove_fs_rule_ok(struct res_fs_rule *res)
  1210. {
  1211. if (res->com.state == RES_FS_RULE_BUSY)
  1212. return -EBUSY;
  1213. else if (res->com.state != RES_FS_RULE_ALLOCATED)
  1214. return -EPERM;
  1215. return 0;
  1216. }
  1217. static int remove_cq_ok(struct res_cq *res)
  1218. {
  1219. if (res->com.state == RES_CQ_BUSY)
  1220. return -EBUSY;
  1221. else if (res->com.state != RES_CQ_ALLOCATED)
  1222. return -EPERM;
  1223. return 0;
  1224. }
  1225. static int remove_srq_ok(struct res_srq *res)
  1226. {
  1227. if (res->com.state == RES_SRQ_BUSY)
  1228. return -EBUSY;
  1229. else if (res->com.state != RES_SRQ_ALLOCATED)
  1230. return -EPERM;
  1231. return 0;
  1232. }
  1233. static int remove_ok(struct res_common *res, enum mlx4_resource type, int extra)
  1234. {
  1235. switch (type) {
  1236. case RES_QP:
  1237. return remove_qp_ok((struct res_qp *)res);
  1238. case RES_CQ:
  1239. return remove_cq_ok((struct res_cq *)res);
  1240. case RES_SRQ:
  1241. return remove_srq_ok((struct res_srq *)res);
  1242. case RES_MPT:
  1243. return remove_mpt_ok((struct res_mpt *)res);
  1244. case RES_MTT:
  1245. return remove_mtt_ok((struct res_mtt *)res, extra);
  1246. case RES_MAC:
  1247. return -EOPNOTSUPP;
  1248. case RES_EQ:
  1249. return remove_eq_ok((struct res_eq *)res);
  1250. case RES_COUNTER:
  1251. return remove_counter_ok((struct res_counter *)res);
  1252. case RES_XRCD:
  1253. return remove_xrcdn_ok((struct res_xrcdn *)res);
  1254. case RES_FS_RULE:
  1255. return remove_fs_rule_ok((struct res_fs_rule *)res);
  1256. default:
  1257. return -EINVAL;
  1258. }
  1259. }
  1260. static int rem_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
  1261. enum mlx4_resource type, int extra)
  1262. {
  1263. u64 i;
  1264. int err;
  1265. struct mlx4_priv *priv = mlx4_priv(dev);
  1266. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1267. struct res_common *r;
  1268. spin_lock_irq(mlx4_tlock(dev));
  1269. for (i = base; i < base + count; ++i) {
  1270. r = res_tracker_lookup(&tracker->res_tree[type], i);
  1271. if (!r) {
  1272. err = -ENOENT;
  1273. goto out;
  1274. }
  1275. if (r->owner != slave) {
  1276. err = -EPERM;
  1277. goto out;
  1278. }
  1279. err = remove_ok(r, type, extra);
  1280. if (err)
  1281. goto out;
  1282. }
  1283. for (i = base; i < base + count; ++i) {
  1284. r = res_tracker_lookup(&tracker->res_tree[type], i);
  1285. rb_erase(&r->node, &tracker->res_tree[type]);
  1286. list_del(&r->list);
  1287. kfree(r);
  1288. }
  1289. err = 0;
  1290. out:
  1291. spin_unlock_irq(mlx4_tlock(dev));
  1292. return err;
  1293. }
  1294. static int qp_res_start_move_to(struct mlx4_dev *dev, int slave, int qpn,
  1295. enum res_qp_states state, struct res_qp **qp,
  1296. int alloc)
  1297. {
  1298. struct mlx4_priv *priv = mlx4_priv(dev);
  1299. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1300. struct res_qp *r;
  1301. int err = 0;
  1302. spin_lock_irq(mlx4_tlock(dev));
  1303. r = res_tracker_lookup(&tracker->res_tree[RES_QP], qpn);
  1304. if (!r)
  1305. err = -ENOENT;
  1306. else if (r->com.owner != slave)
  1307. err = -EPERM;
  1308. else {
  1309. switch (state) {
  1310. case RES_QP_BUSY:
  1311. mlx4_dbg(dev, "%s: failed RES_QP, 0x%llx\n",
  1312. __func__, r->com.res_id);
  1313. err = -EBUSY;
  1314. break;
  1315. case RES_QP_RESERVED:
  1316. if (r->com.state == RES_QP_MAPPED && !alloc)
  1317. break;
  1318. mlx4_dbg(dev, "failed RES_QP, 0x%llx\n", r->com.res_id);
  1319. err = -EINVAL;
  1320. break;
  1321. case RES_QP_MAPPED:
  1322. if ((r->com.state == RES_QP_RESERVED && alloc) ||
  1323. r->com.state == RES_QP_HW)
  1324. break;
  1325. else {
  1326. mlx4_dbg(dev, "failed RES_QP, 0x%llx\n",
  1327. r->com.res_id);
  1328. err = -EINVAL;
  1329. }
  1330. break;
  1331. case RES_QP_HW:
  1332. if (r->com.state != RES_QP_MAPPED)
  1333. err = -EINVAL;
  1334. break;
  1335. default:
  1336. err = -EINVAL;
  1337. }
  1338. if (!err) {
  1339. r->com.from_state = r->com.state;
  1340. r->com.to_state = state;
  1341. r->com.state = RES_QP_BUSY;
  1342. if (qp)
  1343. *qp = r;
  1344. }
  1345. }
  1346. spin_unlock_irq(mlx4_tlock(dev));
  1347. return err;
  1348. }
  1349. static int mr_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  1350. enum res_mpt_states state, struct res_mpt **mpt)
  1351. {
  1352. struct mlx4_priv *priv = mlx4_priv(dev);
  1353. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1354. struct res_mpt *r;
  1355. int err = 0;
  1356. spin_lock_irq(mlx4_tlock(dev));
  1357. r = res_tracker_lookup(&tracker->res_tree[RES_MPT], index);
  1358. if (!r)
  1359. err = -ENOENT;
  1360. else if (r->com.owner != slave)
  1361. err = -EPERM;
  1362. else {
  1363. switch (state) {
  1364. case RES_MPT_BUSY:
  1365. err = -EINVAL;
  1366. break;
  1367. case RES_MPT_RESERVED:
  1368. if (r->com.state != RES_MPT_MAPPED)
  1369. err = -EINVAL;
  1370. break;
  1371. case RES_MPT_MAPPED:
  1372. if (r->com.state != RES_MPT_RESERVED &&
  1373. r->com.state != RES_MPT_HW)
  1374. err = -EINVAL;
  1375. break;
  1376. case RES_MPT_HW:
  1377. if (r->com.state != RES_MPT_MAPPED)
  1378. err = -EINVAL;
  1379. break;
  1380. default:
  1381. err = -EINVAL;
  1382. }
  1383. if (!err) {
  1384. r->com.from_state = r->com.state;
  1385. r->com.to_state = state;
  1386. r->com.state = RES_MPT_BUSY;
  1387. if (mpt)
  1388. *mpt = r;
  1389. }
  1390. }
  1391. spin_unlock_irq(mlx4_tlock(dev));
  1392. return err;
  1393. }
  1394. static int eq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  1395. enum res_eq_states state, struct res_eq **eq)
  1396. {
  1397. struct mlx4_priv *priv = mlx4_priv(dev);
  1398. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1399. struct res_eq *r;
  1400. int err = 0;
  1401. spin_lock_irq(mlx4_tlock(dev));
  1402. r = res_tracker_lookup(&tracker->res_tree[RES_EQ], index);
  1403. if (!r)
  1404. err = -ENOENT;
  1405. else if (r->com.owner != slave)
  1406. err = -EPERM;
  1407. else {
  1408. switch (state) {
  1409. case RES_EQ_BUSY:
  1410. err = -EINVAL;
  1411. break;
  1412. case RES_EQ_RESERVED:
  1413. if (r->com.state != RES_EQ_HW)
  1414. err = -EINVAL;
  1415. break;
  1416. case RES_EQ_HW:
  1417. if (r->com.state != RES_EQ_RESERVED)
  1418. err = -EINVAL;
  1419. break;
  1420. default:
  1421. err = -EINVAL;
  1422. }
  1423. if (!err) {
  1424. r->com.from_state = r->com.state;
  1425. r->com.to_state = state;
  1426. r->com.state = RES_EQ_BUSY;
  1427. }
  1428. }
  1429. spin_unlock_irq(mlx4_tlock(dev));
  1430. if (!err && eq)
  1431. *eq = r;
  1432. return err;
  1433. }
  1434. static int cq_res_start_move_to(struct mlx4_dev *dev, int slave, int cqn,
  1435. enum res_cq_states state, struct res_cq **cq)
  1436. {
  1437. struct mlx4_priv *priv = mlx4_priv(dev);
  1438. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1439. struct res_cq *r;
  1440. int err;
  1441. spin_lock_irq(mlx4_tlock(dev));
  1442. r = res_tracker_lookup(&tracker->res_tree[RES_CQ], cqn);
  1443. if (!r) {
  1444. err = -ENOENT;
  1445. } else if (r->com.owner != slave) {
  1446. err = -EPERM;
  1447. } else if (state == RES_CQ_ALLOCATED) {
  1448. if (r->com.state != RES_CQ_HW)
  1449. err = -EINVAL;
  1450. else if (atomic_read(&r->ref_count))
  1451. err = -EBUSY;
  1452. else
  1453. err = 0;
  1454. } else if (state != RES_CQ_HW || r->com.state != RES_CQ_ALLOCATED) {
  1455. err = -EINVAL;
  1456. } else {
  1457. err = 0;
  1458. }
  1459. if (!err) {
  1460. r->com.from_state = r->com.state;
  1461. r->com.to_state = state;
  1462. r->com.state = RES_CQ_BUSY;
  1463. if (cq)
  1464. *cq = r;
  1465. }
  1466. spin_unlock_irq(mlx4_tlock(dev));
  1467. return err;
  1468. }
  1469. static int srq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  1470. enum res_srq_states state, struct res_srq **srq)
  1471. {
  1472. struct mlx4_priv *priv = mlx4_priv(dev);
  1473. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1474. struct res_srq *r;
  1475. int err = 0;
  1476. spin_lock_irq(mlx4_tlock(dev));
  1477. r = res_tracker_lookup(&tracker->res_tree[RES_SRQ], index);
  1478. if (!r) {
  1479. err = -ENOENT;
  1480. } else if (r->com.owner != slave) {
  1481. err = -EPERM;
  1482. } else if (state == RES_SRQ_ALLOCATED) {
  1483. if (r->com.state != RES_SRQ_HW)
  1484. err = -EINVAL;
  1485. else if (atomic_read(&r->ref_count))
  1486. err = -EBUSY;
  1487. } else if (state != RES_SRQ_HW || r->com.state != RES_SRQ_ALLOCATED) {
  1488. err = -EINVAL;
  1489. }
  1490. if (!err) {
  1491. r->com.from_state = r->com.state;
  1492. r->com.to_state = state;
  1493. r->com.state = RES_SRQ_BUSY;
  1494. if (srq)
  1495. *srq = r;
  1496. }
  1497. spin_unlock_irq(mlx4_tlock(dev));
  1498. return err;
  1499. }
  1500. static void res_abort_move(struct mlx4_dev *dev, int slave,
  1501. enum mlx4_resource type, int id)
  1502. {
  1503. struct mlx4_priv *priv = mlx4_priv(dev);
  1504. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1505. struct res_common *r;
  1506. spin_lock_irq(mlx4_tlock(dev));
  1507. r = res_tracker_lookup(&tracker->res_tree[type], id);
  1508. if (r && (r->owner == slave))
  1509. r->state = r->from_state;
  1510. spin_unlock_irq(mlx4_tlock(dev));
  1511. }
  1512. static void res_end_move(struct mlx4_dev *dev, int slave,
  1513. enum mlx4_resource type, int id)
  1514. {
  1515. struct mlx4_priv *priv = mlx4_priv(dev);
  1516. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1517. struct res_common *r;
  1518. spin_lock_irq(mlx4_tlock(dev));
  1519. r = res_tracker_lookup(&tracker->res_tree[type], id);
  1520. if (r && (r->owner == slave))
  1521. r->state = r->to_state;
  1522. spin_unlock_irq(mlx4_tlock(dev));
  1523. }
  1524. static int valid_reserved(struct mlx4_dev *dev, int slave, int qpn)
  1525. {
  1526. return mlx4_is_qp_reserved(dev, qpn) &&
  1527. (mlx4_is_master(dev) || mlx4_is_guest_proxy(dev, slave, qpn));
  1528. }
  1529. static int fw_reserved(struct mlx4_dev *dev, int qpn)
  1530. {
  1531. return qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
  1532. }
  1533. static int qp_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1534. u64 in_param, u64 *out_param)
  1535. {
  1536. int err;
  1537. int count;
  1538. int align;
  1539. int base;
  1540. int qpn;
  1541. u8 flags;
  1542. switch (op) {
  1543. case RES_OP_RESERVE:
  1544. count = get_param_l(&in_param) & 0xffffff;
  1545. /* Turn off all unsupported QP allocation flags that the
  1546. * slave tries to set.
  1547. */
  1548. flags = (get_param_l(&in_param) >> 24) & dev->caps.alloc_res_qp_mask;
  1549. align = get_param_h(&in_param);
  1550. err = mlx4_grant_resource(dev, slave, RES_QP, count, 0);
  1551. if (err)
  1552. return err;
  1553. err = __mlx4_qp_reserve_range(dev, count, align, &base, flags);
  1554. if (err) {
  1555. mlx4_release_resource(dev, slave, RES_QP, count, 0);
  1556. return err;
  1557. }
  1558. err = add_res_range(dev, slave, base, count, RES_QP, 0);
  1559. if (err) {
  1560. mlx4_release_resource(dev, slave, RES_QP, count, 0);
  1561. __mlx4_qp_release_range(dev, base, count);
  1562. return err;
  1563. }
  1564. set_param_l(out_param, base);
  1565. break;
  1566. case RES_OP_MAP_ICM:
  1567. qpn = get_param_l(&in_param) & 0x7fffff;
  1568. if (valid_reserved(dev, slave, qpn)) {
  1569. err = add_res_range(dev, slave, qpn, 1, RES_QP, 0);
  1570. if (err)
  1571. return err;
  1572. }
  1573. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED,
  1574. NULL, 1);
  1575. if (err)
  1576. return err;
  1577. if (!fw_reserved(dev, qpn)) {
  1578. err = __mlx4_qp_alloc_icm(dev, qpn);
  1579. if (err) {
  1580. res_abort_move(dev, slave, RES_QP, qpn);
  1581. return err;
  1582. }
  1583. }
  1584. res_end_move(dev, slave, RES_QP, qpn);
  1585. break;
  1586. default:
  1587. err = -EINVAL;
  1588. break;
  1589. }
  1590. return err;
  1591. }
  1592. static int mtt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1593. u64 in_param, u64 *out_param)
  1594. {
  1595. int err = -EINVAL;
  1596. int base;
  1597. int order;
  1598. if (op != RES_OP_RESERVE_AND_MAP)
  1599. return err;
  1600. order = get_param_l(&in_param);
  1601. err = mlx4_grant_resource(dev, slave, RES_MTT, 1 << order, 0);
  1602. if (err)
  1603. return err;
  1604. base = __mlx4_alloc_mtt_range(dev, order);
  1605. if (base == -1) {
  1606. mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
  1607. return -ENOMEM;
  1608. }
  1609. err = add_res_range(dev, slave, base, 1, RES_MTT, order);
  1610. if (err) {
  1611. mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
  1612. __mlx4_free_mtt_range(dev, base, order);
  1613. } else {
  1614. set_param_l(out_param, base);
  1615. }
  1616. return err;
  1617. }
  1618. static int mpt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1619. u64 in_param, u64 *out_param)
  1620. {
  1621. int err = -EINVAL;
  1622. int index;
  1623. int id;
  1624. struct res_mpt *mpt;
  1625. switch (op) {
  1626. case RES_OP_RESERVE:
  1627. err = mlx4_grant_resource(dev, slave, RES_MPT, 1, 0);
  1628. if (err)
  1629. break;
  1630. index = __mlx4_mpt_reserve(dev);
  1631. if (index == -1) {
  1632. mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
  1633. break;
  1634. }
  1635. id = index & mpt_mask(dev);
  1636. err = add_res_range(dev, slave, id, 1, RES_MPT, index);
  1637. if (err) {
  1638. mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
  1639. __mlx4_mpt_release(dev, index);
  1640. break;
  1641. }
  1642. set_param_l(out_param, index);
  1643. break;
  1644. case RES_OP_MAP_ICM:
  1645. index = get_param_l(&in_param);
  1646. id = index & mpt_mask(dev);
  1647. err = mr_res_start_move_to(dev, slave, id,
  1648. RES_MPT_MAPPED, &mpt);
  1649. if (err)
  1650. return err;
  1651. err = __mlx4_mpt_alloc_icm(dev, mpt->key);
  1652. if (err) {
  1653. res_abort_move(dev, slave, RES_MPT, id);
  1654. return err;
  1655. }
  1656. res_end_move(dev, slave, RES_MPT, id);
  1657. break;
  1658. }
  1659. return err;
  1660. }
  1661. static int cq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1662. u64 in_param, u64 *out_param)
  1663. {
  1664. int cqn;
  1665. int err;
  1666. switch (op) {
  1667. case RES_OP_RESERVE_AND_MAP:
  1668. err = mlx4_grant_resource(dev, slave, RES_CQ, 1, 0);
  1669. if (err)
  1670. break;
  1671. err = __mlx4_cq_alloc_icm(dev, &cqn);
  1672. if (err) {
  1673. mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
  1674. break;
  1675. }
  1676. err = add_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  1677. if (err) {
  1678. mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
  1679. __mlx4_cq_free_icm(dev, cqn);
  1680. break;
  1681. }
  1682. set_param_l(out_param, cqn);
  1683. break;
  1684. default:
  1685. err = -EINVAL;
  1686. }
  1687. return err;
  1688. }
  1689. static int srq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1690. u64 in_param, u64 *out_param)
  1691. {
  1692. int srqn;
  1693. int err;
  1694. switch (op) {
  1695. case RES_OP_RESERVE_AND_MAP:
  1696. err = mlx4_grant_resource(dev, slave, RES_SRQ, 1, 0);
  1697. if (err)
  1698. break;
  1699. err = __mlx4_srq_alloc_icm(dev, &srqn);
  1700. if (err) {
  1701. mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
  1702. break;
  1703. }
  1704. err = add_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  1705. if (err) {
  1706. mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
  1707. __mlx4_srq_free_icm(dev, srqn);
  1708. break;
  1709. }
  1710. set_param_l(out_param, srqn);
  1711. break;
  1712. default:
  1713. err = -EINVAL;
  1714. }
  1715. return err;
  1716. }
  1717. static int mac_find_smac_ix_in_slave(struct mlx4_dev *dev, int slave, int port,
  1718. u8 smac_index, u64 *mac)
  1719. {
  1720. struct mlx4_priv *priv = mlx4_priv(dev);
  1721. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1722. struct list_head *mac_list =
  1723. &tracker->slave_list[slave].res_list[RES_MAC];
  1724. struct mac_res *res, *tmp;
  1725. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1726. if (res->smac_index == smac_index && res->port == (u8) port) {
  1727. *mac = res->mac;
  1728. return 0;
  1729. }
  1730. }
  1731. return -ENOENT;
  1732. }
  1733. static int mac_add_to_slave(struct mlx4_dev *dev, int slave, u64 mac, int port, u8 smac_index)
  1734. {
  1735. struct mlx4_priv *priv = mlx4_priv(dev);
  1736. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1737. struct list_head *mac_list =
  1738. &tracker->slave_list[slave].res_list[RES_MAC];
  1739. struct mac_res *res, *tmp;
  1740. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1741. if (res->mac == mac && res->port == (u8) port) {
  1742. /* mac found. update ref count */
  1743. ++res->ref_count;
  1744. return 0;
  1745. }
  1746. }
  1747. if (mlx4_grant_resource(dev, slave, RES_MAC, 1, port))
  1748. return -EINVAL;
  1749. res = kzalloc(sizeof(*res), GFP_KERNEL);
  1750. if (!res) {
  1751. mlx4_release_resource(dev, slave, RES_MAC, 1, port);
  1752. return -ENOMEM;
  1753. }
  1754. res->mac = mac;
  1755. res->port = (u8) port;
  1756. res->smac_index = smac_index;
  1757. res->ref_count = 1;
  1758. list_add_tail(&res->list,
  1759. &tracker->slave_list[slave].res_list[RES_MAC]);
  1760. return 0;
  1761. }
  1762. static void mac_del_from_slave(struct mlx4_dev *dev, int slave, u64 mac,
  1763. int port)
  1764. {
  1765. struct mlx4_priv *priv = mlx4_priv(dev);
  1766. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1767. struct list_head *mac_list =
  1768. &tracker->slave_list[slave].res_list[RES_MAC];
  1769. struct mac_res *res, *tmp;
  1770. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1771. if (res->mac == mac && res->port == (u8) port) {
  1772. if (!--res->ref_count) {
  1773. list_del(&res->list);
  1774. mlx4_release_resource(dev, slave, RES_MAC, 1, port);
  1775. kfree(res);
  1776. }
  1777. break;
  1778. }
  1779. }
  1780. }
  1781. static void rem_slave_macs(struct mlx4_dev *dev, int slave)
  1782. {
  1783. struct mlx4_priv *priv = mlx4_priv(dev);
  1784. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1785. struct list_head *mac_list =
  1786. &tracker->slave_list[slave].res_list[RES_MAC];
  1787. struct mac_res *res, *tmp;
  1788. int i;
  1789. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1790. list_del(&res->list);
  1791. /* dereference the mac the num times the slave referenced it */
  1792. for (i = 0; i < res->ref_count; i++)
  1793. __mlx4_unregister_mac(dev, res->port, res->mac);
  1794. mlx4_release_resource(dev, slave, RES_MAC, 1, res->port);
  1795. kfree(res);
  1796. }
  1797. }
  1798. static int mac_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1799. u64 in_param, u64 *out_param, int in_port)
  1800. {
  1801. int err = -EINVAL;
  1802. int port;
  1803. u64 mac;
  1804. u8 smac_index;
  1805. if (op != RES_OP_RESERVE_AND_MAP)
  1806. return err;
  1807. port = !in_port ? get_param_l(out_param) : in_port;
  1808. port = mlx4_slave_convert_port(
  1809. dev, slave, port);
  1810. if (port < 0)
  1811. return -EINVAL;
  1812. mac = in_param;
  1813. err = __mlx4_register_mac(dev, port, mac);
  1814. if (err >= 0) {
  1815. smac_index = err;
  1816. set_param_l(out_param, err);
  1817. err = 0;
  1818. }
  1819. if (!err) {
  1820. err = mac_add_to_slave(dev, slave, mac, port, smac_index);
  1821. if (err)
  1822. __mlx4_unregister_mac(dev, port, mac);
  1823. }
  1824. return err;
  1825. }
  1826. static int vlan_add_to_slave(struct mlx4_dev *dev, int slave, u16 vlan,
  1827. int port, int vlan_index)
  1828. {
  1829. struct mlx4_priv *priv = mlx4_priv(dev);
  1830. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1831. struct list_head *vlan_list =
  1832. &tracker->slave_list[slave].res_list[RES_VLAN];
  1833. struct vlan_res *res, *tmp;
  1834. list_for_each_entry_safe(res, tmp, vlan_list, list) {
  1835. if (res->vlan == vlan && res->port == (u8) port) {
  1836. /* vlan found. update ref count */
  1837. ++res->ref_count;
  1838. return 0;
  1839. }
  1840. }
  1841. if (mlx4_grant_resource(dev, slave, RES_VLAN, 1, port))
  1842. return -EINVAL;
  1843. res = kzalloc(sizeof(*res), GFP_KERNEL);
  1844. if (!res) {
  1845. mlx4_release_resource(dev, slave, RES_VLAN, 1, port);
  1846. return -ENOMEM;
  1847. }
  1848. res->vlan = vlan;
  1849. res->port = (u8) port;
  1850. res->vlan_index = vlan_index;
  1851. res->ref_count = 1;
  1852. list_add_tail(&res->list,
  1853. &tracker->slave_list[slave].res_list[RES_VLAN]);
  1854. return 0;
  1855. }
  1856. static void vlan_del_from_slave(struct mlx4_dev *dev, int slave, u16 vlan,
  1857. int port)
  1858. {
  1859. struct mlx4_priv *priv = mlx4_priv(dev);
  1860. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1861. struct list_head *vlan_list =
  1862. &tracker->slave_list[slave].res_list[RES_VLAN];
  1863. struct vlan_res *res, *tmp;
  1864. list_for_each_entry_safe(res, tmp, vlan_list, list) {
  1865. if (res->vlan == vlan && res->port == (u8) port) {
  1866. if (!--res->ref_count) {
  1867. list_del(&res->list);
  1868. mlx4_release_resource(dev, slave, RES_VLAN,
  1869. 1, port);
  1870. kfree(res);
  1871. }
  1872. break;
  1873. }
  1874. }
  1875. }
  1876. static void rem_slave_vlans(struct mlx4_dev *dev, int slave)
  1877. {
  1878. struct mlx4_priv *priv = mlx4_priv(dev);
  1879. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1880. struct list_head *vlan_list =
  1881. &tracker->slave_list[slave].res_list[RES_VLAN];
  1882. struct vlan_res *res, *tmp;
  1883. int i;
  1884. list_for_each_entry_safe(res, tmp, vlan_list, list) {
  1885. list_del(&res->list);
  1886. /* dereference the vlan the num times the slave referenced it */
  1887. for (i = 0; i < res->ref_count; i++)
  1888. __mlx4_unregister_vlan(dev, res->port, res->vlan);
  1889. mlx4_release_resource(dev, slave, RES_VLAN, 1, res->port);
  1890. kfree(res);
  1891. }
  1892. }
  1893. static int vlan_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1894. u64 in_param, u64 *out_param, int in_port)
  1895. {
  1896. struct mlx4_priv *priv = mlx4_priv(dev);
  1897. struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
  1898. int err;
  1899. u16 vlan;
  1900. int vlan_index;
  1901. int port;
  1902. port = !in_port ? get_param_l(out_param) : in_port;
  1903. if (!port || op != RES_OP_RESERVE_AND_MAP)
  1904. return -EINVAL;
  1905. port = mlx4_slave_convert_port(
  1906. dev, slave, port);
  1907. if (port < 0)
  1908. return -EINVAL;
  1909. /* upstream kernels had NOP for reg/unreg vlan. Continue this. */
  1910. if (!in_port && port > 0 && port <= dev->caps.num_ports) {
  1911. slave_state[slave].old_vlan_api = true;
  1912. return 0;
  1913. }
  1914. vlan = (u16) in_param;
  1915. err = __mlx4_register_vlan(dev, port, vlan, &vlan_index);
  1916. if (!err) {
  1917. set_param_l(out_param, (u32) vlan_index);
  1918. err = vlan_add_to_slave(dev, slave, vlan, port, vlan_index);
  1919. if (err)
  1920. __mlx4_unregister_vlan(dev, port, vlan);
  1921. }
  1922. return err;
  1923. }
  1924. static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1925. u64 in_param, u64 *out_param, int port)
  1926. {
  1927. u32 index;
  1928. int err;
  1929. if (op != RES_OP_RESERVE)
  1930. return -EINVAL;
  1931. err = mlx4_grant_resource(dev, slave, RES_COUNTER, 1, 0);
  1932. if (err)
  1933. return err;
  1934. err = __mlx4_counter_alloc(dev, &index);
  1935. if (err) {
  1936. mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
  1937. return err;
  1938. }
  1939. err = add_res_range(dev, slave, index, 1, RES_COUNTER, port);
  1940. if (err) {
  1941. __mlx4_counter_free(dev, index);
  1942. mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
  1943. } else {
  1944. set_param_l(out_param, index);
  1945. }
  1946. return err;
  1947. }
  1948. static int xrcdn_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1949. u64 in_param, u64 *out_param)
  1950. {
  1951. u32 xrcdn;
  1952. int err;
  1953. if (op != RES_OP_RESERVE)
  1954. return -EINVAL;
  1955. err = __mlx4_xrcd_alloc(dev, &xrcdn);
  1956. if (err)
  1957. return err;
  1958. err = add_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
  1959. if (err)
  1960. __mlx4_xrcd_free(dev, xrcdn);
  1961. else
  1962. set_param_l(out_param, xrcdn);
  1963. return err;
  1964. }
  1965. int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
  1966. struct mlx4_vhcr *vhcr,
  1967. struct mlx4_cmd_mailbox *inbox,
  1968. struct mlx4_cmd_mailbox *outbox,
  1969. struct mlx4_cmd_info *cmd)
  1970. {
  1971. int err;
  1972. int alop = vhcr->op_modifier;
  1973. switch (vhcr->in_modifier & 0xFF) {
  1974. case RES_QP:
  1975. err = qp_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1976. vhcr->in_param, &vhcr->out_param);
  1977. break;
  1978. case RES_MTT:
  1979. err = mtt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1980. vhcr->in_param, &vhcr->out_param);
  1981. break;
  1982. case RES_MPT:
  1983. err = mpt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1984. vhcr->in_param, &vhcr->out_param);
  1985. break;
  1986. case RES_CQ:
  1987. err = cq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1988. vhcr->in_param, &vhcr->out_param);
  1989. break;
  1990. case RES_SRQ:
  1991. err = srq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1992. vhcr->in_param, &vhcr->out_param);
  1993. break;
  1994. case RES_MAC:
  1995. err = mac_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1996. vhcr->in_param, &vhcr->out_param,
  1997. (vhcr->in_modifier >> 8) & 0xFF);
  1998. break;
  1999. case RES_VLAN:
  2000. err = vlan_alloc_res(dev, slave, vhcr->op_modifier, alop,
  2001. vhcr->in_param, &vhcr->out_param,
  2002. (vhcr->in_modifier >> 8) & 0xFF);
  2003. break;
  2004. case RES_COUNTER:
  2005. err = counter_alloc_res(dev, slave, vhcr->op_modifier, alop,
  2006. vhcr->in_param, &vhcr->out_param, 0);
  2007. break;
  2008. case RES_XRCD:
  2009. err = xrcdn_alloc_res(dev, slave, vhcr->op_modifier, alop,
  2010. vhcr->in_param, &vhcr->out_param);
  2011. break;
  2012. default:
  2013. err = -EINVAL;
  2014. break;
  2015. }
  2016. return err;
  2017. }
  2018. static int qp_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  2019. u64 in_param)
  2020. {
  2021. int err;
  2022. int count;
  2023. int base;
  2024. int qpn;
  2025. switch (op) {
  2026. case RES_OP_RESERVE:
  2027. base = get_param_l(&in_param) & 0x7fffff;
  2028. count = get_param_h(&in_param);
  2029. err = rem_res_range(dev, slave, base, count, RES_QP, 0);
  2030. if (err)
  2031. break;
  2032. mlx4_release_resource(dev, slave, RES_QP, count, 0);
  2033. __mlx4_qp_release_range(dev, base, count);
  2034. break;
  2035. case RES_OP_MAP_ICM:
  2036. qpn = get_param_l(&in_param) & 0x7fffff;
  2037. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_RESERVED,
  2038. NULL, 0);
  2039. if (err)
  2040. return err;
  2041. if (!fw_reserved(dev, qpn))
  2042. __mlx4_qp_free_icm(dev, qpn);
  2043. res_end_move(dev, slave, RES_QP, qpn);
  2044. if (valid_reserved(dev, slave, qpn))
  2045. err = rem_res_range(dev, slave, qpn, 1, RES_QP, 0);
  2046. break;
  2047. default:
  2048. err = -EINVAL;
  2049. break;
  2050. }
  2051. return err;
  2052. }
  2053. static int mtt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  2054. u64 in_param, u64 *out_param)
  2055. {
  2056. int err = -EINVAL;
  2057. int base;
  2058. int order;
  2059. if (op != RES_OP_RESERVE_AND_MAP)
  2060. return err;
  2061. base = get_param_l(&in_param);
  2062. order = get_param_h(&in_param);
  2063. err = rem_res_range(dev, slave, base, 1, RES_MTT, order);
  2064. if (!err) {
  2065. mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
  2066. __mlx4_free_mtt_range(dev, base, order);
  2067. }
  2068. return err;
  2069. }
  2070. static int mpt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  2071. u64 in_param)
  2072. {
  2073. int err = -EINVAL;
  2074. int index;
  2075. int id;
  2076. struct res_mpt *mpt;
  2077. switch (op) {
  2078. case RES_OP_RESERVE:
  2079. index = get_param_l(&in_param);
  2080. id = index & mpt_mask(dev);
  2081. err = get_res(dev, slave, id, RES_MPT, &mpt);
  2082. if (err)
  2083. break;
  2084. index = mpt->key;
  2085. put_res(dev, slave, id, RES_MPT);
  2086. err = rem_res_range(dev, slave, id, 1, RES_MPT, 0);
  2087. if (err)
  2088. break;
  2089. mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
  2090. __mlx4_mpt_release(dev, index);
  2091. break;
  2092. case RES_OP_MAP_ICM:
  2093. index = get_param_l(&in_param);
  2094. id = index & mpt_mask(dev);
  2095. err = mr_res_start_move_to(dev, slave, id,
  2096. RES_MPT_RESERVED, &mpt);
  2097. if (err)
  2098. return err;
  2099. __mlx4_mpt_free_icm(dev, mpt->key);
  2100. res_end_move(dev, slave, RES_MPT, id);
  2101. break;
  2102. default:
  2103. err = -EINVAL;
  2104. break;
  2105. }
  2106. return err;
  2107. }
  2108. static int cq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  2109. u64 in_param, u64 *out_param)
  2110. {
  2111. int cqn;
  2112. int err;
  2113. switch (op) {
  2114. case RES_OP_RESERVE_AND_MAP:
  2115. cqn = get_param_l(&in_param);
  2116. err = rem_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  2117. if (err)
  2118. break;
  2119. mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
  2120. __mlx4_cq_free_icm(dev, cqn);
  2121. break;
  2122. default:
  2123. err = -EINVAL;
  2124. break;
  2125. }
  2126. return err;
  2127. }
  2128. static int srq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  2129. u64 in_param, u64 *out_param)
  2130. {
  2131. int srqn;
  2132. int err;
  2133. switch (op) {
  2134. case RES_OP_RESERVE_AND_MAP:
  2135. srqn = get_param_l(&in_param);
  2136. err = rem_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  2137. if (err)
  2138. break;
  2139. mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
  2140. __mlx4_srq_free_icm(dev, srqn);
  2141. break;
  2142. default:
  2143. err = -EINVAL;
  2144. break;
  2145. }
  2146. return err;
  2147. }
  2148. static int mac_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  2149. u64 in_param, u64 *out_param, int in_port)
  2150. {
  2151. int port;
  2152. int err = 0;
  2153. switch (op) {
  2154. case RES_OP_RESERVE_AND_MAP:
  2155. port = !in_port ? get_param_l(out_param) : in_port;
  2156. port = mlx4_slave_convert_port(
  2157. dev, slave, port);
  2158. if (port < 0)
  2159. return -EINVAL;
  2160. mac_del_from_slave(dev, slave, in_param, port);
  2161. __mlx4_unregister_mac(dev, port, in_param);
  2162. break;
  2163. default:
  2164. err = -EINVAL;
  2165. break;
  2166. }
  2167. return err;
  2168. }
  2169. static int vlan_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  2170. u64 in_param, u64 *out_param, int port)
  2171. {
  2172. struct mlx4_priv *priv = mlx4_priv(dev);
  2173. struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
  2174. int err = 0;
  2175. port = mlx4_slave_convert_port(
  2176. dev, slave, port);
  2177. if (port < 0)
  2178. return -EINVAL;
  2179. switch (op) {
  2180. case RES_OP_RESERVE_AND_MAP:
  2181. if (slave_state[slave].old_vlan_api)
  2182. return 0;
  2183. if (!port)
  2184. return -EINVAL;
  2185. vlan_del_from_slave(dev, slave, in_param, port);
  2186. __mlx4_unregister_vlan(dev, port, in_param);
  2187. break;
  2188. default:
  2189. err = -EINVAL;
  2190. break;
  2191. }
  2192. return err;
  2193. }
  2194. static int counter_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  2195. u64 in_param, u64 *out_param)
  2196. {
  2197. int index;
  2198. int err;
  2199. if (op != RES_OP_RESERVE)
  2200. return -EINVAL;
  2201. index = get_param_l(&in_param);
  2202. if (index == MLX4_SINK_COUNTER_INDEX(dev))
  2203. return 0;
  2204. err = rem_res_range(dev, slave, index, 1, RES_COUNTER, 0);
  2205. if (err)
  2206. return err;
  2207. __mlx4_counter_free(dev, index);
  2208. mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
  2209. return err;
  2210. }
  2211. static int xrcdn_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  2212. u64 in_param, u64 *out_param)
  2213. {
  2214. int xrcdn;
  2215. int err;
  2216. if (op != RES_OP_RESERVE)
  2217. return -EINVAL;
  2218. xrcdn = get_param_l(&in_param);
  2219. err = rem_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
  2220. if (err)
  2221. return err;
  2222. __mlx4_xrcd_free(dev, xrcdn);
  2223. return err;
  2224. }
  2225. int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
  2226. struct mlx4_vhcr *vhcr,
  2227. struct mlx4_cmd_mailbox *inbox,
  2228. struct mlx4_cmd_mailbox *outbox,
  2229. struct mlx4_cmd_info *cmd)
  2230. {
  2231. int err = -EINVAL;
  2232. int alop = vhcr->op_modifier;
  2233. switch (vhcr->in_modifier & 0xFF) {
  2234. case RES_QP:
  2235. err = qp_free_res(dev, slave, vhcr->op_modifier, alop,
  2236. vhcr->in_param);
  2237. break;
  2238. case RES_MTT:
  2239. err = mtt_free_res(dev, slave, vhcr->op_modifier, alop,
  2240. vhcr->in_param, &vhcr->out_param);
  2241. break;
  2242. case RES_MPT:
  2243. err = mpt_free_res(dev, slave, vhcr->op_modifier, alop,
  2244. vhcr->in_param);
  2245. break;
  2246. case RES_CQ:
  2247. err = cq_free_res(dev, slave, vhcr->op_modifier, alop,
  2248. vhcr->in_param, &vhcr->out_param);
  2249. break;
  2250. case RES_SRQ:
  2251. err = srq_free_res(dev, slave, vhcr->op_modifier, alop,
  2252. vhcr->in_param, &vhcr->out_param);
  2253. break;
  2254. case RES_MAC:
  2255. err = mac_free_res(dev, slave, vhcr->op_modifier, alop,
  2256. vhcr->in_param, &vhcr->out_param,
  2257. (vhcr->in_modifier >> 8) & 0xFF);
  2258. break;
  2259. case RES_VLAN:
  2260. err = vlan_free_res(dev, slave, vhcr->op_modifier, alop,
  2261. vhcr->in_param, &vhcr->out_param,
  2262. (vhcr->in_modifier >> 8) & 0xFF);
  2263. break;
  2264. case RES_COUNTER:
  2265. err = counter_free_res(dev, slave, vhcr->op_modifier, alop,
  2266. vhcr->in_param, &vhcr->out_param);
  2267. break;
  2268. case RES_XRCD:
  2269. err = xrcdn_free_res(dev, slave, vhcr->op_modifier, alop,
  2270. vhcr->in_param, &vhcr->out_param);
  2271. default:
  2272. break;
  2273. }
  2274. return err;
  2275. }
  2276. /* ugly but other choices are uglier */
  2277. static int mr_phys_mpt(struct mlx4_mpt_entry *mpt)
  2278. {
  2279. return (be32_to_cpu(mpt->flags) >> 9) & 1;
  2280. }
  2281. static int mr_get_mtt_addr(struct mlx4_mpt_entry *mpt)
  2282. {
  2283. return (int)be64_to_cpu(mpt->mtt_addr) & 0xfffffff8;
  2284. }
  2285. static int mr_get_mtt_size(struct mlx4_mpt_entry *mpt)
  2286. {
  2287. return be32_to_cpu(mpt->mtt_sz);
  2288. }
  2289. static u32 mr_get_pd(struct mlx4_mpt_entry *mpt)
  2290. {
  2291. return be32_to_cpu(mpt->pd_flags) & 0x00ffffff;
  2292. }
  2293. static int mr_is_fmr(struct mlx4_mpt_entry *mpt)
  2294. {
  2295. return be32_to_cpu(mpt->pd_flags) & MLX4_MPT_PD_FLAG_FAST_REG;
  2296. }
  2297. static int mr_is_bind_enabled(struct mlx4_mpt_entry *mpt)
  2298. {
  2299. return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_BIND_ENABLE;
  2300. }
  2301. static int mr_is_region(struct mlx4_mpt_entry *mpt)
  2302. {
  2303. return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_REGION;
  2304. }
  2305. static int qp_get_mtt_addr(struct mlx4_qp_context *qpc)
  2306. {
  2307. return be32_to_cpu(qpc->mtt_base_addr_l) & 0xfffffff8;
  2308. }
  2309. static int srq_get_mtt_addr(struct mlx4_srq_context *srqc)
  2310. {
  2311. return be32_to_cpu(srqc->mtt_base_addr_l) & 0xfffffff8;
  2312. }
  2313. static int qp_get_mtt_size(struct mlx4_qp_context *qpc)
  2314. {
  2315. int page_shift = (qpc->log_page_size & 0x3f) + 12;
  2316. int log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;
  2317. int log_sq_sride = qpc->sq_size_stride & 7;
  2318. int log_rq_size = (qpc->rq_size_stride >> 3) & 0xf;
  2319. int log_rq_stride = qpc->rq_size_stride & 7;
  2320. int srq = (be32_to_cpu(qpc->srqn) >> 24) & 1;
  2321. int rss = (be32_to_cpu(qpc->flags) >> 13) & 1;
  2322. u32 ts = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
  2323. int xrc = (ts == MLX4_QP_ST_XRC) ? 1 : 0;
  2324. int sq_size;
  2325. int rq_size;
  2326. int total_pages;
  2327. int total_mem;
  2328. int page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f;
  2329. sq_size = 1 << (log_sq_size + log_sq_sride + 4);
  2330. rq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4));
  2331. total_mem = sq_size + rq_size;
  2332. total_pages =
  2333. roundup_pow_of_two((total_mem + (page_offset << 6)) >>
  2334. page_shift);
  2335. return total_pages;
  2336. }
  2337. static int check_mtt_range(struct mlx4_dev *dev, int slave, int start,
  2338. int size, struct res_mtt *mtt)
  2339. {
  2340. int res_start = mtt->com.res_id;
  2341. int res_size = (1 << mtt->order);
  2342. if (start < res_start || start + size > res_start + res_size)
  2343. return -EPERM;
  2344. return 0;
  2345. }
  2346. int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  2347. struct mlx4_vhcr *vhcr,
  2348. struct mlx4_cmd_mailbox *inbox,
  2349. struct mlx4_cmd_mailbox *outbox,
  2350. struct mlx4_cmd_info *cmd)
  2351. {
  2352. int err;
  2353. int index = vhcr->in_modifier;
  2354. struct res_mtt *mtt;
  2355. struct res_mpt *mpt = NULL;
  2356. int mtt_base = mr_get_mtt_addr(inbox->buf) / dev->caps.mtt_entry_sz;
  2357. int phys;
  2358. int id;
  2359. u32 pd;
  2360. int pd_slave;
  2361. id = index & mpt_mask(dev);
  2362. err = mr_res_start_move_to(dev, slave, id, RES_MPT_HW, &mpt);
  2363. if (err)
  2364. return err;
  2365. /* Disable memory windows for VFs. */
  2366. if (!mr_is_region(inbox->buf)) {
  2367. err = -EPERM;
  2368. goto ex_abort;
  2369. }
  2370. /* Make sure that the PD bits related to the slave id are zeros. */
  2371. pd = mr_get_pd(inbox->buf);
  2372. pd_slave = (pd >> 17) & 0x7f;
  2373. if (pd_slave != 0 && --pd_slave != slave) {
  2374. err = -EPERM;
  2375. goto ex_abort;
  2376. }
  2377. if (mr_is_fmr(inbox->buf)) {
  2378. /* FMR and Bind Enable are forbidden in slave devices. */
  2379. if (mr_is_bind_enabled(inbox->buf)) {
  2380. err = -EPERM;
  2381. goto ex_abort;
  2382. }
  2383. /* FMR and Memory Windows are also forbidden. */
  2384. if (!mr_is_region(inbox->buf)) {
  2385. err = -EPERM;
  2386. goto ex_abort;
  2387. }
  2388. }
  2389. phys = mr_phys_mpt(inbox->buf);
  2390. if (!phys) {
  2391. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2392. if (err)
  2393. goto ex_abort;
  2394. err = check_mtt_range(dev, slave, mtt_base,
  2395. mr_get_mtt_size(inbox->buf), mtt);
  2396. if (err)
  2397. goto ex_put;
  2398. mpt->mtt = mtt;
  2399. }
  2400. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2401. if (err)
  2402. goto ex_put;
  2403. if (!phys) {
  2404. atomic_inc(&mtt->ref_count);
  2405. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2406. }
  2407. res_end_move(dev, slave, RES_MPT, id);
  2408. return 0;
  2409. ex_put:
  2410. if (!phys)
  2411. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2412. ex_abort:
  2413. res_abort_move(dev, slave, RES_MPT, id);
  2414. return err;
  2415. }
  2416. int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  2417. struct mlx4_vhcr *vhcr,
  2418. struct mlx4_cmd_mailbox *inbox,
  2419. struct mlx4_cmd_mailbox *outbox,
  2420. struct mlx4_cmd_info *cmd)
  2421. {
  2422. int err;
  2423. int index = vhcr->in_modifier;
  2424. struct res_mpt *mpt;
  2425. int id;
  2426. id = index & mpt_mask(dev);
  2427. err = mr_res_start_move_to(dev, slave, id, RES_MPT_MAPPED, &mpt);
  2428. if (err)
  2429. return err;
  2430. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2431. if (err)
  2432. goto ex_abort;
  2433. if (mpt->mtt)
  2434. atomic_dec(&mpt->mtt->ref_count);
  2435. res_end_move(dev, slave, RES_MPT, id);
  2436. return 0;
  2437. ex_abort:
  2438. res_abort_move(dev, slave, RES_MPT, id);
  2439. return err;
  2440. }
  2441. int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
  2442. struct mlx4_vhcr *vhcr,
  2443. struct mlx4_cmd_mailbox *inbox,
  2444. struct mlx4_cmd_mailbox *outbox,
  2445. struct mlx4_cmd_info *cmd)
  2446. {
  2447. int err;
  2448. int index = vhcr->in_modifier;
  2449. struct res_mpt *mpt;
  2450. int id;
  2451. id = index & mpt_mask(dev);
  2452. err = get_res(dev, slave, id, RES_MPT, &mpt);
  2453. if (err)
  2454. return err;
  2455. if (mpt->com.from_state == RES_MPT_MAPPED) {
  2456. /* In order to allow rereg in SRIOV, we need to alter the MPT entry. To do
  2457. * that, the VF must read the MPT. But since the MPT entry memory is not
  2458. * in the VF's virtual memory space, it must use QUERY_MPT to obtain the
  2459. * entry contents. To guarantee that the MPT cannot be changed, the driver
  2460. * must perform HW2SW_MPT before this query and return the MPT entry to HW
  2461. * ownership fofollowing the change. The change here allows the VF to
  2462. * perform QUERY_MPT also when the entry is in SW ownership.
  2463. */
  2464. struct mlx4_mpt_entry *mpt_entry = mlx4_table_find(
  2465. &mlx4_priv(dev)->mr_table.dmpt_table,
  2466. mpt->key, NULL);
  2467. if (NULL == mpt_entry || NULL == outbox->buf) {
  2468. err = -EINVAL;
  2469. goto out;
  2470. }
  2471. memcpy(outbox->buf, mpt_entry, sizeof(*mpt_entry));
  2472. err = 0;
  2473. } else if (mpt->com.from_state == RES_MPT_HW) {
  2474. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2475. } else {
  2476. err = -EBUSY;
  2477. goto out;
  2478. }
  2479. out:
  2480. put_res(dev, slave, id, RES_MPT);
  2481. return err;
  2482. }
  2483. static int qp_get_rcqn(struct mlx4_qp_context *qpc)
  2484. {
  2485. return be32_to_cpu(qpc->cqn_recv) & 0xffffff;
  2486. }
  2487. static int qp_get_scqn(struct mlx4_qp_context *qpc)
  2488. {
  2489. return be32_to_cpu(qpc->cqn_send) & 0xffffff;
  2490. }
  2491. static u32 qp_get_srqn(struct mlx4_qp_context *qpc)
  2492. {
  2493. return be32_to_cpu(qpc->srqn) & 0x1ffffff;
  2494. }
  2495. static void adjust_proxy_tun_qkey(struct mlx4_dev *dev, struct mlx4_vhcr *vhcr,
  2496. struct mlx4_qp_context *context)
  2497. {
  2498. u32 qpn = vhcr->in_modifier & 0xffffff;
  2499. u32 qkey = 0;
  2500. if (mlx4_get_parav_qkey(dev, qpn, &qkey))
  2501. return;
  2502. /* adjust qkey in qp context */
  2503. context->qkey = cpu_to_be32(qkey);
  2504. }
  2505. static int adjust_qp_sched_queue(struct mlx4_dev *dev, int slave,
  2506. struct mlx4_qp_context *qpc,
  2507. struct mlx4_cmd_mailbox *inbox);
  2508. int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
  2509. struct mlx4_vhcr *vhcr,
  2510. struct mlx4_cmd_mailbox *inbox,
  2511. struct mlx4_cmd_mailbox *outbox,
  2512. struct mlx4_cmd_info *cmd)
  2513. {
  2514. int err;
  2515. int qpn = vhcr->in_modifier & 0x7fffff;
  2516. struct res_mtt *mtt;
  2517. struct res_qp *qp;
  2518. struct mlx4_qp_context *qpc = inbox->buf + 8;
  2519. int mtt_base = qp_get_mtt_addr(qpc) / dev->caps.mtt_entry_sz;
  2520. int mtt_size = qp_get_mtt_size(qpc);
  2521. struct res_cq *rcq;
  2522. struct res_cq *scq;
  2523. int rcqn = qp_get_rcqn(qpc);
  2524. int scqn = qp_get_scqn(qpc);
  2525. u32 srqn = qp_get_srqn(qpc) & 0xffffff;
  2526. int use_srq = (qp_get_srqn(qpc) >> 24) & 1;
  2527. struct res_srq *srq;
  2528. int local_qpn = be32_to_cpu(qpc->local_qpn) & 0xffffff;
  2529. err = adjust_qp_sched_queue(dev, slave, qpc, inbox);
  2530. if (err)
  2531. return err;
  2532. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_HW, &qp, 0);
  2533. if (err)
  2534. return err;
  2535. qp->local_qpn = local_qpn;
  2536. qp->sched_queue = 0;
  2537. qp->param3 = 0;
  2538. qp->vlan_control = 0;
  2539. qp->fvl_rx = 0;
  2540. qp->pri_path_fl = 0;
  2541. qp->vlan_index = 0;
  2542. qp->feup = 0;
  2543. qp->qpc_flags = be32_to_cpu(qpc->flags);
  2544. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2545. if (err)
  2546. goto ex_abort;
  2547. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  2548. if (err)
  2549. goto ex_put_mtt;
  2550. err = get_res(dev, slave, rcqn, RES_CQ, &rcq);
  2551. if (err)
  2552. goto ex_put_mtt;
  2553. if (scqn != rcqn) {
  2554. err = get_res(dev, slave, scqn, RES_CQ, &scq);
  2555. if (err)
  2556. goto ex_put_rcq;
  2557. } else
  2558. scq = rcq;
  2559. if (use_srq) {
  2560. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  2561. if (err)
  2562. goto ex_put_scq;
  2563. }
  2564. adjust_proxy_tun_qkey(dev, vhcr, qpc);
  2565. update_pkey_index(dev, slave, inbox);
  2566. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2567. if (err)
  2568. goto ex_put_srq;
  2569. atomic_inc(&mtt->ref_count);
  2570. qp->mtt = mtt;
  2571. atomic_inc(&rcq->ref_count);
  2572. qp->rcq = rcq;
  2573. atomic_inc(&scq->ref_count);
  2574. qp->scq = scq;
  2575. if (scqn != rcqn)
  2576. put_res(dev, slave, scqn, RES_CQ);
  2577. if (use_srq) {
  2578. atomic_inc(&srq->ref_count);
  2579. put_res(dev, slave, srqn, RES_SRQ);
  2580. qp->srq = srq;
  2581. }
  2582. /* Save param3 for dynamic changes from VST back to VGT */
  2583. qp->param3 = qpc->param3;
  2584. put_res(dev, slave, rcqn, RES_CQ);
  2585. put_res(dev, slave, mtt_base, RES_MTT);
  2586. res_end_move(dev, slave, RES_QP, qpn);
  2587. return 0;
  2588. ex_put_srq:
  2589. if (use_srq)
  2590. put_res(dev, slave, srqn, RES_SRQ);
  2591. ex_put_scq:
  2592. if (scqn != rcqn)
  2593. put_res(dev, slave, scqn, RES_CQ);
  2594. ex_put_rcq:
  2595. put_res(dev, slave, rcqn, RES_CQ);
  2596. ex_put_mtt:
  2597. put_res(dev, slave, mtt_base, RES_MTT);
  2598. ex_abort:
  2599. res_abort_move(dev, slave, RES_QP, qpn);
  2600. return err;
  2601. }
  2602. static int eq_get_mtt_addr(struct mlx4_eq_context *eqc)
  2603. {
  2604. return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8;
  2605. }
  2606. static int eq_get_mtt_size(struct mlx4_eq_context *eqc)
  2607. {
  2608. int log_eq_size = eqc->log_eq_size & 0x1f;
  2609. int page_shift = (eqc->log_page_size & 0x3f) + 12;
  2610. if (log_eq_size + 5 < page_shift)
  2611. return 1;
  2612. return 1 << (log_eq_size + 5 - page_shift);
  2613. }
  2614. static int cq_get_mtt_addr(struct mlx4_cq_context *cqc)
  2615. {
  2616. return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8;
  2617. }
  2618. static int cq_get_mtt_size(struct mlx4_cq_context *cqc)
  2619. {
  2620. int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f;
  2621. int page_shift = (cqc->log_page_size & 0x3f) + 12;
  2622. if (log_cq_size + 5 < page_shift)
  2623. return 1;
  2624. return 1 << (log_cq_size + 5 - page_shift);
  2625. }
  2626. int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  2627. struct mlx4_vhcr *vhcr,
  2628. struct mlx4_cmd_mailbox *inbox,
  2629. struct mlx4_cmd_mailbox *outbox,
  2630. struct mlx4_cmd_info *cmd)
  2631. {
  2632. int err;
  2633. int eqn = vhcr->in_modifier;
  2634. int res_id = (slave << 10) | eqn;
  2635. struct mlx4_eq_context *eqc = inbox->buf;
  2636. int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz;
  2637. int mtt_size = eq_get_mtt_size(eqc);
  2638. struct res_eq *eq;
  2639. struct res_mtt *mtt;
  2640. err = add_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  2641. if (err)
  2642. return err;
  2643. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_HW, &eq);
  2644. if (err)
  2645. goto out_add;
  2646. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2647. if (err)
  2648. goto out_move;
  2649. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  2650. if (err)
  2651. goto out_put;
  2652. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2653. if (err)
  2654. goto out_put;
  2655. atomic_inc(&mtt->ref_count);
  2656. eq->mtt = mtt;
  2657. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2658. res_end_move(dev, slave, RES_EQ, res_id);
  2659. return 0;
  2660. out_put:
  2661. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2662. out_move:
  2663. res_abort_move(dev, slave, RES_EQ, res_id);
  2664. out_add:
  2665. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  2666. return err;
  2667. }
  2668. int mlx4_CONFIG_DEV_wrapper(struct mlx4_dev *dev, int slave,
  2669. struct mlx4_vhcr *vhcr,
  2670. struct mlx4_cmd_mailbox *inbox,
  2671. struct mlx4_cmd_mailbox *outbox,
  2672. struct mlx4_cmd_info *cmd)
  2673. {
  2674. int err;
  2675. u8 get = vhcr->op_modifier;
  2676. if (get != 1)
  2677. return -EPERM;
  2678. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2679. return err;
  2680. }
  2681. static int get_containing_mtt(struct mlx4_dev *dev, int slave, int start,
  2682. int len, struct res_mtt **res)
  2683. {
  2684. struct mlx4_priv *priv = mlx4_priv(dev);
  2685. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2686. struct res_mtt *mtt;
  2687. int err = -EINVAL;
  2688. spin_lock_irq(mlx4_tlock(dev));
  2689. list_for_each_entry(mtt, &tracker->slave_list[slave].res_list[RES_MTT],
  2690. com.list) {
  2691. if (!check_mtt_range(dev, slave, start, len, mtt)) {
  2692. *res = mtt;
  2693. mtt->com.from_state = mtt->com.state;
  2694. mtt->com.state = RES_MTT_BUSY;
  2695. err = 0;
  2696. break;
  2697. }
  2698. }
  2699. spin_unlock_irq(mlx4_tlock(dev));
  2700. return err;
  2701. }
  2702. static int verify_qp_parameters(struct mlx4_dev *dev,
  2703. struct mlx4_vhcr *vhcr,
  2704. struct mlx4_cmd_mailbox *inbox,
  2705. enum qp_transition transition, u8 slave)
  2706. {
  2707. u32 qp_type;
  2708. u32 qpn;
  2709. struct mlx4_qp_context *qp_ctx;
  2710. enum mlx4_qp_optpar optpar;
  2711. int port;
  2712. int num_gids;
  2713. qp_ctx = inbox->buf + 8;
  2714. qp_type = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
  2715. optpar = be32_to_cpu(*(__be32 *) inbox->buf);
  2716. if (slave != mlx4_master_func_num(dev)) {
  2717. qp_ctx->params2 &= ~MLX4_QP_BIT_FPP;
  2718. /* setting QP rate-limit is disallowed for VFs */
  2719. if (qp_ctx->rate_limit_params)
  2720. return -EPERM;
  2721. }
  2722. switch (qp_type) {
  2723. case MLX4_QP_ST_RC:
  2724. case MLX4_QP_ST_XRC:
  2725. case MLX4_QP_ST_UC:
  2726. switch (transition) {
  2727. case QP_TRANS_INIT2RTR:
  2728. case QP_TRANS_RTR2RTS:
  2729. case QP_TRANS_RTS2RTS:
  2730. case QP_TRANS_SQD2SQD:
  2731. case QP_TRANS_SQD2RTS:
  2732. if (slave != mlx4_master_func_num(dev)) {
  2733. if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH) {
  2734. port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
  2735. if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB)
  2736. num_gids = mlx4_get_slave_num_gids(dev, slave, port);
  2737. else
  2738. num_gids = 1;
  2739. if (qp_ctx->pri_path.mgid_index >= num_gids)
  2740. return -EINVAL;
  2741. }
  2742. if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
  2743. port = (qp_ctx->alt_path.sched_queue >> 6 & 1) + 1;
  2744. if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB)
  2745. num_gids = mlx4_get_slave_num_gids(dev, slave, port);
  2746. else
  2747. num_gids = 1;
  2748. if (qp_ctx->alt_path.mgid_index >= num_gids)
  2749. return -EINVAL;
  2750. }
  2751. }
  2752. break;
  2753. default:
  2754. break;
  2755. }
  2756. break;
  2757. case MLX4_QP_ST_MLX:
  2758. qpn = vhcr->in_modifier & 0x7fffff;
  2759. port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
  2760. if (transition == QP_TRANS_INIT2RTR &&
  2761. slave != mlx4_master_func_num(dev) &&
  2762. mlx4_is_qp_reserved(dev, qpn) &&
  2763. !mlx4_vf_smi_enabled(dev, slave, port)) {
  2764. /* only enabled VFs may create MLX proxy QPs */
  2765. mlx4_err(dev, "%s: unprivileged slave %d attempting to create an MLX proxy special QP on port %d\n",
  2766. __func__, slave, port);
  2767. return -EPERM;
  2768. }
  2769. break;
  2770. default:
  2771. break;
  2772. }
  2773. return 0;
  2774. }
  2775. int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
  2776. struct mlx4_vhcr *vhcr,
  2777. struct mlx4_cmd_mailbox *inbox,
  2778. struct mlx4_cmd_mailbox *outbox,
  2779. struct mlx4_cmd_info *cmd)
  2780. {
  2781. struct mlx4_mtt mtt;
  2782. __be64 *page_list = inbox->buf;
  2783. u64 *pg_list = (u64 *)page_list;
  2784. int i;
  2785. struct res_mtt *rmtt = NULL;
  2786. int start = be64_to_cpu(page_list[0]);
  2787. int npages = vhcr->in_modifier;
  2788. int err;
  2789. err = get_containing_mtt(dev, slave, start, npages, &rmtt);
  2790. if (err)
  2791. return err;
  2792. /* Call the SW implementation of write_mtt:
  2793. * - Prepare a dummy mtt struct
  2794. * - Translate inbox contents to simple addresses in host endianness */
  2795. mtt.offset = 0; /* TBD this is broken but I don't handle it since
  2796. we don't really use it */
  2797. mtt.order = 0;
  2798. mtt.page_shift = 0;
  2799. for (i = 0; i < npages; ++i)
  2800. pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL);
  2801. err = __mlx4_write_mtt(dev, &mtt, be64_to_cpu(page_list[0]), npages,
  2802. ((u64 *)page_list + 2));
  2803. if (rmtt)
  2804. put_res(dev, slave, rmtt->com.res_id, RES_MTT);
  2805. return err;
  2806. }
  2807. int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  2808. struct mlx4_vhcr *vhcr,
  2809. struct mlx4_cmd_mailbox *inbox,
  2810. struct mlx4_cmd_mailbox *outbox,
  2811. struct mlx4_cmd_info *cmd)
  2812. {
  2813. int eqn = vhcr->in_modifier;
  2814. int res_id = eqn | (slave << 10);
  2815. struct res_eq *eq;
  2816. int err;
  2817. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_RESERVED, &eq);
  2818. if (err)
  2819. return err;
  2820. err = get_res(dev, slave, eq->mtt->com.res_id, RES_MTT, NULL);
  2821. if (err)
  2822. goto ex_abort;
  2823. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2824. if (err)
  2825. goto ex_put;
  2826. atomic_dec(&eq->mtt->ref_count);
  2827. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  2828. res_end_move(dev, slave, RES_EQ, res_id);
  2829. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  2830. return 0;
  2831. ex_put:
  2832. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  2833. ex_abort:
  2834. res_abort_move(dev, slave, RES_EQ, res_id);
  2835. return err;
  2836. }
  2837. int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe)
  2838. {
  2839. struct mlx4_priv *priv = mlx4_priv(dev);
  2840. struct mlx4_slave_event_eq_info *event_eq;
  2841. struct mlx4_cmd_mailbox *mailbox;
  2842. u32 in_modifier = 0;
  2843. int err;
  2844. int res_id;
  2845. struct res_eq *req;
  2846. if (!priv->mfunc.master.slave_state)
  2847. return -EINVAL;
  2848. /* check for slave valid, slave not PF, and slave active */
  2849. if (slave < 0 || slave > dev->persist->num_vfs ||
  2850. slave == dev->caps.function ||
  2851. !priv->mfunc.master.slave_state[slave].active)
  2852. return 0;
  2853. event_eq = &priv->mfunc.master.slave_state[slave].event_eq[eqe->type];
  2854. /* Create the event only if the slave is registered */
  2855. if (event_eq->eqn < 0)
  2856. return 0;
  2857. mutex_lock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  2858. res_id = (slave << 10) | event_eq->eqn;
  2859. err = get_res(dev, slave, res_id, RES_EQ, &req);
  2860. if (err)
  2861. goto unlock;
  2862. if (req->com.from_state != RES_EQ_HW) {
  2863. err = -EINVAL;
  2864. goto put;
  2865. }
  2866. mailbox = mlx4_alloc_cmd_mailbox(dev);
  2867. if (IS_ERR(mailbox)) {
  2868. err = PTR_ERR(mailbox);
  2869. goto put;
  2870. }
  2871. if (eqe->type == MLX4_EVENT_TYPE_CMD) {
  2872. ++event_eq->token;
  2873. eqe->event.cmd.token = cpu_to_be16(event_eq->token);
  2874. }
  2875. memcpy(mailbox->buf, (u8 *) eqe, 28);
  2876. in_modifier = (slave & 0xff) | ((event_eq->eqn & 0x3ff) << 16);
  2877. err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
  2878. MLX4_CMD_GEN_EQE, MLX4_CMD_TIME_CLASS_B,
  2879. MLX4_CMD_NATIVE);
  2880. put_res(dev, slave, res_id, RES_EQ);
  2881. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  2882. mlx4_free_cmd_mailbox(dev, mailbox);
  2883. return err;
  2884. put:
  2885. put_res(dev, slave, res_id, RES_EQ);
  2886. unlock:
  2887. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  2888. return err;
  2889. }
  2890. int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
  2891. struct mlx4_vhcr *vhcr,
  2892. struct mlx4_cmd_mailbox *inbox,
  2893. struct mlx4_cmd_mailbox *outbox,
  2894. struct mlx4_cmd_info *cmd)
  2895. {
  2896. int eqn = vhcr->in_modifier;
  2897. int res_id = eqn | (slave << 10);
  2898. struct res_eq *eq;
  2899. int err;
  2900. err = get_res(dev, slave, res_id, RES_EQ, &eq);
  2901. if (err)
  2902. return err;
  2903. if (eq->com.from_state != RES_EQ_HW) {
  2904. err = -EINVAL;
  2905. goto ex_put;
  2906. }
  2907. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2908. ex_put:
  2909. put_res(dev, slave, res_id, RES_EQ);
  2910. return err;
  2911. }
  2912. int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2913. struct mlx4_vhcr *vhcr,
  2914. struct mlx4_cmd_mailbox *inbox,
  2915. struct mlx4_cmd_mailbox *outbox,
  2916. struct mlx4_cmd_info *cmd)
  2917. {
  2918. int err;
  2919. int cqn = vhcr->in_modifier;
  2920. struct mlx4_cq_context *cqc = inbox->buf;
  2921. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  2922. struct res_cq *cq = NULL;
  2923. struct res_mtt *mtt;
  2924. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_HW, &cq);
  2925. if (err)
  2926. return err;
  2927. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2928. if (err)
  2929. goto out_move;
  2930. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  2931. if (err)
  2932. goto out_put;
  2933. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2934. if (err)
  2935. goto out_put;
  2936. atomic_inc(&mtt->ref_count);
  2937. cq->mtt = mtt;
  2938. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2939. res_end_move(dev, slave, RES_CQ, cqn);
  2940. return 0;
  2941. out_put:
  2942. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2943. out_move:
  2944. res_abort_move(dev, slave, RES_CQ, cqn);
  2945. return err;
  2946. }
  2947. int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2948. struct mlx4_vhcr *vhcr,
  2949. struct mlx4_cmd_mailbox *inbox,
  2950. struct mlx4_cmd_mailbox *outbox,
  2951. struct mlx4_cmd_info *cmd)
  2952. {
  2953. int err;
  2954. int cqn = vhcr->in_modifier;
  2955. struct res_cq *cq = NULL;
  2956. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_ALLOCATED, &cq);
  2957. if (err)
  2958. return err;
  2959. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2960. if (err)
  2961. goto out_move;
  2962. atomic_dec(&cq->mtt->ref_count);
  2963. res_end_move(dev, slave, RES_CQ, cqn);
  2964. return 0;
  2965. out_move:
  2966. res_abort_move(dev, slave, RES_CQ, cqn);
  2967. return err;
  2968. }
  2969. int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2970. struct mlx4_vhcr *vhcr,
  2971. struct mlx4_cmd_mailbox *inbox,
  2972. struct mlx4_cmd_mailbox *outbox,
  2973. struct mlx4_cmd_info *cmd)
  2974. {
  2975. int cqn = vhcr->in_modifier;
  2976. struct res_cq *cq;
  2977. int err;
  2978. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  2979. if (err)
  2980. return err;
  2981. if (cq->com.from_state != RES_CQ_HW)
  2982. goto ex_put;
  2983. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2984. ex_put:
  2985. put_res(dev, slave, cqn, RES_CQ);
  2986. return err;
  2987. }
  2988. static int handle_resize(struct mlx4_dev *dev, int slave,
  2989. struct mlx4_vhcr *vhcr,
  2990. struct mlx4_cmd_mailbox *inbox,
  2991. struct mlx4_cmd_mailbox *outbox,
  2992. struct mlx4_cmd_info *cmd,
  2993. struct res_cq *cq)
  2994. {
  2995. int err;
  2996. struct res_mtt *orig_mtt;
  2997. struct res_mtt *mtt;
  2998. struct mlx4_cq_context *cqc = inbox->buf;
  2999. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  3000. err = get_res(dev, slave, cq->mtt->com.res_id, RES_MTT, &orig_mtt);
  3001. if (err)
  3002. return err;
  3003. if (orig_mtt != cq->mtt) {
  3004. err = -EINVAL;
  3005. goto ex_put;
  3006. }
  3007. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  3008. if (err)
  3009. goto ex_put;
  3010. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  3011. if (err)
  3012. goto ex_put1;
  3013. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  3014. if (err)
  3015. goto ex_put1;
  3016. atomic_dec(&orig_mtt->ref_count);
  3017. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  3018. atomic_inc(&mtt->ref_count);
  3019. cq->mtt = mtt;
  3020. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  3021. return 0;
  3022. ex_put1:
  3023. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  3024. ex_put:
  3025. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  3026. return err;
  3027. }
  3028. int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  3029. struct mlx4_vhcr *vhcr,
  3030. struct mlx4_cmd_mailbox *inbox,
  3031. struct mlx4_cmd_mailbox *outbox,
  3032. struct mlx4_cmd_info *cmd)
  3033. {
  3034. int cqn = vhcr->in_modifier;
  3035. struct res_cq *cq;
  3036. int err;
  3037. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  3038. if (err)
  3039. return err;
  3040. if (cq->com.from_state != RES_CQ_HW)
  3041. goto ex_put;
  3042. if (vhcr->op_modifier == 0) {
  3043. err = handle_resize(dev, slave, vhcr, inbox, outbox, cmd, cq);
  3044. goto ex_put;
  3045. }
  3046. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  3047. ex_put:
  3048. put_res(dev, slave, cqn, RES_CQ);
  3049. return err;
  3050. }
  3051. static int srq_get_mtt_size(struct mlx4_srq_context *srqc)
  3052. {
  3053. int log_srq_size = (be32_to_cpu(srqc->state_logsize_srqn) >> 24) & 0xf;
  3054. int log_rq_stride = srqc->logstride & 7;
  3055. int page_shift = (srqc->log_page_size & 0x3f) + 12;
  3056. if (log_srq_size + log_rq_stride + 4 < page_shift)
  3057. return 1;
  3058. return 1 << (log_srq_size + log_rq_stride + 4 - page_shift);
  3059. }
  3060. int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  3061. struct mlx4_vhcr *vhcr,
  3062. struct mlx4_cmd_mailbox *inbox,
  3063. struct mlx4_cmd_mailbox *outbox,
  3064. struct mlx4_cmd_info *cmd)
  3065. {
  3066. int err;
  3067. int srqn = vhcr->in_modifier;
  3068. struct res_mtt *mtt;
  3069. struct res_srq *srq = NULL;
  3070. struct mlx4_srq_context *srqc = inbox->buf;
  3071. int mtt_base = srq_get_mtt_addr(srqc) / dev->caps.mtt_entry_sz;
  3072. if (srqn != (be32_to_cpu(srqc->state_logsize_srqn) & 0xffffff))
  3073. return -EINVAL;
  3074. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_HW, &srq);
  3075. if (err)
  3076. return err;
  3077. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  3078. if (err)
  3079. goto ex_abort;
  3080. err = check_mtt_range(dev, slave, mtt_base, srq_get_mtt_size(srqc),
  3081. mtt);
  3082. if (err)
  3083. goto ex_put_mtt;
  3084. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  3085. if (err)
  3086. goto ex_put_mtt;
  3087. atomic_inc(&mtt->ref_count);
  3088. srq->mtt = mtt;
  3089. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  3090. res_end_move(dev, slave, RES_SRQ, srqn);
  3091. return 0;
  3092. ex_put_mtt:
  3093. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  3094. ex_abort:
  3095. res_abort_move(dev, slave, RES_SRQ, srqn);
  3096. return err;
  3097. }
  3098. int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  3099. struct mlx4_vhcr *vhcr,
  3100. struct mlx4_cmd_mailbox *inbox,
  3101. struct mlx4_cmd_mailbox *outbox,
  3102. struct mlx4_cmd_info *cmd)
  3103. {
  3104. int err;
  3105. int srqn = vhcr->in_modifier;
  3106. struct res_srq *srq = NULL;
  3107. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_ALLOCATED, &srq);
  3108. if (err)
  3109. return err;
  3110. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  3111. if (err)
  3112. goto ex_abort;
  3113. atomic_dec(&srq->mtt->ref_count);
  3114. if (srq->cq)
  3115. atomic_dec(&srq->cq->ref_count);
  3116. res_end_move(dev, slave, RES_SRQ, srqn);
  3117. return 0;
  3118. ex_abort:
  3119. res_abort_move(dev, slave, RES_SRQ, srqn);
  3120. return err;
  3121. }
  3122. int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  3123. struct mlx4_vhcr *vhcr,
  3124. struct mlx4_cmd_mailbox *inbox,
  3125. struct mlx4_cmd_mailbox *outbox,
  3126. struct mlx4_cmd_info *cmd)
  3127. {
  3128. int err;
  3129. int srqn = vhcr->in_modifier;
  3130. struct res_srq *srq;
  3131. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  3132. if (err)
  3133. return err;
  3134. if (srq->com.from_state != RES_SRQ_HW) {
  3135. err = -EBUSY;
  3136. goto out;
  3137. }
  3138. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  3139. out:
  3140. put_res(dev, slave, srqn, RES_SRQ);
  3141. return err;
  3142. }
  3143. int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  3144. struct mlx4_vhcr *vhcr,
  3145. struct mlx4_cmd_mailbox *inbox,
  3146. struct mlx4_cmd_mailbox *outbox,
  3147. struct mlx4_cmd_info *cmd)
  3148. {
  3149. int err;
  3150. int srqn = vhcr->in_modifier;
  3151. struct res_srq *srq;
  3152. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  3153. if (err)
  3154. return err;
  3155. if (srq->com.from_state != RES_SRQ_HW) {
  3156. err = -EBUSY;
  3157. goto out;
  3158. }
  3159. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  3160. out:
  3161. put_res(dev, slave, srqn, RES_SRQ);
  3162. return err;
  3163. }
  3164. int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
  3165. struct mlx4_vhcr *vhcr,
  3166. struct mlx4_cmd_mailbox *inbox,
  3167. struct mlx4_cmd_mailbox *outbox,
  3168. struct mlx4_cmd_info *cmd)
  3169. {
  3170. int err;
  3171. int qpn = vhcr->in_modifier & 0x7fffff;
  3172. struct res_qp *qp;
  3173. err = get_res(dev, slave, qpn, RES_QP, &qp);
  3174. if (err)
  3175. return err;
  3176. if (qp->com.from_state != RES_QP_HW) {
  3177. err = -EBUSY;
  3178. goto out;
  3179. }
  3180. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  3181. out:
  3182. put_res(dev, slave, qpn, RES_QP);
  3183. return err;
  3184. }
  3185. int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
  3186. struct mlx4_vhcr *vhcr,
  3187. struct mlx4_cmd_mailbox *inbox,
  3188. struct mlx4_cmd_mailbox *outbox,
  3189. struct mlx4_cmd_info *cmd)
  3190. {
  3191. struct mlx4_qp_context *context = inbox->buf + 8;
  3192. adjust_proxy_tun_qkey(dev, vhcr, context);
  3193. update_pkey_index(dev, slave, inbox);
  3194. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  3195. }
  3196. static int adjust_qp_sched_queue(struct mlx4_dev *dev, int slave,
  3197. struct mlx4_qp_context *qpc,
  3198. struct mlx4_cmd_mailbox *inbox)
  3199. {
  3200. enum mlx4_qp_optpar optpar = be32_to_cpu(*(__be32 *)inbox->buf);
  3201. u8 pri_sched_queue;
  3202. int port = mlx4_slave_convert_port(
  3203. dev, slave, (qpc->pri_path.sched_queue >> 6 & 1) + 1) - 1;
  3204. if (port < 0)
  3205. return -EINVAL;
  3206. pri_sched_queue = (qpc->pri_path.sched_queue & ~(1 << 6)) |
  3207. ((port & 1) << 6);
  3208. if (optpar & (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH | MLX4_QP_OPTPAR_SCHED_QUEUE) ||
  3209. qpc->pri_path.sched_queue || mlx4_is_eth(dev, port + 1)) {
  3210. qpc->pri_path.sched_queue = pri_sched_queue;
  3211. }
  3212. if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
  3213. port = mlx4_slave_convert_port(
  3214. dev, slave, (qpc->alt_path.sched_queue >> 6 & 1)
  3215. + 1) - 1;
  3216. if (port < 0)
  3217. return -EINVAL;
  3218. qpc->alt_path.sched_queue =
  3219. (qpc->alt_path.sched_queue & ~(1 << 6)) |
  3220. (port & 1) << 6;
  3221. }
  3222. return 0;
  3223. }
  3224. static int roce_verify_mac(struct mlx4_dev *dev, int slave,
  3225. struct mlx4_qp_context *qpc,
  3226. struct mlx4_cmd_mailbox *inbox)
  3227. {
  3228. u64 mac;
  3229. int port;
  3230. u32 ts = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
  3231. u8 sched = *(u8 *)(inbox->buf + 64);
  3232. u8 smac_ix;
  3233. port = (sched >> 6 & 1) + 1;
  3234. if (mlx4_is_eth(dev, port) && (ts != MLX4_QP_ST_MLX)) {
  3235. smac_ix = qpc->pri_path.grh_mylmc & 0x7f;
  3236. if (mac_find_smac_ix_in_slave(dev, slave, port, smac_ix, &mac))
  3237. return -ENOENT;
  3238. }
  3239. return 0;
  3240. }
  3241. int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
  3242. struct mlx4_vhcr *vhcr,
  3243. struct mlx4_cmd_mailbox *inbox,
  3244. struct mlx4_cmd_mailbox *outbox,
  3245. struct mlx4_cmd_info *cmd)
  3246. {
  3247. int err;
  3248. struct mlx4_qp_context *qpc = inbox->buf + 8;
  3249. int qpn = vhcr->in_modifier & 0x7fffff;
  3250. struct res_qp *qp;
  3251. u8 orig_sched_queue;
  3252. u8 orig_vlan_control = qpc->pri_path.vlan_control;
  3253. u8 orig_fvl_rx = qpc->pri_path.fvl_rx;
  3254. u8 orig_pri_path_fl = qpc->pri_path.fl;
  3255. u8 orig_vlan_index = qpc->pri_path.vlan_index;
  3256. u8 orig_feup = qpc->pri_path.feup;
  3257. err = adjust_qp_sched_queue(dev, slave, qpc, inbox);
  3258. if (err)
  3259. return err;
  3260. err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_INIT2RTR, slave);
  3261. if (err)
  3262. return err;
  3263. if (roce_verify_mac(dev, slave, qpc, inbox))
  3264. return -EINVAL;
  3265. update_pkey_index(dev, slave, inbox);
  3266. update_gid(dev, inbox, (u8)slave);
  3267. adjust_proxy_tun_qkey(dev, vhcr, qpc);
  3268. orig_sched_queue = qpc->pri_path.sched_queue;
  3269. err = get_res(dev, slave, qpn, RES_QP, &qp);
  3270. if (err)
  3271. return err;
  3272. if (qp->com.from_state != RES_QP_HW) {
  3273. err = -EBUSY;
  3274. goto out;
  3275. }
  3276. err = update_vport_qp_param(dev, inbox, slave, qpn);
  3277. if (err)
  3278. goto out;
  3279. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  3280. out:
  3281. /* if no error, save sched queue value passed in by VF. This is
  3282. * essentially the QOS value provided by the VF. This will be useful
  3283. * if we allow dynamic changes from VST back to VGT
  3284. */
  3285. if (!err) {
  3286. qp->sched_queue = orig_sched_queue;
  3287. qp->vlan_control = orig_vlan_control;
  3288. qp->fvl_rx = orig_fvl_rx;
  3289. qp->pri_path_fl = orig_pri_path_fl;
  3290. qp->vlan_index = orig_vlan_index;
  3291. qp->feup = orig_feup;
  3292. }
  3293. put_res(dev, slave, qpn, RES_QP);
  3294. return err;
  3295. }
  3296. int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  3297. struct mlx4_vhcr *vhcr,
  3298. struct mlx4_cmd_mailbox *inbox,
  3299. struct mlx4_cmd_mailbox *outbox,
  3300. struct mlx4_cmd_info *cmd)
  3301. {
  3302. int err;
  3303. struct mlx4_qp_context *context = inbox->buf + 8;
  3304. err = adjust_qp_sched_queue(dev, slave, context, inbox);
  3305. if (err)
  3306. return err;
  3307. err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_RTR2RTS, slave);
  3308. if (err)
  3309. return err;
  3310. update_pkey_index(dev, slave, inbox);
  3311. update_gid(dev, inbox, (u8)slave);
  3312. adjust_proxy_tun_qkey(dev, vhcr, context);
  3313. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  3314. }
  3315. int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  3316. struct mlx4_vhcr *vhcr,
  3317. struct mlx4_cmd_mailbox *inbox,
  3318. struct mlx4_cmd_mailbox *outbox,
  3319. struct mlx4_cmd_info *cmd)
  3320. {
  3321. int err;
  3322. struct mlx4_qp_context *context = inbox->buf + 8;
  3323. err = adjust_qp_sched_queue(dev, slave, context, inbox);
  3324. if (err)
  3325. return err;
  3326. err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_RTS2RTS, slave);
  3327. if (err)
  3328. return err;
  3329. update_pkey_index(dev, slave, inbox);
  3330. update_gid(dev, inbox, (u8)slave);
  3331. adjust_proxy_tun_qkey(dev, vhcr, context);
  3332. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  3333. }
  3334. int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  3335. struct mlx4_vhcr *vhcr,
  3336. struct mlx4_cmd_mailbox *inbox,
  3337. struct mlx4_cmd_mailbox *outbox,
  3338. struct mlx4_cmd_info *cmd)
  3339. {
  3340. struct mlx4_qp_context *context = inbox->buf + 8;
  3341. int err = adjust_qp_sched_queue(dev, slave, context, inbox);
  3342. if (err)
  3343. return err;
  3344. adjust_proxy_tun_qkey(dev, vhcr, context);
  3345. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  3346. }
  3347. int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
  3348. struct mlx4_vhcr *vhcr,
  3349. struct mlx4_cmd_mailbox *inbox,
  3350. struct mlx4_cmd_mailbox *outbox,
  3351. struct mlx4_cmd_info *cmd)
  3352. {
  3353. int err;
  3354. struct mlx4_qp_context *context = inbox->buf + 8;
  3355. err = adjust_qp_sched_queue(dev, slave, context, inbox);
  3356. if (err)
  3357. return err;
  3358. err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_SQD2SQD, slave);
  3359. if (err)
  3360. return err;
  3361. adjust_proxy_tun_qkey(dev, vhcr, context);
  3362. update_gid(dev, inbox, (u8)slave);
  3363. update_pkey_index(dev, slave, inbox);
  3364. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  3365. }
  3366. int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  3367. struct mlx4_vhcr *vhcr,
  3368. struct mlx4_cmd_mailbox *inbox,
  3369. struct mlx4_cmd_mailbox *outbox,
  3370. struct mlx4_cmd_info *cmd)
  3371. {
  3372. int err;
  3373. struct mlx4_qp_context *context = inbox->buf + 8;
  3374. err = adjust_qp_sched_queue(dev, slave, context, inbox);
  3375. if (err)
  3376. return err;
  3377. err = verify_qp_parameters(dev, vhcr, inbox, QP_TRANS_SQD2RTS, slave);
  3378. if (err)
  3379. return err;
  3380. adjust_proxy_tun_qkey(dev, vhcr, context);
  3381. update_gid(dev, inbox, (u8)slave);
  3382. update_pkey_index(dev, slave, inbox);
  3383. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  3384. }
  3385. int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
  3386. struct mlx4_vhcr *vhcr,
  3387. struct mlx4_cmd_mailbox *inbox,
  3388. struct mlx4_cmd_mailbox *outbox,
  3389. struct mlx4_cmd_info *cmd)
  3390. {
  3391. int err;
  3392. int qpn = vhcr->in_modifier & 0x7fffff;
  3393. struct res_qp *qp;
  3394. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, &qp, 0);
  3395. if (err)
  3396. return err;
  3397. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  3398. if (err)
  3399. goto ex_abort;
  3400. atomic_dec(&qp->mtt->ref_count);
  3401. atomic_dec(&qp->rcq->ref_count);
  3402. atomic_dec(&qp->scq->ref_count);
  3403. if (qp->srq)
  3404. atomic_dec(&qp->srq->ref_count);
  3405. res_end_move(dev, slave, RES_QP, qpn);
  3406. return 0;
  3407. ex_abort:
  3408. res_abort_move(dev, slave, RES_QP, qpn);
  3409. return err;
  3410. }
  3411. static struct res_gid *find_gid(struct mlx4_dev *dev, int slave,
  3412. struct res_qp *rqp, u8 *gid)
  3413. {
  3414. struct res_gid *res;
  3415. list_for_each_entry(res, &rqp->mcg_list, list) {
  3416. if (!memcmp(res->gid, gid, 16))
  3417. return res;
  3418. }
  3419. return NULL;
  3420. }
  3421. static int add_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  3422. u8 *gid, enum mlx4_protocol prot,
  3423. enum mlx4_steer_type steer, u64 reg_id)
  3424. {
  3425. struct res_gid *res;
  3426. int err;
  3427. res = kzalloc(sizeof(*res), GFP_KERNEL);
  3428. if (!res)
  3429. return -ENOMEM;
  3430. spin_lock_irq(&rqp->mcg_spl);
  3431. if (find_gid(dev, slave, rqp, gid)) {
  3432. kfree(res);
  3433. err = -EEXIST;
  3434. } else {
  3435. memcpy(res->gid, gid, 16);
  3436. res->prot = prot;
  3437. res->steer = steer;
  3438. res->reg_id = reg_id;
  3439. list_add_tail(&res->list, &rqp->mcg_list);
  3440. err = 0;
  3441. }
  3442. spin_unlock_irq(&rqp->mcg_spl);
  3443. return err;
  3444. }
  3445. static int rem_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  3446. u8 *gid, enum mlx4_protocol prot,
  3447. enum mlx4_steer_type steer, u64 *reg_id)
  3448. {
  3449. struct res_gid *res;
  3450. int err;
  3451. spin_lock_irq(&rqp->mcg_spl);
  3452. res = find_gid(dev, slave, rqp, gid);
  3453. if (!res || res->prot != prot || res->steer != steer)
  3454. err = -EINVAL;
  3455. else {
  3456. *reg_id = res->reg_id;
  3457. list_del(&res->list);
  3458. kfree(res);
  3459. err = 0;
  3460. }
  3461. spin_unlock_irq(&rqp->mcg_spl);
  3462. return err;
  3463. }
  3464. static int qp_attach(struct mlx4_dev *dev, int slave, struct mlx4_qp *qp,
  3465. u8 gid[16], int block_loopback, enum mlx4_protocol prot,
  3466. enum mlx4_steer_type type, u64 *reg_id)
  3467. {
  3468. switch (dev->caps.steering_mode) {
  3469. case MLX4_STEERING_MODE_DEVICE_MANAGED: {
  3470. int port = mlx4_slave_convert_port(dev, slave, gid[5]);
  3471. if (port < 0)
  3472. return port;
  3473. return mlx4_trans_to_dmfs_attach(dev, qp, gid, port,
  3474. block_loopback, prot,
  3475. reg_id);
  3476. }
  3477. case MLX4_STEERING_MODE_B0:
  3478. if (prot == MLX4_PROT_ETH) {
  3479. int port = mlx4_slave_convert_port(dev, slave, gid[5]);
  3480. if (port < 0)
  3481. return port;
  3482. gid[5] = port;
  3483. }
  3484. return mlx4_qp_attach_common(dev, qp, gid,
  3485. block_loopback, prot, type);
  3486. default:
  3487. return -EINVAL;
  3488. }
  3489. }
  3490. static int qp_detach(struct mlx4_dev *dev, struct mlx4_qp *qp,
  3491. u8 gid[16], enum mlx4_protocol prot,
  3492. enum mlx4_steer_type type, u64 reg_id)
  3493. {
  3494. switch (dev->caps.steering_mode) {
  3495. case MLX4_STEERING_MODE_DEVICE_MANAGED:
  3496. return mlx4_flow_detach(dev, reg_id);
  3497. case MLX4_STEERING_MODE_B0:
  3498. return mlx4_qp_detach_common(dev, qp, gid, prot, type);
  3499. default:
  3500. return -EINVAL;
  3501. }
  3502. }
  3503. static int mlx4_adjust_port(struct mlx4_dev *dev, int slave,
  3504. u8 *gid, enum mlx4_protocol prot)
  3505. {
  3506. int real_port;
  3507. if (prot != MLX4_PROT_ETH)
  3508. return 0;
  3509. if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0 ||
  3510. dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
  3511. real_port = mlx4_slave_convert_port(dev, slave, gid[5]);
  3512. if (real_port < 0)
  3513. return -EINVAL;
  3514. gid[5] = real_port;
  3515. }
  3516. return 0;
  3517. }
  3518. int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
  3519. struct mlx4_vhcr *vhcr,
  3520. struct mlx4_cmd_mailbox *inbox,
  3521. struct mlx4_cmd_mailbox *outbox,
  3522. struct mlx4_cmd_info *cmd)
  3523. {
  3524. struct mlx4_qp qp; /* dummy for calling attach/detach */
  3525. u8 *gid = inbox->buf;
  3526. enum mlx4_protocol prot = (vhcr->in_modifier >> 28) & 0x7;
  3527. int err;
  3528. int qpn;
  3529. struct res_qp *rqp;
  3530. u64 reg_id = 0;
  3531. int attach = vhcr->op_modifier;
  3532. int block_loopback = vhcr->in_modifier >> 31;
  3533. u8 steer_type_mask = 2;
  3534. enum mlx4_steer_type type = (gid[7] & steer_type_mask) >> 1;
  3535. qpn = vhcr->in_modifier & 0xffffff;
  3536. err = get_res(dev, slave, qpn, RES_QP, &rqp);
  3537. if (err)
  3538. return err;
  3539. qp.qpn = qpn;
  3540. if (attach) {
  3541. err = qp_attach(dev, slave, &qp, gid, block_loopback, prot,
  3542. type, &reg_id);
  3543. if (err) {
  3544. pr_err("Fail to attach rule to qp 0x%x\n", qpn);
  3545. goto ex_put;
  3546. }
  3547. err = add_mcg_res(dev, slave, rqp, gid, prot, type, reg_id);
  3548. if (err)
  3549. goto ex_detach;
  3550. } else {
  3551. err = mlx4_adjust_port(dev, slave, gid, prot);
  3552. if (err)
  3553. goto ex_put;
  3554. err = rem_mcg_res(dev, slave, rqp, gid, prot, type, &reg_id);
  3555. if (err)
  3556. goto ex_put;
  3557. err = qp_detach(dev, &qp, gid, prot, type, reg_id);
  3558. if (err)
  3559. pr_err("Fail to detach rule from qp 0x%x reg_id = 0x%llx\n",
  3560. qpn, reg_id);
  3561. }
  3562. put_res(dev, slave, qpn, RES_QP);
  3563. return err;
  3564. ex_detach:
  3565. qp_detach(dev, &qp, gid, prot, type, reg_id);
  3566. ex_put:
  3567. put_res(dev, slave, qpn, RES_QP);
  3568. return err;
  3569. }
  3570. /*
  3571. * MAC validation for Flow Steering rules.
  3572. * VF can attach rules only with a mac address which is assigned to it.
  3573. */
  3574. static int validate_eth_header_mac(int slave, struct _rule_hw *eth_header,
  3575. struct list_head *rlist)
  3576. {
  3577. struct mac_res *res, *tmp;
  3578. __be64 be_mac;
  3579. /* make sure it isn't multicast or broadcast mac*/
  3580. if (!is_multicast_ether_addr(eth_header->eth.dst_mac) &&
  3581. !is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
  3582. list_for_each_entry_safe(res, tmp, rlist, list) {
  3583. be_mac = cpu_to_be64(res->mac << 16);
  3584. if (ether_addr_equal((u8 *)&be_mac, eth_header->eth.dst_mac))
  3585. return 0;
  3586. }
  3587. pr_err("MAC %pM doesn't belong to VF %d, Steering rule rejected\n",
  3588. eth_header->eth.dst_mac, slave);
  3589. return -EINVAL;
  3590. }
  3591. return 0;
  3592. }
  3593. /*
  3594. * In case of missing eth header, append eth header with a MAC address
  3595. * assigned to the VF.
  3596. */
  3597. static int add_eth_header(struct mlx4_dev *dev, int slave,
  3598. struct mlx4_cmd_mailbox *inbox,
  3599. struct list_head *rlist, int header_id)
  3600. {
  3601. struct mac_res *res, *tmp;
  3602. u8 port;
  3603. struct mlx4_net_trans_rule_hw_ctrl *ctrl;
  3604. struct mlx4_net_trans_rule_hw_eth *eth_header;
  3605. struct mlx4_net_trans_rule_hw_ipv4 *ip_header;
  3606. struct mlx4_net_trans_rule_hw_tcp_udp *l4_header;
  3607. __be64 be_mac = 0;
  3608. __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
  3609. ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
  3610. port = ctrl->port;
  3611. eth_header = (struct mlx4_net_trans_rule_hw_eth *)(ctrl + 1);
  3612. /* Clear a space in the inbox for eth header */
  3613. switch (header_id) {
  3614. case MLX4_NET_TRANS_RULE_ID_IPV4:
  3615. ip_header =
  3616. (struct mlx4_net_trans_rule_hw_ipv4 *)(eth_header + 1);
  3617. memmove(ip_header, eth_header,
  3618. sizeof(*ip_header) + sizeof(*l4_header));
  3619. break;
  3620. case MLX4_NET_TRANS_RULE_ID_TCP:
  3621. case MLX4_NET_TRANS_RULE_ID_UDP:
  3622. l4_header = (struct mlx4_net_trans_rule_hw_tcp_udp *)
  3623. (eth_header + 1);
  3624. memmove(l4_header, eth_header, sizeof(*l4_header));
  3625. break;
  3626. default:
  3627. return -EINVAL;
  3628. }
  3629. list_for_each_entry_safe(res, tmp, rlist, list) {
  3630. if (port == res->port) {
  3631. be_mac = cpu_to_be64(res->mac << 16);
  3632. break;
  3633. }
  3634. }
  3635. if (!be_mac) {
  3636. pr_err("Failed adding eth header to FS rule, Can't find matching MAC for port %d\n",
  3637. port);
  3638. return -EINVAL;
  3639. }
  3640. memset(eth_header, 0, sizeof(*eth_header));
  3641. eth_header->size = sizeof(*eth_header) >> 2;
  3642. eth_header->id = cpu_to_be16(__sw_id_hw[MLX4_NET_TRANS_RULE_ID_ETH]);
  3643. memcpy(eth_header->dst_mac, &be_mac, ETH_ALEN);
  3644. memcpy(eth_header->dst_mac_msk, &mac_msk, ETH_ALEN);
  3645. return 0;
  3646. }
  3647. #define MLX4_UPD_QP_PATH_MASK_SUPPORTED ( \
  3648. 1ULL << MLX4_UPD_QP_PATH_MASK_MAC_INDEX |\
  3649. 1ULL << MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB)
  3650. int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave,
  3651. struct mlx4_vhcr *vhcr,
  3652. struct mlx4_cmd_mailbox *inbox,
  3653. struct mlx4_cmd_mailbox *outbox,
  3654. struct mlx4_cmd_info *cmd_info)
  3655. {
  3656. int err;
  3657. u32 qpn = vhcr->in_modifier & 0xffffff;
  3658. struct res_qp *rqp;
  3659. u64 mac;
  3660. unsigned port;
  3661. u64 pri_addr_path_mask;
  3662. struct mlx4_update_qp_context *cmd;
  3663. int smac_index;
  3664. cmd = (struct mlx4_update_qp_context *)inbox->buf;
  3665. pri_addr_path_mask = be64_to_cpu(cmd->primary_addr_path_mask);
  3666. if (cmd->qp_mask || cmd->secondary_addr_path_mask ||
  3667. (pri_addr_path_mask & ~MLX4_UPD_QP_PATH_MASK_SUPPORTED))
  3668. return -EPERM;
  3669. if ((pri_addr_path_mask &
  3670. (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB)) &&
  3671. !(dev->caps.flags2 &
  3672. MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB)) {
  3673. mlx4_warn(dev, "Src check LB for slave %d isn't supported\n",
  3674. slave);
  3675. return -EOPNOTSUPP;
  3676. }
  3677. /* Just change the smac for the QP */
  3678. err = get_res(dev, slave, qpn, RES_QP, &rqp);
  3679. if (err) {
  3680. mlx4_err(dev, "Updating qpn 0x%x for slave %d rejected\n", qpn, slave);
  3681. return err;
  3682. }
  3683. port = (rqp->sched_queue >> 6 & 1) + 1;
  3684. if (pri_addr_path_mask & (1ULL << MLX4_UPD_QP_PATH_MASK_MAC_INDEX)) {
  3685. smac_index = cmd->qp_context.pri_path.grh_mylmc;
  3686. err = mac_find_smac_ix_in_slave(dev, slave, port,
  3687. smac_index, &mac);
  3688. if (err) {
  3689. mlx4_err(dev, "Failed to update qpn 0x%x, MAC is invalid. smac_ix: %d\n",
  3690. qpn, smac_index);
  3691. goto err_mac;
  3692. }
  3693. }
  3694. err = mlx4_cmd(dev, inbox->dma,
  3695. vhcr->in_modifier, 0,
  3696. MLX4_CMD_UPDATE_QP, MLX4_CMD_TIME_CLASS_A,
  3697. MLX4_CMD_NATIVE);
  3698. if (err) {
  3699. mlx4_err(dev, "Failed to update qpn on qpn 0x%x, command failed\n", qpn);
  3700. goto err_mac;
  3701. }
  3702. err_mac:
  3703. put_res(dev, slave, qpn, RES_QP);
  3704. return err;
  3705. }
  3706. static u32 qp_attach_mbox_size(void *mbox)
  3707. {
  3708. u32 size = sizeof(struct mlx4_net_trans_rule_hw_ctrl);
  3709. struct _rule_hw *rule_header;
  3710. rule_header = (struct _rule_hw *)(mbox + size);
  3711. while (rule_header->size) {
  3712. size += rule_header->size * sizeof(u32);
  3713. rule_header += 1;
  3714. }
  3715. return size;
  3716. }
  3717. static int mlx4_do_mirror_rule(struct mlx4_dev *dev, struct res_fs_rule *fs_rule);
  3718. int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
  3719. struct mlx4_vhcr *vhcr,
  3720. struct mlx4_cmd_mailbox *inbox,
  3721. struct mlx4_cmd_mailbox *outbox,
  3722. struct mlx4_cmd_info *cmd)
  3723. {
  3724. struct mlx4_priv *priv = mlx4_priv(dev);
  3725. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3726. struct list_head *rlist = &tracker->slave_list[slave].res_list[RES_MAC];
  3727. int err;
  3728. int qpn;
  3729. struct res_qp *rqp;
  3730. struct mlx4_net_trans_rule_hw_ctrl *ctrl;
  3731. struct _rule_hw *rule_header;
  3732. int header_id;
  3733. struct res_fs_rule *rrule;
  3734. u32 mbox_size;
  3735. if (dev->caps.steering_mode !=
  3736. MLX4_STEERING_MODE_DEVICE_MANAGED)
  3737. return -EOPNOTSUPP;
  3738. ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
  3739. err = mlx4_slave_convert_port(dev, slave, ctrl->port);
  3740. if (err <= 0)
  3741. return -EINVAL;
  3742. ctrl->port = err;
  3743. qpn = be32_to_cpu(ctrl->qpn) & 0xffffff;
  3744. err = get_res(dev, slave, qpn, RES_QP, &rqp);
  3745. if (err) {
  3746. pr_err("Steering rule with qpn 0x%x rejected\n", qpn);
  3747. return err;
  3748. }
  3749. rule_header = (struct _rule_hw *)(ctrl + 1);
  3750. header_id = map_hw_to_sw_id(be16_to_cpu(rule_header->id));
  3751. if (header_id == MLX4_NET_TRANS_RULE_ID_ETH)
  3752. mlx4_handle_eth_header_mcast_prio(ctrl, rule_header);
  3753. switch (header_id) {
  3754. case MLX4_NET_TRANS_RULE_ID_ETH:
  3755. if (validate_eth_header_mac(slave, rule_header, rlist)) {
  3756. err = -EINVAL;
  3757. goto err_put_qp;
  3758. }
  3759. break;
  3760. case MLX4_NET_TRANS_RULE_ID_IB:
  3761. break;
  3762. case MLX4_NET_TRANS_RULE_ID_IPV4:
  3763. case MLX4_NET_TRANS_RULE_ID_TCP:
  3764. case MLX4_NET_TRANS_RULE_ID_UDP:
  3765. pr_warn("Can't attach FS rule without L2 headers, adding L2 header\n");
  3766. if (add_eth_header(dev, slave, inbox, rlist, header_id)) {
  3767. err = -EINVAL;
  3768. goto err_put_qp;
  3769. }
  3770. vhcr->in_modifier +=
  3771. sizeof(struct mlx4_net_trans_rule_hw_eth) >> 2;
  3772. break;
  3773. default:
  3774. pr_err("Corrupted mailbox\n");
  3775. err = -EINVAL;
  3776. goto err_put_qp;
  3777. }
  3778. err = mlx4_cmd_imm(dev, inbox->dma, &vhcr->out_param,
  3779. vhcr->in_modifier, 0,
  3780. MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
  3781. MLX4_CMD_NATIVE);
  3782. if (err)
  3783. goto err_put_qp;
  3784. err = add_res_range(dev, slave, vhcr->out_param, 1, RES_FS_RULE, qpn);
  3785. if (err) {
  3786. mlx4_err(dev, "Fail to add flow steering resources\n");
  3787. goto err_detach;
  3788. }
  3789. err = get_res(dev, slave, vhcr->out_param, RES_FS_RULE, &rrule);
  3790. if (err)
  3791. goto err_detach;
  3792. mbox_size = qp_attach_mbox_size(inbox->buf);
  3793. rrule->mirr_mbox = kmalloc(mbox_size, GFP_KERNEL);
  3794. if (!rrule->mirr_mbox) {
  3795. err = -ENOMEM;
  3796. goto err_put_rule;
  3797. }
  3798. rrule->mirr_mbox_size = mbox_size;
  3799. rrule->mirr_rule_id = 0;
  3800. memcpy(rrule->mirr_mbox, inbox->buf, mbox_size);
  3801. /* set different port */
  3802. ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)rrule->mirr_mbox;
  3803. if (ctrl->port == 1)
  3804. ctrl->port = 2;
  3805. else
  3806. ctrl->port = 1;
  3807. if (mlx4_is_bonded(dev))
  3808. mlx4_do_mirror_rule(dev, rrule);
  3809. atomic_inc(&rqp->ref_count);
  3810. err_put_rule:
  3811. put_res(dev, slave, vhcr->out_param, RES_FS_RULE);
  3812. err_detach:
  3813. /* detach rule on error */
  3814. if (err)
  3815. mlx4_cmd(dev, vhcr->out_param, 0, 0,
  3816. MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
  3817. MLX4_CMD_NATIVE);
  3818. err_put_qp:
  3819. put_res(dev, slave, qpn, RES_QP);
  3820. return err;
  3821. }
  3822. static int mlx4_undo_mirror_rule(struct mlx4_dev *dev, struct res_fs_rule *fs_rule)
  3823. {
  3824. int err;
  3825. err = rem_res_range(dev, fs_rule->com.owner, fs_rule->com.res_id, 1, RES_FS_RULE, 0);
  3826. if (err) {
  3827. mlx4_err(dev, "Fail to remove flow steering resources\n");
  3828. return err;
  3829. }
  3830. mlx4_cmd(dev, fs_rule->com.res_id, 0, 0, MLX4_QP_FLOW_STEERING_DETACH,
  3831. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
  3832. return 0;
  3833. }
  3834. int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
  3835. struct mlx4_vhcr *vhcr,
  3836. struct mlx4_cmd_mailbox *inbox,
  3837. struct mlx4_cmd_mailbox *outbox,
  3838. struct mlx4_cmd_info *cmd)
  3839. {
  3840. int err;
  3841. struct res_qp *rqp;
  3842. struct res_fs_rule *rrule;
  3843. u64 mirr_reg_id;
  3844. int qpn;
  3845. if (dev->caps.steering_mode !=
  3846. MLX4_STEERING_MODE_DEVICE_MANAGED)
  3847. return -EOPNOTSUPP;
  3848. err = get_res(dev, slave, vhcr->in_param, RES_FS_RULE, &rrule);
  3849. if (err)
  3850. return err;
  3851. if (!rrule->mirr_mbox) {
  3852. mlx4_err(dev, "Mirror rules cannot be removed explicitly\n");
  3853. put_res(dev, slave, vhcr->in_param, RES_FS_RULE);
  3854. return -EINVAL;
  3855. }
  3856. mirr_reg_id = rrule->mirr_rule_id;
  3857. kfree(rrule->mirr_mbox);
  3858. qpn = rrule->qpn;
  3859. /* Release the rule form busy state before removal */
  3860. put_res(dev, slave, vhcr->in_param, RES_FS_RULE);
  3861. err = get_res(dev, slave, qpn, RES_QP, &rqp);
  3862. if (err)
  3863. return err;
  3864. if (mirr_reg_id && mlx4_is_bonded(dev)) {
  3865. err = get_res(dev, slave, mirr_reg_id, RES_FS_RULE, &rrule);
  3866. if (err) {
  3867. mlx4_err(dev, "Fail to get resource of mirror rule\n");
  3868. } else {
  3869. put_res(dev, slave, mirr_reg_id, RES_FS_RULE);
  3870. mlx4_undo_mirror_rule(dev, rrule);
  3871. }
  3872. }
  3873. err = rem_res_range(dev, slave, vhcr->in_param, 1, RES_FS_RULE, 0);
  3874. if (err) {
  3875. mlx4_err(dev, "Fail to remove flow steering resources\n");
  3876. goto out;
  3877. }
  3878. err = mlx4_cmd(dev, vhcr->in_param, 0, 0,
  3879. MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
  3880. MLX4_CMD_NATIVE);
  3881. if (!err)
  3882. atomic_dec(&rqp->ref_count);
  3883. out:
  3884. put_res(dev, slave, qpn, RES_QP);
  3885. return err;
  3886. }
  3887. enum {
  3888. BUSY_MAX_RETRIES = 10
  3889. };
  3890. int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
  3891. struct mlx4_vhcr *vhcr,
  3892. struct mlx4_cmd_mailbox *inbox,
  3893. struct mlx4_cmd_mailbox *outbox,
  3894. struct mlx4_cmd_info *cmd)
  3895. {
  3896. int err;
  3897. int index = vhcr->in_modifier & 0xffff;
  3898. err = get_res(dev, slave, index, RES_COUNTER, NULL);
  3899. if (err)
  3900. return err;
  3901. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  3902. put_res(dev, slave, index, RES_COUNTER);
  3903. return err;
  3904. }
  3905. static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
  3906. {
  3907. struct res_gid *rgid;
  3908. struct res_gid *tmp;
  3909. struct mlx4_qp qp; /* dummy for calling attach/detach */
  3910. list_for_each_entry_safe(rgid, tmp, &rqp->mcg_list, list) {
  3911. switch (dev->caps.steering_mode) {
  3912. case MLX4_STEERING_MODE_DEVICE_MANAGED:
  3913. mlx4_flow_detach(dev, rgid->reg_id);
  3914. break;
  3915. case MLX4_STEERING_MODE_B0:
  3916. qp.qpn = rqp->local_qpn;
  3917. (void) mlx4_qp_detach_common(dev, &qp, rgid->gid,
  3918. rgid->prot, rgid->steer);
  3919. break;
  3920. }
  3921. list_del(&rgid->list);
  3922. kfree(rgid);
  3923. }
  3924. }
  3925. static int _move_all_busy(struct mlx4_dev *dev, int slave,
  3926. enum mlx4_resource type, int print)
  3927. {
  3928. struct mlx4_priv *priv = mlx4_priv(dev);
  3929. struct mlx4_resource_tracker *tracker =
  3930. &priv->mfunc.master.res_tracker;
  3931. struct list_head *rlist = &tracker->slave_list[slave].res_list[type];
  3932. struct res_common *r;
  3933. struct res_common *tmp;
  3934. int busy;
  3935. busy = 0;
  3936. spin_lock_irq(mlx4_tlock(dev));
  3937. list_for_each_entry_safe(r, tmp, rlist, list) {
  3938. if (r->owner == slave) {
  3939. if (!r->removing) {
  3940. if (r->state == RES_ANY_BUSY) {
  3941. if (print)
  3942. mlx4_dbg(dev,
  3943. "%s id 0x%llx is busy\n",
  3944. resource_str(type),
  3945. r->res_id);
  3946. ++busy;
  3947. } else {
  3948. r->from_state = r->state;
  3949. r->state = RES_ANY_BUSY;
  3950. r->removing = 1;
  3951. }
  3952. }
  3953. }
  3954. }
  3955. spin_unlock_irq(mlx4_tlock(dev));
  3956. return busy;
  3957. }
  3958. static int move_all_busy(struct mlx4_dev *dev, int slave,
  3959. enum mlx4_resource type)
  3960. {
  3961. unsigned long begin;
  3962. int busy;
  3963. begin = jiffies;
  3964. do {
  3965. busy = _move_all_busy(dev, slave, type, 0);
  3966. if (time_after(jiffies, begin + 5 * HZ))
  3967. break;
  3968. if (busy)
  3969. cond_resched();
  3970. } while (busy);
  3971. if (busy)
  3972. busy = _move_all_busy(dev, slave, type, 1);
  3973. return busy;
  3974. }
  3975. static void rem_slave_qps(struct mlx4_dev *dev, int slave)
  3976. {
  3977. struct mlx4_priv *priv = mlx4_priv(dev);
  3978. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3979. struct list_head *qp_list =
  3980. &tracker->slave_list[slave].res_list[RES_QP];
  3981. struct res_qp *qp;
  3982. struct res_qp *tmp;
  3983. int state;
  3984. u64 in_param;
  3985. int qpn;
  3986. int err;
  3987. err = move_all_busy(dev, slave, RES_QP);
  3988. if (err)
  3989. mlx4_warn(dev, "rem_slave_qps: Could not move all qps to busy for slave %d\n",
  3990. slave);
  3991. spin_lock_irq(mlx4_tlock(dev));
  3992. list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
  3993. spin_unlock_irq(mlx4_tlock(dev));
  3994. if (qp->com.owner == slave) {
  3995. qpn = qp->com.res_id;
  3996. detach_qp(dev, slave, qp);
  3997. state = qp->com.from_state;
  3998. while (state != 0) {
  3999. switch (state) {
  4000. case RES_QP_RESERVED:
  4001. spin_lock_irq(mlx4_tlock(dev));
  4002. rb_erase(&qp->com.node,
  4003. &tracker->res_tree[RES_QP]);
  4004. list_del(&qp->com.list);
  4005. spin_unlock_irq(mlx4_tlock(dev));
  4006. if (!valid_reserved(dev, slave, qpn)) {
  4007. __mlx4_qp_release_range(dev, qpn, 1);
  4008. mlx4_release_resource(dev, slave,
  4009. RES_QP, 1, 0);
  4010. }
  4011. kfree(qp);
  4012. state = 0;
  4013. break;
  4014. case RES_QP_MAPPED:
  4015. if (!valid_reserved(dev, slave, qpn))
  4016. __mlx4_qp_free_icm(dev, qpn);
  4017. state = RES_QP_RESERVED;
  4018. break;
  4019. case RES_QP_HW:
  4020. in_param = slave;
  4021. err = mlx4_cmd(dev, in_param,
  4022. qp->local_qpn, 2,
  4023. MLX4_CMD_2RST_QP,
  4024. MLX4_CMD_TIME_CLASS_A,
  4025. MLX4_CMD_NATIVE);
  4026. if (err)
  4027. mlx4_dbg(dev, "rem_slave_qps: failed to move slave %d qpn %d to reset\n",
  4028. slave, qp->local_qpn);
  4029. atomic_dec(&qp->rcq->ref_count);
  4030. atomic_dec(&qp->scq->ref_count);
  4031. atomic_dec(&qp->mtt->ref_count);
  4032. if (qp->srq)
  4033. atomic_dec(&qp->srq->ref_count);
  4034. state = RES_QP_MAPPED;
  4035. break;
  4036. default:
  4037. state = 0;
  4038. }
  4039. }
  4040. }
  4041. spin_lock_irq(mlx4_tlock(dev));
  4042. }
  4043. spin_unlock_irq(mlx4_tlock(dev));
  4044. }
  4045. static void rem_slave_srqs(struct mlx4_dev *dev, int slave)
  4046. {
  4047. struct mlx4_priv *priv = mlx4_priv(dev);
  4048. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  4049. struct list_head *srq_list =
  4050. &tracker->slave_list[slave].res_list[RES_SRQ];
  4051. struct res_srq *srq;
  4052. struct res_srq *tmp;
  4053. int state;
  4054. u64 in_param;
  4055. LIST_HEAD(tlist);
  4056. int srqn;
  4057. int err;
  4058. err = move_all_busy(dev, slave, RES_SRQ);
  4059. if (err)
  4060. mlx4_warn(dev, "rem_slave_srqs: Could not move all srqs - too busy for slave %d\n",
  4061. slave);
  4062. spin_lock_irq(mlx4_tlock(dev));
  4063. list_for_each_entry_safe(srq, tmp, srq_list, com.list) {
  4064. spin_unlock_irq(mlx4_tlock(dev));
  4065. if (srq->com.owner == slave) {
  4066. srqn = srq->com.res_id;
  4067. state = srq->com.from_state;
  4068. while (state != 0) {
  4069. switch (state) {
  4070. case RES_SRQ_ALLOCATED:
  4071. __mlx4_srq_free_icm(dev, srqn);
  4072. spin_lock_irq(mlx4_tlock(dev));
  4073. rb_erase(&srq->com.node,
  4074. &tracker->res_tree[RES_SRQ]);
  4075. list_del(&srq->com.list);
  4076. spin_unlock_irq(mlx4_tlock(dev));
  4077. mlx4_release_resource(dev, slave,
  4078. RES_SRQ, 1, 0);
  4079. kfree(srq);
  4080. state = 0;
  4081. break;
  4082. case RES_SRQ_HW:
  4083. in_param = slave;
  4084. err = mlx4_cmd(dev, in_param, srqn, 1,
  4085. MLX4_CMD_HW2SW_SRQ,
  4086. MLX4_CMD_TIME_CLASS_A,
  4087. MLX4_CMD_NATIVE);
  4088. if (err)
  4089. mlx4_dbg(dev, "rem_slave_srqs: failed to move slave %d srq %d to SW ownership\n",
  4090. slave, srqn);
  4091. atomic_dec(&srq->mtt->ref_count);
  4092. if (srq->cq)
  4093. atomic_dec(&srq->cq->ref_count);
  4094. state = RES_SRQ_ALLOCATED;
  4095. break;
  4096. default:
  4097. state = 0;
  4098. }
  4099. }
  4100. }
  4101. spin_lock_irq(mlx4_tlock(dev));
  4102. }
  4103. spin_unlock_irq(mlx4_tlock(dev));
  4104. }
  4105. static void rem_slave_cqs(struct mlx4_dev *dev, int slave)
  4106. {
  4107. struct mlx4_priv *priv = mlx4_priv(dev);
  4108. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  4109. struct list_head *cq_list =
  4110. &tracker->slave_list[slave].res_list[RES_CQ];
  4111. struct res_cq *cq;
  4112. struct res_cq *tmp;
  4113. int state;
  4114. u64 in_param;
  4115. LIST_HEAD(tlist);
  4116. int cqn;
  4117. int err;
  4118. err = move_all_busy(dev, slave, RES_CQ);
  4119. if (err)
  4120. mlx4_warn(dev, "rem_slave_cqs: Could not move all cqs - too busy for slave %d\n",
  4121. slave);
  4122. spin_lock_irq(mlx4_tlock(dev));
  4123. list_for_each_entry_safe(cq, tmp, cq_list, com.list) {
  4124. spin_unlock_irq(mlx4_tlock(dev));
  4125. if (cq->com.owner == slave && !atomic_read(&cq->ref_count)) {
  4126. cqn = cq->com.res_id;
  4127. state = cq->com.from_state;
  4128. while (state != 0) {
  4129. switch (state) {
  4130. case RES_CQ_ALLOCATED:
  4131. __mlx4_cq_free_icm(dev, cqn);
  4132. spin_lock_irq(mlx4_tlock(dev));
  4133. rb_erase(&cq->com.node,
  4134. &tracker->res_tree[RES_CQ]);
  4135. list_del(&cq->com.list);
  4136. spin_unlock_irq(mlx4_tlock(dev));
  4137. mlx4_release_resource(dev, slave,
  4138. RES_CQ, 1, 0);
  4139. kfree(cq);
  4140. state = 0;
  4141. break;
  4142. case RES_CQ_HW:
  4143. in_param = slave;
  4144. err = mlx4_cmd(dev, in_param, cqn, 1,
  4145. MLX4_CMD_HW2SW_CQ,
  4146. MLX4_CMD_TIME_CLASS_A,
  4147. MLX4_CMD_NATIVE);
  4148. if (err)
  4149. mlx4_dbg(dev, "rem_slave_cqs: failed to move slave %d cq %d to SW ownership\n",
  4150. slave, cqn);
  4151. atomic_dec(&cq->mtt->ref_count);
  4152. state = RES_CQ_ALLOCATED;
  4153. break;
  4154. default:
  4155. state = 0;
  4156. }
  4157. }
  4158. }
  4159. spin_lock_irq(mlx4_tlock(dev));
  4160. }
  4161. spin_unlock_irq(mlx4_tlock(dev));
  4162. }
  4163. static void rem_slave_mrs(struct mlx4_dev *dev, int slave)
  4164. {
  4165. struct mlx4_priv *priv = mlx4_priv(dev);
  4166. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  4167. struct list_head *mpt_list =
  4168. &tracker->slave_list[slave].res_list[RES_MPT];
  4169. struct res_mpt *mpt;
  4170. struct res_mpt *tmp;
  4171. int state;
  4172. u64 in_param;
  4173. LIST_HEAD(tlist);
  4174. int mptn;
  4175. int err;
  4176. err = move_all_busy(dev, slave, RES_MPT);
  4177. if (err)
  4178. mlx4_warn(dev, "rem_slave_mrs: Could not move all mpts - too busy for slave %d\n",
  4179. slave);
  4180. spin_lock_irq(mlx4_tlock(dev));
  4181. list_for_each_entry_safe(mpt, tmp, mpt_list, com.list) {
  4182. spin_unlock_irq(mlx4_tlock(dev));
  4183. if (mpt->com.owner == slave) {
  4184. mptn = mpt->com.res_id;
  4185. state = mpt->com.from_state;
  4186. while (state != 0) {
  4187. switch (state) {
  4188. case RES_MPT_RESERVED:
  4189. __mlx4_mpt_release(dev, mpt->key);
  4190. spin_lock_irq(mlx4_tlock(dev));
  4191. rb_erase(&mpt->com.node,
  4192. &tracker->res_tree[RES_MPT]);
  4193. list_del(&mpt->com.list);
  4194. spin_unlock_irq(mlx4_tlock(dev));
  4195. mlx4_release_resource(dev, slave,
  4196. RES_MPT, 1, 0);
  4197. kfree(mpt);
  4198. state = 0;
  4199. break;
  4200. case RES_MPT_MAPPED:
  4201. __mlx4_mpt_free_icm(dev, mpt->key);
  4202. state = RES_MPT_RESERVED;
  4203. break;
  4204. case RES_MPT_HW:
  4205. in_param = slave;
  4206. err = mlx4_cmd(dev, in_param, mptn, 0,
  4207. MLX4_CMD_HW2SW_MPT,
  4208. MLX4_CMD_TIME_CLASS_A,
  4209. MLX4_CMD_NATIVE);
  4210. if (err)
  4211. mlx4_dbg(dev, "rem_slave_mrs: failed to move slave %d mpt %d to SW ownership\n",
  4212. slave, mptn);
  4213. if (mpt->mtt)
  4214. atomic_dec(&mpt->mtt->ref_count);
  4215. state = RES_MPT_MAPPED;
  4216. break;
  4217. default:
  4218. state = 0;
  4219. }
  4220. }
  4221. }
  4222. spin_lock_irq(mlx4_tlock(dev));
  4223. }
  4224. spin_unlock_irq(mlx4_tlock(dev));
  4225. }
  4226. static void rem_slave_mtts(struct mlx4_dev *dev, int slave)
  4227. {
  4228. struct mlx4_priv *priv = mlx4_priv(dev);
  4229. struct mlx4_resource_tracker *tracker =
  4230. &priv->mfunc.master.res_tracker;
  4231. struct list_head *mtt_list =
  4232. &tracker->slave_list[slave].res_list[RES_MTT];
  4233. struct res_mtt *mtt;
  4234. struct res_mtt *tmp;
  4235. int state;
  4236. LIST_HEAD(tlist);
  4237. int base;
  4238. int err;
  4239. err = move_all_busy(dev, slave, RES_MTT);
  4240. if (err)
  4241. mlx4_warn(dev, "rem_slave_mtts: Could not move all mtts - too busy for slave %d\n",
  4242. slave);
  4243. spin_lock_irq(mlx4_tlock(dev));
  4244. list_for_each_entry_safe(mtt, tmp, mtt_list, com.list) {
  4245. spin_unlock_irq(mlx4_tlock(dev));
  4246. if (mtt->com.owner == slave) {
  4247. base = mtt->com.res_id;
  4248. state = mtt->com.from_state;
  4249. while (state != 0) {
  4250. switch (state) {
  4251. case RES_MTT_ALLOCATED:
  4252. __mlx4_free_mtt_range(dev, base,
  4253. mtt->order);
  4254. spin_lock_irq(mlx4_tlock(dev));
  4255. rb_erase(&mtt->com.node,
  4256. &tracker->res_tree[RES_MTT]);
  4257. list_del(&mtt->com.list);
  4258. spin_unlock_irq(mlx4_tlock(dev));
  4259. mlx4_release_resource(dev, slave, RES_MTT,
  4260. 1 << mtt->order, 0);
  4261. kfree(mtt);
  4262. state = 0;
  4263. break;
  4264. default:
  4265. state = 0;
  4266. }
  4267. }
  4268. }
  4269. spin_lock_irq(mlx4_tlock(dev));
  4270. }
  4271. spin_unlock_irq(mlx4_tlock(dev));
  4272. }
  4273. static int mlx4_do_mirror_rule(struct mlx4_dev *dev, struct res_fs_rule *fs_rule)
  4274. {
  4275. struct mlx4_cmd_mailbox *mailbox;
  4276. int err;
  4277. struct res_fs_rule *mirr_rule;
  4278. u64 reg_id;
  4279. mailbox = mlx4_alloc_cmd_mailbox(dev);
  4280. if (IS_ERR(mailbox))
  4281. return PTR_ERR(mailbox);
  4282. if (!fs_rule->mirr_mbox) {
  4283. mlx4_err(dev, "rule mirroring mailbox is null\n");
  4284. return -EINVAL;
  4285. }
  4286. memcpy(mailbox->buf, fs_rule->mirr_mbox, fs_rule->mirr_mbox_size);
  4287. err = mlx4_cmd_imm(dev, mailbox->dma, &reg_id, fs_rule->mirr_mbox_size >> 2, 0,
  4288. MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
  4289. MLX4_CMD_NATIVE);
  4290. mlx4_free_cmd_mailbox(dev, mailbox);
  4291. if (err)
  4292. goto err;
  4293. err = add_res_range(dev, fs_rule->com.owner, reg_id, 1, RES_FS_RULE, fs_rule->qpn);
  4294. if (err)
  4295. goto err_detach;
  4296. err = get_res(dev, fs_rule->com.owner, reg_id, RES_FS_RULE, &mirr_rule);
  4297. if (err)
  4298. goto err_rem;
  4299. fs_rule->mirr_rule_id = reg_id;
  4300. mirr_rule->mirr_rule_id = 0;
  4301. mirr_rule->mirr_mbox_size = 0;
  4302. mirr_rule->mirr_mbox = NULL;
  4303. put_res(dev, fs_rule->com.owner, reg_id, RES_FS_RULE);
  4304. return 0;
  4305. err_rem:
  4306. rem_res_range(dev, fs_rule->com.owner, reg_id, 1, RES_FS_RULE, 0);
  4307. err_detach:
  4308. mlx4_cmd(dev, reg_id, 0, 0, MLX4_QP_FLOW_STEERING_DETACH,
  4309. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
  4310. err:
  4311. return err;
  4312. }
  4313. static int mlx4_mirror_fs_rules(struct mlx4_dev *dev, bool bond)
  4314. {
  4315. struct mlx4_priv *priv = mlx4_priv(dev);
  4316. struct mlx4_resource_tracker *tracker =
  4317. &priv->mfunc.master.res_tracker;
  4318. struct rb_root *root = &tracker->res_tree[RES_FS_RULE];
  4319. struct rb_node *p;
  4320. struct res_fs_rule *fs_rule;
  4321. int err = 0;
  4322. LIST_HEAD(mirr_list);
  4323. for (p = rb_first(root); p; p = rb_next(p)) {
  4324. fs_rule = rb_entry(p, struct res_fs_rule, com.node);
  4325. if ((bond && fs_rule->mirr_mbox_size) ||
  4326. (!bond && !fs_rule->mirr_mbox_size))
  4327. list_add_tail(&fs_rule->mirr_list, &mirr_list);
  4328. }
  4329. list_for_each_entry(fs_rule, &mirr_list, mirr_list) {
  4330. if (bond)
  4331. err += mlx4_do_mirror_rule(dev, fs_rule);
  4332. else
  4333. err += mlx4_undo_mirror_rule(dev, fs_rule);
  4334. }
  4335. return err;
  4336. }
  4337. int mlx4_bond_fs_rules(struct mlx4_dev *dev)
  4338. {
  4339. return mlx4_mirror_fs_rules(dev, true);
  4340. }
  4341. int mlx4_unbond_fs_rules(struct mlx4_dev *dev)
  4342. {
  4343. return mlx4_mirror_fs_rules(dev, false);
  4344. }
  4345. static void rem_slave_fs_rule(struct mlx4_dev *dev, int slave)
  4346. {
  4347. struct mlx4_priv *priv = mlx4_priv(dev);
  4348. struct mlx4_resource_tracker *tracker =
  4349. &priv->mfunc.master.res_tracker;
  4350. struct list_head *fs_rule_list =
  4351. &tracker->slave_list[slave].res_list[RES_FS_RULE];
  4352. struct res_fs_rule *fs_rule;
  4353. struct res_fs_rule *tmp;
  4354. int state;
  4355. u64 base;
  4356. int err;
  4357. err = move_all_busy(dev, slave, RES_FS_RULE);
  4358. if (err)
  4359. mlx4_warn(dev, "rem_slave_fs_rule: Could not move all mtts to busy for slave %d\n",
  4360. slave);
  4361. spin_lock_irq(mlx4_tlock(dev));
  4362. list_for_each_entry_safe(fs_rule, tmp, fs_rule_list, com.list) {
  4363. spin_unlock_irq(mlx4_tlock(dev));
  4364. if (fs_rule->com.owner == slave) {
  4365. base = fs_rule->com.res_id;
  4366. state = fs_rule->com.from_state;
  4367. while (state != 0) {
  4368. switch (state) {
  4369. case RES_FS_RULE_ALLOCATED:
  4370. /* detach rule */
  4371. err = mlx4_cmd(dev, base, 0, 0,
  4372. MLX4_QP_FLOW_STEERING_DETACH,
  4373. MLX4_CMD_TIME_CLASS_A,
  4374. MLX4_CMD_NATIVE);
  4375. spin_lock_irq(mlx4_tlock(dev));
  4376. rb_erase(&fs_rule->com.node,
  4377. &tracker->res_tree[RES_FS_RULE]);
  4378. list_del(&fs_rule->com.list);
  4379. spin_unlock_irq(mlx4_tlock(dev));
  4380. kfree(fs_rule);
  4381. state = 0;
  4382. break;
  4383. default:
  4384. state = 0;
  4385. }
  4386. }
  4387. }
  4388. spin_lock_irq(mlx4_tlock(dev));
  4389. }
  4390. spin_unlock_irq(mlx4_tlock(dev));
  4391. }
  4392. static void rem_slave_eqs(struct mlx4_dev *dev, int slave)
  4393. {
  4394. struct mlx4_priv *priv = mlx4_priv(dev);
  4395. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  4396. struct list_head *eq_list =
  4397. &tracker->slave_list[slave].res_list[RES_EQ];
  4398. struct res_eq *eq;
  4399. struct res_eq *tmp;
  4400. int err;
  4401. int state;
  4402. LIST_HEAD(tlist);
  4403. int eqn;
  4404. err = move_all_busy(dev, slave, RES_EQ);
  4405. if (err)
  4406. mlx4_warn(dev, "rem_slave_eqs: Could not move all eqs - too busy for slave %d\n",
  4407. slave);
  4408. spin_lock_irq(mlx4_tlock(dev));
  4409. list_for_each_entry_safe(eq, tmp, eq_list, com.list) {
  4410. spin_unlock_irq(mlx4_tlock(dev));
  4411. if (eq->com.owner == slave) {
  4412. eqn = eq->com.res_id;
  4413. state = eq->com.from_state;
  4414. while (state != 0) {
  4415. switch (state) {
  4416. case RES_EQ_RESERVED:
  4417. spin_lock_irq(mlx4_tlock(dev));
  4418. rb_erase(&eq->com.node,
  4419. &tracker->res_tree[RES_EQ]);
  4420. list_del(&eq->com.list);
  4421. spin_unlock_irq(mlx4_tlock(dev));
  4422. kfree(eq);
  4423. state = 0;
  4424. break;
  4425. case RES_EQ_HW:
  4426. err = mlx4_cmd(dev, slave, eqn & 0x3ff,
  4427. 1, MLX4_CMD_HW2SW_EQ,
  4428. MLX4_CMD_TIME_CLASS_A,
  4429. MLX4_CMD_NATIVE);
  4430. if (err)
  4431. mlx4_dbg(dev, "rem_slave_eqs: failed to move slave %d eqs %d to SW ownership\n",
  4432. slave, eqn & 0x3ff);
  4433. atomic_dec(&eq->mtt->ref_count);
  4434. state = RES_EQ_RESERVED;
  4435. break;
  4436. default:
  4437. state = 0;
  4438. }
  4439. }
  4440. }
  4441. spin_lock_irq(mlx4_tlock(dev));
  4442. }
  4443. spin_unlock_irq(mlx4_tlock(dev));
  4444. }
  4445. static void rem_slave_counters(struct mlx4_dev *dev, int slave)
  4446. {
  4447. struct mlx4_priv *priv = mlx4_priv(dev);
  4448. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  4449. struct list_head *counter_list =
  4450. &tracker->slave_list[slave].res_list[RES_COUNTER];
  4451. struct res_counter *counter;
  4452. struct res_counter *tmp;
  4453. int err;
  4454. int *counters_arr = NULL;
  4455. int i, j;
  4456. err = move_all_busy(dev, slave, RES_COUNTER);
  4457. if (err)
  4458. mlx4_warn(dev, "rem_slave_counters: Could not move all counters - too busy for slave %d\n",
  4459. slave);
  4460. counters_arr = kmalloc_array(dev->caps.max_counters,
  4461. sizeof(*counters_arr), GFP_KERNEL);
  4462. if (!counters_arr)
  4463. return;
  4464. do {
  4465. i = 0;
  4466. j = 0;
  4467. spin_lock_irq(mlx4_tlock(dev));
  4468. list_for_each_entry_safe(counter, tmp, counter_list, com.list) {
  4469. if (counter->com.owner == slave) {
  4470. counters_arr[i++] = counter->com.res_id;
  4471. rb_erase(&counter->com.node,
  4472. &tracker->res_tree[RES_COUNTER]);
  4473. list_del(&counter->com.list);
  4474. kfree(counter);
  4475. }
  4476. }
  4477. spin_unlock_irq(mlx4_tlock(dev));
  4478. while (j < i) {
  4479. __mlx4_counter_free(dev, counters_arr[j++]);
  4480. mlx4_release_resource(dev, slave, RES_COUNTER, 1, 0);
  4481. }
  4482. } while (i);
  4483. kfree(counters_arr);
  4484. }
  4485. static void rem_slave_xrcdns(struct mlx4_dev *dev, int slave)
  4486. {
  4487. struct mlx4_priv *priv = mlx4_priv(dev);
  4488. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  4489. struct list_head *xrcdn_list =
  4490. &tracker->slave_list[slave].res_list[RES_XRCD];
  4491. struct res_xrcdn *xrcd;
  4492. struct res_xrcdn *tmp;
  4493. int err;
  4494. int xrcdn;
  4495. err = move_all_busy(dev, slave, RES_XRCD);
  4496. if (err)
  4497. mlx4_warn(dev, "rem_slave_xrcdns: Could not move all xrcdns - too busy for slave %d\n",
  4498. slave);
  4499. spin_lock_irq(mlx4_tlock(dev));
  4500. list_for_each_entry_safe(xrcd, tmp, xrcdn_list, com.list) {
  4501. if (xrcd->com.owner == slave) {
  4502. xrcdn = xrcd->com.res_id;
  4503. rb_erase(&xrcd->com.node, &tracker->res_tree[RES_XRCD]);
  4504. list_del(&xrcd->com.list);
  4505. kfree(xrcd);
  4506. __mlx4_xrcd_free(dev, xrcdn);
  4507. }
  4508. }
  4509. spin_unlock_irq(mlx4_tlock(dev));
  4510. }
  4511. void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave)
  4512. {
  4513. struct mlx4_priv *priv = mlx4_priv(dev);
  4514. mlx4_reset_roce_gids(dev, slave);
  4515. mutex_lock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  4516. rem_slave_vlans(dev, slave);
  4517. rem_slave_macs(dev, slave);
  4518. rem_slave_fs_rule(dev, slave);
  4519. rem_slave_qps(dev, slave);
  4520. rem_slave_srqs(dev, slave);
  4521. rem_slave_cqs(dev, slave);
  4522. rem_slave_mrs(dev, slave);
  4523. rem_slave_eqs(dev, slave);
  4524. rem_slave_mtts(dev, slave);
  4525. rem_slave_counters(dev, slave);
  4526. rem_slave_xrcdns(dev, slave);
  4527. mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  4528. }
  4529. static void update_qos_vpp(struct mlx4_update_qp_context *ctx,
  4530. struct mlx4_vf_immed_vlan_work *work)
  4531. {
  4532. ctx->qp_mask |= cpu_to_be64(1ULL << MLX4_UPD_QP_MASK_QOS_VPP);
  4533. ctx->qp_context.qos_vport = work->qos_vport;
  4534. }
  4535. void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work)
  4536. {
  4537. struct mlx4_vf_immed_vlan_work *work =
  4538. container_of(_work, struct mlx4_vf_immed_vlan_work, work);
  4539. struct mlx4_cmd_mailbox *mailbox;
  4540. struct mlx4_update_qp_context *upd_context;
  4541. struct mlx4_dev *dev = &work->priv->dev;
  4542. struct mlx4_resource_tracker *tracker =
  4543. &work->priv->mfunc.master.res_tracker;
  4544. struct list_head *qp_list =
  4545. &tracker->slave_list[work->slave].res_list[RES_QP];
  4546. struct res_qp *qp;
  4547. struct res_qp *tmp;
  4548. u64 qp_path_mask_vlan_ctrl =
  4549. ((1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED) |
  4550. (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P) |
  4551. (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED) |
  4552. (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED) |
  4553. (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P) |
  4554. (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED));
  4555. u64 qp_path_mask = ((1ULL << MLX4_UPD_QP_PATH_MASK_VLAN_INDEX) |
  4556. (1ULL << MLX4_UPD_QP_PATH_MASK_FVL) |
  4557. (1ULL << MLX4_UPD_QP_PATH_MASK_CV) |
  4558. (1ULL << MLX4_UPD_QP_PATH_MASK_SV) |
  4559. (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN) |
  4560. (1ULL << MLX4_UPD_QP_PATH_MASK_FEUP) |
  4561. (1ULL << MLX4_UPD_QP_PATH_MASK_FVL_RX) |
  4562. (1ULL << MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE));
  4563. int err;
  4564. int port, errors = 0;
  4565. u8 vlan_control;
  4566. if (mlx4_is_slave(dev)) {
  4567. mlx4_warn(dev, "Trying to update-qp in slave %d\n",
  4568. work->slave);
  4569. goto out;
  4570. }
  4571. mailbox = mlx4_alloc_cmd_mailbox(dev);
  4572. if (IS_ERR(mailbox))
  4573. goto out;
  4574. if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE) /* block all */
  4575. vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
  4576. MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
  4577. MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED |
  4578. MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
  4579. MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED |
  4580. MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
  4581. else if (!work->vlan_id)
  4582. vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
  4583. MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
  4584. else if (work->vlan_proto == htons(ETH_P_8021AD))
  4585. vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED |
  4586. MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
  4587. MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
  4588. MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
  4589. else /* vst 802.1Q */
  4590. vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
  4591. MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
  4592. MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
  4593. upd_context = mailbox->buf;
  4594. upd_context->qp_mask = cpu_to_be64(1ULL << MLX4_UPD_QP_MASK_VSD);
  4595. spin_lock_irq(mlx4_tlock(dev));
  4596. list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
  4597. spin_unlock_irq(mlx4_tlock(dev));
  4598. if (qp->com.owner == work->slave) {
  4599. if (qp->com.from_state != RES_QP_HW ||
  4600. !qp->sched_queue || /* no INIT2RTR trans yet */
  4601. mlx4_is_qp_reserved(dev, qp->local_qpn) ||
  4602. qp->qpc_flags & (1 << MLX4_RSS_QPC_FLAG_OFFSET)) {
  4603. spin_lock_irq(mlx4_tlock(dev));
  4604. continue;
  4605. }
  4606. port = (qp->sched_queue >> 6 & 1) + 1;
  4607. if (port != work->port) {
  4608. spin_lock_irq(mlx4_tlock(dev));
  4609. continue;
  4610. }
  4611. if (MLX4_QP_ST_RC == ((qp->qpc_flags >> 16) & 0xff))
  4612. upd_context->primary_addr_path_mask = cpu_to_be64(qp_path_mask);
  4613. else
  4614. upd_context->primary_addr_path_mask =
  4615. cpu_to_be64(qp_path_mask | qp_path_mask_vlan_ctrl);
  4616. if (work->vlan_id == MLX4_VGT) {
  4617. upd_context->qp_context.param3 = qp->param3;
  4618. upd_context->qp_context.pri_path.vlan_control = qp->vlan_control;
  4619. upd_context->qp_context.pri_path.fvl_rx = qp->fvl_rx;
  4620. upd_context->qp_context.pri_path.vlan_index = qp->vlan_index;
  4621. upd_context->qp_context.pri_path.fl = qp->pri_path_fl;
  4622. upd_context->qp_context.pri_path.feup = qp->feup;
  4623. upd_context->qp_context.pri_path.sched_queue =
  4624. qp->sched_queue;
  4625. } else {
  4626. upd_context->qp_context.param3 = qp->param3 & ~cpu_to_be32(MLX4_STRIP_VLAN);
  4627. upd_context->qp_context.pri_path.vlan_control = vlan_control;
  4628. upd_context->qp_context.pri_path.vlan_index = work->vlan_ix;
  4629. upd_context->qp_context.pri_path.fvl_rx =
  4630. qp->fvl_rx | MLX4_FVL_RX_FORCE_ETH_VLAN;
  4631. upd_context->qp_context.pri_path.fl =
  4632. qp->pri_path_fl | MLX4_FL_ETH_HIDE_CQE_VLAN;
  4633. if (work->vlan_proto == htons(ETH_P_8021AD))
  4634. upd_context->qp_context.pri_path.fl |= MLX4_FL_SV;
  4635. else
  4636. upd_context->qp_context.pri_path.fl |= MLX4_FL_CV;
  4637. upd_context->qp_context.pri_path.feup =
  4638. qp->feup | MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN;
  4639. upd_context->qp_context.pri_path.sched_queue =
  4640. qp->sched_queue & 0xC7;
  4641. upd_context->qp_context.pri_path.sched_queue |=
  4642. ((work->qos & 0x7) << 3);
  4643. if (dev->caps.flags2 &
  4644. MLX4_DEV_CAP_FLAG2_QOS_VPP)
  4645. update_qos_vpp(upd_context, work);
  4646. }
  4647. err = mlx4_cmd(dev, mailbox->dma,
  4648. qp->local_qpn & 0xffffff,
  4649. 0, MLX4_CMD_UPDATE_QP,
  4650. MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
  4651. if (err) {
  4652. mlx4_info(dev, "UPDATE_QP failed for slave %d, port %d, qpn %d (%d)\n",
  4653. work->slave, port, qp->local_qpn, err);
  4654. errors++;
  4655. }
  4656. }
  4657. spin_lock_irq(mlx4_tlock(dev));
  4658. }
  4659. spin_unlock_irq(mlx4_tlock(dev));
  4660. mlx4_free_cmd_mailbox(dev, mailbox);
  4661. if (errors)
  4662. mlx4_err(dev, "%d UPDATE_QP failures for slave %d, port %d\n",
  4663. errors, work->slave, work->port);
  4664. /* unregister previous vlan_id if needed and we had no errors
  4665. * while updating the QPs
  4666. */
  4667. if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN && !errors &&
  4668. NO_INDX != work->orig_vlan_ix)
  4669. __mlx4_unregister_vlan(&work->priv->dev, work->port,
  4670. work->orig_vlan_id);
  4671. out:
  4672. kfree(work);
  4673. return;
  4674. }