scif_dma.c 52 KB

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  1. /*
  2. * Intel MIC Platform Software Stack (MPSS)
  3. *
  4. * Copyright(c) 2015 Intel Corporation.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License, version 2, as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * Intel SCIF driver.
  16. *
  17. */
  18. #include "scif_main.h"
  19. #include "scif_map.h"
  20. /*
  21. * struct scif_dma_comp_cb - SCIF DMA completion callback
  22. *
  23. * @dma_completion_func: DMA completion callback
  24. * @cb_cookie: DMA completion callback cookie
  25. * @temp_buf: Temporary buffer
  26. * @temp_buf_to_free: Temporary buffer to be freed
  27. * @is_cache: Is a kmem_cache allocated buffer
  28. * @dst_offset: Destination registration offset
  29. * @dst_window: Destination registration window
  30. * @len: Length of the temp buffer
  31. * @temp_phys: DMA address of the temp buffer
  32. * @sdev: The SCIF device
  33. * @header_padding: padding for cache line alignment
  34. */
  35. struct scif_dma_comp_cb {
  36. void (*dma_completion_func)(void *cookie);
  37. void *cb_cookie;
  38. u8 *temp_buf;
  39. u8 *temp_buf_to_free;
  40. bool is_cache;
  41. s64 dst_offset;
  42. struct scif_window *dst_window;
  43. size_t len;
  44. dma_addr_t temp_phys;
  45. struct scif_dev *sdev;
  46. int header_padding;
  47. };
  48. /**
  49. * struct scif_copy_work - Work for DMA copy
  50. *
  51. * @src_offset: Starting source offset
  52. * @dst_offset: Starting destination offset
  53. * @src_window: Starting src registered window
  54. * @dst_window: Starting dst registered window
  55. * @loopback: true if this is a loopback DMA transfer
  56. * @len: Length of the transfer
  57. * @comp_cb: DMA copy completion callback
  58. * @remote_dev: The remote SCIF peer device
  59. * @fence_type: polling or interrupt based
  60. * @ordered: is this a tail byte ordered DMA transfer
  61. */
  62. struct scif_copy_work {
  63. s64 src_offset;
  64. s64 dst_offset;
  65. struct scif_window *src_window;
  66. struct scif_window *dst_window;
  67. int loopback;
  68. size_t len;
  69. struct scif_dma_comp_cb *comp_cb;
  70. struct scif_dev *remote_dev;
  71. int fence_type;
  72. bool ordered;
  73. };
  74. /**
  75. * scif_reserve_dma_chan:
  76. * @ep: Endpoint Descriptor.
  77. *
  78. * This routine reserves a DMA channel for a particular
  79. * endpoint. All DMA transfers for an endpoint are always
  80. * programmed on the same DMA channel.
  81. */
  82. int scif_reserve_dma_chan(struct scif_endpt *ep)
  83. {
  84. int err = 0;
  85. struct scif_dev *scifdev;
  86. struct scif_hw_dev *sdev;
  87. struct dma_chan *chan;
  88. /* Loopback DMAs are not supported on the management node */
  89. if (!scif_info.nodeid && scifdev_self(ep->remote_dev))
  90. return 0;
  91. if (scif_info.nodeid)
  92. scifdev = &scif_dev[0];
  93. else
  94. scifdev = ep->remote_dev;
  95. sdev = scifdev->sdev;
  96. if (!sdev->num_dma_ch)
  97. return -ENODEV;
  98. chan = sdev->dma_ch[scifdev->dma_ch_idx];
  99. scifdev->dma_ch_idx = (scifdev->dma_ch_idx + 1) % sdev->num_dma_ch;
  100. mutex_lock(&ep->rma_info.rma_lock);
  101. ep->rma_info.dma_chan = chan;
  102. mutex_unlock(&ep->rma_info.rma_lock);
  103. return err;
  104. }
  105. #ifdef CONFIG_MMU_NOTIFIER
  106. /**
  107. * scif_rma_destroy_tcw:
  108. *
  109. * This routine destroys temporary cached windows
  110. */
  111. static
  112. void __scif_rma_destroy_tcw(struct scif_mmu_notif *mmn,
  113. u64 start, u64 len)
  114. {
  115. struct list_head *item, *tmp;
  116. struct scif_window *window;
  117. u64 start_va, end_va;
  118. u64 end = start + len;
  119. if (end <= start)
  120. return;
  121. list_for_each_safe(item, tmp, &mmn->tc_reg_list) {
  122. window = list_entry(item, struct scif_window, list);
  123. if (!len)
  124. break;
  125. start_va = window->va_for_temp;
  126. end_va = start_va + (window->nr_pages << PAGE_SHIFT);
  127. if (start < start_va && end <= start_va)
  128. break;
  129. if (start >= end_va)
  130. continue;
  131. __scif_rma_destroy_tcw_helper(window);
  132. }
  133. }
  134. static void scif_rma_destroy_tcw(struct scif_mmu_notif *mmn, u64 start, u64 len)
  135. {
  136. struct scif_endpt *ep = mmn->ep;
  137. spin_lock(&ep->rma_info.tc_lock);
  138. __scif_rma_destroy_tcw(mmn, start, len);
  139. spin_unlock(&ep->rma_info.tc_lock);
  140. }
  141. static void scif_rma_destroy_tcw_ep(struct scif_endpt *ep)
  142. {
  143. struct list_head *item, *tmp;
  144. struct scif_mmu_notif *mmn;
  145. list_for_each_safe(item, tmp, &ep->rma_info.mmn_list) {
  146. mmn = list_entry(item, struct scif_mmu_notif, list);
  147. scif_rma_destroy_tcw(mmn, 0, ULONG_MAX);
  148. }
  149. }
  150. static void __scif_rma_destroy_tcw_ep(struct scif_endpt *ep)
  151. {
  152. struct list_head *item, *tmp;
  153. struct scif_mmu_notif *mmn;
  154. spin_lock(&ep->rma_info.tc_lock);
  155. list_for_each_safe(item, tmp, &ep->rma_info.mmn_list) {
  156. mmn = list_entry(item, struct scif_mmu_notif, list);
  157. __scif_rma_destroy_tcw(mmn, 0, ULONG_MAX);
  158. }
  159. spin_unlock(&ep->rma_info.tc_lock);
  160. }
  161. static bool scif_rma_tc_can_cache(struct scif_endpt *ep, size_t cur_bytes)
  162. {
  163. if ((cur_bytes >> PAGE_SHIFT) > scif_info.rma_tc_limit)
  164. return false;
  165. if ((atomic_read(&ep->rma_info.tcw_total_pages)
  166. + (cur_bytes >> PAGE_SHIFT)) >
  167. scif_info.rma_tc_limit) {
  168. dev_info(scif_info.mdev.this_device,
  169. "%s %d total=%d, current=%zu reached max\n",
  170. __func__, __LINE__,
  171. atomic_read(&ep->rma_info.tcw_total_pages),
  172. (1 + (cur_bytes >> PAGE_SHIFT)));
  173. scif_rma_destroy_tcw_invalid();
  174. __scif_rma_destroy_tcw_ep(ep);
  175. }
  176. return true;
  177. }
  178. static void scif_mmu_notifier_release(struct mmu_notifier *mn,
  179. struct mm_struct *mm)
  180. {
  181. struct scif_mmu_notif *mmn;
  182. mmn = container_of(mn, struct scif_mmu_notif, ep_mmu_notifier);
  183. scif_rma_destroy_tcw(mmn, 0, ULONG_MAX);
  184. schedule_work(&scif_info.misc_work);
  185. }
  186. static void scif_mmu_notifier_invalidate_range_start(struct mmu_notifier *mn,
  187. struct mm_struct *mm,
  188. unsigned long start,
  189. unsigned long end)
  190. {
  191. struct scif_mmu_notif *mmn;
  192. mmn = container_of(mn, struct scif_mmu_notif, ep_mmu_notifier);
  193. scif_rma_destroy_tcw(mmn, start, end - start);
  194. }
  195. static void scif_mmu_notifier_invalidate_range_end(struct mmu_notifier *mn,
  196. struct mm_struct *mm,
  197. unsigned long start,
  198. unsigned long end)
  199. {
  200. /*
  201. * Nothing to do here, everything needed was done in
  202. * invalidate_range_start.
  203. */
  204. }
  205. static const struct mmu_notifier_ops scif_mmu_notifier_ops = {
  206. .release = scif_mmu_notifier_release,
  207. .clear_flush_young = NULL,
  208. .invalidate_range_start = scif_mmu_notifier_invalidate_range_start,
  209. .invalidate_range_end = scif_mmu_notifier_invalidate_range_end};
  210. static void scif_ep_unregister_mmu_notifier(struct scif_endpt *ep)
  211. {
  212. struct scif_endpt_rma_info *rma = &ep->rma_info;
  213. struct scif_mmu_notif *mmn = NULL;
  214. struct list_head *item, *tmp;
  215. mutex_lock(&ep->rma_info.mmn_lock);
  216. list_for_each_safe(item, tmp, &rma->mmn_list) {
  217. mmn = list_entry(item, struct scif_mmu_notif, list);
  218. mmu_notifier_unregister(&mmn->ep_mmu_notifier, mmn->mm);
  219. list_del(item);
  220. kfree(mmn);
  221. }
  222. mutex_unlock(&ep->rma_info.mmn_lock);
  223. }
  224. static void scif_init_mmu_notifier(struct scif_mmu_notif *mmn,
  225. struct mm_struct *mm, struct scif_endpt *ep)
  226. {
  227. mmn->ep = ep;
  228. mmn->mm = mm;
  229. mmn->ep_mmu_notifier.ops = &scif_mmu_notifier_ops;
  230. INIT_LIST_HEAD(&mmn->list);
  231. INIT_LIST_HEAD(&mmn->tc_reg_list);
  232. }
  233. static struct scif_mmu_notif *
  234. scif_find_mmu_notifier(struct mm_struct *mm, struct scif_endpt_rma_info *rma)
  235. {
  236. struct scif_mmu_notif *mmn;
  237. list_for_each_entry(mmn, &rma->mmn_list, list)
  238. if (mmn->mm == mm)
  239. return mmn;
  240. return NULL;
  241. }
  242. static struct scif_mmu_notif *
  243. scif_add_mmu_notifier(struct mm_struct *mm, struct scif_endpt *ep)
  244. {
  245. struct scif_mmu_notif *mmn
  246. = kzalloc(sizeof(*mmn), GFP_KERNEL);
  247. if (!mmn)
  248. return ERR_PTR(-ENOMEM);
  249. scif_init_mmu_notifier(mmn, current->mm, ep);
  250. if (mmu_notifier_register(&mmn->ep_mmu_notifier, current->mm)) {
  251. kfree(mmn);
  252. return ERR_PTR(-EBUSY);
  253. }
  254. list_add(&mmn->list, &ep->rma_info.mmn_list);
  255. return mmn;
  256. }
  257. /*
  258. * Called from the misc thread to destroy temporary cached windows and
  259. * unregister the MMU notifier for the SCIF endpoint.
  260. */
  261. void scif_mmu_notif_handler(struct work_struct *work)
  262. {
  263. struct list_head *pos, *tmpq;
  264. struct scif_endpt *ep;
  265. restart:
  266. scif_rma_destroy_tcw_invalid();
  267. spin_lock(&scif_info.rmalock);
  268. list_for_each_safe(pos, tmpq, &scif_info.mmu_notif_cleanup) {
  269. ep = list_entry(pos, struct scif_endpt, mmu_list);
  270. list_del(&ep->mmu_list);
  271. spin_unlock(&scif_info.rmalock);
  272. scif_rma_destroy_tcw_ep(ep);
  273. scif_ep_unregister_mmu_notifier(ep);
  274. goto restart;
  275. }
  276. spin_unlock(&scif_info.rmalock);
  277. }
  278. static bool scif_is_set_reg_cache(int flags)
  279. {
  280. return !!(flags & SCIF_RMA_USECACHE);
  281. }
  282. #else
  283. static struct scif_mmu_notif *
  284. scif_find_mmu_notifier(struct mm_struct *mm,
  285. struct scif_endpt_rma_info *rma)
  286. {
  287. return NULL;
  288. }
  289. static struct scif_mmu_notif *
  290. scif_add_mmu_notifier(struct mm_struct *mm, struct scif_endpt *ep)
  291. {
  292. return NULL;
  293. }
  294. void scif_mmu_notif_handler(struct work_struct *work)
  295. {
  296. }
  297. static bool scif_is_set_reg_cache(int flags)
  298. {
  299. return false;
  300. }
  301. static bool scif_rma_tc_can_cache(struct scif_endpt *ep, size_t cur_bytes)
  302. {
  303. return false;
  304. }
  305. #endif
  306. /**
  307. * scif_register_temp:
  308. * @epd: End Point Descriptor.
  309. * @addr: virtual address to/from which to copy
  310. * @len: length of range to copy
  311. * @out_offset: computed offset returned by reference.
  312. * @out_window: allocated registered window returned by reference.
  313. *
  314. * Create a temporary registered window. The peer will not know about this
  315. * window. This API is used for scif_vreadfrom()/scif_vwriteto() API's.
  316. */
  317. static int
  318. scif_register_temp(scif_epd_t epd, unsigned long addr, size_t len, int prot,
  319. off_t *out_offset, struct scif_window **out_window)
  320. {
  321. struct scif_endpt *ep = (struct scif_endpt *)epd;
  322. int err;
  323. scif_pinned_pages_t pinned_pages;
  324. size_t aligned_len;
  325. aligned_len = ALIGN(len, PAGE_SIZE);
  326. err = __scif_pin_pages((void *)(addr & PAGE_MASK),
  327. aligned_len, &prot, 0, &pinned_pages);
  328. if (err)
  329. return err;
  330. pinned_pages->prot = prot;
  331. /* Compute the offset for this registration */
  332. err = scif_get_window_offset(ep, 0, 0,
  333. aligned_len >> PAGE_SHIFT,
  334. (s64 *)out_offset);
  335. if (err)
  336. goto error_unpin;
  337. /* Allocate and prepare self registration window */
  338. *out_window = scif_create_window(ep, aligned_len >> PAGE_SHIFT,
  339. *out_offset, true);
  340. if (!*out_window) {
  341. scif_free_window_offset(ep, NULL, *out_offset);
  342. err = -ENOMEM;
  343. goto error_unpin;
  344. }
  345. (*out_window)->pinned_pages = pinned_pages;
  346. (*out_window)->nr_pages = pinned_pages->nr_pages;
  347. (*out_window)->prot = pinned_pages->prot;
  348. (*out_window)->va_for_temp = addr & PAGE_MASK;
  349. err = scif_map_window(ep->remote_dev, *out_window);
  350. if (err) {
  351. /* Something went wrong! Rollback */
  352. scif_destroy_window(ep, *out_window);
  353. *out_window = NULL;
  354. } else {
  355. *out_offset |= (addr - (*out_window)->va_for_temp);
  356. }
  357. return err;
  358. error_unpin:
  359. if (err)
  360. dev_err(&ep->remote_dev->sdev->dev,
  361. "%s %d err %d\n", __func__, __LINE__, err);
  362. scif_unpin_pages(pinned_pages);
  363. return err;
  364. }
  365. #define SCIF_DMA_TO (3 * HZ)
  366. /*
  367. * scif_sync_dma - Program a DMA without an interrupt descriptor
  368. *
  369. * @dev - The address of the pointer to the device instance used
  370. * for DMA registration.
  371. * @chan - DMA channel to be used.
  372. * @sync_wait: Wait for DMA to complete?
  373. *
  374. * Return 0 on success and -errno on error.
  375. */
  376. static int scif_sync_dma(struct scif_hw_dev *sdev, struct dma_chan *chan,
  377. bool sync_wait)
  378. {
  379. int err = 0;
  380. struct dma_async_tx_descriptor *tx = NULL;
  381. enum dma_ctrl_flags flags = DMA_PREP_FENCE;
  382. dma_cookie_t cookie;
  383. struct dma_device *ddev;
  384. if (!chan) {
  385. err = -EIO;
  386. dev_err(&sdev->dev, "%s %d err %d\n",
  387. __func__, __LINE__, err);
  388. return err;
  389. }
  390. ddev = chan->device;
  391. tx = ddev->device_prep_dma_memcpy(chan, 0, 0, 0, flags);
  392. if (!tx) {
  393. err = -ENOMEM;
  394. dev_err(&sdev->dev, "%s %d err %d\n",
  395. __func__, __LINE__, err);
  396. goto release;
  397. }
  398. cookie = tx->tx_submit(tx);
  399. if (dma_submit_error(cookie)) {
  400. err = -ENOMEM;
  401. dev_err(&sdev->dev, "%s %d err %d\n",
  402. __func__, __LINE__, err);
  403. goto release;
  404. }
  405. if (!sync_wait) {
  406. dma_async_issue_pending(chan);
  407. } else {
  408. if (dma_sync_wait(chan, cookie) == DMA_COMPLETE) {
  409. err = 0;
  410. } else {
  411. err = -EIO;
  412. dev_err(&sdev->dev, "%s %d err %d\n",
  413. __func__, __LINE__, err);
  414. }
  415. }
  416. release:
  417. return err;
  418. }
  419. static void scif_dma_callback(void *arg)
  420. {
  421. struct completion *done = (struct completion *)arg;
  422. complete(done);
  423. }
  424. #define SCIF_DMA_SYNC_WAIT true
  425. #define SCIF_DMA_POLL BIT(0)
  426. #define SCIF_DMA_INTR BIT(1)
  427. /*
  428. * scif_async_dma - Program a DMA with an interrupt descriptor
  429. *
  430. * @dev - The address of the pointer to the device instance used
  431. * for DMA registration.
  432. * @chan - DMA channel to be used.
  433. * Return 0 on success and -errno on error.
  434. */
  435. static int scif_async_dma(struct scif_hw_dev *sdev, struct dma_chan *chan)
  436. {
  437. int err = 0;
  438. struct dma_device *ddev;
  439. struct dma_async_tx_descriptor *tx = NULL;
  440. enum dma_ctrl_flags flags = DMA_PREP_INTERRUPT | DMA_PREP_FENCE;
  441. DECLARE_COMPLETION_ONSTACK(done_wait);
  442. dma_cookie_t cookie;
  443. enum dma_status status;
  444. if (!chan) {
  445. err = -EIO;
  446. dev_err(&sdev->dev, "%s %d err %d\n",
  447. __func__, __LINE__, err);
  448. return err;
  449. }
  450. ddev = chan->device;
  451. tx = ddev->device_prep_dma_memcpy(chan, 0, 0, 0, flags);
  452. if (!tx) {
  453. err = -ENOMEM;
  454. dev_err(&sdev->dev, "%s %d err %d\n",
  455. __func__, __LINE__, err);
  456. goto release;
  457. }
  458. reinit_completion(&done_wait);
  459. tx->callback = scif_dma_callback;
  460. tx->callback_param = &done_wait;
  461. cookie = tx->tx_submit(tx);
  462. if (dma_submit_error(cookie)) {
  463. err = -ENOMEM;
  464. dev_err(&sdev->dev, "%s %d err %d\n",
  465. __func__, __LINE__, err);
  466. goto release;
  467. }
  468. dma_async_issue_pending(chan);
  469. err = wait_for_completion_timeout(&done_wait, SCIF_DMA_TO);
  470. if (!err) {
  471. err = -EIO;
  472. dev_err(&sdev->dev, "%s %d err %d\n",
  473. __func__, __LINE__, err);
  474. goto release;
  475. }
  476. err = 0;
  477. status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
  478. if (status != DMA_COMPLETE) {
  479. err = -EIO;
  480. dev_err(&sdev->dev, "%s %d err %d\n",
  481. __func__, __LINE__, err);
  482. goto release;
  483. }
  484. release:
  485. return err;
  486. }
  487. /*
  488. * scif_drain_dma_poll - Drain all outstanding DMA operations for a particular
  489. * DMA channel via polling.
  490. *
  491. * @sdev - The SCIF device
  492. * @chan - DMA channel
  493. * Return 0 on success and -errno on error.
  494. */
  495. static int scif_drain_dma_poll(struct scif_hw_dev *sdev, struct dma_chan *chan)
  496. {
  497. if (!chan)
  498. return -EINVAL;
  499. return scif_sync_dma(sdev, chan, SCIF_DMA_SYNC_WAIT);
  500. }
  501. /*
  502. * scif_drain_dma_intr - Drain all outstanding DMA operations for a particular
  503. * DMA channel via interrupt based blocking wait.
  504. *
  505. * @sdev - The SCIF device
  506. * @chan - DMA channel
  507. * Return 0 on success and -errno on error.
  508. */
  509. int scif_drain_dma_intr(struct scif_hw_dev *sdev, struct dma_chan *chan)
  510. {
  511. if (!chan)
  512. return -EINVAL;
  513. return scif_async_dma(sdev, chan);
  514. }
  515. /**
  516. * scif_rma_destroy_windows:
  517. *
  518. * This routine destroys all windows queued for cleanup
  519. */
  520. void scif_rma_destroy_windows(void)
  521. {
  522. struct list_head *item, *tmp;
  523. struct scif_window *window;
  524. struct scif_endpt *ep;
  525. struct dma_chan *chan;
  526. might_sleep();
  527. restart:
  528. spin_lock(&scif_info.rmalock);
  529. list_for_each_safe(item, tmp, &scif_info.rma) {
  530. window = list_entry(item, struct scif_window,
  531. list);
  532. ep = (struct scif_endpt *)window->ep;
  533. chan = ep->rma_info.dma_chan;
  534. list_del_init(&window->list);
  535. spin_unlock(&scif_info.rmalock);
  536. if (!chan || !scifdev_alive(ep) ||
  537. !scif_drain_dma_intr(ep->remote_dev->sdev,
  538. ep->rma_info.dma_chan))
  539. /* Remove window from global list */
  540. window->unreg_state = OP_COMPLETED;
  541. else
  542. dev_warn(&ep->remote_dev->sdev->dev,
  543. "DMA engine hung?\n");
  544. if (window->unreg_state == OP_COMPLETED) {
  545. if (window->type == SCIF_WINDOW_SELF)
  546. scif_destroy_window(ep, window);
  547. else
  548. scif_destroy_remote_window(window);
  549. atomic_dec(&ep->rma_info.tw_refcount);
  550. }
  551. goto restart;
  552. }
  553. spin_unlock(&scif_info.rmalock);
  554. }
  555. /**
  556. * scif_rma_destroy_tcw:
  557. *
  558. * This routine destroys temporary cached registered windows
  559. * which have been queued for cleanup.
  560. */
  561. void scif_rma_destroy_tcw_invalid(void)
  562. {
  563. struct list_head *item, *tmp;
  564. struct scif_window *window;
  565. struct scif_endpt *ep;
  566. struct dma_chan *chan;
  567. might_sleep();
  568. restart:
  569. spin_lock(&scif_info.rmalock);
  570. list_for_each_safe(item, tmp, &scif_info.rma_tc) {
  571. window = list_entry(item, struct scif_window, list);
  572. ep = (struct scif_endpt *)window->ep;
  573. chan = ep->rma_info.dma_chan;
  574. list_del_init(&window->list);
  575. spin_unlock(&scif_info.rmalock);
  576. mutex_lock(&ep->rma_info.rma_lock);
  577. if (!chan || !scifdev_alive(ep) ||
  578. !scif_drain_dma_intr(ep->remote_dev->sdev,
  579. ep->rma_info.dma_chan)) {
  580. atomic_sub(window->nr_pages,
  581. &ep->rma_info.tcw_total_pages);
  582. scif_destroy_window(ep, window);
  583. atomic_dec(&ep->rma_info.tcw_refcount);
  584. } else {
  585. dev_warn(&ep->remote_dev->sdev->dev,
  586. "DMA engine hung?\n");
  587. }
  588. mutex_unlock(&ep->rma_info.rma_lock);
  589. goto restart;
  590. }
  591. spin_unlock(&scif_info.rmalock);
  592. }
  593. static inline
  594. void *_get_local_va(off_t off, struct scif_window *window, size_t len)
  595. {
  596. int page_nr = (off - window->offset) >> PAGE_SHIFT;
  597. off_t page_off = off & ~PAGE_MASK;
  598. void *va = NULL;
  599. if (window->type == SCIF_WINDOW_SELF) {
  600. struct page **pages = window->pinned_pages->pages;
  601. va = page_address(pages[page_nr]) + page_off;
  602. }
  603. return va;
  604. }
  605. static inline
  606. void *ioremap_remote(off_t off, struct scif_window *window,
  607. size_t len, struct scif_dev *dev,
  608. struct scif_window_iter *iter)
  609. {
  610. dma_addr_t phys = scif_off_to_dma_addr(window, off, NULL, iter);
  611. /*
  612. * If the DMA address is not card relative then we need the DMA
  613. * addresses to be an offset into the bar. The aperture base was already
  614. * added so subtract it here since scif_ioremap is going to add it again
  615. */
  616. if (!scifdev_self(dev) && window->type == SCIF_WINDOW_PEER &&
  617. dev->sdev->aper && !dev->sdev->card_rel_da)
  618. phys = phys - dev->sdev->aper->pa;
  619. return scif_ioremap(phys, len, dev);
  620. }
  621. static inline void
  622. iounmap_remote(void *virt, size_t size, struct scif_copy_work *work)
  623. {
  624. scif_iounmap(virt, size, work->remote_dev);
  625. }
  626. /*
  627. * Takes care of ordering issue caused by
  628. * 1. Hardware: Only in the case of cpu copy from mgmt node to card
  629. * because of WC memory.
  630. * 2. Software: If memcpy reorders copy instructions for optimization.
  631. * This could happen at both mgmt node and card.
  632. */
  633. static inline void
  634. scif_ordered_memcpy_toio(char *dst, const char *src, size_t count)
  635. {
  636. if (!count)
  637. return;
  638. memcpy_toio((void __iomem __force *)dst, src, --count);
  639. /* Order the last byte with the previous stores */
  640. wmb();
  641. *(dst + count) = *(src + count);
  642. }
  643. static inline void scif_unaligned_cpy_toio(char *dst, const char *src,
  644. size_t count, bool ordered)
  645. {
  646. if (ordered)
  647. scif_ordered_memcpy_toio(dst, src, count);
  648. else
  649. memcpy_toio((void __iomem __force *)dst, src, count);
  650. }
  651. static inline
  652. void scif_ordered_memcpy_fromio(char *dst, const char *src, size_t count)
  653. {
  654. if (!count)
  655. return;
  656. memcpy_fromio(dst, (void __iomem __force *)src, --count);
  657. /* Order the last byte with the previous loads */
  658. rmb();
  659. *(dst + count) = *(src + count);
  660. }
  661. static inline void scif_unaligned_cpy_fromio(char *dst, const char *src,
  662. size_t count, bool ordered)
  663. {
  664. if (ordered)
  665. scif_ordered_memcpy_fromio(dst, src, count);
  666. else
  667. memcpy_fromio(dst, (void __iomem __force *)src, count);
  668. }
  669. #define SCIF_RMA_ERROR_CODE (~(dma_addr_t)0x0)
  670. /*
  671. * scif_off_to_dma_addr:
  672. * Obtain the dma_addr given the window and the offset.
  673. * @window: Registered window.
  674. * @off: Window offset.
  675. * @nr_bytes: Return the number of contiguous bytes till next DMA addr index.
  676. * @index: Return the index of the dma_addr array found.
  677. * @start_off: start offset of index of the dma addr array found.
  678. * The nr_bytes provides the callee an estimate of the maximum possible
  679. * DMA xfer possible while the index/start_off provide faster lookups
  680. * for the next iteration.
  681. */
  682. dma_addr_t scif_off_to_dma_addr(struct scif_window *window, s64 off,
  683. size_t *nr_bytes, struct scif_window_iter *iter)
  684. {
  685. int i, page_nr;
  686. s64 start, end;
  687. off_t page_off;
  688. if (window->nr_pages == window->nr_contig_chunks) {
  689. page_nr = (off - window->offset) >> PAGE_SHIFT;
  690. page_off = off & ~PAGE_MASK;
  691. if (nr_bytes)
  692. *nr_bytes = PAGE_SIZE - page_off;
  693. return window->dma_addr[page_nr] | page_off;
  694. }
  695. if (iter) {
  696. i = iter->index;
  697. start = iter->offset;
  698. } else {
  699. i = 0;
  700. start = window->offset;
  701. }
  702. for (; i < window->nr_contig_chunks; i++) {
  703. end = start + (window->num_pages[i] << PAGE_SHIFT);
  704. if (off >= start && off < end) {
  705. if (iter) {
  706. iter->index = i;
  707. iter->offset = start;
  708. }
  709. if (nr_bytes)
  710. *nr_bytes = end - off;
  711. return (window->dma_addr[i] + (off - start));
  712. }
  713. start += (window->num_pages[i] << PAGE_SHIFT);
  714. }
  715. dev_err(scif_info.mdev.this_device,
  716. "%s %d BUG. Addr not found? window %p off 0x%llx\n",
  717. __func__, __LINE__, window, off);
  718. return SCIF_RMA_ERROR_CODE;
  719. }
  720. /*
  721. * Copy between rma window and temporary buffer
  722. */
  723. static void scif_rma_local_cpu_copy(s64 offset, struct scif_window *window,
  724. u8 *temp, size_t rem_len, bool to_temp)
  725. {
  726. void *window_virt;
  727. size_t loop_len;
  728. int offset_in_page;
  729. s64 end_offset;
  730. offset_in_page = offset & ~PAGE_MASK;
  731. loop_len = PAGE_SIZE - offset_in_page;
  732. if (rem_len < loop_len)
  733. loop_len = rem_len;
  734. window_virt = _get_local_va(offset, window, loop_len);
  735. if (!window_virt)
  736. return;
  737. if (to_temp)
  738. memcpy(temp, window_virt, loop_len);
  739. else
  740. memcpy(window_virt, temp, loop_len);
  741. offset += loop_len;
  742. temp += loop_len;
  743. rem_len -= loop_len;
  744. end_offset = window->offset +
  745. (window->nr_pages << PAGE_SHIFT);
  746. while (rem_len) {
  747. if (offset == end_offset) {
  748. window = list_next_entry(window, list);
  749. end_offset = window->offset +
  750. (window->nr_pages << PAGE_SHIFT);
  751. }
  752. loop_len = min(PAGE_SIZE, rem_len);
  753. window_virt = _get_local_va(offset, window, loop_len);
  754. if (!window_virt)
  755. return;
  756. if (to_temp)
  757. memcpy(temp, window_virt, loop_len);
  758. else
  759. memcpy(window_virt, temp, loop_len);
  760. offset += loop_len;
  761. temp += loop_len;
  762. rem_len -= loop_len;
  763. }
  764. }
  765. /**
  766. * scif_rma_completion_cb:
  767. * @data: RMA cookie
  768. *
  769. * RMA interrupt completion callback.
  770. */
  771. static void scif_rma_completion_cb(void *data)
  772. {
  773. struct scif_dma_comp_cb *comp_cb = data;
  774. /* Free DMA Completion CB. */
  775. if (comp_cb->dst_window)
  776. scif_rma_local_cpu_copy(comp_cb->dst_offset,
  777. comp_cb->dst_window,
  778. comp_cb->temp_buf +
  779. comp_cb->header_padding,
  780. comp_cb->len, false);
  781. scif_unmap_single(comp_cb->temp_phys, comp_cb->sdev,
  782. SCIF_KMEM_UNALIGNED_BUF_SIZE);
  783. if (comp_cb->is_cache)
  784. kmem_cache_free(unaligned_cache,
  785. comp_cb->temp_buf_to_free);
  786. else
  787. kfree(comp_cb->temp_buf_to_free);
  788. }
  789. /* Copies between temporary buffer and offsets provided in work */
  790. static int
  791. scif_rma_list_dma_copy_unaligned(struct scif_copy_work *work,
  792. u8 *temp, struct dma_chan *chan,
  793. bool src_local)
  794. {
  795. struct scif_dma_comp_cb *comp_cb = work->comp_cb;
  796. dma_addr_t window_dma_addr, temp_dma_addr;
  797. dma_addr_t temp_phys = comp_cb->temp_phys;
  798. size_t loop_len, nr_contig_bytes = 0, remaining_len = work->len;
  799. int offset_in_ca, ret = 0;
  800. s64 end_offset, offset;
  801. struct scif_window *window;
  802. void *window_virt_addr;
  803. size_t tail_len;
  804. struct dma_async_tx_descriptor *tx;
  805. struct dma_device *dev = chan->device;
  806. dma_cookie_t cookie;
  807. if (src_local) {
  808. offset = work->dst_offset;
  809. window = work->dst_window;
  810. } else {
  811. offset = work->src_offset;
  812. window = work->src_window;
  813. }
  814. offset_in_ca = offset & (L1_CACHE_BYTES - 1);
  815. if (offset_in_ca) {
  816. loop_len = L1_CACHE_BYTES - offset_in_ca;
  817. loop_len = min(loop_len, remaining_len);
  818. window_virt_addr = ioremap_remote(offset, window,
  819. loop_len,
  820. work->remote_dev,
  821. NULL);
  822. if (!window_virt_addr)
  823. return -ENOMEM;
  824. if (src_local)
  825. scif_unaligned_cpy_toio(window_virt_addr, temp,
  826. loop_len,
  827. work->ordered &&
  828. !(remaining_len - loop_len));
  829. else
  830. scif_unaligned_cpy_fromio(temp, window_virt_addr,
  831. loop_len, work->ordered &&
  832. !(remaining_len - loop_len));
  833. iounmap_remote(window_virt_addr, loop_len, work);
  834. offset += loop_len;
  835. temp += loop_len;
  836. temp_phys += loop_len;
  837. remaining_len -= loop_len;
  838. }
  839. offset_in_ca = offset & ~PAGE_MASK;
  840. end_offset = window->offset +
  841. (window->nr_pages << PAGE_SHIFT);
  842. tail_len = remaining_len & (L1_CACHE_BYTES - 1);
  843. remaining_len -= tail_len;
  844. while (remaining_len) {
  845. if (offset == end_offset) {
  846. window = list_next_entry(window, list);
  847. end_offset = window->offset +
  848. (window->nr_pages << PAGE_SHIFT);
  849. }
  850. if (scif_is_mgmt_node())
  851. temp_dma_addr = temp_phys;
  852. else
  853. /* Fix if we ever enable IOMMU on the card */
  854. temp_dma_addr = (dma_addr_t)virt_to_phys(temp);
  855. window_dma_addr = scif_off_to_dma_addr(window, offset,
  856. &nr_contig_bytes,
  857. NULL);
  858. loop_len = min(nr_contig_bytes, remaining_len);
  859. if (src_local) {
  860. if (work->ordered && !tail_len &&
  861. !(remaining_len - loop_len) &&
  862. loop_len != L1_CACHE_BYTES) {
  863. /*
  864. * Break up the last chunk of the transfer into
  865. * two steps. if there is no tail to guarantee
  866. * DMA ordering. SCIF_DMA_POLLING inserts
  867. * a status update descriptor in step 1 which
  868. * acts as a double sided synchronization fence
  869. * for the DMA engine to ensure that the last
  870. * cache line in step 2 is updated last.
  871. */
  872. /* Step 1) DMA: Body Length - L1_CACHE_BYTES. */
  873. tx =
  874. dev->device_prep_dma_memcpy(chan,
  875. window_dma_addr,
  876. temp_dma_addr,
  877. loop_len -
  878. L1_CACHE_BYTES,
  879. DMA_PREP_FENCE);
  880. if (!tx) {
  881. ret = -ENOMEM;
  882. goto err;
  883. }
  884. cookie = tx->tx_submit(tx);
  885. if (dma_submit_error(cookie)) {
  886. ret = -ENOMEM;
  887. goto err;
  888. }
  889. dma_async_issue_pending(chan);
  890. offset += (loop_len - L1_CACHE_BYTES);
  891. temp_dma_addr += (loop_len - L1_CACHE_BYTES);
  892. window_dma_addr += (loop_len - L1_CACHE_BYTES);
  893. remaining_len -= (loop_len - L1_CACHE_BYTES);
  894. loop_len = remaining_len;
  895. /* Step 2) DMA: L1_CACHE_BYTES */
  896. tx =
  897. dev->device_prep_dma_memcpy(chan,
  898. window_dma_addr,
  899. temp_dma_addr,
  900. loop_len, 0);
  901. if (!tx) {
  902. ret = -ENOMEM;
  903. goto err;
  904. }
  905. cookie = tx->tx_submit(tx);
  906. if (dma_submit_error(cookie)) {
  907. ret = -ENOMEM;
  908. goto err;
  909. }
  910. dma_async_issue_pending(chan);
  911. } else {
  912. tx =
  913. dev->device_prep_dma_memcpy(chan,
  914. window_dma_addr,
  915. temp_dma_addr,
  916. loop_len, 0);
  917. if (!tx) {
  918. ret = -ENOMEM;
  919. goto err;
  920. }
  921. cookie = tx->tx_submit(tx);
  922. if (dma_submit_error(cookie)) {
  923. ret = -ENOMEM;
  924. goto err;
  925. }
  926. dma_async_issue_pending(chan);
  927. }
  928. } else {
  929. tx = dev->device_prep_dma_memcpy(chan, temp_dma_addr,
  930. window_dma_addr, loop_len, 0);
  931. if (!tx) {
  932. ret = -ENOMEM;
  933. goto err;
  934. }
  935. cookie = tx->tx_submit(tx);
  936. if (dma_submit_error(cookie)) {
  937. ret = -ENOMEM;
  938. goto err;
  939. }
  940. dma_async_issue_pending(chan);
  941. }
  942. if (ret < 0)
  943. goto err;
  944. offset += loop_len;
  945. temp += loop_len;
  946. temp_phys += loop_len;
  947. remaining_len -= loop_len;
  948. offset_in_ca = 0;
  949. }
  950. if (tail_len) {
  951. if (offset == end_offset) {
  952. window = list_next_entry(window, list);
  953. end_offset = window->offset +
  954. (window->nr_pages << PAGE_SHIFT);
  955. }
  956. window_virt_addr = ioremap_remote(offset, window, tail_len,
  957. work->remote_dev,
  958. NULL);
  959. if (!window_virt_addr)
  960. return -ENOMEM;
  961. /*
  962. * The CPU copy for the tail bytes must be initiated only once
  963. * previous DMA transfers for this endpoint have completed
  964. * to guarantee ordering.
  965. */
  966. if (work->ordered) {
  967. struct scif_dev *rdev = work->remote_dev;
  968. ret = scif_drain_dma_intr(rdev->sdev, chan);
  969. if (ret)
  970. return ret;
  971. }
  972. if (src_local)
  973. scif_unaligned_cpy_toio(window_virt_addr, temp,
  974. tail_len, work->ordered);
  975. else
  976. scif_unaligned_cpy_fromio(temp, window_virt_addr,
  977. tail_len, work->ordered);
  978. iounmap_remote(window_virt_addr, tail_len, work);
  979. }
  980. tx = dev->device_prep_dma_memcpy(chan, 0, 0, 0, DMA_PREP_INTERRUPT);
  981. if (!tx) {
  982. ret = -ENOMEM;
  983. return ret;
  984. }
  985. tx->callback = &scif_rma_completion_cb;
  986. tx->callback_param = comp_cb;
  987. cookie = tx->tx_submit(tx);
  988. if (dma_submit_error(cookie)) {
  989. ret = -ENOMEM;
  990. return ret;
  991. }
  992. dma_async_issue_pending(chan);
  993. return 0;
  994. err:
  995. dev_err(scif_info.mdev.this_device,
  996. "%s %d Desc Prog Failed ret %d\n",
  997. __func__, __LINE__, ret);
  998. return ret;
  999. }
  1000. /*
  1001. * _scif_rma_list_dma_copy_aligned:
  1002. *
  1003. * Traverse all the windows and perform DMA copy.
  1004. */
  1005. static int _scif_rma_list_dma_copy_aligned(struct scif_copy_work *work,
  1006. struct dma_chan *chan)
  1007. {
  1008. dma_addr_t src_dma_addr, dst_dma_addr;
  1009. size_t loop_len, remaining_len, src_contig_bytes = 0;
  1010. size_t dst_contig_bytes = 0;
  1011. struct scif_window_iter src_win_iter;
  1012. struct scif_window_iter dst_win_iter;
  1013. s64 end_src_offset, end_dst_offset;
  1014. struct scif_window *src_window = work->src_window;
  1015. struct scif_window *dst_window = work->dst_window;
  1016. s64 src_offset = work->src_offset, dst_offset = work->dst_offset;
  1017. int ret = 0;
  1018. struct dma_async_tx_descriptor *tx;
  1019. struct dma_device *dev = chan->device;
  1020. dma_cookie_t cookie;
  1021. remaining_len = work->len;
  1022. scif_init_window_iter(src_window, &src_win_iter);
  1023. scif_init_window_iter(dst_window, &dst_win_iter);
  1024. end_src_offset = src_window->offset +
  1025. (src_window->nr_pages << PAGE_SHIFT);
  1026. end_dst_offset = dst_window->offset +
  1027. (dst_window->nr_pages << PAGE_SHIFT);
  1028. while (remaining_len) {
  1029. if (src_offset == end_src_offset) {
  1030. src_window = list_next_entry(src_window, list);
  1031. end_src_offset = src_window->offset +
  1032. (src_window->nr_pages << PAGE_SHIFT);
  1033. scif_init_window_iter(src_window, &src_win_iter);
  1034. }
  1035. if (dst_offset == end_dst_offset) {
  1036. dst_window = list_next_entry(dst_window, list);
  1037. end_dst_offset = dst_window->offset +
  1038. (dst_window->nr_pages << PAGE_SHIFT);
  1039. scif_init_window_iter(dst_window, &dst_win_iter);
  1040. }
  1041. /* compute dma addresses for transfer */
  1042. src_dma_addr = scif_off_to_dma_addr(src_window, src_offset,
  1043. &src_contig_bytes,
  1044. &src_win_iter);
  1045. dst_dma_addr = scif_off_to_dma_addr(dst_window, dst_offset,
  1046. &dst_contig_bytes,
  1047. &dst_win_iter);
  1048. loop_len = min(src_contig_bytes, dst_contig_bytes);
  1049. loop_len = min(loop_len, remaining_len);
  1050. if (work->ordered && !(remaining_len - loop_len)) {
  1051. /*
  1052. * Break up the last chunk of the transfer into two
  1053. * steps to ensure that the last byte in step 2 is
  1054. * updated last.
  1055. */
  1056. /* Step 1) DMA: Body Length - 1 */
  1057. tx = dev->device_prep_dma_memcpy(chan, dst_dma_addr,
  1058. src_dma_addr,
  1059. loop_len - 1,
  1060. DMA_PREP_FENCE);
  1061. if (!tx) {
  1062. ret = -ENOMEM;
  1063. goto err;
  1064. }
  1065. cookie = tx->tx_submit(tx);
  1066. if (dma_submit_error(cookie)) {
  1067. ret = -ENOMEM;
  1068. goto err;
  1069. }
  1070. src_offset += (loop_len - 1);
  1071. dst_offset += (loop_len - 1);
  1072. src_dma_addr += (loop_len - 1);
  1073. dst_dma_addr += (loop_len - 1);
  1074. remaining_len -= (loop_len - 1);
  1075. loop_len = remaining_len;
  1076. /* Step 2) DMA: 1 BYTES */
  1077. tx = dev->device_prep_dma_memcpy(chan, dst_dma_addr,
  1078. src_dma_addr, loop_len, 0);
  1079. if (!tx) {
  1080. ret = -ENOMEM;
  1081. goto err;
  1082. }
  1083. cookie = tx->tx_submit(tx);
  1084. if (dma_submit_error(cookie)) {
  1085. ret = -ENOMEM;
  1086. goto err;
  1087. }
  1088. dma_async_issue_pending(chan);
  1089. } else {
  1090. tx = dev->device_prep_dma_memcpy(chan, dst_dma_addr,
  1091. src_dma_addr, loop_len, 0);
  1092. if (!tx) {
  1093. ret = -ENOMEM;
  1094. goto err;
  1095. }
  1096. cookie = tx->tx_submit(tx);
  1097. if (dma_submit_error(cookie)) {
  1098. ret = -ENOMEM;
  1099. goto err;
  1100. }
  1101. }
  1102. src_offset += loop_len;
  1103. dst_offset += loop_len;
  1104. remaining_len -= loop_len;
  1105. }
  1106. return ret;
  1107. err:
  1108. dev_err(scif_info.mdev.this_device,
  1109. "%s %d Desc Prog Failed ret %d\n",
  1110. __func__, __LINE__, ret);
  1111. return ret;
  1112. }
  1113. /*
  1114. * scif_rma_list_dma_copy_aligned:
  1115. *
  1116. * Traverse all the windows and perform DMA copy.
  1117. */
  1118. static int scif_rma_list_dma_copy_aligned(struct scif_copy_work *work,
  1119. struct dma_chan *chan)
  1120. {
  1121. dma_addr_t src_dma_addr, dst_dma_addr;
  1122. size_t loop_len, remaining_len, tail_len, src_contig_bytes = 0;
  1123. size_t dst_contig_bytes = 0;
  1124. int src_cache_off;
  1125. s64 end_src_offset, end_dst_offset;
  1126. struct scif_window_iter src_win_iter;
  1127. struct scif_window_iter dst_win_iter;
  1128. void *src_virt, *dst_virt;
  1129. struct scif_window *src_window = work->src_window;
  1130. struct scif_window *dst_window = work->dst_window;
  1131. s64 src_offset = work->src_offset, dst_offset = work->dst_offset;
  1132. int ret = 0;
  1133. struct dma_async_tx_descriptor *tx;
  1134. struct dma_device *dev = chan->device;
  1135. dma_cookie_t cookie;
  1136. remaining_len = work->len;
  1137. scif_init_window_iter(src_window, &src_win_iter);
  1138. scif_init_window_iter(dst_window, &dst_win_iter);
  1139. src_cache_off = src_offset & (L1_CACHE_BYTES - 1);
  1140. if (src_cache_off != 0) {
  1141. /* Head */
  1142. loop_len = L1_CACHE_BYTES - src_cache_off;
  1143. loop_len = min(loop_len, remaining_len);
  1144. src_dma_addr = __scif_off_to_dma_addr(src_window, src_offset);
  1145. dst_dma_addr = __scif_off_to_dma_addr(dst_window, dst_offset);
  1146. if (src_window->type == SCIF_WINDOW_SELF)
  1147. src_virt = _get_local_va(src_offset, src_window,
  1148. loop_len);
  1149. else
  1150. src_virt = ioremap_remote(src_offset, src_window,
  1151. loop_len,
  1152. work->remote_dev, NULL);
  1153. if (!src_virt)
  1154. return -ENOMEM;
  1155. if (dst_window->type == SCIF_WINDOW_SELF)
  1156. dst_virt = _get_local_va(dst_offset, dst_window,
  1157. loop_len);
  1158. else
  1159. dst_virt = ioremap_remote(dst_offset, dst_window,
  1160. loop_len,
  1161. work->remote_dev, NULL);
  1162. if (!dst_virt) {
  1163. if (src_window->type != SCIF_WINDOW_SELF)
  1164. iounmap_remote(src_virt, loop_len, work);
  1165. return -ENOMEM;
  1166. }
  1167. if (src_window->type == SCIF_WINDOW_SELF)
  1168. scif_unaligned_cpy_toio(dst_virt, src_virt, loop_len,
  1169. remaining_len == loop_len ?
  1170. work->ordered : false);
  1171. else
  1172. scif_unaligned_cpy_fromio(dst_virt, src_virt, loop_len,
  1173. remaining_len == loop_len ?
  1174. work->ordered : false);
  1175. if (src_window->type != SCIF_WINDOW_SELF)
  1176. iounmap_remote(src_virt, loop_len, work);
  1177. if (dst_window->type != SCIF_WINDOW_SELF)
  1178. iounmap_remote(dst_virt, loop_len, work);
  1179. src_offset += loop_len;
  1180. dst_offset += loop_len;
  1181. remaining_len -= loop_len;
  1182. }
  1183. end_src_offset = src_window->offset +
  1184. (src_window->nr_pages << PAGE_SHIFT);
  1185. end_dst_offset = dst_window->offset +
  1186. (dst_window->nr_pages << PAGE_SHIFT);
  1187. tail_len = remaining_len & (L1_CACHE_BYTES - 1);
  1188. remaining_len -= tail_len;
  1189. while (remaining_len) {
  1190. if (src_offset == end_src_offset) {
  1191. src_window = list_next_entry(src_window, list);
  1192. end_src_offset = src_window->offset +
  1193. (src_window->nr_pages << PAGE_SHIFT);
  1194. scif_init_window_iter(src_window, &src_win_iter);
  1195. }
  1196. if (dst_offset == end_dst_offset) {
  1197. dst_window = list_next_entry(dst_window, list);
  1198. end_dst_offset = dst_window->offset +
  1199. (dst_window->nr_pages << PAGE_SHIFT);
  1200. scif_init_window_iter(dst_window, &dst_win_iter);
  1201. }
  1202. /* compute dma addresses for transfer */
  1203. src_dma_addr = scif_off_to_dma_addr(src_window, src_offset,
  1204. &src_contig_bytes,
  1205. &src_win_iter);
  1206. dst_dma_addr = scif_off_to_dma_addr(dst_window, dst_offset,
  1207. &dst_contig_bytes,
  1208. &dst_win_iter);
  1209. loop_len = min(src_contig_bytes, dst_contig_bytes);
  1210. loop_len = min(loop_len, remaining_len);
  1211. if (work->ordered && !tail_len &&
  1212. !(remaining_len - loop_len)) {
  1213. /*
  1214. * Break up the last chunk of the transfer into two
  1215. * steps. if there is no tail to gurantee DMA ordering.
  1216. * Passing SCIF_DMA_POLLING inserts a status update
  1217. * descriptor in step 1 which acts as a double sided
  1218. * synchronization fence for the DMA engine to ensure
  1219. * that the last cache line in step 2 is updated last.
  1220. */
  1221. /* Step 1) DMA: Body Length - L1_CACHE_BYTES. */
  1222. tx = dev->device_prep_dma_memcpy(chan, dst_dma_addr,
  1223. src_dma_addr,
  1224. loop_len -
  1225. L1_CACHE_BYTES,
  1226. DMA_PREP_FENCE);
  1227. if (!tx) {
  1228. ret = -ENOMEM;
  1229. goto err;
  1230. }
  1231. cookie = tx->tx_submit(tx);
  1232. if (dma_submit_error(cookie)) {
  1233. ret = -ENOMEM;
  1234. goto err;
  1235. }
  1236. dma_async_issue_pending(chan);
  1237. src_offset += (loop_len - L1_CACHE_BYTES);
  1238. dst_offset += (loop_len - L1_CACHE_BYTES);
  1239. src_dma_addr += (loop_len - L1_CACHE_BYTES);
  1240. dst_dma_addr += (loop_len - L1_CACHE_BYTES);
  1241. remaining_len -= (loop_len - L1_CACHE_BYTES);
  1242. loop_len = remaining_len;
  1243. /* Step 2) DMA: L1_CACHE_BYTES */
  1244. tx = dev->device_prep_dma_memcpy(chan, dst_dma_addr,
  1245. src_dma_addr,
  1246. loop_len, 0);
  1247. if (!tx) {
  1248. ret = -ENOMEM;
  1249. goto err;
  1250. }
  1251. cookie = tx->tx_submit(tx);
  1252. if (dma_submit_error(cookie)) {
  1253. ret = -ENOMEM;
  1254. goto err;
  1255. }
  1256. dma_async_issue_pending(chan);
  1257. } else {
  1258. tx = dev->device_prep_dma_memcpy(chan, dst_dma_addr,
  1259. src_dma_addr,
  1260. loop_len, 0);
  1261. if (!tx) {
  1262. ret = -ENOMEM;
  1263. goto err;
  1264. }
  1265. cookie = tx->tx_submit(tx);
  1266. if (dma_submit_error(cookie)) {
  1267. ret = -ENOMEM;
  1268. goto err;
  1269. }
  1270. dma_async_issue_pending(chan);
  1271. }
  1272. src_offset += loop_len;
  1273. dst_offset += loop_len;
  1274. remaining_len -= loop_len;
  1275. }
  1276. remaining_len = tail_len;
  1277. if (remaining_len) {
  1278. loop_len = remaining_len;
  1279. if (src_offset == end_src_offset)
  1280. src_window = list_next_entry(src_window, list);
  1281. if (dst_offset == end_dst_offset)
  1282. dst_window = list_next_entry(dst_window, list);
  1283. src_dma_addr = __scif_off_to_dma_addr(src_window, src_offset);
  1284. dst_dma_addr = __scif_off_to_dma_addr(dst_window, dst_offset);
  1285. /*
  1286. * The CPU copy for the tail bytes must be initiated only once
  1287. * previous DMA transfers for this endpoint have completed to
  1288. * guarantee ordering.
  1289. */
  1290. if (work->ordered) {
  1291. struct scif_dev *rdev = work->remote_dev;
  1292. ret = scif_drain_dma_poll(rdev->sdev, chan);
  1293. if (ret)
  1294. return ret;
  1295. }
  1296. if (src_window->type == SCIF_WINDOW_SELF)
  1297. src_virt = _get_local_va(src_offset, src_window,
  1298. loop_len);
  1299. else
  1300. src_virt = ioremap_remote(src_offset, src_window,
  1301. loop_len,
  1302. work->remote_dev, NULL);
  1303. if (!src_virt)
  1304. return -ENOMEM;
  1305. if (dst_window->type == SCIF_WINDOW_SELF)
  1306. dst_virt = _get_local_va(dst_offset, dst_window,
  1307. loop_len);
  1308. else
  1309. dst_virt = ioremap_remote(dst_offset, dst_window,
  1310. loop_len,
  1311. work->remote_dev, NULL);
  1312. if (!dst_virt) {
  1313. if (src_window->type != SCIF_WINDOW_SELF)
  1314. iounmap_remote(src_virt, loop_len, work);
  1315. return -ENOMEM;
  1316. }
  1317. if (src_window->type == SCIF_WINDOW_SELF)
  1318. scif_unaligned_cpy_toio(dst_virt, src_virt, loop_len,
  1319. work->ordered);
  1320. else
  1321. scif_unaligned_cpy_fromio(dst_virt, src_virt,
  1322. loop_len, work->ordered);
  1323. if (src_window->type != SCIF_WINDOW_SELF)
  1324. iounmap_remote(src_virt, loop_len, work);
  1325. if (dst_window->type != SCIF_WINDOW_SELF)
  1326. iounmap_remote(dst_virt, loop_len, work);
  1327. remaining_len -= loop_len;
  1328. }
  1329. return ret;
  1330. err:
  1331. dev_err(scif_info.mdev.this_device,
  1332. "%s %d Desc Prog Failed ret %d\n",
  1333. __func__, __LINE__, ret);
  1334. return ret;
  1335. }
  1336. /*
  1337. * scif_rma_list_cpu_copy:
  1338. *
  1339. * Traverse all the windows and perform CPU copy.
  1340. */
  1341. static int scif_rma_list_cpu_copy(struct scif_copy_work *work)
  1342. {
  1343. void *src_virt, *dst_virt;
  1344. size_t loop_len, remaining_len;
  1345. int src_page_off, dst_page_off;
  1346. s64 src_offset = work->src_offset, dst_offset = work->dst_offset;
  1347. struct scif_window *src_window = work->src_window;
  1348. struct scif_window *dst_window = work->dst_window;
  1349. s64 end_src_offset, end_dst_offset;
  1350. int ret = 0;
  1351. struct scif_window_iter src_win_iter;
  1352. struct scif_window_iter dst_win_iter;
  1353. remaining_len = work->len;
  1354. scif_init_window_iter(src_window, &src_win_iter);
  1355. scif_init_window_iter(dst_window, &dst_win_iter);
  1356. while (remaining_len) {
  1357. src_page_off = src_offset & ~PAGE_MASK;
  1358. dst_page_off = dst_offset & ~PAGE_MASK;
  1359. loop_len = min(PAGE_SIZE -
  1360. max(src_page_off, dst_page_off),
  1361. remaining_len);
  1362. if (src_window->type == SCIF_WINDOW_SELF)
  1363. src_virt = _get_local_va(src_offset, src_window,
  1364. loop_len);
  1365. else
  1366. src_virt = ioremap_remote(src_offset, src_window,
  1367. loop_len,
  1368. work->remote_dev,
  1369. &src_win_iter);
  1370. if (!src_virt) {
  1371. ret = -ENOMEM;
  1372. goto error;
  1373. }
  1374. if (dst_window->type == SCIF_WINDOW_SELF)
  1375. dst_virt = _get_local_va(dst_offset, dst_window,
  1376. loop_len);
  1377. else
  1378. dst_virt = ioremap_remote(dst_offset, dst_window,
  1379. loop_len,
  1380. work->remote_dev,
  1381. &dst_win_iter);
  1382. if (!dst_virt) {
  1383. if (src_window->type == SCIF_WINDOW_PEER)
  1384. iounmap_remote(src_virt, loop_len, work);
  1385. ret = -ENOMEM;
  1386. goto error;
  1387. }
  1388. if (work->loopback) {
  1389. memcpy(dst_virt, src_virt, loop_len);
  1390. } else {
  1391. if (src_window->type == SCIF_WINDOW_SELF)
  1392. memcpy_toio((void __iomem __force *)dst_virt,
  1393. src_virt, loop_len);
  1394. else
  1395. memcpy_fromio(dst_virt,
  1396. (void __iomem __force *)src_virt,
  1397. loop_len);
  1398. }
  1399. if (src_window->type == SCIF_WINDOW_PEER)
  1400. iounmap_remote(src_virt, loop_len, work);
  1401. if (dst_window->type == SCIF_WINDOW_PEER)
  1402. iounmap_remote(dst_virt, loop_len, work);
  1403. src_offset += loop_len;
  1404. dst_offset += loop_len;
  1405. remaining_len -= loop_len;
  1406. if (remaining_len) {
  1407. end_src_offset = src_window->offset +
  1408. (src_window->nr_pages << PAGE_SHIFT);
  1409. end_dst_offset = dst_window->offset +
  1410. (dst_window->nr_pages << PAGE_SHIFT);
  1411. if (src_offset == end_src_offset) {
  1412. src_window = list_next_entry(src_window, list);
  1413. scif_init_window_iter(src_window,
  1414. &src_win_iter);
  1415. }
  1416. if (dst_offset == end_dst_offset) {
  1417. dst_window = list_next_entry(dst_window, list);
  1418. scif_init_window_iter(dst_window,
  1419. &dst_win_iter);
  1420. }
  1421. }
  1422. }
  1423. error:
  1424. return ret;
  1425. }
  1426. static int scif_rma_list_dma_copy_wrapper(struct scif_endpt *epd,
  1427. struct scif_copy_work *work,
  1428. struct dma_chan *chan, off_t loffset)
  1429. {
  1430. int src_cache_off, dst_cache_off;
  1431. s64 src_offset = work->src_offset, dst_offset = work->dst_offset;
  1432. u8 *temp = NULL;
  1433. bool src_local = true, dst_local = false;
  1434. struct scif_dma_comp_cb *comp_cb;
  1435. dma_addr_t src_dma_addr, dst_dma_addr;
  1436. int err;
  1437. if (is_dma_copy_aligned(chan->device, 1, 1, 1))
  1438. return _scif_rma_list_dma_copy_aligned(work, chan);
  1439. src_cache_off = src_offset & (L1_CACHE_BYTES - 1);
  1440. dst_cache_off = dst_offset & (L1_CACHE_BYTES - 1);
  1441. if (dst_cache_off == src_cache_off)
  1442. return scif_rma_list_dma_copy_aligned(work, chan);
  1443. if (work->loopback)
  1444. return scif_rma_list_cpu_copy(work);
  1445. src_dma_addr = __scif_off_to_dma_addr(work->src_window, src_offset);
  1446. dst_dma_addr = __scif_off_to_dma_addr(work->dst_window, dst_offset);
  1447. src_local = work->src_window->type == SCIF_WINDOW_SELF;
  1448. dst_local = work->dst_window->type == SCIF_WINDOW_SELF;
  1449. dst_local = dst_local;
  1450. /* Allocate dma_completion cb */
  1451. comp_cb = kzalloc(sizeof(*comp_cb), GFP_KERNEL);
  1452. if (!comp_cb)
  1453. goto error;
  1454. work->comp_cb = comp_cb;
  1455. comp_cb->cb_cookie = comp_cb;
  1456. comp_cb->dma_completion_func = &scif_rma_completion_cb;
  1457. if (work->len + (L1_CACHE_BYTES << 1) < SCIF_KMEM_UNALIGNED_BUF_SIZE) {
  1458. comp_cb->is_cache = false;
  1459. /* Allocate padding bytes to align to a cache line */
  1460. temp = kmalloc(work->len + (L1_CACHE_BYTES << 1),
  1461. GFP_KERNEL);
  1462. if (!temp)
  1463. goto free_comp_cb;
  1464. comp_cb->temp_buf_to_free = temp;
  1465. /* kmalloc(..) does not guarantee cache line alignment */
  1466. if (!IS_ALIGNED((u64)temp, L1_CACHE_BYTES))
  1467. temp = PTR_ALIGN(temp, L1_CACHE_BYTES);
  1468. } else {
  1469. comp_cb->is_cache = true;
  1470. temp = kmem_cache_alloc(unaligned_cache, GFP_KERNEL);
  1471. if (!temp)
  1472. goto free_comp_cb;
  1473. comp_cb->temp_buf_to_free = temp;
  1474. }
  1475. if (src_local) {
  1476. temp += dst_cache_off;
  1477. scif_rma_local_cpu_copy(work->src_offset, work->src_window,
  1478. temp, work->len, true);
  1479. } else {
  1480. comp_cb->dst_window = work->dst_window;
  1481. comp_cb->dst_offset = work->dst_offset;
  1482. work->src_offset = work->src_offset - src_cache_off;
  1483. comp_cb->len = work->len;
  1484. work->len = ALIGN(work->len + src_cache_off, L1_CACHE_BYTES);
  1485. comp_cb->header_padding = src_cache_off;
  1486. }
  1487. comp_cb->temp_buf = temp;
  1488. err = scif_map_single(&comp_cb->temp_phys, temp,
  1489. work->remote_dev, SCIF_KMEM_UNALIGNED_BUF_SIZE);
  1490. if (err)
  1491. goto free_temp_buf;
  1492. comp_cb->sdev = work->remote_dev;
  1493. if (scif_rma_list_dma_copy_unaligned(work, temp, chan, src_local) < 0)
  1494. goto free_temp_buf;
  1495. if (!src_local)
  1496. work->fence_type = SCIF_DMA_INTR;
  1497. return 0;
  1498. free_temp_buf:
  1499. if (comp_cb->is_cache)
  1500. kmem_cache_free(unaligned_cache, comp_cb->temp_buf_to_free);
  1501. else
  1502. kfree(comp_cb->temp_buf_to_free);
  1503. free_comp_cb:
  1504. kfree(comp_cb);
  1505. error:
  1506. return -ENOMEM;
  1507. }
  1508. /**
  1509. * scif_rma_copy:
  1510. * @epd: end point descriptor.
  1511. * @loffset: offset in local registered address space to/from which to copy
  1512. * @addr: user virtual address to/from which to copy
  1513. * @len: length of range to copy
  1514. * @roffset: offset in remote registered address space to/from which to copy
  1515. * @flags: flags
  1516. * @dir: LOCAL->REMOTE or vice versa.
  1517. * @last_chunk: true if this is the last chunk of a larger transfer
  1518. *
  1519. * Validate parameters, check if src/dst registered ranges requested for copy
  1520. * are valid and initiate either CPU or DMA copy.
  1521. */
  1522. static int scif_rma_copy(scif_epd_t epd, off_t loffset, unsigned long addr,
  1523. size_t len, off_t roffset, int flags,
  1524. enum scif_rma_dir dir, bool last_chunk)
  1525. {
  1526. struct scif_endpt *ep = (struct scif_endpt *)epd;
  1527. struct scif_rma_req remote_req;
  1528. struct scif_rma_req req;
  1529. struct scif_window *local_window = NULL;
  1530. struct scif_window *remote_window = NULL;
  1531. struct scif_copy_work copy_work;
  1532. bool loopback;
  1533. int err = 0;
  1534. struct dma_chan *chan;
  1535. struct scif_mmu_notif *mmn = NULL;
  1536. bool cache = false;
  1537. struct device *spdev;
  1538. err = scif_verify_epd(ep);
  1539. if (err)
  1540. return err;
  1541. if (flags && !(flags & (SCIF_RMA_USECPU | SCIF_RMA_USECACHE |
  1542. SCIF_RMA_SYNC | SCIF_RMA_ORDERED)))
  1543. return -EINVAL;
  1544. loopback = scifdev_self(ep->remote_dev) ? true : false;
  1545. copy_work.fence_type = ((flags & SCIF_RMA_SYNC) && last_chunk) ?
  1546. SCIF_DMA_POLL : 0;
  1547. copy_work.ordered = !!((flags & SCIF_RMA_ORDERED) && last_chunk);
  1548. /* Use CPU for Mgmt node <-> Mgmt node copies */
  1549. if (loopback && scif_is_mgmt_node()) {
  1550. flags |= SCIF_RMA_USECPU;
  1551. copy_work.fence_type = 0x0;
  1552. }
  1553. cache = scif_is_set_reg_cache(flags);
  1554. remote_req.out_window = &remote_window;
  1555. remote_req.offset = roffset;
  1556. remote_req.nr_bytes = len;
  1557. /*
  1558. * If transfer is from local to remote then the remote window
  1559. * must be writeable and vice versa.
  1560. */
  1561. remote_req.prot = dir == SCIF_LOCAL_TO_REMOTE ? VM_WRITE : VM_READ;
  1562. remote_req.type = SCIF_WINDOW_PARTIAL;
  1563. remote_req.head = &ep->rma_info.remote_reg_list;
  1564. spdev = scif_get_peer_dev(ep->remote_dev);
  1565. if (IS_ERR(spdev)) {
  1566. err = PTR_ERR(spdev);
  1567. return err;
  1568. }
  1569. if (addr && cache) {
  1570. mutex_lock(&ep->rma_info.mmn_lock);
  1571. mmn = scif_find_mmu_notifier(current->mm, &ep->rma_info);
  1572. if (!mmn)
  1573. mmn = scif_add_mmu_notifier(current->mm, ep);
  1574. mutex_unlock(&ep->rma_info.mmn_lock);
  1575. if (IS_ERR(mmn)) {
  1576. scif_put_peer_dev(spdev);
  1577. return PTR_ERR(mmn);
  1578. }
  1579. cache = cache && !scif_rma_tc_can_cache(ep, len);
  1580. }
  1581. mutex_lock(&ep->rma_info.rma_lock);
  1582. if (addr) {
  1583. req.out_window = &local_window;
  1584. req.nr_bytes = ALIGN(len + (addr & ~PAGE_MASK),
  1585. PAGE_SIZE);
  1586. req.va_for_temp = addr & PAGE_MASK;
  1587. req.prot = (dir == SCIF_LOCAL_TO_REMOTE ?
  1588. VM_READ : VM_WRITE | VM_READ);
  1589. /* Does a valid local window exist? */
  1590. if (mmn) {
  1591. spin_lock(&ep->rma_info.tc_lock);
  1592. req.head = &mmn->tc_reg_list;
  1593. err = scif_query_tcw(ep, &req);
  1594. spin_unlock(&ep->rma_info.tc_lock);
  1595. }
  1596. if (!mmn || err) {
  1597. err = scif_register_temp(epd, req.va_for_temp,
  1598. req.nr_bytes, req.prot,
  1599. &loffset, &local_window);
  1600. if (err) {
  1601. mutex_unlock(&ep->rma_info.rma_lock);
  1602. goto error;
  1603. }
  1604. if (!cache)
  1605. goto skip_cache;
  1606. atomic_inc(&ep->rma_info.tcw_refcount);
  1607. atomic_add_return(local_window->nr_pages,
  1608. &ep->rma_info.tcw_total_pages);
  1609. if (mmn) {
  1610. spin_lock(&ep->rma_info.tc_lock);
  1611. scif_insert_tcw(local_window,
  1612. &mmn->tc_reg_list);
  1613. spin_unlock(&ep->rma_info.tc_lock);
  1614. }
  1615. }
  1616. skip_cache:
  1617. loffset = local_window->offset +
  1618. (addr - local_window->va_for_temp);
  1619. } else {
  1620. req.out_window = &local_window;
  1621. req.offset = loffset;
  1622. /*
  1623. * If transfer is from local to remote then the self window
  1624. * must be readable and vice versa.
  1625. */
  1626. req.prot = dir == SCIF_LOCAL_TO_REMOTE ? VM_READ : VM_WRITE;
  1627. req.nr_bytes = len;
  1628. req.type = SCIF_WINDOW_PARTIAL;
  1629. req.head = &ep->rma_info.reg_list;
  1630. /* Does a valid local window exist? */
  1631. err = scif_query_window(&req);
  1632. if (err) {
  1633. mutex_unlock(&ep->rma_info.rma_lock);
  1634. goto error;
  1635. }
  1636. }
  1637. /* Does a valid remote window exist? */
  1638. err = scif_query_window(&remote_req);
  1639. if (err) {
  1640. mutex_unlock(&ep->rma_info.rma_lock);
  1641. goto error;
  1642. }
  1643. /*
  1644. * Prepare copy_work for submitting work to the DMA kernel thread
  1645. * or CPU copy routine.
  1646. */
  1647. copy_work.len = len;
  1648. copy_work.loopback = loopback;
  1649. copy_work.remote_dev = ep->remote_dev;
  1650. if (dir == SCIF_LOCAL_TO_REMOTE) {
  1651. copy_work.src_offset = loffset;
  1652. copy_work.src_window = local_window;
  1653. copy_work.dst_offset = roffset;
  1654. copy_work.dst_window = remote_window;
  1655. } else {
  1656. copy_work.src_offset = roffset;
  1657. copy_work.src_window = remote_window;
  1658. copy_work.dst_offset = loffset;
  1659. copy_work.dst_window = local_window;
  1660. }
  1661. if (flags & SCIF_RMA_USECPU) {
  1662. scif_rma_list_cpu_copy(&copy_work);
  1663. } else {
  1664. chan = ep->rma_info.dma_chan;
  1665. err = scif_rma_list_dma_copy_wrapper(epd, &copy_work,
  1666. chan, loffset);
  1667. }
  1668. if (addr && !cache)
  1669. atomic_inc(&ep->rma_info.tw_refcount);
  1670. mutex_unlock(&ep->rma_info.rma_lock);
  1671. if (last_chunk) {
  1672. struct scif_dev *rdev = ep->remote_dev;
  1673. if (copy_work.fence_type == SCIF_DMA_POLL)
  1674. err = scif_drain_dma_poll(rdev->sdev,
  1675. ep->rma_info.dma_chan);
  1676. else if (copy_work.fence_type == SCIF_DMA_INTR)
  1677. err = scif_drain_dma_intr(rdev->sdev,
  1678. ep->rma_info.dma_chan);
  1679. }
  1680. if (addr && !cache)
  1681. scif_queue_for_cleanup(local_window, &scif_info.rma);
  1682. scif_put_peer_dev(spdev);
  1683. return err;
  1684. error:
  1685. if (err) {
  1686. if (addr && local_window && !cache)
  1687. scif_destroy_window(ep, local_window);
  1688. dev_err(scif_info.mdev.this_device,
  1689. "%s %d err %d len 0x%lx\n",
  1690. __func__, __LINE__, err, len);
  1691. }
  1692. scif_put_peer_dev(spdev);
  1693. return err;
  1694. }
  1695. int scif_readfrom(scif_epd_t epd, off_t loffset, size_t len,
  1696. off_t roffset, int flags)
  1697. {
  1698. int err;
  1699. dev_dbg(scif_info.mdev.this_device,
  1700. "SCIFAPI readfrom: ep %p loffset 0x%lx len 0x%lx offset 0x%lx flags 0x%x\n",
  1701. epd, loffset, len, roffset, flags);
  1702. if (scif_unaligned(loffset, roffset)) {
  1703. while (len > SCIF_MAX_UNALIGNED_BUF_SIZE) {
  1704. err = scif_rma_copy(epd, loffset, 0x0,
  1705. SCIF_MAX_UNALIGNED_BUF_SIZE,
  1706. roffset, flags,
  1707. SCIF_REMOTE_TO_LOCAL, false);
  1708. if (err)
  1709. goto readfrom_err;
  1710. loffset += SCIF_MAX_UNALIGNED_BUF_SIZE;
  1711. roffset += SCIF_MAX_UNALIGNED_BUF_SIZE;
  1712. len -= SCIF_MAX_UNALIGNED_BUF_SIZE;
  1713. }
  1714. }
  1715. err = scif_rma_copy(epd, loffset, 0x0, len,
  1716. roffset, flags, SCIF_REMOTE_TO_LOCAL, true);
  1717. readfrom_err:
  1718. return err;
  1719. }
  1720. EXPORT_SYMBOL_GPL(scif_readfrom);
  1721. int scif_writeto(scif_epd_t epd, off_t loffset, size_t len,
  1722. off_t roffset, int flags)
  1723. {
  1724. int err;
  1725. dev_dbg(scif_info.mdev.this_device,
  1726. "SCIFAPI writeto: ep %p loffset 0x%lx len 0x%lx roffset 0x%lx flags 0x%x\n",
  1727. epd, loffset, len, roffset, flags);
  1728. if (scif_unaligned(loffset, roffset)) {
  1729. while (len > SCIF_MAX_UNALIGNED_BUF_SIZE) {
  1730. err = scif_rma_copy(epd, loffset, 0x0,
  1731. SCIF_MAX_UNALIGNED_BUF_SIZE,
  1732. roffset, flags,
  1733. SCIF_LOCAL_TO_REMOTE, false);
  1734. if (err)
  1735. goto writeto_err;
  1736. loffset += SCIF_MAX_UNALIGNED_BUF_SIZE;
  1737. roffset += SCIF_MAX_UNALIGNED_BUF_SIZE;
  1738. len -= SCIF_MAX_UNALIGNED_BUF_SIZE;
  1739. }
  1740. }
  1741. err = scif_rma_copy(epd, loffset, 0x0, len,
  1742. roffset, flags, SCIF_LOCAL_TO_REMOTE, true);
  1743. writeto_err:
  1744. return err;
  1745. }
  1746. EXPORT_SYMBOL_GPL(scif_writeto);
  1747. int scif_vreadfrom(scif_epd_t epd, void *addr, size_t len,
  1748. off_t roffset, int flags)
  1749. {
  1750. int err;
  1751. dev_dbg(scif_info.mdev.this_device,
  1752. "SCIFAPI vreadfrom: ep %p addr %p len 0x%lx roffset 0x%lx flags 0x%x\n",
  1753. epd, addr, len, roffset, flags);
  1754. if (scif_unaligned((off_t __force)addr, roffset)) {
  1755. if (len > SCIF_MAX_UNALIGNED_BUF_SIZE)
  1756. flags &= ~SCIF_RMA_USECACHE;
  1757. while (len > SCIF_MAX_UNALIGNED_BUF_SIZE) {
  1758. err = scif_rma_copy(epd, 0, (u64)addr,
  1759. SCIF_MAX_UNALIGNED_BUF_SIZE,
  1760. roffset, flags,
  1761. SCIF_REMOTE_TO_LOCAL, false);
  1762. if (err)
  1763. goto vreadfrom_err;
  1764. addr += SCIF_MAX_UNALIGNED_BUF_SIZE;
  1765. roffset += SCIF_MAX_UNALIGNED_BUF_SIZE;
  1766. len -= SCIF_MAX_UNALIGNED_BUF_SIZE;
  1767. }
  1768. }
  1769. err = scif_rma_copy(epd, 0, (u64)addr, len,
  1770. roffset, flags, SCIF_REMOTE_TO_LOCAL, true);
  1771. vreadfrom_err:
  1772. return err;
  1773. }
  1774. EXPORT_SYMBOL_GPL(scif_vreadfrom);
  1775. int scif_vwriteto(scif_epd_t epd, void *addr, size_t len,
  1776. off_t roffset, int flags)
  1777. {
  1778. int err;
  1779. dev_dbg(scif_info.mdev.this_device,
  1780. "SCIFAPI vwriteto: ep %p addr %p len 0x%lx roffset 0x%lx flags 0x%x\n",
  1781. epd, addr, len, roffset, flags);
  1782. if (scif_unaligned((off_t __force)addr, roffset)) {
  1783. if (len > SCIF_MAX_UNALIGNED_BUF_SIZE)
  1784. flags &= ~SCIF_RMA_USECACHE;
  1785. while (len > SCIF_MAX_UNALIGNED_BUF_SIZE) {
  1786. err = scif_rma_copy(epd, 0, (u64)addr,
  1787. SCIF_MAX_UNALIGNED_BUF_SIZE,
  1788. roffset, flags,
  1789. SCIF_LOCAL_TO_REMOTE, false);
  1790. if (err)
  1791. goto vwriteto_err;
  1792. addr += SCIF_MAX_UNALIGNED_BUF_SIZE;
  1793. roffset += SCIF_MAX_UNALIGNED_BUF_SIZE;
  1794. len -= SCIF_MAX_UNALIGNED_BUF_SIZE;
  1795. }
  1796. }
  1797. err = scif_rma_copy(epd, 0, (u64)addr, len,
  1798. roffset, flags, SCIF_LOCAL_TO_REMOTE, true);
  1799. vwriteto_err:
  1800. return err;
  1801. }
  1802. EXPORT_SYMBOL_GPL(scif_vwriteto);