pci-me.c 12 KB

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  1. /*
  2. *
  3. * Intel Management Engine Interface (Intel MEI) Linux driver
  4. * Copyright (c) 2003-2012, Intel Corporation.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms and conditions of the GNU General Public License,
  8. * version 2, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. */
  16. #include <linux/module.h>
  17. #include <linux/moduleparam.h>
  18. #include <linux/kernel.h>
  19. #include <linux/device.h>
  20. #include <linux/fs.h>
  21. #include <linux/errno.h>
  22. #include <linux/types.h>
  23. #include <linux/fcntl.h>
  24. #include <linux/pci.h>
  25. #include <linux/poll.h>
  26. #include <linux/ioctl.h>
  27. #include <linux/cdev.h>
  28. #include <linux/sched.h>
  29. #include <linux/uuid.h>
  30. #include <linux/compat.h>
  31. #include <linux/jiffies.h>
  32. #include <linux/interrupt.h>
  33. #include <linux/pm_domain.h>
  34. #include <linux/pm_runtime.h>
  35. #include <linux/mei.h>
  36. #include "mei_dev.h"
  37. #include "client.h"
  38. #include "hw-me-regs.h"
  39. #include "hw-me.h"
  40. /* mei_pci_tbl - PCI Device ID Table */
  41. static const struct pci_device_id mei_me_pci_tbl[] = {
  42. {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
  43. {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
  44. {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
  45. {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
  46. {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
  47. {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
  48. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
  49. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
  50. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
  51. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
  52. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},
  53. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
  54. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
  55. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
  56. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
  57. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
  58. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
  59. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
  60. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
  61. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},
  62. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
  63. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
  64. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
  65. {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},
  66. {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH_CFG)},
  67. {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH_CFG)},
  68. {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
  69. {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
  70. {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH_CFG)},
  71. {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH_CFG)},
  72. {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH_CFG)},
  73. {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_CFG)},
  74. {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_CFG)},
  75. {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
  76. {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_CFG)},
  77. {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
  78. {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
  79. {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
  80. {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
  81. {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_CFG)},
  82. {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_CFG)},
  83. {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH8_CFG)},
  84. {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
  85. {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
  86. {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
  87. {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
  88. /* required last entry */
  89. {0, }
  90. };
  91. MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
  92. #ifdef CONFIG_PM
  93. static inline void mei_me_set_pm_domain(struct mei_device *dev);
  94. static inline void mei_me_unset_pm_domain(struct mei_device *dev);
  95. #else
  96. static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
  97. static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
  98. #endif /* CONFIG_PM */
  99. /**
  100. * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
  101. *
  102. * @pdev: PCI device structure
  103. * @cfg: per generation config
  104. *
  105. * Return: true if ME Interface is valid, false otherwise
  106. */
  107. static bool mei_me_quirk_probe(struct pci_dev *pdev,
  108. const struct mei_cfg *cfg)
  109. {
  110. if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
  111. dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
  112. return false;
  113. }
  114. return true;
  115. }
  116. /**
  117. * mei_me_probe - Device Initialization Routine
  118. *
  119. * @pdev: PCI device structure
  120. * @ent: entry in kcs_pci_tbl
  121. *
  122. * Return: 0 on success, <0 on failure.
  123. */
  124. static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  125. {
  126. const struct mei_cfg *cfg;
  127. struct mei_device *dev;
  128. struct mei_me_hw *hw;
  129. unsigned int irqflags;
  130. int err;
  131. cfg = mei_me_get_cfg(ent->driver_data);
  132. if (!cfg)
  133. return -ENODEV;
  134. if (!mei_me_quirk_probe(pdev, cfg))
  135. return -ENODEV;
  136. /* enable pci dev */
  137. err = pcim_enable_device(pdev);
  138. if (err) {
  139. dev_err(&pdev->dev, "failed to enable pci device.\n");
  140. goto end;
  141. }
  142. /* set PCI host mastering */
  143. pci_set_master(pdev);
  144. /* pci request regions and mapping IO device memory for mei driver */
  145. err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
  146. if (err) {
  147. dev_err(&pdev->dev, "failed to get pci regions.\n");
  148. goto end;
  149. }
  150. if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) ||
  151. dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
  152. err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
  153. if (err)
  154. err = dma_set_coherent_mask(&pdev->dev,
  155. DMA_BIT_MASK(32));
  156. }
  157. if (err) {
  158. dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
  159. goto end;
  160. }
  161. /* allocates and initializes the mei dev structure */
  162. dev = mei_me_dev_init(pdev, cfg);
  163. if (!dev) {
  164. err = -ENOMEM;
  165. goto end;
  166. }
  167. hw = to_me_hw(dev);
  168. hw->mem_addr = pcim_iomap_table(pdev)[0];
  169. pci_enable_msi(pdev);
  170. /* request and enable interrupt */
  171. irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
  172. err = request_threaded_irq(pdev->irq,
  173. mei_me_irq_quick_handler,
  174. mei_me_irq_thread_handler,
  175. irqflags, KBUILD_MODNAME, dev);
  176. if (err) {
  177. dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
  178. pdev->irq);
  179. goto end;
  180. }
  181. if (mei_start(dev)) {
  182. dev_err(&pdev->dev, "init hw failure.\n");
  183. err = -ENODEV;
  184. goto release_irq;
  185. }
  186. pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
  187. pm_runtime_use_autosuspend(&pdev->dev);
  188. err = mei_register(dev, &pdev->dev);
  189. if (err)
  190. goto stop;
  191. pci_set_drvdata(pdev, dev);
  192. /*
  193. * MEI requires to resume from runtime suspend mode
  194. * in order to perform link reset flow upon system suspend.
  195. */
  196. pdev->dev_flags |= PCI_DEV_FLAGS_NEEDS_RESUME;
  197. /*
  198. * For not wake-able HW runtime pm framework
  199. * can't be used on pci device level.
  200. * Use domain runtime pm callbacks instead.
  201. */
  202. if (!pci_dev_run_wake(pdev))
  203. mei_me_set_pm_domain(dev);
  204. if (mei_pg_is_enabled(dev))
  205. pm_runtime_put_noidle(&pdev->dev);
  206. dev_dbg(&pdev->dev, "initialization successful.\n");
  207. return 0;
  208. stop:
  209. mei_stop(dev);
  210. release_irq:
  211. mei_cancel_work(dev);
  212. mei_disable_interrupts(dev);
  213. free_irq(pdev->irq, dev);
  214. end:
  215. dev_err(&pdev->dev, "initialization failed.\n");
  216. return err;
  217. }
  218. /**
  219. * mei_me_shutdown - Device Removal Routine
  220. *
  221. * @pdev: PCI device structure
  222. *
  223. * mei_me_shutdown is called from the reboot notifier
  224. * it's a simplified version of remove so we go down
  225. * faster.
  226. */
  227. static void mei_me_shutdown(struct pci_dev *pdev)
  228. {
  229. struct mei_device *dev;
  230. dev = pci_get_drvdata(pdev);
  231. if (!dev)
  232. return;
  233. dev_dbg(&pdev->dev, "shutdown\n");
  234. mei_stop(dev);
  235. if (!pci_dev_run_wake(pdev))
  236. mei_me_unset_pm_domain(dev);
  237. mei_disable_interrupts(dev);
  238. free_irq(pdev->irq, dev);
  239. }
  240. /**
  241. * mei_me_remove - Device Removal Routine
  242. *
  243. * @pdev: PCI device structure
  244. *
  245. * mei_me_remove is called by the PCI subsystem to alert the driver
  246. * that it should release a PCI device.
  247. */
  248. static void mei_me_remove(struct pci_dev *pdev)
  249. {
  250. struct mei_device *dev;
  251. dev = pci_get_drvdata(pdev);
  252. if (!dev)
  253. return;
  254. if (mei_pg_is_enabled(dev))
  255. pm_runtime_get_noresume(&pdev->dev);
  256. dev_dbg(&pdev->dev, "stop\n");
  257. mei_stop(dev);
  258. if (!pci_dev_run_wake(pdev))
  259. mei_me_unset_pm_domain(dev);
  260. mei_disable_interrupts(dev);
  261. free_irq(pdev->irq, dev);
  262. mei_deregister(dev);
  263. }
  264. #ifdef CONFIG_PM_SLEEP
  265. static int mei_me_pci_suspend(struct device *device)
  266. {
  267. struct pci_dev *pdev = to_pci_dev(device);
  268. struct mei_device *dev = pci_get_drvdata(pdev);
  269. if (!dev)
  270. return -ENODEV;
  271. dev_dbg(&pdev->dev, "suspend\n");
  272. mei_stop(dev);
  273. mei_disable_interrupts(dev);
  274. free_irq(pdev->irq, dev);
  275. pci_disable_msi(pdev);
  276. return 0;
  277. }
  278. static int mei_me_pci_resume(struct device *device)
  279. {
  280. struct pci_dev *pdev = to_pci_dev(device);
  281. struct mei_device *dev;
  282. unsigned int irqflags;
  283. int err;
  284. dev = pci_get_drvdata(pdev);
  285. if (!dev)
  286. return -ENODEV;
  287. pci_enable_msi(pdev);
  288. irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
  289. /* request and enable interrupt */
  290. err = request_threaded_irq(pdev->irq,
  291. mei_me_irq_quick_handler,
  292. mei_me_irq_thread_handler,
  293. irqflags, KBUILD_MODNAME, dev);
  294. if (err) {
  295. dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
  296. pdev->irq);
  297. return err;
  298. }
  299. err = mei_restart(dev);
  300. if (err)
  301. return err;
  302. /* Start timer if stopped in suspend */
  303. schedule_delayed_work(&dev->timer_work, HZ);
  304. return 0;
  305. }
  306. #endif /* CONFIG_PM_SLEEP */
  307. #ifdef CONFIG_PM
  308. static int mei_me_pm_runtime_idle(struct device *device)
  309. {
  310. struct pci_dev *pdev = to_pci_dev(device);
  311. struct mei_device *dev;
  312. dev_dbg(&pdev->dev, "rpm: me: runtime_idle\n");
  313. dev = pci_get_drvdata(pdev);
  314. if (!dev)
  315. return -ENODEV;
  316. if (mei_write_is_idle(dev))
  317. pm_runtime_autosuspend(device);
  318. return -EBUSY;
  319. }
  320. static int mei_me_pm_runtime_suspend(struct device *device)
  321. {
  322. struct pci_dev *pdev = to_pci_dev(device);
  323. struct mei_device *dev;
  324. int ret;
  325. dev_dbg(&pdev->dev, "rpm: me: runtime suspend\n");
  326. dev = pci_get_drvdata(pdev);
  327. if (!dev)
  328. return -ENODEV;
  329. mutex_lock(&dev->device_lock);
  330. if (mei_write_is_idle(dev))
  331. ret = mei_me_pg_enter_sync(dev);
  332. else
  333. ret = -EAGAIN;
  334. mutex_unlock(&dev->device_lock);
  335. dev_dbg(&pdev->dev, "rpm: me: runtime suspend ret=%d\n", ret);
  336. if (ret && ret != -EAGAIN)
  337. schedule_work(&dev->reset_work);
  338. return ret;
  339. }
  340. static int mei_me_pm_runtime_resume(struct device *device)
  341. {
  342. struct pci_dev *pdev = to_pci_dev(device);
  343. struct mei_device *dev;
  344. int ret;
  345. dev_dbg(&pdev->dev, "rpm: me: runtime resume\n");
  346. dev = pci_get_drvdata(pdev);
  347. if (!dev)
  348. return -ENODEV;
  349. mutex_lock(&dev->device_lock);
  350. ret = mei_me_pg_exit_sync(dev);
  351. mutex_unlock(&dev->device_lock);
  352. dev_dbg(&pdev->dev, "rpm: me: runtime resume ret = %d\n", ret);
  353. if (ret)
  354. schedule_work(&dev->reset_work);
  355. return ret;
  356. }
  357. /**
  358. * mei_me_set_pm_domain - fill and set pm domain structure for device
  359. *
  360. * @dev: mei_device
  361. */
  362. static inline void mei_me_set_pm_domain(struct mei_device *dev)
  363. {
  364. struct pci_dev *pdev = to_pci_dev(dev->dev);
  365. if (pdev->dev.bus && pdev->dev.bus->pm) {
  366. dev->pg_domain.ops = *pdev->dev.bus->pm;
  367. dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
  368. dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
  369. dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
  370. dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
  371. }
  372. }
  373. /**
  374. * mei_me_unset_pm_domain - clean pm domain structure for device
  375. *
  376. * @dev: mei_device
  377. */
  378. static inline void mei_me_unset_pm_domain(struct mei_device *dev)
  379. {
  380. /* stop using pm callbacks if any */
  381. dev_pm_domain_set(dev->dev, NULL);
  382. }
  383. static const struct dev_pm_ops mei_me_pm_ops = {
  384. SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
  385. mei_me_pci_resume)
  386. SET_RUNTIME_PM_OPS(
  387. mei_me_pm_runtime_suspend,
  388. mei_me_pm_runtime_resume,
  389. mei_me_pm_runtime_idle)
  390. };
  391. #define MEI_ME_PM_OPS (&mei_me_pm_ops)
  392. #else
  393. #define MEI_ME_PM_OPS NULL
  394. #endif /* CONFIG_PM */
  395. /*
  396. * PCI driver structure
  397. */
  398. static struct pci_driver mei_me_driver = {
  399. .name = KBUILD_MODNAME,
  400. .id_table = mei_me_pci_tbl,
  401. .probe = mei_me_probe,
  402. .remove = mei_me_remove,
  403. .shutdown = mei_me_shutdown,
  404. .driver.pm = MEI_ME_PM_OPS,
  405. .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
  406. };
  407. module_pci_driver(mei_me_driver);
  408. MODULE_AUTHOR("Intel Corporation");
  409. MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
  410. MODULE_LICENSE("GPL v2");